Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate comprising a first region and a second region surrounding the first region, the substrate having a via in the first region; forming a first metal layer on the bottom surface and the sidewall of the via, and the top surface of the substrate; after forming the first metal layer, forming an etching stop layer covering the second region and exposing the first region; forming a second metal layer on the first metal layer between the etching stop layer; and removing the etching stop layer and the second metal layer between the etching stop layer. In the embodiment of the present application, the etching stop layer can protect the first metal layer on the substrate from being damaged, and at the same time of removing the second metal layer between the etching stop layer, the second metal layer between the first metal layer is not easy to be etched, that is, the etching stop layer can accurately control the thickness of the first metal layer and the second metal layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the increasingly precise semiconductor manufacturing technology, integrated circuits have undergone major changes, and the number of components integrated on the same chip has increased from tens or hundreds to millions. In order to meet the requirements of circuit density, the manufacturing process of semiconductor integrated circuit chips uses batch processing technology to form various types of complex devices on a substrate and connect them to each other to achieve complete electronic functions. At present, ultra-low-k interlayer dielectric layers are mostly used as dielectric materials to isolate metal interconnects between wires, and interconnection structures are used to provide wiring between devices on IC chips and the entire package. In this technology, devices such as field effect transistors (FETs) are first formed on the surface of a semiconductor substrate, and then interconnection structures are formed in the back end of line (BEOL) of integrated circuit manufacturing.

[0003] With the continuous reduction of the size of semiconductor substrates and the increasing performance of devices, more and more transistors are formed on the semiconductor substrate, and it is inevitable to use interconnection structures to connect the transistors. However, compared to the miniaturization and integration of components, the number of conductor lines in the circuit is increasing, and the quality of the formation of the interconnection structure has a great influence on the performance of the back end of line (BEOL) circuit, and in severe cases, it will affect the normal operation of the semiconductor device.

[0004] Magnetic random access memory (MRAM) is a non-volatile magnetic random memory. "Non-volatile" means that the memory remains complete after the power is turned off. MRAM devices have the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM), and can basically repeat writing an infinite number of times. Magnetic random access memory is a "full-energy" solid-state memory. Therefore, its application prospect is very promising, and it is expected to dominate the next generation of memory market. SUMMARY

[0005] The problem solved by the embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which optimizes the electrical performance of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure forming method, comprising: providing a substrate, the substrate comprising a first region and a second region surrounding the first region, the substrate having a via in the first region; forming a first metal layer on the bottom surface and sidewall of the via and the top surface of the substrate; after forming the first metal layer, forming an etching stop layer covering the second region and exposing the first region; forming a second metal layer on the first metal layer between the etching stop layer; removing the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer.

[0007] Optionally, the semiconductor structure forming method further comprises: after removing the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer, performing a planarization treatment on the first metal layer and the second metal layer.

[0008] Optionally, the material of the etching stop layer comprises one or more of amorphous silicon, silicon nitride, ethyl silicate, silicon oxynitride, silicon carbon nitride and silicon oxide.

[0009] Optionally, in the step of forming the etching stop layer, the thickness of the etching stop layer is 10-12 nm.

[0010] Optionally, the step of forming the etching stop layer comprises: forming an etching stop material layer covering the via and the substrate; after forming the etching stop material layer, forming a mask layer covering the second region and exposing the first region; etching the etching stop material layer with the mask layer as a mask, and the remaining etching stop material layer serving as the etching stop layer; the semiconductor structure forming method further comprises: after forming the etching stop layer, removing the mask layer.

[0011] Optionally, the etching stop material layer is etched with a dry etching process with the mask layer as a mask to form the etching stop layer.

[0012] Optionally, the etching stop material layer is formed by a chemical vapor deposition process.

[0013] Optionally, in the step of forming the first metal layer, the thickness of the first metal layer is 8-12 nm.

[0014] Optionally, the first metal layer is formed by an atomic layer deposition process or an electroplating process.

[0015] Optionally, in the process of removing the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer, the etching selectivity ratio of the etching stop layer to the second metal layer is 0.7-1.2.

[0016] Optionally, a chemical mechanical polishing process is used to remove the etching stop layer and a second metal layer located between the etching stop layer and higher than the first metal layer.

[0017] Optionally, the process parameters for removing the etching stop layer and a second metal layer located between the etching stop layer and higher than the first metal layer include: a process time of 8-12 seconds; a basic polishing solution, and a volume percentage of oxidizing agent of 0.5-2%.

[0018] Optionally, in the step of planarizing the first metal layer and the second metal layer, the height difference between the top surface of the first metal layer and the top surface of the second metal layer is less than 3 nm.

[0019] Optionally, the process parameters for planarizing the first metal layer and the second metal layer include: an acidic polishing solution, a volume percentage of oxidizing agent of 0.5-3%, and a process time of less than 5 seconds.

[0020] Optionally, the step of forming a second metal layer on the first metal layer between the etching stop layers includes: forming a metal material film on the etching stop layers and the first metal layer exposed by the etching stop layers; removing the metal material film higher than the etching stop layers with the top of the etching stop layer as a removal stop position, and the remaining metal material film as the second metal layer.

[0021] Optionally, a chemical mechanical polishing process is used to remove the metal material film higher than the etching stop layer.

[0022] Correspondingly, the embodiment of the present application also provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region surrounding the first region, the substrate in the first region having a via; a first metal layer located on the surface of the substrate and the bottom surface and sidewall of the via; a second metal layer located on the first metal layer of the first region, and the top surface of the second metal layer being higher than the top surface of the first metal layer; and an etching stop layer located on the first metal layer at the side of the second metal layer.

[0023] Optionally, the material of the etching stop layer comprises one or more of amorphous silicon, silicon nitride, ethyl silicate, silicon oxynitride, silicon carbon nitride, and silicon oxide.

[0024] Optionally, the thickness of the etching stop layer is 10-12 nm.

[0025] Optionally, the thickness of the first metal layer is 8-12 nm.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0027] In the method for forming the semiconductor structure, in the process of removing the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer, the first metal layer and the second metal layer below the etching stop layer are reserved, that is, the thickness of the first metal layer and the second metal layer on the substrate can be controlled, so that the reliability and yield of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure can be optimized. In addition, in the process of removing the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer, the etching selectivity of the second metal layer and the etching stop layer is adjusted to make the removal rates of the second metal layer and the etching stop layer consistent, so that the height difference between the top surface of the first metal layer and the top surface of the second metal layer is small, the surface roughness of the first metal layer and the second metal layer is small, and the reliability and yield of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure can be optimized.

[0028] In an optional solution, after the etching stop layer and the second metal layer located between the etching stop layer and higher than the first metal layer are removed, the first metal layer and the second metal layer are subjected to a planarization treatment. In the process of planarizing the first metal layer and the second metal layer, because the materials of the first metal layer and the second metal layer are both metal, the etching rate of the first metal layer is approximately the same as the etching rate of the second metal layer, and the planarization process can reduce the height difference between the top surface of the first metal layer and the top surface of the second metal layer, so that the surface roughness of the first metal layer and the second metal layer is small, and the reliability and yield of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure can be optimized. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figures 1-2 is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0030] Figures 3-5 is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0031] Figures 6-14 is a structure diagram corresponding to each step in a method for forming a semiconductor structure;

[0032] Figure 15 is a structure diagram of a semiconductor structure. DETAILED DESCRIPTION

[0033] As can be known from the background art, the device formed at present still has the problem of poor performance. The reasons for poor performance of the device will be analyzed in combination with a forming method of a semiconductor structure.

[0034] Reference Figures 1-2 is shown, a forming method of a semiconductor structure is shown.

[0035] As Figure 1 shown, a substrate is provided, the substrate includes a first region I and a second region II surrounding the first region I, the substrate includes a dielectric layer 1, the dielectric layer 1 of the first region I has a via (not shown in the figure); a metal material layer 2 is formed on the side wall and bottom of the via and the dielectric layer 1.

[0036] As Figure 2 shown, the metal material layer 2 is planarized by a chemical mechanical polishing process (CMP), and the remaining metal material layer 2 serves as a metal layer 3.

[0037] The thickness of the metal material layer 2 is relatively large, usually 500-800 nm, and the thickness of the metal layer 3 is usually 50-150 nm. In the process of planarizing the metal material layer 2 by chemical mechanical polishing, the thickness of the metal material layer 2 removed by planarization is relatively large, which makes it difficult to accurately control the thickness of the metal layer 3, and when the semiconductor structure is working, the resistivity of the semiconductor structure cannot meet the process requirements, and the reliability and yield of the semiconductor structure are poor.

[0038] Reference Figures 3-5 is shown, a forming method of another semiconductor structure is shown.

[0039] As Figure 3 shown, a substrate is provided, the substrate includes a first region I and a second region II surrounding the first region I, the substrate includes a dielectric layer 10, the dielectric layer 10 of the first region I has a via (not shown in the figure); a first metal layer 20 is formed on the side wall and bottom of the via and the dielectric layer 10.

[0040] As Figure 4 shown, the first metal layer 20 above the dielectric layer 10 is removed by a chemical mechanical polishing process with the top of the dielectric layer 10 as a stop position, and the remaining first metal layer 20 in the via serves as a first metal layer 30.

[0041] As Figure 5A second metal layer 40 is formed on the dielectric layer 10 and the first metal layer 30.

[0042] In the step of removing the first metal layer 20 above the dielectric layer 10 by using a chemical mechanical polishing process, the etching rate of the first metal layer 20 is greater than the etching rate of the dielectric layer 10, thus the top surface of the first metal layer 30 is easy to have a dishing, which is lower than the top surface of the dielectric layer 10, and the top surface of the second metal layer 40 in the first region I is lower than the top surface of the second metal layer 40 in the second region II, thus the surface roughness of the top surface of the first metal layer and the top surface of the second metal layer is large, which results in poor reliability and yield of the semiconductor structure.

[0043] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps.

[0044] In the forming method of the semiconductor structure, in the process of removing the etching stop layer and the second metal layer above the first metal layer between the etching stop layer, the first metal layer and the second metal layer below the etching stop layer are reserved, that is, the thickness of the first metal layer and the second metal layer on the substrate can be controlled, thus the reliability and yield of the semiconductor structure can be improved, and the electrical performance of the semiconductor structure is optimized.

[0045] In order to make the above object, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the embodiments of the present application are described in detail below with reference to the drawings.

[0046] Figures 6-14 is a structure diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure.

[0047] Referring to Figure 6 , a substrate 100 is provided, the substrate 100 including a first region I and a second region II surrounding the first region I, the substrate 100 having a via 103 in the first region I.

[0048] The substrate 100 provides process space for subsequent formation of a semiconductor structure.

[0049] The via 103 in the substrate 100 in the first region I prepares for subsequent formation of a first metal layer.

[0050] In the step of providing the substrate 100, the substrate 100 includes a dielectric layer 102.

[0051] The dielectric layer 102 is used to provide a process basis for the via 103.

[0052] Specifically, the material of the dielectric layer 102 is a low-k dielectric material, which is advantageous for reducing parasitic capacitance between back-end-of-line (BEOL) structures, and thus for reducing BEOL RC delay. Specifically, the material of the dielectric layer 102 is SiCOH.

[0053] In the step of providing the substrate 100, the substrate 100 further includes a bottom etching stop layer 101 at the bottom of the dielectric layer 102.

[0054] The material of the bottom etching stop layer 101 and the dielectric layer 102 is different, and in the step of forming the via 103 through the dielectric layer 102, the bottom etching stop layer 101 is used to temporarily stop etching, so that the dielectric layer 102 in the first region I and the second region II is less likely to have problems of etching excess or etching deficiency caused by inconsistent etching rates.

[0055] In this embodiment, the material of the bottom etching stop layer 101 includes one or more of SiO2, SiN, SiON, SiOC, and metal oxide. In this embodiment, the material of the bottom etching stop layer 101 includes SiN, which is a commonly used dielectric material in processes, has a relatively low cost, and has high process compatibility, which is advantageous for reducing the process difficulty and process cost of forming the bottom etching stop layer 101.

[0056] It should be noted that the semiconductor structure further includes a bottom dielectric layer 200 and an interconnection line 201 in the bottom dielectric layer 200, at the bottom of the substrate 100.

[0057] The bottom dielectric layer 200 is used to electrically isolate the interconnection line 201.

[0058] In this embodiment, the material of the bottom dielectric layer 200 is low-k dielectric material, which is beneficial to reduce the parasitic capacitance between the interconnection lines 201 and reduce the back-end RC delay. Specifically, the material of the bottom dielectric layer 200 is SiCOH.

[0059] It should be noted that the substrate 100 further includes a transistor, and the bottom dielectric layer 200 is usually formed on the transistor. The transistor includes a gate structure and source / drain doped regions on both sides of the gate structure. The substrate 100 further includes a contact hole plug (not shown in the figure) in contact with the source / drain doped regions.

[0060] The interconnection line 201 is used to connect with the contact plug.

[0061] In this embodiment, the material of the interconnection line 201 is copper. In other embodiments, according to actual process, the material of the interconnection line can also be tungsten, aluminum, cobalt or other conductive materials.

[0062] Referring to FIG. 1, a first metal layer 104 is formed on the bottom surface and sidewall of the via 103 (as shown in FIG. 1) and the top surface of the substrate 100. Figure 7 Figure 6 The first metal layer 104 is further used to provide a process basis for a subsequent etching stop layer. The first metal layer 104 is etched in part of the thickness as a part of the metal structure.

[0063] The material of the first metal layer 104 includes one or more of Cu, Co, W, Ta, TaN, Ti and TiN. In this embodiment, the material of the first metal layer 104 includes Cu. The resistivity of Cu is low, which is beneficial to improve the signal delay of the back-end RC, improve the processing speed of the semiconductor structure and reduce the power consumption.

[0064]

[0065] ​​In this embodiment, the first metal layer 104 is formed by an atomic layer deposition (ALD) process. The atomic layer deposition process is a deposition process in which gaseous precursors are alternately introduced into a reaction chamber to be chemisorbed on a substrate to be deposited and to undergo surface reactions. By the atomic layer deposition process, the first metal layer 104 is formed in the form of an atomic layer on the sidewalls and bottom surface of the via 103 and the top surface of the substrate 100, thus facilitating the uniformity of the deposition rate, the thickness uniformity of the first metal layer 104, and the structural uniformity in the first metal layer 104, and the first metal layer 104 has good coverage. In addition, the process temperature of the atomic layer deposition process is generally low, thus facilitating the reduction of thermal budget and the probability of performance deviation of the semiconductor structure. In other embodiments, the first metal layer can also be formed by an electroplating process.

[0066] It should be noted that the thickness of the first metal layer 104 should not be too thick or too thin. If the first metal layer 104 is too thick, it will take too much process time and material to form the first metal layer 104, causing resource waste, reducing the efficiency of forming the first metal layer 104, and the first metal layer 104 being too thick will easily lead to too small a conduction resistance of the first metal layer 104, making the first metal layer 104 not meet the electrical requirements. In addition, in the subsequent formation process of the semiconductor structure, a first metal layer 104 with a relatively large thickness needs to be etched as part of the metal structure, leading to a complex semiconductor structure formation process. If the first metal layer 104 is too thin, the metal structure formed by etching a portion of the thickness of the first metal layer 104 will be too thin, and the semiconductor structure will have a large resistivity and power consumption when working, leading to poor electrical performance of the semiconductor structure. In addition, if the first metal layer 104 is too thin, the surface flatness of the first metal layer 104 is poor, and the surface flatness of the metal structure formed by etching a portion of the thickness of the first metal layer 104 is poor, leading to poor reliability and yield of the semiconductor structure. In this embodiment, the thickness of the first metal layer 104 is 8-12 nm.

[0067] Reference Figures 8-10 After the first metal layer 104 is formed, an etching stop layer 105 covering the second region II and exposing the first region I is formed (as shown in FIG. 1C). Figure 10

[0068] ​Subsequently, a second metal layer is formed on the first metal layer 104 between the etch stop layers 105. During the process of removing the etch stop layers 105 and the second metal layer located between the etch stop layers 105 and above the first metal layer 104, the first metal layer 104 and the second metal layer below the etch stop layers 105 are retained. That is, the thickness of the first metal layer 104 and the second metal layer on the substrate 100 can be controlled, thereby improving the reliability and yield of the semiconductor structure and optimizing the electrical performance of the semiconductor structure.

[0069] Specifically, the material of the etch stop layer 105 includes one or more of amorphous silicon, silicon nitride, tetraethyl orthosilicate, silicon oxynitride, silicon carbide nitride, and silicon oxide. In this embodiment, the material of the etch stop layer 105 includes amorphous silicon.

[0070] It should be noted that in the step of forming the etch stop layer 105, the etch stop layer 105 should not be too thick or too thin. If the etch stop layer 105 is too thick, the process time required to form the etch stop layer 105 will be longer. In the subsequent semiconductor structure formation process, the etch stop layer 105 will also be removed, which will also take a longer time, resulting in a lower semiconductor structure formation efficiency. Subsequently, a metal material film is formed on the etch stop layer 105 and the first metal layer 104. The metal material film above the etch stop layer 105 is removed, and the remaining metal material film serves as the second metal layer. The first metal layer 104 and the second metal layer are planarized, and the remaining first metal layer 104 and the second metal layer serve as the metal structure. If the etch stop layer 105 is too thin, during the removal of the metal material film above the etch stop layer 105, the top of the etch stop layer 105 will not easily serve as a temporary stop. In other words, during the removal of the etch stop layer 105, it is easy to accidentally etch the first metal layer 104 below the etch stop layer 105 and the second metal layer between the first metal layer 104, resulting in a smaller thickness of the first metal layer 104 and the second metal layer on the substrate 100. This leads to lower reliability and yield of the semiconductor structure, and poorer electrical performance. Furthermore, the overall surface roughness of the first metal layer 104 and the second metal layer is difficult to control, further contributing to lower reliability and yield of the semiconductor structure. In this embodiment, the thickness of the etch stop layer 105 is 10 nanometers to 12 nanometers.

[0071] Specifically, the steps for forming the etching stop layer 105 include:

[0072] like Figure 8 As shown, an etch stop material layer 106 is formed covering the via 103 and the substrate 100.

[0073] The etching stop material layer 106 is prepared for forming the etching stop layer.

[0074] In this embodiment, the etching stop material layer 106 is formed by a chemical vapor deposition (CVD) process. The chemical vapor deposition process is a method of generating a thin film by chemical reaction of one or more gaseous compounds or elements containing the elements of the etching stop material layer 106, which has good step coverage, controlled deposition thickness, and high thin film purity.

[0075] As shown in FIG. 1C, after the etching stop material layer 106 is formed, a mask layer 107 covering the second region II and exposing the first region I is formed. Figure 9

[0076] Subsequently, the etching stop material layer 106 is etched with the mask layer 107 as a mask to form the etching stop layer.

[0077] In this embodiment, the mask layer 107 includes an organic material layer 1071, an anti-reflective coating layer 1072 on the organic material layer 1071, and a photoresist layer 1073 on the anti-reflective coating layer 1072.

[0078] In this embodiment, the material of the organic material layer 1071 includes spin on carbon (SOC), ODL (organic dielectric layer) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material.

[0079] In this embodiment, the material of the anti-reflective coating layer 1072 includes BARC (bottom anti-reflective coating) material or DARC (dielectric anti-reflective coating) material.

[0080] It should be noted that the photoresist layer 1073 has a groove 108 exposing the first region I. The groove 108 exposes the position of the etching stop material layer 106 to be removed, and prepares for the subsequent formation of the etching stop layer.

[0081] As shown in FIG. 1C, after the etching stop material layer 106 is formed, a mask layer 107 covering the second region II and exposing the first region I is formed. Figure 10 ​As shown, the etching stop material layer 106 is etched using the mask layer 107 as a mask, and the remaining etching stop material layer 106 serves as the etching stop layer 105.

[0082] In this embodiment, the etching stop material layer 106 is etched using a dry etching process with the mask layer 107 as a mask to form the etching stop layer. The dry etching process has anisotropic etching characteristics and good etching profile control, which is conducive to making the morphology of the etching stop layer meet the process requirements and improving the removal efficiency of the etching stop material layer 106. Moreover, by changing the etching gas, multiple film layers can be etched in the same etching equipment, simplifying the process steps.

[0083] The method for forming the semiconductor structure further includes removing the mask layer 107 after forming the etching stop layer 105.

[0084] The removal of the mask layer 107 is preparation for subsequently forming a second metal layer on the first metal layer 104 between the etching stop layer 105 and the etching stop layer 105.

[0085] In this embodiment, the mask layer 107 is removed using an ashing process.

[0086] It should be noted that the mask layer 107 formed in the step of forming the etching stop layer 105 and the mask formed in the step of forming the via 103 (as shown) can be formed based on the same mask (MASK), which is conducive to cost saving and has strong process operability. Figure 6

[0087] Reference is made to FIG. 1, and a second metal layer 109 (as shown) is formed on the first metal layer 104 between the etching stop layer 105. Figure 11 Figure 12 Figure 12

[0088] The second metal layer 109 and the first metal layer 104 are preparation for subsequently forming a metal structure.

[0089] Specifically, the material of the second metal layer 109 includes one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the second metal layer 109 includes Cu. Cu has a low resistivity, which is conducive to improving the signal delay of the late-stage RC, improving the processing speed of the semiconductor structure, and reducing power consumption.

[0090] Specifically, the step of forming the second metal layer 109 on the first metal layer 104 between the etching stop layer 105 includes:

[0091] Figure 11 ​​​​​As shown, a metal material film 111 is formed on the etch stop layer 105 and the first metal layer 104 exposed by the etch stop layer 105.

[0092] In this embodiment, the metal film 111 is formed using atomic layer deposition (ALD). ALD is a deposition process in which a vapor precursor is alternately pulsed into a reaction chamber, causing chemical adsorption and surface reaction on the substrate to be deposited. Through ALD, the metal film 111 is formed in atomic layers on the first metal layer 104 and the etch stop layer 105, thus improving the uniformity of the deposition rate, the thickness uniformity of the metal film 111, and the structural uniformity within the metal film 111. Furthermore, the process temperature of ALD is typically low, which helps to reduce the thermal budget and lower the probability of semiconductor structural performance deviation. In other embodiments, the metal film 111 can also be formed using electroplating.

[0093] like Figure 12 As shown, with the top of the etching stop layer 105 as the removal stop position, the metal material film 111 above the etching stop layer 105 is removed, and the remaining metal material film 111 serves as the second metal layer 109.

[0094] In the step of removing the metal material film 111 above the etching stop layer 105 by taking the top of the etching stop layer 105 as the removal stop position, the stop position is temporarily located at the top of the etching stop layer 105, and the first metal layer 104 below the etching stop layer 105 is not easily etched, so that the thickness of the final metal structure can be precisely controlled.

[0095] In this embodiment, chemical mechanical polishing (CMP) is used to remove the metal material film 111 above the etch stop layer 105. CMP is a global surface planarization technique.

[0096] It should be noted that in the step of removing the metal material film 111 above the etching stop layer 105, the etching selectivity ratio of the metal material film 111 to the etching stop layer 105 should not be too small. If the etching selectivity ratio of the metal material film 111 to the etching stop layer 105 is too small, when the top of the etching stop layer 105 is polished, the etching stop signal (motor torque) is not obvious, and it is not easy to stop polishing at the top of the etching stop layer 105, which is easy to remove the etching stop layer 105 by mistake, resulting in process confusion of the semiconductor structure, and the corresponding subsequent formed semiconductor structure has defects. In the embodiment, in the step of removing the metal material film 111 above the etching stop layer 105, the etching selectivity ratio of the metal material film 111 to the etching stop layer 105 is greater than 25.

[0097] In the embodiment, the process parameters for removing the metal material film 111 above the etching stop layer 105 include that the polishing solution is acidic.

[0098] The acidic polishing solution provides an acidic environment, in which the etching rate of the metal material film 111 is greater than the etching rate of the etching stop layer 105, so that the metal material film 111 can be quickly removed while the top of the etching stop layer 105 is used as the etching stop position.

[0099] The oxidizing agent is used to oxidize the metal material film 111, which is conducive to improving the polishing rate of the metal material film 111.

[0100] It should be noted that the volume percentage of the oxidizing agent in the polishing solution should not be too large or too small. If the volume percentage of the oxidizing agent in the polishing solution is too small, the oxidation rate of the metal material film 111 by the oxidizing agent is too slow, which is easy to cause the polishing rate of the metal material film 111 to be too slow. If the volume percentage of the oxidizing agent in the polishing solution is too large, continuously increasing the volume percentage of the oxidizing agent in the polishing solution cannot significantly improve the oxidation rate of the metal material film 111, and accordingly the polishing rate of the metal material film 111 is not easy to be significantly improved, which is easy to cause resource waste. In the embodiment, the volume percentage of the oxidizing agent is 0.5% to 3%.

[0101] It should be noted that in the process of removing the metal material film 111 above the etching stop layer 105, the etching rate of the metal material film 111 is greater than the etching rate of the etching stop layer 105, which is easy to cause the top of the second metal layer 109 to have a dishing, that is, the top surface of the etching stop layer 105 is higher than the top surface of the second metal layer 109.

[0102] Reference Figure 13, the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104 are removed.

[0103] , the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104 are removed.

[0104] In the process of removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104, the first metal layer 104 and the second metal layer 109 lower than the etching stop layer 105 are reserved, that is, the thickness of the first metal layer 104 and the second metal layer 109 on the substrate can be controlled, thereby improving the reliability and yield of the semiconductor structure and optimizing the electrical performance of the semiconductor structure. In addition, in the process of removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104, by adjusting the etching selectivity ratio of the second metal layer 109 and the etching stop layer 105, the removal rates of the second metal layer 109 and the etching stop layer 105 are consistent, so that the height difference between the top surface of the first metal layer 104 and the top surface of the second metal layer 109 is small, and the surface roughness of the first metal layer 104 and the second metal layer 109 is small, which is beneficial to improve the reliability and yield of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0105] In this embodiment, the chemical mechanical polishing process is used to remove the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104. The chemical mechanical polishing process is a global surface planarization technology.

[0106] It should be noted that in the step of removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104, the etching selectivity ratio of the etching stop layer 105 to the second metal layer 109 should not be too large or too small. If the etching selectivity ratio is too large, the removal rate of the etching stop layer 105 is higher than that of the second metal layer 109. After the etching stop layer 105 is removed, the top surface of the first metal layer 104 in the second region II is too low relative to the top surface of the second metal layer 109 in the first region I. Correspondingly, after the subsequent planarization treatment of the first metal layer 104 and the second metal layer 109, the top surface of the remaining first metal layer 104 is too high relative to the top surface of the second metal layer 109, that is, the surface roughness of the metal structure top surface as a whole is large, which leads to low reliability and yield of the semiconductor structure. If the etching selectivity ratio is too small, the removal rate of the etching stop layer 105 is lower than that of the second metal layer 109. After the second metal layer 109 between the etching stop layer 105 is removed, the etching stop layer 105 is still prone to remain. In the process of continuing to remove the etching stop layer 105, the remaining second metal layer 109 in the first region I is etched, which leads to that the top surface of the first metal layer 104 in the second region II is too low relative to the top surface of the second metal layer 109 in the first region I. After the subsequent planarization treatment of the first metal layer 104 and the second metal layer 109, the top surface of the remaining first metal layer 104 is too low relative to the top surface of the second metal layer 109, that is, the surface roughness of the metal structure top surface as a whole is large, which leads to low reliability and yield of the semiconductor structure. In the embodiment, in the step of removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104, the etching selectivity ratio of the etching stop layer 105 to the second metal layer 109 is 0.7 to 1.2.

[0107] In the embodiment, the process parameters for removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104 include that the polishing solution is alkaline.

[0108] The alkaline polishing solution provides an alkaline environment. In the alkaline environment, the etching rate of the etching stop layer 105 is similar to the etching rate of the second metal layer 109, so that the etching stop layer 105 and the second metal layer 109 are easily removed at the same time.

[0109] The oxidizing agent is used to oxidize the second metal layer 109, which is conducive to improving the polishing rate of the second metal layer 109.

[0110] It should be noted that the volume percentage of the oxidizing agent in the polishing solution should not be too large or too small. If the volume percentage of the oxidizing agent in the polishing solution is too small, the rate of oxidation of the second metal layer 109 by the oxidizing agent is too slow, which may result in a slow polishing rate of the second metal layer 109. If the volume percentage of the oxidizing agent in the polishing solution is too large, further increasing the volume percentage of the oxidizing agent in the polishing solution cannot significantly increase the polishing rate of the second metal layer 109, which may result in resource waste. In this embodiment, the volume percentage of the oxidizing agent is 0.5% to 2%.

[0111] It should be noted that the process time for removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104 should not be too long or too short. If the process time is too long, the thickness of the first metal layer 104 and the second metal layer 109 higher than the substrate 100 is small during the process of removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104. Accordingly, the thickness of the metal structure formed after the subsequent planarization treatment of the first metal layer 104 and the second metal layer 109 is small, and the resistivity of the semiconductor structure is large during the operation of the semiconductor structure, which may result in large power consumption and poor electrical performance of the semiconductor structure. If the process time is too short, the second metal layer 109 between the etching stop layer 105 and the etching stop layer 105 may be left, which is not conducive to the subsequent operation of the semiconductor formation method. In this embodiment, the process time is 8 seconds to 12 seconds.

[0112] Reference Figure 14 The semiconductor structure formation method further includes: after removing the etching stop layer 105 and the second metal layer 109 located between the etching stop layer 105 and higher than the first metal layer 104, performing planarization treatment on the first metal layer 104 and the second metal layer 109.

[0113] After the planarization treatment of the first metal layer 104 and the second metal layer 109, the remaining first metal layer 104 and second metal layer 109 serve as a metal structure 110.

[0114] In the process of planarizing the first metal layer 104 and the second metal layer 109 by using the planarization process, because the materials of the first metal layer 104 and the second metal layer 109 are both metal, the etching rate of the first metal layer 104 is approximately the same as the etching rate of the second metal layer 109, and the planarization process can further reduce the height difference between the top surface of the first metal layer 104 and the top surface of the second metal layer 109, so that the overall surface roughness of the top surface of the first metal layer 104 and the top surface of the second metal layer 109 is small, which is beneficial to improve the reliability and yield of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0115] The process parameters for planarizing the first metal layer 104 and the second metal layer 109 include that the grinding solution is acidic, and the volume percentage of the oxidizing agent is 0.5% to 3%.

[0116] The acidic grinding solution provides an acidic environment, and the etching rate of the first metal layer 104 and the second metal layer 109 is fast in the acidic environment.

[0117] The oxidizing agent is used to oxidize the first metal layer 104 and the second metal layer 109, which is beneficial to improve the grinding rate of the first metal layer 104 and the second metal layer 109.

[0118] It should be noted that the volume percentage of the oxidizing agent in the grinding solution should not be too large or too small. If the volume percentage of the oxidizing agent in the grinding solution is too small, the oxidation rate of the first metal layer 104 and the second metal layer 109 is too slow, which correspondingly easily leads to a slow grinding rate of the first metal layer 104 and the second metal layer 109. If the volume percentage of the oxidizing agent in the grinding solution is too large, continuously increasing the volume percentage of the oxidizing agent in the grinding solution cannot significantly improve the oxidation rate of the first metal layer 104 and the second metal layer 109, and correspondingly the grinding rate of the first metal layer 104 and the second metal layer 109 also cannot be significantly improved, which easily causes resource waste. In the embodiment, the volume percentage of the oxidizing agent is 0.5% to 3%.

[0119] It should be noted that in the step of planarizing the first metal layer 104 and the second metal layer 109 to form the metal structure 110, the process time should not be too long or too short. If the process time is too long, too much thickness of the first metal layer 104 and the second metal layer 109 will be etched, and correspondingly the thickness of the metal structure 110 on the substrate 100 cannot be well controlled, which leads to low reliability and yield of the semiconductor structure. In the embodiment, in the step of planarizing the first metal layer 104 and the second metal layer 109 to form the metal structure 110, the process time is less than 5 seconds.

[0120] It should be noted that in the step of forming the metal structure 110, the height difference between the top surface of the first metal layer 104 and the top surface of the second metal layer 109 should not be too large. If the height difference is too large, the reliability and yield of the magnetic random access memory (MRAM) formed on the metal structure 110 later will be poor, and the reliability and yield of the semiconductor structure will be low. In the embodiment, in the step of forming the metal structure 110, the height difference between the top surface of the first metal layer 104 and the top surface of the second metal layer 109 is less than 3 nanometers.

[0121] Correspondingly, the embodiment of the present application also provides a semiconductor structure. Referring to Figure 15 , a structure schematic diagram of an embodiment of the semiconductor structure of the present application is shown.

[0122] The semiconductor structure comprises: a substrate 200, the substrate 200 comprising a first region I and a second region II surrounding the first region I, the substrate 200 having a via (not shown in the figure) in the first region I; a first metal layer 204 located on the surface of the substrate 200 and the bottom surface and sidewall of the via; a second metal layer 209 located on the first metal layer 204 in the first region I, and the top surface of the second metal layer 209 being higher than the top surface of the first metal layer 204; and an etching stop layer 205 located on the first metal layer 204 at the side of the second metal layer 209.

[0123] In the semiconductor structure provided by the embodiment of the present application, in the process of removing the etching stop layer 205 and the second metal layer 209 between the etching stop layer 205, the first metal layer 204 and the second metal layer 209 below the etching stop layer 205 are retained, that is, the thickness of the first metal layer 204 and the second metal layer 209 on the substrate 100 can be controlled, thereby improving the reliability and yield of the semiconductor structure and optimizing the electrical performance of the semiconductor structure. In addition, in the process of removing the etching stop layer 205 and the second metal layer 209 between the etching stop layer 205 and higher than the first metal layer 204, by adjusting the etching selectivity ratio of the second metal layer 209 and the etching stop layer 205, the removal rates of the second metal layer 209 and the etching stop layer 205 are consistent, and therefore, the height difference between the top surface of the first metal layer 204 and the top surface of the second metal layer 209 is small, and the surface roughness of the top surface of the first metal layer 204 and the top surface of the second metal layer 209 as a whole is small, which is beneficial to improving the reliability and yield of the semiconductor structure and optimizing the electrical performance of the semiconductor structure.

[0124] After the etching stop layer 205 and the second metal layer 209 between the etching stop layer 205 are removed, the first metal layer 204 and the second metal layer 209 are subjected to a planarization treatment. In the process of planarizing the first metal layer 204 and the second metal layer 209 by using the planarization process, because the materials of the first metal layer 204 and the second metal layer 209 are both metal, the etching rate of the first metal layer 204 is approximately the same as the etching rate of the second metal layer 209, and the planarization process can reduce the height difference between the top surface of the first metal layer 204 and the top surface of the second metal layer 209, so that the overall surface roughness of the top surface of the first metal layer 204 and the top surface of the second metal layer 209 is small, which is beneficial to improve the reliability and yield of the semiconductor structure and optimize the electrical performance of the semiconductor structure.

[0125] The substrate 100 includes a dielectric layer 202.

[0126] Specifically, the material of the dielectric layer 202 is a low-k dielectric material, which is beneficial to reduce the parasitic capacitance between the back-end-of-line interconnection structures, and further beneficial to reduce the back-end-of-line RC delay. Specifically, the material of the dielectric layer 202 is SiCOH.

[0127] The substrate 100 further includes a bottom etching stop layer 201 located at the bottom of the dielectric layer 202.

[0128] The material of the bottom etching stop layer 201 and the dielectric layer 202 is different, and in the step of forming the via hole penetrating through the dielectric layer 202, the bottom etching stop layer 201 is used to temporarily stop etching, so that the dielectric layer 202 in the first region I and the second region II is not prone to the problem of etching excess or etching deficiency caused by inconsistent etching rate.

[0129] In this embodiment, the material of the bottom etching stop layer 201 includes one or more of SiO2, SiN, SiON, SiOC and metal oxide. In this embodiment, the material of the bottom etching stop layer 201 includes SiN, which is a commonly used dielectric material in the process and has a low cost and high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the bottom etching stop layer 201.

[0130] It should be noted that the substrate 100 further includes a bottom dielectric layer 400 and an interconnection line 401 located in the bottom dielectric layer 400.

[0131] The bottom dielectric layer 400 is used for electrically isolating the interconnection line 401.

[0132] In this embodiment, the material of the bottom dielectric layer 400 is low-k dielectric material, which is beneficial to reduce the parasitic capacitance between the interconnection lines 401 and reduce the back-end RC delay. Specifically, the material of the bottom dielectric layer 400 is SiCOH.

[0133] It should be noted that the substrate 100 also includes a transistor, and the bottom dielectric layer 400 is usually formed on the transistor. The transistor includes a gate structure and source / drain doped regions on both sides of the gate structure. The substrate 100 also includes a contact hole plug (not shown in the figure) in contact with the source / drain doped regions.

[0134] The interconnection line 401 is used to connect with the contact plug.

[0135] In this embodiment, the material of the interconnection line 401 is copper. In other embodiments, according to the actual process, the material of the interconnection line can also be tungsten, aluminum, cobalt, and other conductive materials.

[0136] Specifically, the material of the etching stop layer 205 includes one or more of amorphous silicon, silicon nitride, ethyl silicate, silicon oxynitride, silicon carbon nitride, and silicon oxide. In this embodiment, the material of the etching stop layer 205 includes amorphous silicon.

[0137] It should be noted that the etching stop layer 205 cannot be too thick or too thin. If the etching stop layer 205 is too thick, the process time for forming the etching stop layer 205 is relatively long. In the subsequent process of forming the semiconductor structure, the etching stop layer 205 also needs to be removed, which also requires a relatively long process time, resulting in a relatively low efficiency of forming the semiconductor structure. If the etching stop layer 205 is too thin, the first metal layer 204 below the etching stop layer 205 and the second metal layer 209 between the first metal layer 204 are easily damaged in the process of forming the semiconductor structure. In the subsequent process of removing the etching stop layer 205 and the second metal layer 209 between the etching stop layer 205, the thickness of the first metal layer 204 and the second metal layer 209 above the substrate 200 cannot meet the process requirements, resulting in a relatively low reliability and yield of the semiconductor structure, and a relatively poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the etching stop layer 205 is 10-12 nanometers.

[0138] The first metal layer 104 with a partial thickness is etched as part of the metal structure.

[0139] Specifically, the material of the first metal layer 204 includes one or more of Cu, Co, W, Ta, TaN, Ti and TiN. In this embodiment, the material of the first metal layer 204 includes Cu. Cu has a low resistivity, which is beneficial to improve the signal delay of the back-end RC, improve the processing speed of the semiconductor structure, and reduce the power consumption.

[0140] It should be noted that in the step of forming the first metal layer 204, the first metal layer 204 should not be too thick or too thin. If the first metal layer 204 is too thick, it will take too much process time and material to form the first metal layer 204, causing resource waste and reducing the forming efficiency of the first metal layer 204. If the first metal layer 204 is too thick, after the etching stop layer 205 is removed, the first metal layer 204 and the second metal layer 209 need to be removed to form the metal structure, which leads to a complex forming process of the semiconductor structure. If the first metal layer 204 is too thin, the thickness of the metal structure formed on the substrate 200 subsequently is also too thin. In the working of the semiconductor structure, the semiconductor structure has a large resistivity and large power consumption, which leads to poor electrical performance of the semiconductor structure. In this embodiment, in the step of forming the first metal layer 204, the thickness of the first metal layer 204 is 8-12 nm.

[0141] The second metal layer 209 is prepared for the subsequent formation of the metal structure.

[0142] Specifically, the material of the second metal layer 209 includes one or more of Cu, Co, W, Ta, TaN, Ti and TiN. In this embodiment, the material of the second metal layer 209 includes Cu. Cu has a low resistivity, which is beneficial to improve the signal delay of the back-end RC, improve the processing speed of the semiconductor structure, and reduce the power consumption.

[0143] The semiconductor structure can be formed by the forming method described in the foregoing embodiments, or can be formed by other forming methods. For the specific description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0144] Although the embodiments of the present application are disclosed as above, the embodiments of the present application are not limited to this. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present application, and therefore the protection scope of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region surrounding the first region, the substrate having a via in the first region; A first metal layer is formed on the bottom surface and sidewalls of the through hole, and on the top surface of the substrate; After the first metal layer is formed, an etch stop layer is formed that covers the second region and exposes the first region; A second metal layer is formed on the first metal layer between the etching stop layers; Remove the etch stop layer and the second metal layer located between the etch stop layer and above the first metal layer, wherein the second metal layer is present between the first metal layers.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after removing the etch stop layer and the second metal layer located between the etch stop layer and higher than the first metal layer, performing planarization on the first metal layer and the second metal layer.

3. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, The material of the etching stop layer includes one or more of amorphous silicon, silicon nitride, ethyl silicate, silicon oxynitride, silicon carbide, and silicon oxide.

4. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, In the step of forming the etching stop layer, the thickness of the etching stop layer is 10 nanometers to 12 nanometers.

5. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, The steps for forming the etching stop layer include: An etching stop material layer is formed covering the via and the substrate; After forming the etching stop material layer, a mask layer is formed that covers the second region and exposes the first region; The etching stop material layer is etched using the mask layer as a mask, and the remaining etching stop material layer serves as the etching stop layer. The method for forming the semiconductor structure further includes: after forming the etch stop layer, removing the mask layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The etching stop material layer is etched using a dry etching process with the mask layer as a mask to form the etching stop layer.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The etching stop material layer is formed using a chemical vapor deposition process.

8. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, In the step of forming the first metal layer, the thickness of the first metal layer is 8 nanometers to 12 nanometers.

9. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, The first metal layer is formed using atomic layer deposition or electroplating.

10. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, During the removal of the etch stop layer and the second metal layer located between the etch stop layer and above the first metal layer, the etch selectivity ratio of the etch stop layer to the second metal layer is 0.7 to 1.

2.

11. The method for forming a semiconductor structure as described in claim 1 or 2, characterized in that, The etching stop layer and the second metal layer located between the etching stop layer and above the first metal layer are removed using a chemical mechanical polishing process.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process parameters for removing the etch stop layer and the second metal layer located between the etch stop layer and above the first metal layer include: a process time of 8 to 12 seconds; an alkaline polishing solution; and an oxidant volume percentage of 0.5% to 2%.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of planarizing the first metal layer and the second metal layer, the height difference between the top surface of the first metal layer and the top surface of the second metal layer is less than 3 nanometers.

14. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process parameters for planarizing the first and second metal layers include: the grinding solution is acidic, the volume percentage of the oxidant is 0.5% to 3%, and the process time is less than 5 seconds.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second metal layer on the first metal layer between the etch stop layers includes: A metal material film is formed on the etching stop layer and the first metal layer exposed by the etching stop layer; Using the top of the etching stop layer as the removal stop position, the metal material film above the etching stop layer is removed, and the remaining metal material film serves as the second metal layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The metal material film above the etching stop layer is removed using a chemical mechanical polishing process.

17. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first region and a second region surrounding the first region, wherein the substrate in the first region has a via; A first metal layer is located on the surface of the substrate and the bottom and sidewalls of the via; A second metal layer is located on the first metal layer in the first region, and the top surface of the second metal layer is higher than the top surface of the first metal layer, with the second metal layer between the first metal layers; An etching stop layer is located on the first metal layer on the side of the second metal layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The material of the etching stop layer includes one or more of amorphous silicon, silicon nitride, ethyl silicate, silicon oxynitride, silicon carbide, and silicon oxide.

19. The semiconductor structure as claimed in claim 17, characterized in that, The thickness of the etching stop layer is 10 nanometers to 12 nanometers.

20. The semiconductor structure as claimed in claim 17, characterized in that, The thickness of the first metal layer is 8 nanometers to 12 nanometers.

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