Semiconductor device and method of forming the same

Abstract

The structure has a stack of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping each layer and the dielectric feature. A first layer of a first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose portions of the gate dielectric in the first region, while leaving the first gate electrode material in a second region of the substrate. A second gate electrode material is deposited over the exposed portions of the gate dielectric and over the remaining portions of the first gate electrode material. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. BACKGROUND

[0002] The electronics industry continues to demand smaller and faster electronic devices that can simultaneously support more complex and sophisticated functionality. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to make ICs that are lower in cost, higher in performance, and lower in power consumption. To date, these goals have been met to a large extent by reducing IC size (e.g., minimum IC feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of the IC fabrication process. Thus, achieving continued progress in IC devices and their performance requires similar progress in IC fabrication processes and techniques.

[0003] Nanosheet-based devices (sometimes also referred to as all-around gate devices, multi-bridge-channel devices, etc.) are promising candidate devices to push CMOS to the next stage of the technology roadmap due to their better gate control capability, lower leakage current, and full compatibility with FinFET device layouts. Fabrication of nanosheet-based devices requires multiple iterations of etching and deposition. As the spacing between transistors of opposite conductivity becomes smaller and smaller, it becomes increasingly challenging to implement such repeated etching operations without damaging adjacent components. This challenge can result in a decrease in performance or reliability. Thus, while existing semiconductor devices, particularly multi-gate devices, and methods of fabricating the same have been adequate for their intended purposes, they have not been wholly satisfactory in all respects. SUMMARY

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a structure having a substrate and a stack of semiconductor layers located above a surface of the substrate and adjacent to a dielectric component, each of the semiconductor layers being vertically spaced apart from one another within the respective stack; forming a gate dielectric layer wrapping each of the semiconductor layers and the dielectric component; depositing a first layer of a first gate electrode material above the gate dielectric layer and above the dielectric component; recessing the first layer of the first gate electrode material on the dielectric component to a first height below a top surface of the dielectric component; depositing a second layer of the first gate electrode material above the first layer of the first gate electrode material; removing the first gate electrode material in a first region of the substrate to expose a portion of the gate dielectric layer located in the first region without removing the first gate electrode material in a second region of the substrate; and depositing a second gate electrode material above the exposed portion of the gate dielectric layer and on a remaining portion of the first gate electrode material.

[0005] Still other embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first nanostructure over a substrate in a first region between a first pair of dielectric features; forming a second nanostructure over the substrate in a second region between a second pair of dielectric features; forming a gate dielectric layer wrapping the first and second nanostructures; forming a first layer of a first gate electrode material wrapping the gate dielectric layer on the first and second pairs of dielectric features; recessing the first layer to expose top portions of the first and second pairs of dielectric features; forming a second layer of the first gate electrode material on the exposed top portions of the first and second pairs of dielectric features and on the first layer; removing the first gate electrode material between the first pair of dielectric features to expose portions of the gate dielectric layer; and depositing a second gate electrode material on the exposed portions of the gate dielectric layer between the first pair of dielectric features and on remaining portions of the first gate electrode material between the second pair of dielectric features.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a semiconductor substrate having a substrate surface; a semiconductor layer located over the semiconductor substrate and separated from the semiconductor substrate along a first direction perpendicular to the substrate surface; a dielectric feature adjacent to the semiconductor layer extending from the substrate surface along the first direction, the dielectric feature having a first side facing the semiconductor layer and a second side opposite the first side; a gate dielectric layer having a first portion wrapping the semiconductor layer and a second portion located on the first side of the dielectric feature; a first gate electrode layer, wherein the first gate electrode layer includes a first segment wrapping the first portion of the gate dielectric layer and a second segment extending from the first segment to a sidewall surface of the second portion of the gate dielectric layer, the second segment having a top surface higher than a top surface of the first segment of the first gate electrode layer and lower than a top surface of the dielectric feature; and a second gate electrode layer located on the top surface of the first segment of the first gate electrode layer, on the top surface and sidewall surface of the second segment of the first gate electrode layer, and on the first side of the dielectric feature. BRIEF DESCRIPTION OF DRAWINGS

[0007] The application is best understood from the following detailed description when read in connection with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale. Rather, the various components are schematically depicted only.

[0008] Figure 1 is a flowchart of a method for fabricating a semiconductor device according to various aspects of the present application.

[0009] Figure 2A is a schematic top view of a semiconductor device according to various aspects of the present application. Figure 2B and Figure 2C is a schematic cross-sectional view of a semiconductor device in Figure 2A according to embodiments of the present application.

[0010] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 are partial schematic cross-sectional views of a semiconductor device in Figure 2A at various stages of fabrication, such as those associated with the method in Figure 1 . DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. Furthermore, the present application can be repeated with various example reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiment discussed.

[0012] Furthermore, spatially relative terms, such as "under", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the terms "about" and "approximately" as used herein when used in a description of a parameter, value, dimension, etc., mean that the parameter, value, dimension, etc. can be "off" by as much as 10%, unless otherwise stated. For example, the term "about 5 nm" can include dimensions from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0013] The present disclosure relates generally to semiconductor devices such as integrated circuits (ICs), and more particularly, to IC devices having nanosheet-based devices (or nanosheet-based transistors). Nanosheet-based devices refer to transistors having vertically stacked, horizontally oriented multi-channels. The term nanosheet-based devices broadly encompasses such devices having channels of any suitable shape, such as nanowires, nanosheets, nanorods, etc. Nanosheet-based devices are sometimes interchangeably referred to as gate-all-around devices (GAA devices) or multi-bridge-channel devices (MBC devices). Nanosheet-based devices are promising candidate devices to push CMOS to the next stage of the technology roadmap due to their better gate control capability, lower leakage current, and full compatibility with FinFET device layouts. However, nanosheet-based devices have complex device structures, and the limited spacing between device components of nanosheet-based devices sometimes presents more processing challenges. For example, some nanosheet-based devices implement dielectric fins to separate p-type transistors from adjacent n-type transistors. During a multiple patterning gate (MPG) process to form gate electrodes of different materials, some gate material is removed from areas between vertically adjacent channel layers and from areas between sidewall surfaces of the channel layers and sidewall surfaces of the dielectric fins by an etching process. As scaling continues, the reduced spacing in these areas sometimes makes the etching process more difficult to achieve without damaging the gate boundaries. Therefore, there is a need to improve the MPG process for nanosheet-based devices.

[0014] Figure 1is a flowchart of a method 100 for fabricating a semiconductor device according to various aspects of the present disclosure. In some embodiments, the method 100 fabricates a semiconductor device including a nanosheet-based transistor. Additional processing is contemplated by the present disclosure. Additional steps can be provided before, during, and after the method 100, and some steps described below can be moved, replaced, or eliminated according to additional embodiments of the method 100. The fabrication of the device 200 is described below in conjunction with Figures 2A to 14 The method 100 is described. Figure 2A is a partial schematic top view of a semiconductor device 200 at various fabrication stages related to the method 100 according to various aspects of the present disclosure. Figures 2B to 14 is a partial schematic cross-sectional view of the device 200 at various fabrication stages related to the method 100 according to various aspects of the present disclosure.

[0015] In this embodiment, the device 200 is a multi-gate (or multi-gate) device and can be included in microprocessors, memory, and / or other IC devices. In some embodiments, the device 200 is part of an IC chip, a system on a chip (SoC), or portions thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. In some embodiments, the multi-gate device 200 is included in non-volatile memory such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof. For clarity, the device 200 has been simplified to focus on the salient features of the present disclosure. Additional details known to those skilled in the art have been omitted. Figures 2A to 14 to better understand the inventive concepts of the present disclosure. Additional components can be added to the device 200, and some components described below can be replaced, modified, or eliminated in other embodiments of the device 200. The fabrication of the device 200 is described below in conjunction with embodiments of the method 100.

[0016] In operation 102, the method 100 Figure 1 provides or is provided with an initial structure (or workpiece) of the device 200, portions of which are shown in Figures 2A to 2C , according to embodiments. In particular, Figure 2AThe device 200 is shown to include two regions 200A and 200B. The region 200A includes an active region 204A and a gate region 206A that is substantially perpendicular to the active region 204A. The active region 204A includes a pair of source / drain (S / D) regions and a channel region between the pair of S / D regions. The gate region 206A is joined to the channel region. The region 200A also includes dielectric fins 231 that are oriented longitudinally substantially parallel to the active region 204A and on both sides of the active region 204A. The gate region 206A extends in the "y" direction between the two dielectric fins 231. Similarly, the region 200B includes an active region 204B and a gate region 206B that is substantially perpendicular to the active region 204B. The active region 204B includes a pair of S / D regions and a channel region between the pair of S / D regions. The gate region 206B is joined to the channel region. The region 200B also includes dielectric fins 231 that are oriented longitudinally substantially parallel to the active region 204B and on both sides of the active region 204B. The gate region 206B extends in the "y" direction between the two dielectric fins 231.

[0017] Figure 2B A cross-sectional view of the device 200 according to an embodiment is shown, which is a cross-sectional view of the regions 200A and 200B along the Al-Al and Bl-Bl lines, respectively, of Figure 2A FIG. 2. Figure 2C A cross-sectional view of the device 200 according to an embodiment is shown, which is a cross-sectional view of the regions 200A and 200B along the A2-A2 and B2-B2 lines, respectively, of Figure 2A FIG. 3. Figure 2B and Figure 2C The embodiments shown in FIGS. 2 and 3 are nanosheet-based devices, where their channel layers 215 are in the shape of nanoscale sheets. For clarity, the regions 200A and 200B are shown to have the same configuration to better understand the inventive concept of the present disclosure. In various embodiments, the regions 200A and 200B can have different configurations. For example, they can have different numbers of channels and / or their channel layers 215 can have different shapes or sizes. For another example, either of the regions 200A and 200B can be a nanowire FET (i.e., the channel layer 215 is in the shape of a nanoscale wire or a nanoscale rod) or a nanosheet FET.

[0018] Reference is made to Figures 2B to 2CIn the depicted embodiment, the substrate 202 includes silicon. Alternatively or additionally, the substrate 202 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Optionally, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0019] Each of the regions 200A and 200B also includes a pair of S / D components 260. For n-type transistors, the S / D components 260 are n-type. For p-type transistors, the S / D components 260 are p-type. The S / D components 260 can be formed, for example, by epitaxially growing a semiconductor material (e.g., Si, SiGe) to fill the trenches in the device 200 using CVD deposition techniques (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or a combination thereof. Thus, the S / D components 260 are also interchangeably referred to as epitaxial S / D components 260 or epitaxial components 260. The S / D components 260 are doped with appropriate n-type dopants and / or p-type dopants. For example, for n-type transistors, the S / D components 260 can include silicon and be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof; and for p-type transistors, the S / D components 260 can include silicon germanium or germanium and be doped with boron, other p-type dopants, or a combination thereof.

[0020] Each of the regions 200A and 200B also includes a stack of semiconductor layers 215 that overhang the substrate 202 and connect the pair of S / D components 260. The stack of semiconductor layers 215 serves as a transistor channel for the respective transistor. Thus, the semiconductor layers 215 are also referred to as channel layers 215. The channel layers 215 are in contact with the respective gate regions 206A and 206B (e.g., the gate dielectric layers 208 and the gate electrode layers 210) and the respective S / D components 260. Figure 2AThe channel layers 215 can include monocrystalline silicon. Alternatively, the channel layers 215 can include germanium, silicon germanium, or another suitable semiconductor material. Initially, the channel layers 215 are formed as part of a semiconductor layer stack that includes the channel layers 215 and other semiconductor layers of different materials. The semiconductor layer stack is patterned into the shape of fins protruding above the substrate 202 using one or more photolithography processes including a double patterning or multiple patterning process. After the gate trenches 275 are formed, the semiconductor layer stack is selectively etched to remove the other semiconductor layers, leaving the channel layers 215 suspended above the substrate 202 and between the respective S / D components 260. The channel layers 215 are separated from each other and from the substrate 202 by the gaps 277A.

[0021] In some embodiments, each channel layer 215 has a nanoscale dimension, and thus can be referred to as a nanostructure. For example, in some embodiments, each channel layer 215 can have a length (along the "x" direction, which is perpendicular to the plane defined by the "y" and "z" directions) of about 10 nm to about 300 nm and a width (along the "y" direction) of about 10 nm to about 80 nm and a height (along the "z" direction) of about 4 nm to about 8 nm. In some embodiments, the vertical separation ho of the gaps 277A (along the "z" direction) between the channel layers 215 can be about 6 nm to about 15 nm. Thus, depending on the relative dimensions, the channel layers 215 can be referred to as "nanowires" or "nanosheets," which generally refer to channel layers that are suspended in a manner that allows a high-k metal gate to physically wrap around the channel layers. In some embodiments, the channel layers 215 can be cylindrical (e.g., nanowires), rectangular (e.g., nanorods), sheet-shaped (e.g., nanosheets), or have other suitable shapes.

[0022] The device 200 also includes isolation components 230 to isolate various regions, such as the various active regions 204A and 204B. The isolation components 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituents), or combinations thereof. The isolation components 230 can include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. The isolation components 230 can include multiple layers of insulating materials.

[0023] Device 200 also includes gate spacers 247 adjacent to S / D features 260. Gate spacers 247 can include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In some embodiments, gate spacers 247 include a multi-layer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. Device 200 also includes internal spacers 255 vertically positioned between adjacent channel layers 215 and adjacent to S / D features 260. Internal spacers 255 can include a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, internal spacers 255 include a low-k dielectric material. Gate spacers 247 and internal spacers 255 are formed by deposition (e.g., CVD, PVD, ALD, etc.) and etching processes (e.g., dry etching). Gate trenches 275 are provided between opposing gate spacers 247 and opposing internal spacers 255 along the "x" direction. Further, the distance between opposing gate spacers 247 of gate trenches 275 has a distance d3 that defines a gate length. In some embodiments, distance d3 is greater than about 10 nm, for example, from about 19 nm to about 50 nm. If distance d3 is too small, such as less than about 10 nm, then subsequently formed layers, such as sacrificial layers described below, will be difficult to remove and their remnants can interfere with the intended performance. In other words, a larger distance d3 increases the processing window and allows materials to more easily access the internal and deeper regions between and around channel layers 215.

[0024] Device 200 also includes a contact etch stop layer (CESL) 268 disposed above isolation features 230, S / D features 260, and gate spacers 247. CESL 268 includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. CESL 268 can be formed by a deposition process, such as CVD, or other suitable methods. Device 200 also includes an interlayer dielectric (ILD) layer 270 above CESL 268. ILD layer 270 includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric materials, or combinations thereof. ILD layer 270 can be formed by a deposition process, such as CVD, flowable CVD (FCVD), or other suitable methods.

[0025] Dielectric fins 231 (sometimes interchangeably referred to as hybrid fins 231) are disposed above isolation features 230. In some embodiments, dielectric fins 231 include a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, dielectric fins 231 include a low-k dielectric material. Dielectric fins 231 can be formed by a deposition process, such as CVD, flowable CVD (FCVD), or other suitable methods. Figure 2CIn the depicted embodiment, the dielectric fin 231 includes a dielectric liner 232, a dielectric fill layer 233 over the dielectric liner 232, and a dielectric cap 234 over the dielectric liner 232 and the dielectric fill layer 233. In embodiments, the dielectric liner 232 includes a low-k dielectric material, such as a dielectric material including Si, O, N, and C. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, xerogel, aerogel, amorphous carbon fluoride, parylene, BCB, polyimide, or combinations thereof. A low-k dielectric material generally refers to a dielectric material having a low dielectric constant, e.g., lower than the dielectric constant of silicon oxide (k ~ 3.9). The dielectric liner 232 can be deposited using CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In embodiments, the dielectric fill layer 233 includes silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-k dielectric material, other suitable dielectric material, or combinations thereof. The dielectric fill layer 233 can be deposited using a flowable CVD (FCVD) process, which includes, e.g., depositing a flowable material (such as a liquid compound) over the device 200 and converting the flowable material to a solid material through suitable techniques such as thermal annealing and / or ultraviolet radiation treatment. The dielectric fill layer 233 can be deposited using other types of methods. In embodiments, the dielectric cap 234 includes a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3(BTO), (Ba, Sr)TiO3(BST), Si3N4, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or combinations thereof. A high-k dielectric material generally refers to a dielectric material having a high dielectric constant, e.g., greater than the dielectric constant of silicon oxide (k ~ 3.9). The dielectric cap 234 is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof.

[0026] The dielectric fins 231 each have a width dimension tO. In some embodiments, the width dimension tO is about 5 nm to about 30 nm. The dielectric fins 231 cut through portions of the gate structure having different gate materials and isolate adjacent device regions. If the dimension tO is too small, such as less than about 5 nm, the dielectric fins 231 can be too weak to withstand subsequent processing operations and compromise the integrity of the devices they protect. Conversely, if the dimension tO is too large, such as greater than about 30 nm, the cost associated with the valuable chip real estate they occupy outweighs any additional benefits that can be realized. In some embodiments, the dielectric fins 231 (e.g., the dielectric caps 234) extend above the top surface of the channel layer 215, for example, a distance Hl. In some embodiments, the distance Hl is about 5 nm to about 50 nm. If the distance Hl is too small, such as less than 5 nm, there can not be sufficient margin of error to ensure proper isolation between adjacent gate portions. Conversely, if the distance Hl is too high, the additional height does not justify the cost of its material and processing. The gate trenches 275 are provided in the "y" direction between opposing dielectric fins 231. In some embodiments, adjacent dielectric fins 231 are separated by a distance dO. Thus, the gate trenches 275 have a lateral width equal to the distance dO. In some embodiments, the distance dO is about 20 nm to about 100 nm. The gate trenches 275 include a gap 277B between the sidewall surfaces of the channel layer 215 and the dielectric fins 231. The gap 277B has a lateral width wO. In some embodiments, the lateral width wO is about 8 nm to about 17 nm. In addition, the gate trenches 275 also include a gap 277A between vertically adjacent channel layers 215. The gap 277A has a vertical dimension hO. In some embodiments, the vertical dimension hO is about 6 nm to about 15 nm. If the width wO is too small, such as less than about 8 nm, or if the dimension hO is too small, such as less than about 6 nm, there can not be sufficient spacing to form subsequent layers to form proper high-k metal gate structures. Conversely, if the width wO is too large, such as greater than about 17 nm, or if the dimension hO is too large, such as greater than about 15 nm, their additional volume can not justify their chip real estate and / or the material and processing costs associated therewith. In some embodiments, the difference Δ1 between the lateral width wO and the distance hO is at least about 1 nm to about 3 nm. If the difference Δ1 is too small, such as less than about 1 nm to about 3 nm, subsequently formed layers can merge in the gap 277B before merging in the gap 277A. This sometimes cuts off material diffusion paths into and out of the gap 277A. Thus, subsequently formed electrode layers can not completely fill the gap 277A and completely surround the channel layer 215. As a result, gate control of the channel layer 215 can be compromised. In some embodiments, the difference Δ2 between the gate length d3 and the distance hO is at least about 3 nm to about 5 nm.If the difference Δ2 is too small, such as less than about 3 nm to about 5 nm, then the subsequently formed layer can similarly merge across the dimension defined by the inner spacers and prevent full filling of the gap 277A.

[0027] In operation 104, the method 100 Figure 1 forms an interface gate dielectric layer (or simply, interface layer) 280, such as shown in FIG. 2B, on the exposed surfaces of the channel layer 215 in the gate trench 275. Figure 3 Figures 3 to 14 Cross-sectional views of regions 200A and 200B at different processing stages and along the A2-A2 line and the B2-B2 line of FIG. 2A are shown in FIGS. 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21, 2J, 2K, 2L, 2M, 2N, 2O, 2P, 2Q, 2R, 2S, 2T, 2U, 2V, 2W, 2X, 2Y, and 2Z, respectively. Figure 2A Figure 3 In the depicted embodiment, the interface layer 280 wraps around each of the channel layer 215 and partially fills the gap 277A. In this embodiment, the interface layer 280 is disposed on the semiconductor surfaces exposed in the gate trench 275, such as the surfaces of the channel layer 215 and the substrate 202, but not on the dielectric surfaces exposed in the gate trench 275, such as the surfaces of the isolation features 230, the gate spacers 247, and the dielectric fins 231. For example, the interface layer 280 can be formed by an oxidation process, such as thermal oxidation or chemical oxidation, in which the semiconductor surfaces react with oxygen to form semiconductor oxides as the interface layer 280. In such an oxidation process, the dielectric surfaces do not react with oxygen and thus no interface layer 280 is formed thereon. In alternative embodiments, the interface layer 280 is disposed on the isolation features 230, the gate spacers 247, and the dielectric fins 231, for example, by using atomic layer deposition (ALD) or other suitable deposition methods, in addition to being disposed on the channel layer 215 and the substrate 202. The interface layer 280 includes a dielectric material, such as Si02, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. In some embodiments, the interface layer 280 has a thickness of about to about If the interface layer 280 is too thin, such as less than about , its reliability can be poor in some cases. If the interface layer 280 is too thick, such as greater than about , the remaining portion of the gap 277A can be too small to have a high-k dielectric layer and a metal electrode layer filled therein in some cases.

[0028] Still in operation 104, the method 100 Figure 1 further forms a high-k gate dielectric layer (or simply, high-k dielectric layer) 282, such as shown in FIG. 2C, over the interface layer 280 and over other structures exposed in the gate trench 275. Figure 3 Still referring to FIG. 2C, the high-k dielectric layer 282 is formed over the interface layer 280 and over other structures exposed in the gate trench 275, such as the isolation features 230, the gate spacers 247, and the dielectric fins 231. The high-k dielectric layer 282 includes a high-k dielectric material, such as Hf02, Zr02, Ti02, Al203, other high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric layer 282 has a thickness of about Figure 3 ​​A high-k dielectric layer 282 is disposed over the interface layer 280 and wraps each of the channel layers 215. The high-k dielectric layer 282 and the interface layer 280 can be collectively referred to as a gate dielectric layer of the device 200. The gate dielectric layer partially fills the gap 277A. In the present embodiment, the high-k dielectric layer 282 is also disposed on the isolation features 230, the gate spacers 247, and the dielectric fins 231. For example, in embodiments, the high-k dielectric layer 282 is disposed directly on the isolation features 230, the gate spacers 247, and the dielectric fins 231. The high-k dielectric layer 282 includes a high-k dielectric material, such as Hf02, HfSiO, HfSi04, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, Zr02, ZrSi02, ZnO, Al20, AlSiO, Al203, TiO, Ti02, LaO, LaSiO, Ta203, Ta205, Y203, SrTi03, BaZrO, BaTi03(BTO), (Ba,Sr)Ti03(BST), hafnium dioxide-aluminum oxide (Hf02-Al203) alloy, other suitable high-k dielectric materials, or combinations thereof. The high-k dielectric layer 282 is formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In some embodiments, the high-k dielectric layer 282 has a thickness of about 1 nm to about 2 nm. If the high-k dielectric layer 282 has too small a thickness, such as less than about 1 nm, then the integrity of the layer cannot be guaranteed in all cases; whereas if the high-k dielectric layer 282 has too large a thickness, such as greater than about 2 nm, then the spacing between the channel layers 215 can be unnecessarily reduced, making the subsequent formation of the electrode layer potentially challenging.

[0029] After the interface layer 280 and the high-k dielectric layer 282 are formed, the gap 277A and 277B are partially filled. Between vertically adjacent channel layers 215, such as between vertically adjacent surfaces of the high-k dielectric layer 282, a spacing is left. The spacing has a dimension hi along the z-direction. The dimension hi is limited by the dimension ho and the thickness of the high-k gate dielectric layer 282. In some embodiments, the dimension hi is about 1 nm to about 10 nm. Further, a spacing is left between the sidewall surfaces of the high-k dielectric layer 282 and the sidewall surfaces of the dielectric fins 231 (having a dimension wi along the y-direction). The dimension wi is limited by the width wo and the thickness of the high-k gate dielectric layer 282. In some embodiments, the dimension wi is about 4 nm to about 13 nm.

[0030] In operation 106, the method 100 Figure 1 forms an electrode layer 284 over the high-k dielectric layer 282. Referring to Figure 4In regions 200A and 200B, an electrode layer 284 is deposited over high-k dielectric layer 282 and around each of channel layers 215. Electrode layer 284 is also disposed over dielectric fins 231 and isolation features 230. In some embodiments, electrode layer 284 includes an n-type work function metal for n-type transistors, such as Ti, Al, Ag, Mn, Zr, TiC, TiAl, TiAlC, TiAlSiC, TiAlN, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. In some embodiments, electrode layer 284 includes a p-type work function metal for p-type transistors, such as TiN, TaN, TaSN, TiSiN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. Electrode layer 284 has a thickness dimension tl. In some embodiments, thickness dimension tl is about 1 nm to about 4 nm. If dimension tl is too small, such as less than about 1 nm, uniformity of electrode layer 284 can be affected in some cases; conversely, if dimension tl is too large, such as greater than about 4 nm, it can be challenging to remove electrode layer 284 from all areas of the gate trench without leaving residue (as described later). Electrode layer 284 can be deposited using ALD, CVD, PVD, or other suitable processes. In some embodiments, electrode layer 284 also includes a bulk metal layer.

[0031] After electrode layer 284 is formed, gaps 277A and 277B are further partially filled (compare FIG. 2B to FIG. 2C). Figure 3 In some embodiments, a separation of dimension h2 is left in the z-direction between vertically adjacent channel layers 215, such as between vertically adjacent surfaces of electrode layer 284. Dimension h2 is limited by dimension hi and the thickness of electrode layer 284. In some embodiments, dimension h2 is less than about 8 nm. In addition, a separation of dimension w2 is also left in the y-direction between sidewall surfaces of electrode layer 284 and sidewall surfaces of dielectric fins 231. Dimension w2 is limited by dimension wi and the thickness of electrode layer 284. In some embodiments, dimension w2 is about 1 nm to about 12 nm.

[0032] In some methods, a masking element is formed in this processing stage to cover one of the regions 200A and 200B, e.g., to cover region 200B. Subsequently, the electrode layer 284 is removed from the exposed region (e.g., region 200A) in preparation for forming another electrode layer having a different electrode material thereon. This approach can encounter challenges when the dimension w2 is very small. In a typical etching operation, there is sufficient spacing between the features for the etching chemistry to diffuse through. Thus, the etching chemistry can diffuse into the spacing between the features relatively quickly, and on a time scale that is much longer than the reaction time scale between the etching chemistry and the target material. In this typical etching operation, the etching reaction starts around all of the exposed surfaces of the target features at about the same time, and also finishes at about the same time. For example, etching the electrode layer 284 in the top portion of the gate trench 275 (such as over the top surface of the topmost channel layer 215) and in the lower portion of the gate trench 275 (such as in the bottom portion of the gap 277B or in the gap 277A) starts and finishes at substantially the same time. In other words, the chemical reaction step is the only rate-limiting step for the entire etching operation. However, as scaling continues and the spacing between the features continues to shrink, the dimensions for the diffusion paths (such as dimension w2) can become too small for this to be true. For example, the etching chemistry can experience a significant increase in resistance from the narrow channels (such as gap 277B) through which they diffuse. Thus, the diffusion rate of the etching chemistry is significantly reduced, sometimes to an unacceptably slow rate. In addition, the slow entry of the etching chemistry into the interior and deeper regions between the features further delays the start of the etching reaction on the target material therein. For example, the portions of the electrode layer 284 that are in the bottom of the gap 277B and in the gap 277A only start after the etching chemistry has removed some of the electrode layer 284 in the top portion of the gate trench 275, thereby widening the diffusion paths and providing access into these interior and deeper regions. In other words, the etching reaction on the target material becomes sequential rather than simultaneous, depending on its location and environment. This can sometimes result in the late removal of residual material at the end of the etching operation, which can adversely affect the threshold voltage and other key device parameters. One approach to address this challenge is to implement a chemistry that cleans the diffusion paths more quickly. Unfortunately, this chemistry sometimes also damages the hardmask layer that serves as the boundary separating the different polarity transistors, resulting in performance degradation and / or failure. As described in detail below, the present invention addresses this challenge using a different approach.

[0033] Turning to Figure 5 , the present invention provides for depositing a dielectric layer 288A into the gate trench 275, including into the gap 277A and the gap 277B (see Figure 4). Thus, all the spaces between vertically adjacent channel layers 215 and between sidewall surfaces of channel layers 215 and sidewall surfaces of dielectric fins 231 are filled with dielectric layer 288A. In some embodiments, dielectric layer 288A comprises a bottom anti-reflective coating (BARC) material. Dielectric layer 288A serves to protect channel layers 215 and various layers formed thereon from subsequent etching reactions. In embodiments, dielectric layer 288A is formed by spin-coating a BARC material over device 200 and filling gate trench 275. In some embodiments, the BARC material is baked (e.g., at a temperature in a range from about 100 °C to about 200 °C) to induce cross-linking within the BARC material. In some embodiments, dielectric layer 288A has a top surface that extends above a top surface of dielectric fins 231 (including layers formed thereon).

[0034] Turning to Figure 6 In step 108 of method 100 Figure 1 ), a top portion of dielectric layer 288A is partially etched (or pulled back) to a height level 302 below a top surface of dielectric cap 234 and above a top surface of electrode layer 284 that wraps over the topmost channel layer 215. In some embodiments, the partial etching operation simultaneously removes electrode layer 284 above height level 302. In other words, the etched electrode layer 284 has a top surface that is flush with height level 302. Thus, the high-k gate dielectric layer 282 around the top of dielectric fin 231 is exposed above height level 302 and above a top surface of etched dielectric layer 288A. The distance between the top surface of the topmost channel layer 215 and height level 302 (which is also the top surface of etched dielectric layer 288A and the top surface of etched electrode layer 284) is distance H2. Distance H2 is less than distance H1. In some embodiments, distance H2 is in a range from about 4 nm to about 50 nm. Removing electrode layer 284 from the top portion of dielectric fin 231 facilitates maintaining a maximum processing window in subsequent etching operations.

[0035] Turning to Figure 7 After the partial etching operation is completed, etched dielectric layer 288A is entirely removed, thereby re-forming gate trench 275, including gap 277A and gap 277B. Thus, high-k dielectric layer 282 has an exposed top portion located on the top and sidewall surfaces of dielectric fin 231, and a covered portion located on the sidewalls of dielectric fin 231 and around channel layer 215. Meanwhile, electrode layer 284 has a first portion located on the sidewall surfaces of high-k gate dielectric layer 282 on the sidewalls of dielectric fin 231, and a second portion of high-k gate dielectric layer 282 around channel layer 215. Gate trench 275 has a top portion with original lateral dimension d1, and a lower portion with a dimension less than d1, e.g., with a dimension equal to (d1-2t1).

[0036] Turning toFigure 8 In method 100 ( Figure 1 In step 110, another electrode layer 285 is deposited over regions 200A and 200B, such that it at least partially fills the gate trench 275. As described above, a high-k dielectric layer 282 covering the top of the dielectric fin 231 (above height level 302) is exposed in the gate trench 275. The electrode layer 285 is formed over and covers the exposed portion of the high-k dielectric layer 282. In other words, the electrode layer 285 directly intersects with the high-k dielectric layer 282 on the top surface of the dielectric fin 231 and on the top segment of the sidewall surface of the dielectric fin 231. Furthermore, the electrode layer 285 completely fills the gaps 277A and 277B. For example, refer back to the reference. Figure 7 There exists a gap 277A with a vertical dimension h2 along the z-direction between vertically adjacent surfaces of electrode layer 284. After deposition of electrode layer 285, gap 277A is completely filled. In other words, the thickness of electrode layer 285 formed within gap 277A matches the vertical dimension h2 of gap 277A. Therefore, no voids remain between vertically adjacent channel layers 215 after the deposition operation. Similarly, before deposition, there exists a gap 277B with a lateral dimension w2 along the y-direction between the sidewall surface of the channel layer and the dielectric fin 231. After deposition of electrode layer 285, gap 277B is completely filled and gap 277B completely disappears. In other words, the lateral dimension of electrode layer 285 formed within gap 277B matches the lateral dimension w2 of gap 277B. Therefore, no voids remain between channel layer 215 and dielectric fin 231 after the deposition operation.

[0037] Furthermore, the deposition of electrode layer 285 also covers other exposed surfaces of regions 200A and 200B. Therefore, electrode layer 285 is also formed on electrode layer 284 covering the sidewall surfaces of dielectric fin 231, and above the exposed top and sidewall surfaces of high-k dielectric layer 282. Because the sidewall surfaces of dielectric fin 231 are partially covered by electrode layer 284 at the start of deposition, the deposited electrode layer 285 has a stepped profile along the sidewall surfaces of dielectric fin 231.

[0038] Electrode layer 285 may comprise any suitable electrode material. In the depicted embodiment, electrode layer 285 comprises the same material as electrode layer 284. Therefore, although the description and figures show electrode layers 284 and 285 as two distinct layers, in some embodiments, a clear material interface may not exist after fabrication. These layers are collectively referred to below as electrode layer 2845. Figure 8As shown, electrode layer 2845 includes several stepped portions, each with a different lateral dimension along the y-direction. For example, the top segment 2845a of electrode layer 2845 has a lateral dimension t2; the middle segment 2845b of electrode layer 2845 has a lateral dimension t3. The top and middle segments of electrode layer 2845 are located on the sidewall surface of dielectric fin 231. Electrode layer 2845 also includes a lower segment 2845c that fills the entire lateral dimension of gate trench 275. Therefore, lower segment 2845c has a lateral dimension d1 (see...). Figure 7 The lateral dimension d1 is greater than the lateral dimension t3, and the lateral dimension t3 is greater than the lateral dimension t2. In some embodiments, the electrode layer 2845 has a portion 290 in the transition region between the middle segment 2845b and the lower segment 2845c. In some embodiments, the portion 290 includes an angled groove formed during the merging of the electrode layer 285 from opposing growth fronts. Furthermore, the gate trench 275 now has: a top segment having a lateral dimension equal to (d1-2t2); and a lower segment having a lateral dimension equal to (d1-2t3). In some embodiments, the top surface of the electrode layer 2845 and the top surface of the topmost channel layer 215 have a distance H3 along the z-direction. In some embodiments, the distance H3 is greater than 3 nm. If the distance is less than 3 nm, the subsequently formed electrode layers with opposite material polarities may adversely affect the threshold voltage of the transistor. Figure 8 As shown in the figure, distance H3 is less than distance H2.

[0039] Transfer to Figure 9A further dielectric layer 288B is deposited into the gate trench 275 and over the electrode layer 2845. In some embodiments, the dielectric layer 288B can be similar to the dielectric layer 288A. For example, the dielectric layer 288B can similarly be a BARC layer. In some embodiments, the dielectric layer 288B can have a material that is the same or similar to the material of the dielectric layer 288A. The dielectric layer 288B covers the entire lower section 2845c of the electrode layer 2845 and also covers at least part of the middle section 2845b of the electrode layer 2845. In some embodiments, the dielectric layer 288B additionally covers at least the sidewall surface of the top section 2845a of the electrode layer 2845. Subsequently, the dielectric layer 288B is partially etched (or pulled back). The partial etching forms a top surface of the etched dielectric layer 288B at a height level 304 between the top surface of the channel layer 215 and the top surface of the dielectric fin 231. For example, the distance between the top surface of the dielectric layer 288B and the top surface of the topmost channel layer 215 has a vertical dimension H2’. The vertical dimension H2’ can be equal to or less than the vertical dimension H2. In some embodiments, the vertical dimension H2’ can be about 4 nm to about 50 nm. In some embodiments, the top section 2845a of the electrode layer 2845 is completely removed during the partial etching of the dielectric layer 288B. As a result, the high-k gate dielectric layer 282 around the top surface and sidewall surface of the dielectric fin 231 is exposed. In addition, the top portion of the gate trench 275 now has a restored lateral dimension d1. After the partial etching, the remaining portion of the dielectric layer 288B is removed, such that the top surface (such as the lower section 2845c) of the electrode layer 2845 is exposed in the gate trench 275. At this processing stage, the lower portion of the gate trench 275 has a lateral dimension equal to (d1-2t3). In some embodiments, the deposition of the dielectric layer 288B together with the partial etching that removes the top section of the electrode layer 2845 maximizes the processing margin for a subsequent etching operation that removes the electrode layer 2845 in selected device regions, thereby improving device characteristics and performance. However, in some embodiments, the deposition of the dielectric layer 288B and the partial etching operation are omitted.

[0040] Turning to Figure 10A hard mask layer 286 is formed over device regions 200A and 200B. For example, hard mask layer 286 can be formed over the entire exposed surface of device 200, such as over the exposed high-k dielectric layer 282 around the top of dielectric fin 231, and on the top and sidewall surfaces of electrode layer 2845. Hard mask layer 286 can have a profile that conforms to the exposed surfaces of device 200. As described above, gate trench 275 has portions of different lateral dimensions; and electrode layer 2845 also has different lateral dimensions in different regions. Thus, hard mask layer 286 has a multi-step profile. For example, hard mask layer 286 includes a top segment 286a on the top and sidewall surfaces of high-k gate dielectric layer 282 around the top of dielectric fin 231 and directly contacting the top and sidewall surfaces of high-k gate dielectric layer 282 around the top of dielectric fin 231. Hard mask layer 286 also includes a middle segment 286b on the top and sidewall surfaces of middle segment 2845b of electrode layer 2845 and directly contacting the top and sidewall surfaces of middle segment 2845b of electrode layer 2845. Hard mask layer 286 also includes a lower segment 286c on the top of lower segment 2845c of electrode layer 2845 and directly contacting the top of lower segment 2845c of electrode layer 2845. In some embodiments, hard mask layer 286 also fills the angled recesses of portions 290. In some embodiments, hard mask layer 286 has a substantially uniform thickness, such as thickness t4. In some embodiments, thickness t4 is about to about If hard mask layer 286 is too thin, such as less than about 10 nm, in some cases it can be less uniform and effective as a hard mask in subsequent steps. If hard mask layer 286 is too thick, such as greater than about 50 nm, the benefits can not justify the processing cost.

[0041] ​​The hardmask layer 286 comprises a material that enables high etch selectivity between the hardmask layer 286 and the electrode layer 2845 during an etch process. For example, the hardmask layer 286 can be selectively etched in an etch process that minimally (to not) etches the electrode layer 2845, which can be a dry etch process or a wet etch process. In some embodiments, the etch selectivity is 100: 1 or greater. In other words, the etch process etches the hardmask layer 286 at a rate that is at least 100 times greater than the rate at which it etches the electrode layer 2845. In some embodiments, the hardmask layer 286 comprises aluminum oxide, silicon nitride, lanthanum oxide, silicon (such as polysilicon), silicon carbon nitride, silicon carbon oxygen nitride, aluminum nitride, aluminum oxynitride, combinations thereof, or other suitable materials. In some embodiments, the hardmask layer 286 can be deposited using ALD, CVD, thermal processes (such as furnace processes), PVD processes, or other suitable processes, and can be deposited at temperatures ranging from about 100 °C to about 400 °C and pressures ranging from about 1 Torr to 100 Torr.

[0042] Turning to Figure 11 A dielectric layer 288C is formed over the region 200B but not over the region 200A (or the opening having the exposed region 200A). The dielectric layer 288C facilitates selective etching of the hardmask layer 286 and the underlying electrode layer 2845. In some embodiments, the dielectric layer 288C can implement a BARC material similar to the dielectric layers 288A or 288B. In some embodiments, the formation of the dielectric layer 288C implements a photolithography process. For example, a BARC layer is deposited over the device 200. An etch resist (or photoresist) layer is then formed over the BARC layer by spin coating. Subsequently, a pre-exposure bake process is performed, followed by an exposure process, a post-exposure bake process, and development of the exposed etch resist layer in a developer. After development, the etch resist layer becomes an etch resist pattern corresponding to the photomask, where the etch resist pattern covers the device region 200B and exposes the element device 200A. The exposure process can be implemented using a photomask or using a maskless lithography process, such as electron beam writing, ion beam writing, or combinations thereof. Using the etch resist pattern as an etch mask, the BARC layer is patterned such that portions thereof are removed from the device region 200A. In embodiments, etching the BARC layer implements an anisotropic etch process, which can better preserve the remaining portion of the BARC layer over the region 200B and can more finely control the boundary between the regions 200A and 200B.

[0043] At this stage of processing, the hardmask layer 286 in the device region 200A is exposed, while the hardmask layer 286 in the device region 200B is covered and protected under the dielectric layer 288C. At step 112 Figure 1), the method continues to remove the hard mask layer 286 and the electrode layer 2845 from the device region 200A as a whole. According to embodiments, the resulting structure is shown in Figure 11 . The region 200B is protected from the etch process by the dielectric layer 288C. As a result of the etch operation, the high-k gate dielectric layer 282 is exposed in the re-gate trench 275 of the device region 200A. In embodiments, the etch operation applies two etch processes, one etch process to remove the hard mask layer 286 and another etch process to remove the electrode layer 2845. In another embodiment, the etch operation applies one etch process to remove the hard mask layer 286 and 2845. The etch operation provides a high etch selectivity with respect to the high-k dielectric layer 282 with respect to the hard mask layer 286 and 2845. In some embodiments, the etch operation exhibits an etch selectivity of about 10 to about 100. In some embodiments, the etch selectivity is greater than or equal to 100. Without such a high etch selectivity, the hard mask layer 286 can be partially etched away, resulting in gate boundary loss and potential further transistor component damage. The etch operation can implement a wet etch, a dry etch, or a combination thereof. Parameters of the etch operation, such as etch chemistry, etch temperature, etch solution concentration, etch time, other suitable wet etch parameters, or a combination thereof, are controlled to ensure complete removal of the hard mask layer 286 and 2845 in the region 200A with minimal (to no) etching of the high-k dielectric layer 282. In some embodiments, the etch process partially etches the dielectric layer 288C.

[0044] After the etch operation is completed, the high-k dielectric layer 282 (including the portions wrapping the top surface and sidewall surface of the dielectric fin 231 and the portions wrapping the channel layer 215 at 360 degrees) is exposed in the device region 200A. In addition, the gap 277A has its longitudinal dimension restored to the longitudinal dimension hi; and the gap 277B has its lateral dimension restored to the lateral dimension wl. In other words, the distance between the high-k dielectric layer 282 on the dielectric fin 231 sidewall surface and the high-k dielectric layer 282 on the channel layer 215 sidewall surface is the lateral dimension wl. Turning to Figure 12 , the dielectric layer 288C and the hard mask layer 286 in the device region 200B are selectively removed in the etch operation. In some embodiments, the dielectric layer 288C is removed using a lift-off or ashing process. In some embodiments, the etch operation can exhibit a high etch selectivity between the dielectric layer 288C and the hard mask layer 286 with respect to the electrode layer 2845. Thus, the etch operation terminates when it reaches the electrode layer 2845. At this stage of processing, the electrode layer 2845 is completely absent from the device region 200A, while present in and exposed in the device region 200B. Similar to above regarding Figure 9As described, the electrode layer 2845 includes an intermediate segment 2845b having a lateral dimension t3 along the y direction, and a segment 2845c having a lateral dimension d1.

[0045] Transfer to Figure 13 In method 100 ( Figure 1 In step 114, an electrode layer 287 is formed over the device 200. For example, the electrode layer 287 is formed over and directly contacts the high-k gate dielectric layer 282 in the device region 200A. In some embodiments, the electrode layer 287 surrounds the high-k dielectric layer 282 surrounding the channel layer 215 in the device region 200A. Furthermore, the electrode layer 287 is formed on and surrounds the top and sidewall surfaces of the dielectric fins 231 in the device region 200A. Simultaneously, the electrode layer 287 covers the top surface of the electrode layer 2845, such as above the top and sidewall surfaces of the middle segment 2845b of the electrode layer 2845, above the top surface of the lower segment 2845c of the electrode layer 2845, and above the high-k dielectric layer 282 surrounding the dielectric fins 231. Therefore, electrode layer 287 surrounds channel layer 215 in device region 200A, but is spaced apart from channel layer 215 in device region 200B. In some embodiments, electrode layer 2845 comprises n-type work function metal and electrode layer 287 comprises p-type work function metal. In some other embodiments, electrode layer 2845 comprises p-type work function metal and electrode layer 287 comprises n-type work function metal. Similar to electrode layer 2845, electrode layer 287 may comprise more than one layer. Electrode layer 287 may be deposited using ALD, CVD, PVD, other suitable processes, or combinations thereof.

[0046] In some embodiments, a capping layer 289 is formed over the electrode layer 287, enclosing the electrode layer 287. The capping layer 289 protects the underlying electrode layer 287 in subsequent processes. In embodiments, the capping layer 289 comprises TiN, TiSiN, TiO2, TiON, TaN, TaSiN, TaO2, TaON, Si, or combinations thereof. In some embodiments, the capping layer 289 may be deposited using ALD, CVD, thermal processes (such as furnace processes), PVD processes, or other suitable processes. In some embodiments, the capping layer 289 is omitted.

[0047] In some embodiments, electrode layer 287 has a thickness t5, and capping layer 289 has a thickness t6. In some embodiments, void 279 (or air gap 279) is closed by different portions of capping layer 289 located within the region of the original void 277B. Voids in this region can serve as very low-k dielectric spacers and are beneficial for achieving lower capacitance and ultimately improving performance. In some embodiments, the sum of dimensions t5 and t6 is designed to be equal to or greater than half of lateral dimension w1, but less than twice the lateral dimension w1. In other words, the following relationship holds:

[0048] 2*w1>=(t5+t6)>=0.5*w1.

[0049] If the above relationship does not hold, no void is formed, and the associated benefits are lost. In some embodiments, the thickness dimension t5 can be approximately Approximately 2 nm. In some embodiments, the thickness t6 is approximately... to Within the range. If the thickness t5 or t6 is too small, the electrode layer 287 (flush with the capping layer 289 formed thereon) may not be in the gap 277B (see Figure 12 The electrodes 287 (with or without the capping layer 289) are merged within the gap 277B, thus not closing the voids. Instead, continuous openings remain in the gap 277B, which are later filled in subsequent steps. Conversely, if the thickness dimension t5 or the thickness t6 is too thick, the electrode layer 287 can be merged within the gap 277B without leaving any voids. In either case, the benefits associated with having voids may be lost. Furthermore, if the thickness t5 is too small, such as less than approximately Or if the thickness t6 is too small, such as less than approximately In some cases, the uniformity and reliability of the electrode layer 287 or the capping layer 289 may be poor. Figure 13 In the depicted embodiment, the cover layer 289 merges between vertically adjacent channel layers 215, thereby completely filling the gap 277A. However, in some other embodiments, the gap 277A may only be partially filled.

[0050] Proceed to step 116 ( Figure 1over the electrode layer 287 (and, if present, over the cap layer 289), a bulk metal layer 350 is formed. The bulk metal layer 350 can be deposited using ALD, CVD, PVD, plating, or other suitable process to fill any remaining portions of the gate trench 275, including any remaining spacing of the gaps 277A between the vertically adjacent channel layers 215. In some embodiments, because the electrode layer 287 (or the cap layer 289 thereon, if present) merges between the dielectric fins 231 and the channel layers 215, the bulk metal layer 350 can not penetrate into the voids 279. Thus, these voids 279 remain in the device region 200A. Meanwhile, no similar voids are present in the device region 200B. In other words, the electrode layer 2845 continuously extends from the sidewall surfaces of the high-k gate dielectric layer 282 that wrap the channel layers 215 to the sidewall surfaces of the high-k gate dielectric layer 282 that are on the sidewalls of the dielectric fins 231, leaving no open spacing. The bulk metal layer 350 includes a suitable conductive material, such as Al, W, and / or Cu. The bulk metal layer 350 can additionally or jointly include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, a CMP process is implemented to planarize the top surface of the device 200 and to expose the top surface of the dielectric fins 231, such as to expose the top surface of the dielectric caps 234.

[0051] Further fabrication steps can be provided to complete the fabrication of the device 200. For example, the method 100 can form source / drain contacts electrically connected to the source / drain features 260( Figure 2B ), form gate vias electrically connected to the bulk metal layer 350, and form multilayer interconnects connecting the transistors and other components in the device 200 to form a complete IC.

[0052] While not intended to be limiting, one or more embodiments of the present application provide numerous benefits for semiconductor devices and their formation. For example, using embodiments of the present application, processing margins for a multiple-patterning gate process are improved for cases where the spacing between the dielectric fins and the channel layers is very tight. Moreover, only one hardmask is implemented. Furthermore, due to the presence of the voids (or air gaps), capacitance is reduced in the gate structure. Overall performance of the device is thereby improved.

[0053] In one example aspect, the disclosure relates to a method. The method includes providing a structure having a substrate and a stack of semiconductor layers located above a surface of the substrate and adjacent to a dielectric feature. Each of the semiconductor layers is vertically spaced apart from each other within the respective stack. A gate dielectric layer is formed that wraps each of the semiconductor layers and the dielectric feature. A first layer of a first gate electrode material is deposited over the gate dielectric layer and over the dielectric feature. The first layer of the first gate electrode material on the dielectric feature is recessed below a top surface of the dielectric feature by a first height. A second layer of the first gate electrode material is deposited over the first layer of the first gate electrode material. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric layer located in the first region while leaving the first gate electrode material in a second region of the substrate. A second gate electrode material is deposited over the exposed portion of the gate dielectric layer and over the remaining portion of the first gate electrode material.

[0054] In some embodiments, the first region is an n-type device region and the second region is a p-type device region. In some embodiments, the formation of the cap layer encloses an air gap between the dielectric feature and the semiconductor layers. In some embodiments, depositing the first layer includes forming opposing surfaces of the first layer on adjacent semiconductor layers. The opposing surfaces are spaced apart from each other by a first distance. Depositing the second layer includes depositing the second layer having a thickness equal to or greater than the first distance. In some embodiments, depositing the first layer includes forming a first side surface of the first layer on the dielectric feature and a second side surface of the first layer on a sidewall of one of the semiconductor layers, wherein the second side surface faces the first side surface. Further, depositing the second layer includes forming the second layer merging between the first side surface and the second side surface. In some embodiments, depositing the second layer includes depositing over the dielectric feature. Further, the method includes, after depositing the second layer, recessing the second layer to expose a sidewall surface of the dielectric feature. In some embodiments, depositing the second gate electrode material includes depositing a first portion of the second gate electrode material wrapping the semiconductor layers in the first region and depositing a second portion of the second gate electrode material over a top surface of the semiconductor layers in the second region.

[0055] In one example aspect, the disclosure relates to a method. The method includes forming a first nanostructure over a substrate in a first region between a first pair of dielectric components; forming a second nanostructure over the substrate in a second region between a second pair of dielectric components; and forming a gate dielectric layer wrapping the first and second nanostructures. The method also includes forming a first layer of a first gate electrode material wrapping the gate dielectric layer on the first and second pairs of dielectric components. The method further includes recessing the first layer to expose top portions of the first and second pairs of dielectric components. In addition, the method includes forming a second layer of the first gate electrode material on the exposed top portions of the first and second pairs of dielectric components and on the first layer. Moreover, the method includes removing the first gate electrode material between the first pair of dielectric components to expose portions of the gate dielectric layer. The method additionally includes depositing a second gate electrode material on the exposed portions of the gate dielectric layer between the first pair of dielectric components and on remaining portions of the first gate electrode material between the second pair of dielectric components.

[0056] In some embodiments, the first region is an n-type device region and the second region is a p-type device region. In some embodiments, the first layer includes a first portion over the first and second nanostructures and a second portion on top and side surfaces of the first and second pairs of dielectric components. In addition, recessing the first layer includes forming a protective layer covering the first portion of the first layer. Recessing the first layer also includes recessing the protective layer and the second portion of the first layer without reaching top surfaces of the second portion of the first layer. Recessing the first layer additionally includes removing the recessed protective layer. In some embodiments, forming the first layer includes forming openings between vertically adjacent nanostructures. In addition, forming the second layer includes filling the openings with the first gate electrode material. In some embodiments, removing the first gate electrode material between the first pair of dielectric components includes forming a mask element covering the second region and having openings exposing the first region. In addition, removing the first gate electrode material between the first pair of dielectric components also includes removing the first gate electrode material through the openings using a first etching condition; and removing the mask element using a second etching condition. The first gate electrode material has a first etching rate under the first etching condition and a second etching rate under the second etching condition. The mask element has a third etching rate under the first etching condition and a fourth etching rate under the second etching condition. A ratio of the first etching rate to the third etching rate is greater than 10: 1 and a ratio of the third etching rate to the fourth etching rate is less than 1: 10. In some embodiments, the method further includes forming a capping layer wrapping the second gate electrode material and forming a bulk metal layer on the capping layer. Forming the capping layer forms a plurality of voids among portions of the capping layer. Forming the bulk metal layer does not fill the plurality of voids.

[0057] In one example aspect, the disclosure relates to a device. The device includes a semiconductor substrate having a substrate surface, a semiconductor layer located above the semiconductor substrate and separated from the semiconductor substrate along a first direction perpendicular to the substrate surface. The device also includes a dielectric feature adjacent to the semiconductor layer extending from the substrate surface along the first direction. The dielectric feature has a first side facing the semiconductor layer and a second side opposite the first side. The device further includes a gate dielectric layer having a first portion wrapping the semiconductor layer and a second portion located on the first side of the dielectric feature. In addition, the device includes a first gate electrode layer and a second gate electrode layer. The first gate electrode layer includes a first segment wrapping the first portion of the gate dielectric layer and a second segment extending from the first segment to a sidewall surface of the second portion of the gate dielectric layer. In addition, the second segment has a top surface higher than a top surface of the first segment of the first gate electrode layer and lower than a top surface of the dielectric feature. The second gate electrode layer is located on the top surface of the first segment of the first gate electrode layer, on the top surface and the sidewall surface of the second segment of the first gate electrode layer, and on the first side of the dielectric feature.

[0058] In some embodiments, the semiconductor layer is a first semiconductor layer, and the device further includes a second semiconductor layer located between the first semiconductor layer and the semiconductor substrate. The gate dielectric layer has a third portion wrapping the second semiconductor layer. In addition, a sidewall surface of the first portion of the gate dielectric layer is laterally separated from a sidewall surface of the second portion of the gate dielectric layer by a first distance. A bottom surface of the first portion of the gate dielectric layer is vertically spaced apart from a top surface of the third portion of the gate dielectric layer by a second distance. The first distance is greater than the second distance. In some embodiments, the first distance is about 1 nm to about 3 nm greater than the second distance. In some embodiments, a distance between a pair of source / drain features is a third distance. The third distance is about 3 nm to about 5 nm greater than the second distance. In some embodiments, the first gate electrode layer includes an interlayer portion that completely fills a gap between the first portion and the third portion of the gate dielectric layer. In some embodiments, the semiconductor layer is a first semiconductor layer. The device further includes a third semiconductor layer and a fourth semiconductor layer, the first semiconductor layer and the third semiconductor layer being located on two opposite sides of the dielectric feature, and the third semiconductor layer and the fourth semiconductor layer being located on the same side of the dielectric feature. A second side of the dielectric feature faces the third semiconductor layer and the fourth semiconductor layer. The second gate electrode layer includes a first segment wrapping the third semiconductor layer, a second segment wrapping the fourth semiconductor layer, and a third segment located on the second side of the dielectric feature. The first segment, the second segment, and the third segment of the second gate electrode layer enclose a void. In some embodiments, the semiconductor layer is located in a p-type device region. In addition, the device further includes another semiconductor layer located in an n-type device region and a cap layer located above the second gate electrode layer in the p-type device region and the n-type device region. In addition, the second gate electrode layer wraps the another semiconductor layer. The cap layer encloses a plurality of voids in the n-type device region but does not enclose the plurality of voids in the p-type device region.

[0059] The foregoing summary of some embodiments has been presented with sufficient particularity by way of one or more examples to enable a person skilled in the art to make or use the application. Other embodiments can be apparent to those skilled in the art from consideration of the specification and can be practiced without departing from the spirit or scope of the application. Their various concepts, embodiments and examples disclosed herein can be more fully appreciated as they can be implemented in various forms. Therefore, the examples are not to be understood as being limited to the specific examples described and should be taken as exemplary.

Claims

1. A method of forming a semiconductor device, comprising: providing a structure having a substrate and a stack of semiconductor layers located above a surface of the substrate and adjacent to dielectric features, each of the semiconductor layers being vertically spaced apart from one another within a respective stack; forming a gate dielectric layer wrapping each of the semiconductor layers and the dielectric features; depositing a first layer of a first gate electrode material over the gate dielectric layer and over the dielectric features; recessing the first layer of the first gate electrode material on the dielectric features to a first height below a top surface of the dielectric features; depositing a second layer of the first gate electrode material over the first layer of the first gate electrode material; removing the first gate electrode material in a first region of the substrate to expose portions of the gate dielectric layer located in the first region without removing the first gate electrode material in a second region of the substrate; and depositing a second gate electrode material over the exposed portions of the gate dielectric layer and on remaining portions of the first gate electrode material. The first region is an n-type device region and the second region is a p-type device region.

2. The method of claim 1, wherein, forming a cap layer over the second gate electrode material, 3. The method of claim 1, further comprising: wherein the forming of the cap layer encloses an air gap between the dielectric features and the semiconductor layers. depositing the first layer includes forming opposing surfaces of the first layer on adjacent semiconductor layers, the opposing surfaces being spaced apart from one another by a first distance, and 4. The method of claim 1, wherein, wherein depositing the second layer includes depositing a second layer having a thickness equal to or greater than the first distance. depositing the first layer includes forming a first side of the first layer on the dielectric features and a second side of the first layer on a sidewall of one of the semiconductor layers, the second side facing the first side, and 5. The method of claim 1, wherein, wherein depositing the second layer includes forming the second layer merging between the first side and the second side. depositing the second layer includes depositing over the dielectric features, the method further comprising, after depositing the second layer, recessing the second layer to expose sidewall surfaces of the dielectric features.

6. The method of claim 1, wherein, depositing the second gate electrode material includes depositing a first portion of the second gate electrode material wrapping the semiconductor layers in the first region and depositing a second portion of the second gate electrode material over a top surface of the semiconductor layers in the second region.

7. The method of claim 1, wherein, 8. A method of forming a semiconductor device, comprising: forming a first nanostructure over a substrate in a first region between a first pair of dielectric features; forming a second nanostructure over the substrate in a second region between a second pair of dielectric features; forming a gate dielectric layer wrapping the first and second nanostructures; forming a first layer of a first gate electrode material wrapping the gate dielectric layer on the first and second pairs of dielectric features; recessing the first layer to expose tops of the first and second pairs of dielectric features; forming a second layer of the first gate electrode material on the exposed tops of the first and second pairs of dielectric features and on the first layer; ​ removing the first gate electrode material between the first pair of dielectric features to expose portions of the gate dielectric layer; and depositing a second gate electrode material on the exposed portions of the gate dielectric layer between the first pair of dielectric features and on remaining portions of the first gate electrode material between the second pair of dielectric features.

9. The method of claim 8, wherein, The first region is an n-type device region and the second region is a p-type device region.

10. The method of claim 8, wherein, The first layer includes a first portion over the first and second nanostructures and a second portion on top and side surfaces of the first and second pairs of dielectric features, and wherein recessing the first layer includes: forming a protective layer covering the first portion of the first layer; recessing the protective layer and the second portion of the first layer without reaching top surfaces of the second portion of the first layer; removing the recessed protective layer.

11. The method of claim 8, wherein, forming the first layer includes forming openings between vertically adjacent nanostructures, and wherein forming the second layer includes filling the openings with the first gate electrode material.

12. The method of claim 8, wherein, removing the first gate electrode material between the first pair of dielectric features includes: forming a mask element covering the second region and having openings exposing the first region; removing the first gate electrode material through the openings using a first etching condition; and removing the mask element using a second etching condition, wherein the first gate electrode material has a first etching rate under the first etching condition and a second etching rate under the second etching condition, the mask element has a third etching rate under the first etching condition and a fourth etching rate under the second etching condition, and wherein a ratio of the first etching rate to the third etching rate is greater than 10: 1 and a ratio of the third etching rate to the fourth etching rate is less than 1:

10.

13. The method of claim 8, further comprising forming a capping layer wrapping the second gate electrode material, and forming a bulk metal layer on the capping layer, wherein forming the capping layer forms a plurality of voids among portions of the capping layer, and wherein forming the bulk metal layer does not fill the plurality of voids.

14. A semiconductor device, comprising: a semiconductor substrate having a substrate surface; a semiconductor layer over the semiconductor substrate and separated from the semiconductor substrate along a first direction perpendicular to the substrate surface; a dielectric feature adjacent to the semiconductor layer extending from the substrate surface along the first direction, the dielectric feature having a first side facing the semiconductor layer and a second side opposite the first side; a gate dielectric layer having a first portion wrapping the semiconductor layer and a second portion on the first side of the dielectric feature; a first gate electrode layer, wherein the first gate electrode layer includes a first segment wrapping the first portion of the gate dielectric layer, and a second segment extending from the first segment to a sidewall surface of the second portion of the gate dielectric layer, the second segment having a top surface higher than a top surface of the first segment of the first gate electrode layer and lower than a top surface of the dielectric feature; and a second gate electrode layer on a top surface of the first segment of the first gate electrode layer, on a top surface and a sidewall surface of the second segment of the first gate electrode layer, and on the first side surface of the dielectric feature.

15. The semiconductor device of claim 14, wherein, the semiconductor layer is a first semiconductor layer, the device further comprising a second semiconductor layer between the first semiconductor layer and the semiconductor substrate, wherein the gate dielectric layer has a third portion wrapping the second semiconductor layer, wherein a sidewall surface of the first portion of the gate dielectric layer is laterally separated from a sidewall surface of the second portion of the gate dielectric layer by a first distance, a bottom surface of the first portion of the gate dielectric layer is vertically spaced from a top surface of the third portion of the gate dielectric layer by a second distance, and the first distance is greater than the second distance.

16. The semiconductor device of claim 15, wherein, the first distance is about 1 nm to about 3 nm greater than the second distance, wherein the about indicates within + / - 10% of the described numerical value.

17. The semiconductor device of claim 15, further comprising: a pair of source / drain features on either end of the semiconductor layer, wherein a distance between the pair of source / drain features is a third distance, and wherein the third distance is about 3 nm to about 5 nm greater than the second distance, wherein the about indicates within + / - 10% of the described numerical value.

18. The semiconductor device of claim 15, wherein, the first gate electrode layer includes an interlayer portion that completely fills a gap between the first portion and the third portion of the gate dielectric layer.

19. The semiconductor device of claim 14, wherein, the semiconductor layer is a first semiconductor layer, the semiconductor device further comprising a third semiconductor layer and a fourth semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer are on two opposite sides of the dielectric feature, the third semiconductor layer and the fourth semiconductor layer are on the same side of the dielectric feature, and the second side surface of the dielectric feature faces the third semiconductor layer and the fourth semiconductor layer, wherein the second gate electrode layer includes a first segment wrapping the third semiconductor layer, a second segment wrapping the fourth semiconductor layer, and a third segment on the second side surface of the dielectric feature, wherein the first segment, the second segment, and the third segment of the second gate electrode layer enclose a void.

20. The semiconductor device of claim 14, wherein, the semiconductor layer is in a p-type device region, the semiconductor device further comprising another semiconductor layer in an n-type device region and a cap layer over the second gate electrode layer in the p-type device region and the n-type device region, wherein the second gate electrode layer wraps the another semiconductor layer, and wherein the cap layer encloses a plurality of voids in the n-type device region but does not enclose a plurality of voids in the p-type device region.

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