Semiconductor device and method of manufacturing semiconductor device

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of this embodiment includes a wiring substrate comprising: a plurality of electrodes disposed on a first surface; a first resin layer disposed on the first surface around the plurality of electrodes; and a second resin layer disposed on the first resin layer. A first semiconductor chip is connected to the first electrode among the plurality of electrodes. A second semiconductor chip is disposed above the first semiconductor chip, is larger than the first semiconductor chip, and is connected to the second electrode among the plurality of electrodes via metal wires. A third resin layer is disposed between the first semiconductor chip and the second semiconductor chip, and between the second resin layer and the second semiconductor chip, covering the first semiconductor chip.

Description

[0001] [Cross-reference to related applications]

[0002] This application is based on and asserts the priority interest of prior art Japanese Patent Application No. 2020-138900, filed on August 19, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0004] A System-in-Package (SiP) project is underway, which encapsulates multiple semiconductor chips on a wiring substrate. During the stacking of multiple semiconductor chips, other chips are bonded to the lower semiconductor chip via a Die Attachment Film (DAF). The DAF is then molten and embedded between the lower and upper semiconductor chips.

[0005] However, molten DAF can sometimes seep out or recede from the edge of the semiconductor chip. DAF seepage can cause poor wire bonding connections on the pads adjacent to the semiconductor chip. Furthermore, DAF seepage and loss can cause the upper semiconductor chip to tilt, warp, or crack, leading to reduced reliability. Summary of the Invention

[0006] One embodiment provides a semiconductor device and a method for manufacturing the semiconductor device capable of suppressing resin seepage and shrinkage between multiple stacked semiconductor chips.

[0007] The semiconductor device of the embodiment includes: a wiring substrate comprising a plurality of electrodes, a first resin layer and a second resin layer, the plurality of electrodes being disposed on a first surface, the first resin layer being disposed on the first surface surrounding the plurality of electrodes, and the second resin layer being disposed on the first resin layer; a first semiconductor chip connected to the first electrode among the plurality of electrodes; a second semiconductor chip disposed above the first semiconductor chip, being larger than the first semiconductor chip, and having a third electrode formed thereon; a metal wire connecting the second electrode among the plurality of electrodes and the plurality of third electrodes; and a third resin layer disposed between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, covering the first semiconductor chip.

[0008] According to the aforementioned configuration, a semiconductor device and a method for manufacturing the semiconductor device can be provided that can suppress resin exudation and backflow between multiple stacked semiconductor chips. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic top view showing an example of the configuration of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a cross-sectional view showing an example of the configuration of a semiconductor element mounted on a wiring substrate.

[0012] Figure 4 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 5 It means succession Figure 4 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0014] Figure 6 It means succession Figure 5 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0015] Figure 7 It means succession Figure 6 A cross-sectional view of an example of a method for manufacturing a semiconductor device.

[0016] Figure 8 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the second embodiment.

[0017] Figure 9 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the third embodiment.

[0018] Figure 10 This is a top view showing an example of the configuration of the semiconductor device according to the fourth embodiment.

[0019] Figure 11 This is a top view showing an example of the configuration of the semiconductor device according to the fifth embodiment.

[0020] Figure 12 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the sixth embodiment.

[0021] Figure 13 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the seventh embodiment.

[0022] Figure 14 This is a cross-sectional view showing an example of the configuration of the semiconductor device according to the eighth embodiment. Detailed Implementation

[0023] The embodiments are described with reference to the accompanying drawings. The invention is not limited to the embodiments described below. In the embodiments, "upper direction" or "lower direction" refers to a relative direction, with "upper direction" defined as a direction perpendicular to the surface of the wiring substrate having the semiconductor chip. Therefore, the terms "upper direction" or "lower direction" sometimes differ from the upper or lower direction based on the direction of gravitational acceleration. In this specification and the accompanying drawings, the same reference numerals are used to denote the same elements as those described in the drawings, and detailed descriptions thereof are appropriately omitted.

[0024] The semiconductor device of this embodiment includes a wiring substrate comprising: a plurality of electrodes disposed on a first surface; a first resin layer disposed on the first surface around the plurality of electrodes; and a second resin layer disposed on the first resin layer. A first semiconductor chip is connected to the first electrode among the plurality of electrodes. A second semiconductor chip is disposed above the first semiconductor chip, is larger than the first semiconductor chip, and is connected to the second electrode among the plurality of electrodes via metal wires. A third resin layer is disposed between the first semiconductor chip and the second semiconductor chip, and between the second resin layer and the second semiconductor chip, covering the first semiconductor chip.

[0025] (First Embodiment)

[0026] Figure 1 This is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 of this embodiment is, for example, a NAND (Not AND) type flash memory. The semiconductor device 1 includes a wiring substrate 10, a resin layer (NCP (Non-Conductive Paste)) 20, a controller chip 30, a resin layer (DAF (Die Attach Film)) 40, a NAND type memory chip (hereinafter referred to as a memory chip) 50, an adhesive layer 60, metal wires 70, sealing resin 80, and metal bumps 90. Furthermore, this embodiment is not limited to NAND type flash memory and can be applied to all semiconductor packages containing multiple stacked semiconductor chips.

[0027] The wiring substrate 10 includes: an insulating substrate 11, wiring 12, through-holes 13, electrodes 14 and 15, and solder resists SR1 and SR2. The insulating substrate 11 is made of an insulating material such as glass epoxy resin. The wiring 12 is disposed on the front, back, or inside of the insulating substrate 11 and is electrically connected to the electrodes 14 and 15. The through-holes 13 are provided to penetrate the insulating substrate 11, enabling electrical connection between the wiring 12.

[0028] Electrodes 14 and 15 are disposed on the front side F1 of the wiring substrate 10. Electrode 14, serving as the first electrode, is connected to the metal bump 31 of the controller chip 30 on the front side F1 of the wiring substrate 10. Electrode 15, serving as the second electrode, is connected to the solder pad 51 of the memory chip 50 on the front side F1 of the wiring substrate 10 via a metal wire 70. The wiring 12, electrodes 14 and 15 are made of low-resistance metals such as copper. Although not shown, metal bumps may also be disposed on the back side F2 of the wiring substrate 10 using nickel, solder, or the like. The metal bumps are electrically connected to electrodes 14 and 15 via the wiring 12. Alternatively, the wiring 12 and the insulating substrate 11 may be a multilayer wiring structure with three or more layers.

[0029] Solder resist SR1, serving as the first resin layer, is disposed around electrodes 14 and 15 on the front side F1 of the wiring substrate 10. Solder resist SR1 can be disposed on the front side F1 excluding electrodes 14 and 15, and also on the entire back side F2. Furthermore, solder resist SR1 may cover a portion of electrodes 14 and 15, but not the connection areas of metal bumps 31 or metal lines 70, thus exposing the connection areas of metal bumps 31 or metal lines 70. Additionally, solder resist SR1 exposes a portion of the connection area of ​​wiring 12 on the back side F2. Metal bumps 90 are provided in the exposed connection area of ​​wiring 12. However, in this embodiment, solder resist SR1 is only one example of the first resin layer, and the first resin layer is not limited to this.

[0030] Solder resist SR2, serving as the second resin layer, is disposed on top of solder resist SR1 and, when viewed from above the front surface F1 of the wiring substrate 10, surrounds the controller chip 30. Solder resist SR2 is disposed inside solder resist SR1 in this top-view view, and solder resist SR1 and SR2 are stacked as two layers. Therefore, a step ST exists between solder resist SR1 and SR2 at the end of solder resist SR2. Solder resist SR1 and SR2 can be made of the same material or different materials. Furthermore, the height of solder resist SR2 can be lower than, the same as, or higher than the upper surface of the controller chip 30. In this embodiment, two layers of solder resist SR1 and SR2 are disposed, but three or more layers of solder resist can also be disposed. Furthermore, in this embodiment, solder resist SR2 is only one example of the second resin layer, and the second resin layer is not limited to this.

[0031] On the side of the controller chip 30, which serves as the first semiconductor chip, facing the wiring substrate 10, metal bumps 31 are provided. The metal bumps 31 are connected to the electrodes 14 of the wiring substrate 10. The controller chip 30 is connected to the wiring substrate 10 in a flip-chip manner. The substrate (not shown) of the controller chip 30 is thinned, and semiconductor elements (not shown) are provided on the side where the metal bumps 31 are provided. The semiconductor elements are electrically connected to the wiring 12 of the wiring substrate 10 via the metal bumps 31.

[0032] A resin layer (NCP) 20 is filled between the wiring substrate 10 and the controller chip 30, covering and protecting the connection portion between the electrode 14 and the metal bump 31. Furthermore, the resin layer 20 also fills the space between the controller chip 30 and the solder resists SR1 and SR2, and the resin layer 40, protecting the controller chip 30. The resin layer 20 is in contact with the inner surfaces of the solder resists SR1 and SR2. The resin layer 20 can also reach the upper surface of the solder resist SR2. The resin layer 20 is a non-conductive resin material (NCP), such as a paste made by mixing epoxy resin, acrylic resin, and silicon dioxide.

[0033] A resin layer 40 is disposed between the controller chip 30 and the memory chip 50, and between the solder resist SR2 and the memory chip 50, covering the controller chip 30. The resin layer 40 may be made of an insulating resin such as a die bond film.

[0034] If the thickness of the solder resist SR2 is increased, and the upper surface of the solder resist SR2 is raised, then the height of the upper surface of the solder resist SR2 will be the same as or higher than the upper surface of the controller chip 30.

[0035] The memory chip 50, serving as the second semiconductor chip, is positioned above the controller chip 30. The memory chip 50 is bonded to the controller chip 30 and solder resist SR2 via a resin layer (adhesive layer) 40. The memory chip 50 has, for example, a three-dimensional memory cell array with multiple memory cells arranged in three dimensions on its front side. The resin layer 40 is pre-attached to the back side of the memory chip 50. During the die bonding step, the memory chip 50 is pressed onto the wiring substrate 10 and heated. Thus, the resin layer 40 embeds the controller chip 30 and the resin layer 20, and the memory chip 50 is bonded to the controller chip 30. Viewed from above the front side F1, the memory chip 50 is larger than the controller chip 30. Therefore, the resin layer 40 attached to the back side of the memory chip 50 is also larger than the controller chip 30, allowing it to cover the entire front side of the controller chip 30 during the die bonding step.

[0036] Multiple memory chips 50 can also be stacked on the controller chip 30. Figure 1 In the middle layer, four memory chips 50 are stacked, but the number of stacked memory chips 50 is not particularly limited. An adhesive layer 60 is pre-attached to the back of the multiple memory chips 50. The memory chips 50 are stacked on top of the lower memory chips 50, and the two layers are bonded together using the adhesive layer 60.

[0037] Metal wires 70 electrically connect the pads 51 of the memory chip 50 to any electrode 15 of the wiring substrate 10. Thus, the semiconductor element of the memory chip 50 is connected to the wiring 12 of the wiring substrate 10 via the metal wires 70. Sealing resin 80 covers and protects the overall structure on the wiring substrate 10, including the controller chip 30, the memory chip 50, and the metal wires 70.

[0038] Metal bump 90 is electrically connected to a portion of wiring 12 on the back side F2. Metal bump 90 is made of a low-resistance metal, such as solder.

[0039] Figure 2 This is a schematic top view showing an example of the configuration of the semiconductor device 1 according to the first embodiment. Figure 2 This shows the planar layout of solder resist SR1, SR2, controller chip 30, memory chip 50, etc., as viewed from above the front side F1 of the wiring substrate 10.

[0040] The solder resist SR1 generally covers the entire front side F1 of the wiring substrate 10, excluding the electrodes (pads) 14 and 15. The solder resist SR1 is not located in the formation areas of the electrodes 14 and 15, and has openings OP1 and OP2. Figure 2 The opening OP3 represents the opening portion of solder resist SR2, with solder resist SR1 exposed inside the opening OP3. Within the area of ​​opening OP3, the opening OP1 of solder resist SR1 is almost entirely hidden beneath resin layer 20. Furthermore, in... Figure 2 Not shown in the diagram, in opening OP1, solder resist SR1 exposes electrode 14. In opening OP2, solder resist SR1 exposes electrode 15.

[0041] Solder resist SR2 is placed on top of solder resist SR1, positioned within the area of ​​solder resist SR1 in a manner that does not block the openings OP1 and OP2 of solder resist SR1 when viewed from above the front side F1. Solder resist SR1 is disposed below solder resist SR2, and solder resist SR1 and SR2 are two overlapping layers.

[0042] Viewed from above the front of F1, solder resist SR2 is disposed around the controller chip 30, surrounding it. Therefore, solder resist SR2 is formed into a generally quadrilateral frame shape with a hole (opening OP3) in the center. Solder resist SR2 can also be a generally polygonal frame shape, a generally circular ring shape, or a generally elliptical ring shape. That is, solder resist SR2 has an outer edge E2_out and an inner edge E2_in, the shapes of which can be any of the following: generally quadrilateral, generally polygonal, generally circular, or generally elliptical. Furthermore, the shapes of the outer edge E2_out and the inner edge E2_in can be similar to each other or different shapes. Solder resist SR2 is disposed on solder resist SR1; therefore, in the aforementioned top view, the outer edge E2_out and the inner edge E2_in overlap the solder resist SR1.

[0043] The outer edge E2_out of the solder resist SR2 is located outside the outer edge E30 of the controller chip 30 and the outer edge E50 of the memory chip 50, and does not overlap with the formation area (opening OP2) of the electrode 15. Therefore, the outer edge E2_out of the solder resist SR2 is located between the opening OP2 of the solder resist SR1 and the outer edge E50 of the memory chip 50.

[0044] Furthermore, the inner edge E2_in of the solder resist SR2 is located inside the outer edge E50 of the memory chip 50 and outside the outer edge E30 of the controller chip 30. Moreover, the inner edge E2_in of the solder resist SR2 (the end edge of the opening OP3) does not overlap with the formation area of ​​the electrode 14 (opening OP1). Therefore, the inner edge E2_in of the solder resist SR2 (the end edge of the opening OP3) is located between the opening OP1 of the solder resist SR1 or the outer edge E30 of the controller chip 30 and the outer edge E50 of the memory chip 50.

[0045] Viewed from above the front of F1, the controller chip 30 is connected to the electrode 14 in a flip-chip configuration. Therefore, the area overlapping the electrode 14 (opening OP1) is positioned inside the opening OP3. In other words, in this top view, the outer edge E30 of the controller chip 30 is located inside the opening OP3. Alternatively, the outer edge E30 of the controller chip 30 can be located inside or outside the opening OP1. That is, the controller chip 30 can be smaller than the opening OP1 of the solder resist SR1 and located inside it, or it can be larger than the opening OP1.

[0046] The memory chip 50 is larger than the controller chip 30. In the top view, the outer edge E50 of the memory chip 50 is located outside the outer edge E30 of the controller chip 30. Furthermore, in order to connect the solder pad 51 of the memory chip 50 to the electrode 15 via the metal wire 70, the outer edge E50 of the memory chip 50 does not reach the opening OP2. Therefore, the outer edge E50 of the memory chip 50 is located between the formation area of ​​the electrode 15 (opening OP2) and the controller chip 30. When viewed from above the front side F1, the memory chip 50 overlaps the controller chip 30, the opening OP1, and the solder resist SR2, and is positioned inside the outer edge E2_out of the solder resist SR2.

[0047] Figure 2 The memory chip 50 shown represents the outer edge E50 of the memory chip 50 in the next lower layer. The controller chip 30 and solder resist SR2 are directly coated with it. Figure 1 If the resin layer 40 does not bleed or shrink, its size is approximately the same as that of the memory chip 50. Therefore, when viewed from above the front side F1, the outer edge E50 of the memory chip 50 roughly coincides with and overlaps with the outer edge of the resin layer 40. In this case, when viewed from above the front side F1, the outer edge E2_out of the solder resist SR2 is located on the outer side of the outer edge of the resin layer 40.

[0048] A resin layer (NCP) 20 covers a protective electrode 14 between the controller chip 30 and the wiring substrate 10. When viewed from above the front side F1, the outer edge E20 of the resin layer 20 overlaps with either the solder resist SR1 or SR2.

[0049] like Figure 1 As shown, the resin layer (DAF) 40 is attached to the back of the memory chip 50. When the memory chip 50 is deposited on the controller chip 30, the resin layer 40 covers the entire controller chip 30 and the resin layer 20.

[0050] Here, as Figure 1 As shown, multiple solder resists SR1 and SR2 are selectively formed to a thicker thickness around the controller chip 30. Therefore, when stacking the memory chip 50, the multiple solder resists SR1 and SR2 are substantially thicker below the resin layer 40. Consequently, the thickness T40 of the resin layer 40 between the memory chip 50 and the solder resist SR2 becomes thinner.

[0051] If solder resist SR2 is not used, the thickness of the resin layer 40 between the memory chip 50 and the solder resist SR1 will increase. In this case, the thickness of the resin layer 40 pre-attached to the memory chip 50 needs to be increased, thus increasing the possibility that the resin layer 40 may seep out or recede from the outer edge E50 of the memory chip 50 when the memory chip 50 is attached to the controller chip 30. When the resin layer 40 seeps out and reaches the electrode 15, it may result in failure to wire bond to the electrode 15. In addition, the memory chip 50 becomes more prone to tilting relative to the front surface F1 of the wiring substrate 10 or the upper surface of the controller chip 30. This can cause warping or cracking of the memory chip 50, reducing the reliability of the semiconductor device 1.

[0052] Furthermore, in order to thin the resin layer 40, if only the solder resist SR1 is thickened, the thickness of the solder resist on the front side F1 of the wiring substrate 10, excluding openings OP1 and OP2, will be increased overall. In this case, the solder resist SR1 at the outer edge of opening OP2 will be thickened, potentially causing the metal wire 70 to come into contact with the solder resist SR1. Furthermore, if the solder resist SR1 is thickened overall, as... Figure 3 As shown, the thickness Tsr1 of the solder resist SR1 under other semiconductor components (resistors, capacitors, etc.) besides controller chip 30 and memory chip 50 also increases. Figure 3 This is a cross-sectional view showing an example of a semiconductor element SE mounted on a wiring substrate 10. The semiconductor element SE, along with the controller chip 30 and the memory chip 50, are mounted together on the same wiring substrate 10. In this case, when the semiconductor element SE is mounted on the wiring substrate 10, the solder resist SR1 interferes with the connection of the semiconductor element SE, making it difficult to connect the semiconductor element SE to the wiring substrate 10.

[0053] Furthermore, due to the different thicknesses of the solder resist SR1 on the front side F1 and the solder resist (not shown) on the back side F2 of the wiring substrate 10, the stress imbalance applied to the wiring substrate 10 may cause the wiring substrate 10 to warp.

[0054] In contrast, in the semiconductor device 1 of this embodiment, solder resist SR2 and solder resist SR1 are separate, with SR2 deposited on top of solder resist SR1. Therefore, solder resist SR2 is selectively disposed around the controller chip 30 to which the memory chip 50 is attached, and not on any other solder resist SR1. That is, solder resist SR2 is only disposed in the area where the resin layer 40 is disposed.

[0055] This allows the thickness of the resin layer 40 to be correspondingly thinner than the thickness of the solder resist SR2. By thinning the resin layer 40, it is less likely to seep out from the outer edge E50 of the memory chip 50 or shrink back when the memory chip 50 is attached to the controller chip 30. Therefore, it does not hinder wire bonding of the counter electrode 15. Furthermore, the memory chip 50 is less likely to tilt relative to the front surface F1 of the wiring substrate 10 or the upper surface of the controller chip 30, becoming approximately flat. This helps improve the reliability of the semiconductor device 1. Moreover, the embeddability of the resin layer 40 is improved, suppressing voids remaining between the resin layer 40 and the solder resist SR2, the resin layer 20, and the controller chip 30.

[0056] Furthermore, solder resist SR2 is located within the range of solder resist SR1, and has opening OP2. Figure 1 The step difference ST. Therefore, the solder resists SR1 and SR2 gradually thicken in a stepped manner at the outer edge of the opening OP2, which can suppress the metal line 70 from interfering with the solder resists SR1 and SR2.

[0057] Furthermore, solder resist SR2 is disposed around the controller chip 30, but not on the solder resist SR1. Consequently, the thickness of the solder resist SR1 itself ( Figure 3 The Tsr1 layer is not thick enough to suppress interference between the semiconductor element SE and the solder resist SR1 when other semiconductor elements SE are mounted on the wiring substrate 10.

[0058] Furthermore, the solder resist SR2 only needs to be applied within the minimum necessary range on the front side F1 of the wiring substrate 10. Therefore, the thickness difference between the solder resist SR1 on the front side F1 and the solder resist on the back side F2 is not significant, which can suppress the warping of the wiring substrate 10.

[0059] Next, the manufacturing method of the semiconductor device 1 in this embodiment will be described.

[0060] Figures 4-7 This is a cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0061] First, such as Figure 4 As shown, the material (NCP) of the resin layer 20 is supplied to the mounting position of the controller chip 30 on the wiring substrate 10. The wiring substrate 10 includes an insulating substrate 11, wiring 12, electrodes 14 and 15, and solder resists SR1 and SR2. Wiring 12 is disposed on the front side and inside of the insulating substrate 11. Electrodes 14 and 15 are exposed on the front side F1 from the insulating substrate 11 and the solder resists SR1 and SR2.

[0062] Solder resist SR1 is disposed around electrodes 14 and 15, and openings OP1 and OP2 are formed in the areas of electrodes 14 and 15. Solder resist SR2 is disposed on top of solder resist SR1 within the area of ​​solder resist SR1. Solder resist SR2 is disposed in a manner that surrounds the mounting position of controller chip 30. Therefore, solder resist SR1 and SR2 have a step ST at the ends of openings OP1 and OP2. That is, the inner and outer edges of solder resist SR1 and SR2 have a step ST. As a result, the paste-like material of resin layer 20 is less likely to overflow from opening OP1. In addition, the metal wire 70 bonded to electrode 15 is less likely to interfere with solder resist SR1 and SR2.

[0063] The resin layer 20 is made of a non-conductive paste-like resin material (NCP). When the controller chip 30 is flip-chip connected to the wiring substrate 10, the resin layer 20 fills the space between the controller chip 30 and the wiring substrate 10, connecting them. Furthermore, the resin layer 20 can be made of not only NCP, but also NCF (Non-Conductive Film) or CUF (Capillary Under Fill).

[0064] Secondly, such as Figure 5 As shown, the crimping device 100 adsorbs the controller chip 30 through the FAB (Film Assist Bonding) film 95, and places the controller chip 30 on the wiring substrate 10. At this time, the crimping device 100 deposits the controller chip 30 on the wiring substrate 10 in such a way that the metal bumps 31 of the controller chip 30 correspond to the electrodes 14 of the wiring substrate 10.

[0065] The crimping device 100 has a suction port 105 connected to a vacuum pump (not shown), through which the controller chip 30 is adsorbed. The adsorption surface of the crimping device 100 presses the controller chip 30 onto the wiring substrate 10, and makes the upper surface of the resin layer 20 substantially flat. To prevent the material of the resin layer 20 from adhering to the crimping device 100, a FAB film 95, which serves as a resin film, is interposed between the crimping device 100 and the controller chip 30.

[0066] After the crimping device 100 deposits the controller chip 30 onto the wiring substrate 10, it applies pressure and heats both the wiring substrate 10 and the controller chip 30. This connects (welds) the metal bumps 31 of the controller chip 30 to the electrodes 14 of the wiring substrate 10. During the deposition of the controller chip 30 onto the wiring substrate 10, the resin layer 20 fills the space between the controller chip 30 and the wiring substrate 10. The resin layer 20 may also extend slightly upwards along the side of the controller chip 30.

[0067] Secondly, such as Figure 6 As shown, a memory chip 50 with a resin layer 40 attached to its back is attached to a controller chip 30 and solder resist SR2. At this time, while heating, the memory chip 50 is pressed against the controller chip 30, and the controller chip 30 and resin layer 20 are covered with the resin layer 40. Then, the resin layer 40 is heated and pressurized to eliminate gaps and harden. In this way, the memory chip 50 is bonded to the controller chip 30 via the resin layer 40.

[0068] When viewed from above the front of F1, as shown in the reference... Figure 2 As explained, in this top view, the memory chip 50 and resin layer 40 are larger than the controller chip 30 and smaller than the solder resist SR2. Furthermore, the solder resist SR2 is arranged to surround the controller chip 30. Therefore, the resin layer 40 covers the controller chip 30 and is bonded to the solder resist SR2. Thus, even though the resin layer 40 is relatively thin, the covered memory chip 50 and resin layer 20 can be embedded within it.

[0069] Next, other memory chips 50 are further deposited on top of the memory chip 50. At this time, an adhesive layer 60 is provided between the memory chips 50, and the multiple memory chips 50 are bonded to each other through the adhesive layer 60.

[0070] Subsequently, other semiconductor components are connected to the wiring substrate 10. The pads 51 and electrodes 15 are bonded together via metal wires 70. Furthermore, the memory chip 50 and the metal wires 70 are sealed with sealing resin 80. Metal bumps 90 are formed on the wiring (or pads) 12 on the second surface F2. Thus, the process is completed. Figure 1 The package of semiconductor device 1 shown.

[0071] According to this embodiment, by overlapping two layers of solder resist SR1 and SR2, the thickness of the controller chip 30 and the resin layer 20 embedded in the resin layer 40 is reduced. This suppresses the seepage and shrinkage of the resin layer 40, and allows the resin layer 40 to adequately embed the memory chip 50 and the resin layer 20. Furthermore, by overlapping solder resist SR2 onto solder resist SR1, the thickness of the resin layer 40 can be reduced. This allows the memory chip 50 to be arranged substantially parallel to the front surface F1 of the controller chip 30 or the wiring substrate 10.

[0072] Furthermore, solder resist SR2 is located within the range of solder resist SR1, and has a step difference ST at the opening OP2. Therefore, solder resists SR1 and SR2 gradually thicken in a stepped manner at the outer edge of the opening OP2, which can suppress the metal line 70 from interfering with solder resists SR1 and SR2.

[0073] Furthermore, solder resist SR2 is disposed around the controller chip 30, but not on the other solder resist SR1. Therefore, when other semiconductor components SE are mounted on the wiring substrate 10, interference from the solder resist SR1 with the other semiconductor components SE can be suppressed.

[0074] Furthermore, the solder resist SR2 is applied to the front side F1 of the wiring substrate 10 within the minimum necessary range. Therefore, the thickness difference between the solder resist SR1 on the front side F1 and the solder resist on the back side F2 is not significant, which can suppress the warping of the wiring substrate 10.

[0075] (Second Implementation)

[0076] Figure 8 This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. In the second embodiment, the memory chip 50 and the resin layer 40 are offset to one side of the controller chip 30. Consequently, a portion of the resin layer 20 and the controller chip 30 are exposed from the resin layer 40. Thus, when viewed from above the front side F1, the memory chip 50 and the resin layer 40 can also be offset to one side of the controller chip 30. Other configurations of the second embodiment can be the same as the corresponding configuration of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0077] (Third Implementation)

[0078] Figure 9 This is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the third embodiment. In the third embodiment, when viewed from above the front side F1, the inner edge E2_in of the solder resist SR2 is located at approximately the same position as the inner edge E2_in of the solder resist SR1 and overlaps with it. Other configurations of the third embodiment are the same as the corresponding configuration of the first embodiment. Therefore, the third embodiment can obtain the same effects as the first embodiment.

[0079] (Fourth implementation)

[0080] Figure 10 This is a top view showing an example configuration of the semiconductor device 1 according to the fourth embodiment. In the fourth embodiment, when viewed from above the front side F1, the solder resist SR2 is divided into multiple parts. Each part of the solder resist SR2 is approximately quadrilateral, making it easier to process and arrange compared to a frame-shaped solder resist SR2. On the other hand, there is a concern that the resin layer 40 may seep out from the gaps in the solder resist SR2. However, by arranging the solder resist SR2 in a manner that sufficiently narrows the gaps, the seepage of the resin layer 40 can be suppressed. Other configurations of the fourth embodiment can be the same as the corresponding configuration of the first embodiment. Therefore, the fourth embodiment can achieve the same effects as the first embodiment.

[0081] (Fifth Embodiment)

[0082] Figure 11 This is a top view showing an example configuration of the semiconductor device 1 according to the fifth embodiment. In the fifth embodiment, when viewed from above the front side F1, the inner edge E2_in of the solder resist SR2 is processed to conform to the shape of the resin layer 20 penetrating from the outer edge E30 of the controller chip 30. For example, when the resin layer 20 penetrating around the outer edge E30 of the controller chip 30 in a generally circular or generally elliptical shape, the inner edge E2_in of the solder resist SR2 is processed into a generally circular or generally elliptical shape along the resin layer 20. This makes it easier for the resin layer 20 to remain inside the solder resist SR2, suppressing excessive overflow onto the solder resist SR2. Other configurations of the fifth embodiment can be the same as the corresponding configuration of the first embodiment. Therefore, the fifth embodiment can achieve the same effects as the first embodiment.

[0083] (Sixth Embodiment)

[0084] Figure 12 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the sixth embodiment. In the sixth embodiment, the outer surfaces F3 of the solder resists SR1 and SR2 are inclined. For example, the outer surfaces F3 of the solder resists SR1 and SR2 are inclined in a substantially vertical direction relative to the front surface F1 in a manner that widens from the upper surface of the solder resist SR2 toward the bottom surface of the solder resist SR1 (in a manner with a downward sloping edge). In addition, the inner wall surfaces of the solder resists SR1 and SR2 may also be inclined.

[0085] Therefore, the solder resists SR1 and SR2 and the metal wire 70 are less likely to interfere with each other. Other configurations in the sixth embodiment can be the same as the corresponding configuration in the first embodiment. Therefore, the sixth embodiment can achieve the same effects as the first embodiment.

[0086] (Seventh Embodiment)

[0087] Figure 13 This is a cross-sectional view showing a configuration example of the semiconductor device 1 according to the seventh embodiment. In the seventh embodiment, the inner end of the solder resist SR1 extends below the controller chip 30. When viewed from above the front side F1, the inner side surface (inner edge) F4 of the solder resist SR1 is closer to the center of the controller chip 30 than the side surface (outer edge) F30 of the controller chip 30. That is, in this top view, the entire inner periphery of the solder resist SR1 is located inside the entire outer periphery of the bottommost controller chip 30, and the inner edge of the solder resist SR1 overlaps with the controller chip 30.

[0088] With this configuration, the gap between the solder resist SR1 and the controller chip 30 becomes narrower. Therefore, as Figure 5As shown, when the controller chip 30 is bonded to the wiring substrate 10, the resin layer 20 is compressed between the solder resist SR1 and the controller chip 30. This suppresses the formation of voids in the resin layer 20.

[0089] The other configurations of the seventh embodiment can be the same as those of the first embodiment. Therefore, the seventh embodiment can achieve the same effects as the first embodiment.

[0090] (Eighth Embodiment)

[0091] Figure 14 This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the eighth embodiment. In the eighth embodiment, solder resists SR1 and SR2 are formed as a single unit. For example, solder resist SR1 is formed to be thicker, and solder resist SR2 is omitted. Using photolithography and etching techniques, solder resist SR1 is processed to have a step, so that the inner surface F4 of solder resist SR1 enters below the controller chip 30. Thus, solder resist SR2 is omitted, and the same configuration as in the seventh embodiment is obtained. According to this configuration, the eighth embodiment can obtain the same effects as the seventh embodiment.

[0092] Certain embodiments of the present invention have been described, but these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments and methods described herein can be implemented in various other forms, and various omissions, substitutions, and modifications can be made to the embodiments and methods described herein without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention, as well as within the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a wiring substrate, the wiring substrate including a plurality of electrodes, a first resin layer and a second resin layer, the plurality of electrodes being disposed on a first surface, the first resin layer being disposed on the first surface surrounding the plurality of electrodes, and the second resin layer being disposed on the first resin layer; The first semiconductor chip is electrically connected to the first electrode among the plurality of electrodes, and its upper surface is higher than the top of the second resin layer; A second semiconductor chip, disposed above the first semiconductor chip, is larger than the first semiconductor chip and is connected to the second electrode among the plurality of electrodes via a metal wire; as well as The third resin layer is disposed between the first semiconductor chip and the second semiconductor chip, and between the second resin layer and the second semiconductor chip, and is in contact with the upper surface of the first semiconductor chip and the upper surface of the second resin layer, covering the first semiconductor chip. The second resin layer extends beyond the third resin layer; The first semiconductor chip has a bottom surface facing the first surface, and is electrically connected to the first electrode via a third electrode disposed on the bottom surface.

2. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the second resin layer surrounds the first semiconductor chip.

3. The semiconductor device according to claim 1, wherein, when viewed from above the first surface, the outer edge of the second resin layer is located between the first semiconductor chip and the second electrode.

4. The semiconductor device according to claim 1, wherein, when viewed from above the first surface, the outer edge of the second resin layer is located further outward than the outer edge of the second semiconductor chip and overlaps the first resin layer.

5. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the outer edge of the second resin layer is located further outward than the outer edge of the third resin layer and overlaps the first resin layer.

6. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the inner edge of the second resin layer is located further outward than the outer edge of the first semiconductor chip and overlaps the first resin layer.

7. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the inner edges of the first resin layer and the inner edges of the second resin layer substantially overlap.

8. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the outer edge of the second semiconductor chip is located further outward than the outer edge of the first semiconductor chip and is located between the second electrode and the first semiconductor chip.

9. The semiconductor device according to claim 1, wherein, when viewed from above the first surface, the outer edge of the second semiconductor chip and the outer edge of the third resin layer substantially overlap.

10. The semiconductor device according to claim 1, further comprising: a fourth resin layer disposed between the wiring substrate and the first semiconductor chip; The third resin layer covers the first semiconductor chip and the fourth resin layer.

11. The semiconductor device of claim 10, wherein, when viewed from above the first surface, the outer edge of the fourth resin layer overlaps either the first or the second resin layer.

12. The semiconductor device of claim 1, wherein the outer edges of the first and second resin layers have a step difference.

13. The semiconductor device of claim 1, wherein the inner edges of the first and second resin layers have a step difference.

14. The semiconductor device of claim 1, wherein, when viewed from above the first surface, the inner edge of the first resin layer is closer to the center of the first semiconductor chip than the outer edge of the first semiconductor chip.

15. The semiconductor device of claim 14, wherein the first and second resin layers are integral when viewed from above the first surface.

16. The semiconductor device of claim 1, wherein the height from the first surface to the upper surface of the second resin layer is lower than the height from the first surface to the upper surface of the first semiconductor chip.

17. The semiconductor device of claim 10, wherein the fourth resin layer is in direct contact with the third electrode.

18. The semiconductor device of claim 10, wherein the fourth resin layer is disposed on the upper surface of the second resin layer.

19. The semiconductor device of claim 10, wherein the fourth resin layer is generally circular or generally elliptical when viewed from above the first surface.

20. The semiconductor device of claim 1, wherein the first resin layer is disposed on a first side of the second electrode above the first surface, the first side being the opposite side of a second side of the second electrode above the first surface, and the first semiconductor chip is disposed on the second side of the second electrode above the first surface.

21. A method for manufacturing a semiconductor device, comprising: On a wiring substrate, a first semiconductor chip with an upper surface higher than the top of a second resin layer is electrically connected to a first electrode among a plurality of electrodes. The wiring substrate includes the plurality of electrodes, a first resin layer and a second resin layer. The plurality of electrodes are disposed on a first surface. The first resin layer is disposed on the first surface around the plurality of electrodes. The second resin layer is disposed on the first resin layer. The second semiconductor chip is bonded to the first semiconductor chip via the third resin layer. When viewed from above the first surface, the second semiconductor chip is larger than the first semiconductor chip and smaller than the second resin layer. The second electrode among the plurality of electrodes is connected to the second semiconductor chip via a metal wire; as well as The first semiconductor chip and the second resin layer are brought into contact with the third resin layer. The second resin layer extends beyond the third resin layer; The first semiconductor chip has a bottom surface facing the first surface, and is electrically connected to the first electrode via a third electrode disposed on the bottom surface.

22. The method of claim 21, wherein, when viewed from above the first surface, the second resin layer surrounds the first semiconductor chip.

23. The method of claim 21, wherein, when viewed from above the first surface, the outer edge of the second resin layer is located between the first semiconductor chip and the second electrode.

24. The method of claim 21, wherein, when viewed from above the first surface, the outer edge of the second resin layer is located further outward than the outer edges of the second semiconductor chip and the third resin layer, and overlaps the first resin layer.

25. The method of claim 21, further comprising: A fourth resin layer is supplied between the wiring substrate and the first semiconductor chip; The third resin layer is formed in such a way that it covers the first semiconductor chip and the fourth resin layer.

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