Memory unit and method for reading data from memory unit

Abstract

A memory cell includes a semiconductor substrate, a transistor, and a first antifuse structure. The transistor is located above the semiconductor substrate. The first antifuse structure is located above the semiconductor substrate and adjacent to the transistor, and includes a first end and a second end. The first end of the first antifuse structure is located within the semiconductor substrate and laterally surrounds the transistor. The second end of the first antifuse structure is located above and spaced apart from the first end of the first antifuse structure. This allows for a high-density semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to a memory cell and a method for reading data from the memory cell. Background Art

[0002] Fuse elements are commonly used in semiconductor devices such as memory or logic devices. Antifuses have electrical characteristics opposite to fuses and can repair defective cells by replacing them with redundant cells.

[0003] Generally speaking, an antifuse is controlled by a control gate adjacent to the antifuse. Therefore, a unit cell is defined as 1T1C (1 transistor-1 controller), which refers to a structure composed of a transistor (transistor, control gate) and a capacitor (controller, antifuse). However, as the number of antifuses required in a semiconductor device increases, multiple unit cells occupy a large area. In order to achieve high-density semiconductor devices, it is desirable to reduce the size of the unit cell as much as possible. Summary of the Invention

[0004] The present disclosure relates to a memory cell and a method for reading data from the memory cell.

[0005] According to some embodiments of the present disclosure, a memory cell includes a semiconductor substrate, a transistor, and a first antifuse structure. The transistor is located above the semiconductor substrate. The first antifuse structure is located above the semiconductor substrate and adjacent to the transistor, and includes a first end and a second end. The first end of the first antifuse structure is located within the semiconductor substrate and laterally surrounds the transistor. The second end of the first antifuse structure is located above the first end of the first antifuse structure and is spaced apart from the first end of the first antifuse structure.

[0006] In some embodiments of the present disclosure, a dielectric layer is located between the first end and the second end of the first antifuse structure.

[0007] In some embodiments of the present disclosure, a distance between a top surface of the first end and a bottom surface of the second end is between about 15 angstroms and about 30 angstroms.

[0008] In some embodiments of the present disclosure, the memory cell further includes an isolation structure laterally surrounding the transistor.

[0009] In some embodiments of the present disclosure, the isolation structure contacts the first end of the first antifuse structure and one of the source and the drain of the transistor.

[0010] In some embodiments of the present disclosure, the first end of the first antifuse structure laterally surrounds the isolation structure.

[0011] In some embodiments of the present disclosure, the memory cell further includes a well region located in the semiconductor substrate, wherein the well region is in contact with the first end of the first antifuse structure and the channel of the transistor.

[0012] In some embodiments of the present disclosure, a top surface of the first end of the first antifuse structure is lower than a top surface of the gate of the transistor.

[0013] In some embodiments of the present disclosure, a bottom surface of the second end of the first antifuse structure is lower than a top surface of the gate of the transistor.

[0014] In some embodiments of the present disclosure, the memory cell further includes a contact connected to the gate and the drain of the transistor.

[0015] In some embodiments of the present disclosure, the memory cell further includes a first doped region located in the semiconductor substrate and laterally surrounding the first end of the first antifuse structure, and the first doped region is spaced apart from the first end of the first antifuse structure.

[0016] In some embodiments of the present disclosure, the conductivity type of the first doped region is the same as the conductivity type of the first end of the first antifuse structure.

[0017] In some embodiments of the present disclosure, the memory cell further includes a second doped region located in the semiconductor substrate and laterally surrounding the first doped region, and the first doped region has a conductivity type different from that of the second doped region.

[0018] In some embodiments of the present disclosure, the memory cell further includes a second anti-fuse structure located above the semiconductor substrate and adjacent to the transistor, wherein the first anti-fuse structure and the second anti-fuse structure share a first end.

[0019] In some embodiments of the present disclosure, the second antifuse structure further includes a second end located above the first end, and the second end of the first antifuse structure and the second end of the second antifuse structure are spaced apart from each other.

[0020] In some embodiments of the present disclosure, the first end of the first antifuse structure is ring-shaped in a top view.

[0021] According to some embodiments of the present disclosure, a method for reading data from a memory cell is provided, wherein the memory cell includes a transistor and at least one antifuse structure formed above a semiconductor substrate, and a well region within the semiconductor substrate is connected to a channel of the transistor and a first end of the antifuse structure, and the method includes the following steps: providing a first voltage to the source and drain of the transistor; providing a second voltage to the first end and the second end of the antifuse structure; and determining the state of the antifuse structure by detecting a current flowing through the transistor channel.

[0022] In the above-described embodiments of the present disclosure, since the first antifuse structure can function as a capacitor in the memory cell and the first end of the first antifuse structure can be disposed in the semiconductor substrate, the size of the memory cell can be reduced, and the number of capacitors in a single semiconductor device (e.g., a memory device having a plurality of memory cells) can be increased without occupying a large area. As a result, a high-density semiconductor device can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present disclosure may be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings:

[0024] Figure 1 1 is a top view illustrating a memory cell according to some embodiments of the present disclosure;

[0025] Figure 2 According to some embodiments Figure 1 A cross-sectional view of the memory cell along line a-a' is shown;

[0026] Figure 3 According to some embodiments of the present disclosure Figure 1 The circuit layout of the memory cell shown;

[0027] Figure 4 According to some other embodiments of the present disclosure Figure 1 The circuit layout of the memory cell shown;

[0028] Figure 5 To include Figure 1 a top view of a memory device showing a plurality of memory cells; and

[0029] Figure 6 According to some embodiments of the present disclosure Figure 5 The circuit layout of the memory device is shown. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0031] As used herein, "about," "approximately," or "substantially" generally means within 20%, within 10%, or within 5% of a given value or range. The numerical quantities given herein are approximate, meaning that if not explicitly stated, the meaning of the term "about," "approximately," or "substantially" can be inferred.

[0032] Figure 1 FIG1 is a top view of a memory cell 100 according to some embodiments of the present disclosure. Figure 1 . The memory cell 100 includes a transistor T, a first annular region R1, a second annular region R2, and a third annular region R3. The first annular region R1 laterally surrounds the transistor T, the second annular region R2 laterally surrounds the first annular region R1, and the third annular region R3 laterally surrounds the second annular region R2. In some embodiments, the transistor T is substantially located at the center of the memory cell 100 when viewed from above. In some embodiments, the first annular region R1, the second annular region R2, and the third annular region R3 are laterally spaced apart from each other. The transistor T includes a gate structure G, a source region S, and a drain region D to maintain the operation of the memory cell 100. At least one anti-fuse structure AF is formed in the first annular region R1 and serves as a capacitor of the memory cell 100. The second annular region R2 and the third annular region R3 are used to maintain the operation of the memory cell 100.

[0033] Figure 2 According to some embodiments Figure 1 The cross-sectional view of the memory cell 100 along the line a-a' is shown. Figure 2 . The memory cell 100 includes a semiconductor substrate 110, at least one first doping region 130, at least one second doping region 140, and at least one third doping region 120. The transistor T and the anti-fuse structure AF are located above the semiconductor substrate 110, and the anti-fuse structure AF is adjacent to the transistor T. The source region S, the drain region D, the channel region C between the source region S and the drain region D, the first doping region 130, the second doping region 140, and the third doping region 120 are located in the semiconductor substrate 110, and the gate structure G is located above the semiconductor substrate 110. In some embodiments, the gate spacer GS may laterally surround the gate structure G. In some embodiments, the gate structure G may include a conductive material, such as a metal or other suitable material, and the gate spacer GS may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable material. In some embodiments, the third doping region 120 laterally surrounds the transistor T, so that the third doping region 120 forms Figure 1 In some embodiments, the first doping region 130 laterally surrounds the third doping region 120, so that the first doping region 130 forms a Figure 1In some embodiments, the second doping region 140 laterally surrounds the first doping region 130, so that the second doping region 140 forms a Figure 1 In other words, the first doping region 130 , the second doping region 140 and the third doping region 120 are each annular in shape in a top view.

[0034] refer to Figure 1 and Figure 2 . In some embodiments, the source region S, the drain region D, and the second doping region 140 are doped with n-type dopants, such as arsenic or phosphorus, and the third doping region 120 and the first doping region 130 are doped with p-type dopants, such as boron. In an alternative embodiment, the source region S, the drain region D, and the second doping region 140 are doped with p-type dopants, such as boron, and the third doping region 120 and the first doping region 130 are doped with n-type dopants, such as arsenic or phosphorus. The memory cell 100 may further include a plurality of isolation structures 152, 154, 156, and 158 embedded in the semiconductor substrate 110 to isolate the source region S, the drain region D, the third doping region 120, the first doping region 130, and the second doping region 140, so that the source region S, the drain region D, the third doping region 120, the first doping region 130, and the second doping region 140 are spaced apart from each other and electrically isolated from each other. For example, the isolation structure 152 laterally surrounds the transistor T, the third doped region 120 laterally surrounds the isolation structure 152, the isolation structure 154 laterally surrounds the third doped region 120, the first doped region 130 laterally surrounds the isolation structure 154, the isolation structure 156 laterally surrounds the first doped region 130, the second doped region 140 laterally surrounds the isolation structure 156, and the isolation structure 158 laterally surrounds the second doped region 140. In some embodiments, the isolation structure 152 contacts the third doped region 120 and one of the source region S and the drain region D of the transistor T. In some embodiments, the isolation structures 152, 154, 156, and 158 are shallow trench isolation (STI) structures including a dielectric material, such as silicon oxide, silicon nitride, or other suitable materials.

[0035] Memory cell 100 further includes a first well region 102 and a second well region 104 in semiconductor substrate 110. Second well region 104 may surround first well region 102. Source region S, drain region D, channel region C, third doped region 120, and first doped region 130 are located within first well region 102, and second doped region 140 is located within second well region 104. In some embodiments, the conductivity type of first well region 102 is the same as that of third doped region 120 and first doped region 130, and the conductivity type of second well region 104 is the same as that of second doped region 140. In some embodiments, first well region 102 may contact third doped region 120 and channel region C of transistor T. In some embodiments, memory cell 100 further includes a deep well region 106 located below first well region 102 and second well region 104. The conductivity type of deep well region 106 is the same as that of second well region 104. Deep well region 106 serves to electrically isolate semiconductor substrate 110.

[0036] Memory cell 100 further includes at least one first conductive contact 160, at least one second conductive contact 170, at least one third conductive contact 180, at least one fourth conductive contact 190, and at least one fifth conductive contact 195. For clarity, the second conductive contact 170, the third conductive contact 180, the fourth conductive contact 190, and the fifth conductive contact 195 will be discussed first below. Second conductive contact 170 is formed on and in contact with first doped region 130, such that second conductive contact 170 is electrically connected to first doped region 130. Second conductive contact 170 may be referred to as a pickup contact that interconnects first doped region 130 with a signal line formed on the first doped region 130. In some embodiments, second conductive contact 170 is electrically connected to a signal source via the connected signal line to provide a desired voltage potential to semiconductor substrate 110. On the other hand, a third conductive contact 180 is formed on and in contact with the second doped region 140, electrically connecting the third conductive contact 180 to the second doped region 140. The third conductive contact 180 can be referred to as a pickup contact that interconnects the second doped region 140 with a power line formed on the second doped region 140. In some embodiments, the third conductive contact 180 is electrically connected to a power source (e.g., Vdd source) via the connected power line to maintain operation of the memory cell 100. Furthermore, a fourth conductive contact 190 and a fifth conductive contact 195 are formed on and in contact with the transistor T, electrically connecting the fourth conductive contact 190 and the fifth conductive contact 195 to the transistor T. In some embodiments, the fourth conductive contact 190 contacts the gate structure G and drain region D of the transistor T and is electrically connected to a power source (e.g., Vdd source), while the fifth conductive contact 195 contacts the source region S of the transistor T and is electrically connected to a ground reference. In other words, the fourth conductive contact 190 can be connected to the gate structure G and the drain region D of the transistor T and electrically connected to a power source, thereby maintaining the operation of the memory cell 100 .

[0037] The first conductive contact 160 is formed on the third doping region 120 and is vertically spaced apart from the third doping region 120, so that the third doping region 120 and the first conductive contact 160 can be electrically isolated from each other and serve as the anti-fuse structure AF mentioned above. In other words, the anti-fuse structure AF includes the third doping region 120 and the first conductive contact 160 that are vertically spaced apart from each other. The third doping region 120 can serve as the bottom electrode (or first end) of the anti-fuse structure AF, and the first conductive contact 160 can serve as the top electrode (or second end) of the anti-fuse structure AF. In addition, the anti-fuse structure AF including the third doping region 120 and the first conductive contact 160 can be partially embedded in the semiconductor substrate 110. In other words, a portion of the anti-fuse structure AF (for example, the third doping region 120 of the anti-fuse structure AF) can be embedded in the semiconductor substrate 110. For example, in Figure 2 In the embodiment of the present invention, the bottom electrode of the anti-fuse structure AF (i.e., the third doped region 120) is embedded in the semiconductor substrate 110, and the top electrode of the anti-fuse structure AF (i.e., the first conductive contact 160) is located above the semiconductor substrate 110. In some embodiments, a plurality of first conductive contacts 160 are disposed on the third doped region 120 and surround the transistor T. In some embodiments, the first conductive contact 160, the second conductive contact 170, the third conductive contact 180, the fourth conductive contact 190, and the fifth conductive contact 195 may include a conductive material, such as copper, tungsten, or other suitable materials.

[0038] In some embodiments, the antifuse structure AF further includes a dielectric layer 200 vertically sandwiched between the third doped region 120 and the first conductive contact 160. That is, the third doped region 120 and the first conductive contact 160 are located on opposite sides of the dielectric layer 200. In some embodiments, the thickness T1 of the dielectric layer 200 is between approximately 15 angstroms and approximately 30 angstroms. That is, the distance D between the top surface 121 of the third doped region 120 and the bottom surface 163 of the first conductive contact 160 is between approximately 15 angstroms and approximately 30 angstroms. If the thickness T1 of the dielectric layer 200 is less than approximately 15 angstroms, the antifuse structure AF is easily programmed, and the states "0" and "1" may be indistinguishable. If the thickness T of the dielectric layer 200 is greater than approximately 30 angstroms, the voltage required to blow the antifuse structure AF increases. In some embodiments, the top surface 121 of the third doped region 120 is lower than the top surface G1 of the gate structure G of the transistor T. In some embodiments, a bottom surface 163 of the first conductive contact 160 is lower than a top surface G1 of the gate structure G of the transistor T. The operation of the antifuse structure AF and its effect on the memory cell 100 will be discussed in the following description.

[0039] In some embodiments, the memory cell 100 further includes an interlayer dielectric layer 210 covering the semiconductor substrate 110 and covering the transistor T, the first doped region 130, the second doped region 140, the third doped region 120, and the isolation structures 152, 154, 156, and 158. Furthermore, the interlayer dielectric layer 210 is interposed between the first conductive contact 160, the second conductive contact 170, the third conductive contact 180, the fourth conductive contact 190, and the fifth conductive contact 195 to prevent accidental contact between the first conductive contact 160, the second conductive contact 170, the third conductive contact 180, the fourth conductive contact 190, and the fifth conductive contact 195. In some embodiments, the interlayer dielectric layer 210 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable materials.

[0040] In some embodiments, the interlayer dielectric layer 210 and the dielectric layer 200 located between the third doped region 120 and the first conductive contact 160 can be formed to substantially eliminate an interface therebetween. For example, the interlayer dielectric layer 210 is formed above the semiconductor substrate 110. A blind via is formed in the interlayer dielectric layer 210 that does not expose the third doped region 120. A hole for the first conductive contact 160 is then formed in the blind via, such that the portion of the interlayer dielectric layer 210 between the third doped region 120 and the first conductive contact 160 is referred to as the dielectric layer 200.

[0041] In some embodiments, the memory cell 100 further includes a plurality of anti-fuse structures AF located above the semiconductor substrate 110 and adjacent to the transistor T. The plurality of anti-fuse structures AF share a first end (i.e., the third doped region 120), and each anti-fuse structure AF includes a second end (i.e., a first conductive contact 160) located above the first end. In some embodiments, as Figure 1 As shown, the second ends of the plurality of anti-fuse structures AF are spaced apart from each other. Since the plurality of anti-fuse structures AF share the same first end, the anti-fuse structures AF can be formed at a high density along the first annular region R1.

[0042] Since the third doped region 120, the first conductive contact 160, and the dielectric layer 200 located between the third doped region 120 and the first conductive contact 160 can serve as a capacitor of the memory cell 100 (i.e., an antifuse structure AF), the size of the memory cell 100 can be reduced, and the number of capacitors in a single semiconductor device (e.g., a memory device having a plurality of memory cells 100) can be increased without occupying a large area. Therefore, a high-density semiconductor device can be realized. It should be noted that the connection relationship, materials, and advantages of the above-mentioned elements will not be repeated. In the following description, methods for writing data into the memory cell 100 and reading data from the memory cell 100 will be discussed.

[0043] Figure 3According to some embodiments of the present disclosure Figure 1 The circuit layout of the memory cell 100 is shown. Figure 2 and Figure 3 The source of the transistor T (e.g., source region S) is electrically connected to the ground reference via the first power line PL1, and the drain of the transistor T (e.g., drain region D) is electrically connected to the Vdd power supply via the second power line PL2. Therefore, current can flow through the channel region C of the transistor T (see Figure 2 In some embodiments, the gate of transistor T (e.g., gate structure G) is also electrically connected to the Vdd power supply via the second power line PL2. On the other hand, the second end of the anti-fuse structure AF (e.g., first conductive contact 160) is electrically connected to the first signal line SL1, and the first end of the anti-fuse structure AF (e.g., doped region 120) is electrically connected to the second signal line SL2. In some embodiments, the first end of the anti-fuse structure AF is electrically connected to the second signal line SL2 via the first doped region 130 and the second conductive contact 170. In some embodiments, the power lines PL1, PL2, and the second signal line SL2 are substantially parallel to each other, and the first signal line SL1 is substantially perpendicular to the power lines PL1, PL2, and the second signal line SL2.

[0044] A first voltage potential and a second voltage potential can be provided to the anti-fuse structure AF via a first signal line SL1 and a second signal line SL2, respectively. When the voltage difference between the first voltage potential and the second voltage potential is greater than the breakdown voltage of the anti-fuse structure AF (e.g., approximately 3V), the anti-fuse structure AF is blown, causing the current between the first and second terminals of the current anti-fuse structure AF to change, and data is written into the memory cell 100. For example, in a blown anti-fuse structure AF, the first and second terminals are short-circuited (e.g., in state 1), and in an unblown anti-fuse structure AF, the first and second terminals are open (e.g., in state 0).

[0045] Furthermore, the state of transistor T does not affect data writing. In some embodiments, when data is written to memory cell 100, transistor T may be in an operating state, i.e., source region S is electrically connected to the ground reference, and drain region D and gate structure G are electrically connected to the Vdd power supply. In an alternative embodiment, when data is written to memory cell 100, transistor T may be in a non-operating state, i.e., source region S, drain region D, and gate structure G are electrically connected to a floating node, thereby saving the cost of maintaining transistor T in operation.

[0046] After data is written to the memory cell 100, the data can be read from the memory cell 100 by determining whether the antifuse structure AF is blown. More specifically, after the antifuse structure AF is blown, a first voltage difference is provided to the antifuse structure AF by applying a third voltage potential and a fourth voltage potential to the antifuse structure AF, and a second voltage difference is provided to the transistor T by applying a fifth voltage potential and a sixth voltage potential to the transistor T. If the antifuse structure AF is blown, the first and second ends of the antifuse structure AF are short-circuited, and a first current flows through the antifuse structure AF to the semiconductor substrate 110. Simultaneously, a second current flows through the channel region C of the transistor T. Therefore, the first current of the antifuse structure AF affects the second current flowing through the first well region 102 of the semiconductor substrate 110 and through the channel region C. As a result, the second current generated by the transistor T may be reduced by the first current, a phenomenon known as the "body effect." On the other hand, if the anti-fuse structure AF is not blown, when a voltage potential is applied to the anti-fuse structure AF, the anti-fuse structure AF is open between the first terminal and the second terminal, and no current flows through the anti-fuse structure AF to the semiconductor substrate 110. Therefore, the second current generated by the transistor T remains unchanged in this case.

[0047] Because the second current generated by transistor T decreases after the antifuse structure AF blows, the blown state of the antifuse structure AF can be easily determined. In some embodiments, a third voltage potential and a fourth voltage potential can be provided to the second terminal and the first terminal of the antifuse structure AF via a first signal line SL1 and a second signal line SL2, respectively, and a fifth voltage potential and a sixth voltage potential can be provided to the source and the drain of the antifuse structure AF via a first power line PL1 and a second power line PL2, respectively. In some embodiments, the first voltage difference provided to the antifuse structure AF can be less than the breakdown voltage of the antifuse structure AF. For example, the first voltage difference can be approximately 1V, such that the first voltage difference does not change the state of the corresponding antifuse structure AF. By detecting the drop in the second current caused by the body effect, whether the antifuse structure AF has blown (or the state of the antifuse structure AF) can be determined, and data can be read from the memory cell 100 accordingly.

[0048] Figure 4 According to some other embodiments of the present disclosure Figure 1 The circuit layout of the memory cell 100 is shown. Figure 4 . Figure 4 The illustrated layout of the memory cell 100 includes two antifuse structures AF electrically connected in parallel, thereby preventing malfunction of the memory cell 100 due to a failure of any antifuse structure AF. Although not shown here, more than two antifuse structures AF may be electrically connected in parallel in the memory cell 100.

[0049] Figure 5 To include Figure 1 A top view of a memory device 1000 is shown showing a plurality of memory cells 100 . Figure 6 According to some embodiments of the present disclosure Figure 5 The circuit layout of the memory device 1000 is shown. Figure 5 and Figure 6 The memory device 1000 includes a plurality of memory cells 100 (e.g., memory cells 100a-100d) arranged in a matrix to further realize a high-density memory device 1000. In addition, since the plurality of memory cells 100 are arranged in a matrix, the first power line PL1, the second power line PL2, the first signal line SL1, and the second signal line SL2 can be shared by the memory cells 100. For example, the first power line PL1a can be shared by the memory cells 100a and 100b, the second power line PL2a can be shared by the memory cells 100a and 100b, the first signal line SL1a can be shared by the memory cells 100a and 100b, and the second signal line SL2a can be shared by the memory cells 100a and 100c. For another example, the first power line PL1b may be shared by the memory cells 100c and 100d, the second power line PL1b may be shared by the memory cells 100c and 100d, the first signal line SL1b may be shared by the memory cells 100c and 100d, and the second signal line SL2b may be shared by the memory cells 100b and 100d. Figure 5 As shown, the third annular region R3 including the second doped region 140 and the third conductive contact 180 may also be shared by adjacent memory cells 100 .

[0050] In some embodiments, when the breakdown voltage of each antifuse structure AF in memory cells 100a-100d is approximately 3V, and the antifuse structure AF in memory cell 100a is predetermined to be blown, the voltage potential provided by the first signal line SL1a may be approximately -5V, the voltage potential provided by the first signal line SL1b may be approximately -1V, the voltage potential provided by the second signal line SL2a may be approximately 0V, and the voltage potential provided by the second signal line SL2b may be approximately -3V. Therefore, the voltage difference between the first and second ends of the antifuse structure AF in memory cell 100a is approximately 5V, which is higher than the breakdown voltage of the antifuse structure AF, causing the antifuse structure AF in memory cell 100a to blow. On the other hand, since the voltage differences between the first and second ends of the antifuse structures AF in memory cells 100b-100d are approximately 1V, 2V, and 2V, respectively, the antifuse structures AF in memory cells 100a-100c do not blow.

[0051] In some embodiments, when determining which anti-fuse structure AF is blown, the voltage potentials provided by the first signal lines SL1a and SL1b may be approximately -1V, respectively, and the voltage potentials provided by the second signal lines SL2a and SL2b may be 0V, respectively, so that current can flow through the blown anti-fuse structure AF, and due to the body effect, data can be read from the memory device 1000.

[0052] According to the aforementioned embodiments of the present disclosure, since the third doped region, the first conductive contact, and the dielectric layer between the third doped region and the first conductive contact can serve as a capacitor for the memory cell (i.e., an antifuse structure), the size of the memory cell can be reduced, and the number of capacitors in a single semiconductor device (e.g., a memory device having a plurality of memory cells) can be increased without occupying a larger area. Thus, a high-density semiconductor device can be realized.

[0053] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0054] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure as long as such modifications and variations fall within the scope of the claims.

[0055]

Explanation of symbols

[0056] 100, 100a~100d: memory unit

[0057] 152,154,156,158: Isolation structure

[0058] 160: first conductive contact

[0059] 170: Second conductive contact

[0060] 180: third conductive contact

[0061] 1000:Memory device

[0062] a-a': line

[0063] AF: Antifuse structure

[0064] D: Drain region

[0065] G: Gate structure

[0066] PL1, PL1a, PL1b: First Power Line

[0067] PL2, PL2a, PL2b: Second power line

[0068] R1: First annular area

[0069] R2: Second annular area

[0070] R3: The third ring area

[0071] SL1, SL1a, SL1b: First signal line

[0072] SL2, SL2a, SL2b: Second signal line

[0073] S: Source region

[0074] T: Transistor

[0075] T1: Thickness.

Claims

1. A memory unit, characterized in that: Include: semiconductor substrates; a transistor located above the semiconductor substrate; A first antifuse structure is located above the semiconductor substrate and adjacent to the transistor, the first antifuse structure comprising: A first end is located in the semiconductor substrate and laterally surrounds the transistor; and a second end located above the first end of the first antifuse structure and spaced apart from the first end of the first antifuse structure; a first doped region located in the semiconductor substrate and laterally surrounding the first end of the first antifuse structure, the first doped region being spaced apart from the first end of the first antifuse structure, wherein the first doped region has the same conductivity type as the first end of the first antifuse structure; as well as The second doping region is located in the semiconductor substrate and laterally surrounds the first doping region. The second doping region is spaced apart from the first doping region. The conductivity type of the first doping region is different from that of the second doping region. 2 . The memory cell according to claim 1 , wherein a dielectric layer is located between the first end and the second end of the first antifuse structure. 3 . The memory cell of claim 1 , wherein a distance between a top surface of the first end and a bottom surface of the second end is between 15 angstroms and 30 angstroms.

4. The memory cell according to claim 1, further comprising an isolation structure laterally surrounding the transistor. 5 . The memory cell of claim 4 , wherein the isolation structure is in contact with the first end of the first antifuse structure and one of a source and a drain of the transistor. 6 . The memory cell of claim 4 , wherein the first end of the first antifuse structure laterally surrounds the isolation structure. 7 . The memory cell according to claim 1 , further comprising a well region located in the semiconductor substrate, wherein the well region is in contact with the first end of the first antifuse structure and the channel of the transistor. 8 . The memory cell according to claim 1 , wherein a top surface of the first end of the first antifuse structure is lower than a top surface of the gate of the transistor. 9 . The memory cell according to claim 1 , wherein a bottom surface of the second end of the first antifuse structure is lower than a top surface of the gate of the transistor.

10. The memory cell according to claim 1, further comprising a contact connecting the gate and the drain of the transistor. 11 . The memory cell according to claim 1 , further comprising a second antifuse structure located above the semiconductor substrate and adjacent to the transistor, wherein the first antifuse structure and the second antifuse structure share the first end. 12 . The memory cell of claim 11 , wherein the second antifuse structure further comprises a second end located above the first end, and the second end of the first antifuse and the second end of the second antifuse structure are spaced apart from each other. 13 . The memory cell according to claim 1 , wherein the first end of the first antifuse structure is ring-shaped in a top view.

14. A method for reading data from a memory cell, characterized in that: The memory cell includes a transistor and at least one antifuse structure formed above a semiconductor substrate, and a well region in the semiconductor substrate is connected to a channel of the transistor and a first end of the antifuse structure. The memory cell includes a first doped region and a second doped region, wherein the first doped region is located in the semiconductor substrate and laterally surrounds the first end of the antifuse structure, the first doped region is spaced apart from the first end of the antifuse structure, and the conductivity type of the first doped region is the same as the conductivity type of the first end of the antifuse structure. The second doped region is located in the semiconductor substrate and laterally surrounds the first doped region, the second doped region is spaced apart from the first doped region, and the conductivity type of the first doped region is different from the conductivity type of the second doped region. The method includes: providing a first voltage to the source and drain of the transistor; providing a second voltage to the first terminal and the second terminal of the antifuse structure; and The state of the anti-fuse structure is determined by detecting the current flowing through the channel of the transistor.

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