Semiconductor device and method of forming the same, semiconductor structure

Abstract

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present invention includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut structure extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature. Embodiments of the invention also relate to semiconductor structures.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same, and semiconductor structures. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than its predecessor. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] As integrated circuit (IC) technology advances to smaller technology nodes, ensuring satisfactory mask coverage becomes increasingly difficult. For example, some gate dicing components consist of a top and a bottom formed sequentially using photolithography and etching processes. When mask alignment is not ideal, the top may not bond to the bottom. Therefore, while existing gate dicing components and their formation processes are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a first gate structure disposed above a first rear-side dielectric member; a second gate structure disposed above a second rear-side dielectric member; a gate dicing member extending continuously from between the first gate structure and the second gate structure to between the first rear-side dielectric member and the second rear-side dielectric member; and a pad disposed between the gate dicing member and the first rear-side dielectric member and between the gate dicing member and the second rear-side dielectric member.

[0005] Another embodiment of the present invention provides a semiconductor structure including: a dielectric layer; a contact etch stop layer (CESL) disposed above the dielectric layer; an isolation member disposed above the contact etch stop layer; and a gate dicing member extending through the isolation member, the contact etch stop layer, and the dielectric layer, wherein the gate dicing member is disposed between a first gate structure and a second gate structure, and between a third gate structure and a fourth gate structure.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a first plurality of channel members over a first substrate portion of a workpiece, and forming a second plurality of channel members over a second substrate portion of the workpiece, the first substrate portion and the second substrate portion being spaced apart by an isolation member; forming a joint gate structure to enclose each of the first plurality of channel members and each of the second plurality of channel members; flipping the workpiece; after the flipping, forming a guide opening through the isolation member; extending the guide opening through the joint gate structure to form a gate dicing opening, the gate dicing opening dividing the joint gate structure into a first gate structure and a second gate structure; and after the extension, depositing a dielectric material in the gate dicing opening to form a gate dicing member. Attached Figure Description

[0007] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart of a method for forming a semiconductor device having a rear-side contact element according to one or more aspects of the present invention is shown.

[0009] Figures 2A to 11A , Figures 2B to 11B , Figures 2C to 11C , Figures 2D to 11D and Figures 2E to 11E The invention illustrates one or more aspects of the invention according to... Figure 1 A partial cross-sectional view of the workpiece during the manufacturing process of the method.

[0010] Figures 12 to 19 The use of one or more aspects of the invention is shown. Figure 1 The method is used to fabricate optional semiconductor structures or intermediate structures. Detailed Implementation

[0011] It should be understood that the following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0013] Furthermore, as those skilled in the art will understand, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to cover values ​​within a reasonable range, taking into account the variations inherent during the manufacturing process. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with the numerical value, a numerical value or range covers a reasonable range including said value, such as within + / - 10% of said value. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where those skilled in the art know that manufacturing tolerances associated with the deposited material layer are + / - 15%. Furthermore, the invention may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In semiconductor manufacturing, diced metal gate (CMG) processing refers to the process of forming dielectric components to divide a continuous gate structure spanning more than one active region into more than one segment. Such dielectric components can be called gate dicing components or dicing components. In some existing CMG processes, gate dicing components are formed on dielectric fins (or hybrid fins). The gate dicing component is on top, and the dielectric fin is on the bottom; they work together to divide the gate structure into two segments. In some example processes, gate dicing components are formed from the front side of a substrate (such as a wafer) using photolithography and etching processes. As semiconductor devices continue to scale down, it becomes increasingly difficult to form gate dicing components upright on top of dielectric fins due to limitations in coverage and critical dimension uniformity (CDU). In some cases, gate dicing components that miss the dielectric fins may cut into the gate structure or channel region, resulting in defects.

[0015] This invention provides a CMG process different from existing technologies, forming dicing members from the back side of the substrate. Furthermore, the dicing members according to the invention extend through the gate structure from the back side of the substrate. That is, the dicing members of the invention individually divide the gate structure into multiple segments without the aid of dielectric fins or hybrid fins. In some cases, the dicing members of the invention can even extend horizontally through more than one gate structure, or vertically through one or more dielectric components or layers above the gate structure. The process of the invention is not only formed from the back side, but also self-aligned to avoid defects associated with mask misalignment. Embodiments of the invention can continue to scale down the cell height while maintaining or increasing the processing window.

[0016] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor device according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2A to 11A , Figures 2B to 11B , Figures 2C to 11C , Figures 2D to 11D and Figures 2E to 11E Description method 100, Figures 2A to 11A , Figures 2B to 11B , Figures 2C to 11C , Figures 2D to 11D and Figures 2E to 11E These are partial cross-sectional views of workpiece 200 at different manufacturing stages according to an embodiment of method 100. Figures 2A to 11A , Figures 2B to 11B , Figures 2C to 11C , Figures 2D to 11D and Figures 2E to 11E In this application, figures ending in A are perspective views of workpiece 200; figures ending in B are partial cross-sectional views along cross-section B-B' in the corresponding perspective view; figures ending in C are partial cross-sectional views along cross-section C-C' in the corresponding perspective view; figures ending in D are partial cross-sectional views along cross-section D-D' in the corresponding perspective view; and figures ending in E are partial cross-sectional views along cross-section E-E' in the corresponding perspective view. Because workpiece 200 is manufactured into semiconductor device 200 after the manufacturing process is completed, workpiece 200 may be referred to as semiconductor device 200 depending on the context. Furthermore, in this application, unless otherwise stated, the same reference numerals denote the same parts.

[0017] Embodiments of the present invention can be implemented as advanced semiconductor devices that may include multi-gate devices. A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has a raised channel (e.g., the gate wrapping the top and sidewalls of a “fin” of semiconductor material extending from the substrate) that is surrounded by a gate on more than one side. The gate structure of an MBC transistor may extend partially or entirely around the channel region to provide access to the channel region on two or more sides. Because the gate structure of an MBC transistor surrounds the channel region, an MBC transistor may also be referred to as a gate-all-around (SGT) transistor or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives MBC transistor alternative names such as nanosheet transistors or nanowire transistors. The use of MBC transistor structures to describe embodiments of the present invention is for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0018] refer to Figure 1 and Figures 2A to 2E Method 100 includes frame 102 for receiving workpiece 200. Figures 2A to 2E Workpiece 200 is shown, with its front side facing upwards. That is, it has not yet been... Figures 2A to 2EThe workpiece 200 shown undergoes back-side processing. Workpiece 200 includes a substrate 202. In one embodiment, substrate 202 includes silicon (Si). In other embodiments, substrate 202 may also include other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon-germanium (SiGe), or diamond. Workpiece 200 includes a first substrate portion 202-1 and a second substrate portion 202-2, each of which is patterned by substrate 202 and may share the same composition as substrate 202. Although in Figures 2A to 2E The diagram shows substrate 202; for simplicity, substrate 202 may be omitted from at least some other figures. (Reference) Figure 2E The first substrate portion 202-1 and the second substrate portion 202-2 are spaced apart from each other by an isolation member 204. In some embodiments, the isolation member 204 is deposited in a trench defining the substrate 202. The isolation member 204 may also be referred to as a shallow trench isolation (STI) member 204. The isolation member 204 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0019] refer to Figure 2E The workpiece 200 includes a plurality of vertically stacked channel members 208 located above a first base portion 202-1 and another plurality of vertically stacked channel members 208 located above a second base portion 202-2. For example... Figure 2CAs shown, in the described embodiment, two vertically stacked channel members 208 are disposed above each of the first substrate portion 202-1 and the second substrate portion 202-2. The channel members 208 may be formed of a semiconductor material similar to that of the substrate 202. In one embodiment, the channel member 208 may include silicon (Si). The channel members 208 located above the first substrate portion 202-1 and the second substrate portion 202-2 are enveloped by a joint gate structure 250 extending along the Y direction. Each joint gate structure 250 may include an interface layer 252, a gate dielectric layer 254 located above the interface layer 252, and a gate electrode layer located above the gate dielectric layer 254. In some embodiments, the interface layer 252 includes silicon oxide. The gate dielectric layer 254 may also be referred to as a high-k dielectric layer because it is formed of a dielectric material with a dielectric constant greater than that of silicon dioxide (approximately 3.9). The gate dielectric layer 254 may include hafnium oxide. Optionally, the gate dielectric layer 254 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0020] The gate electrode layer may comprise a single-layer or multi-layer structure, such as a metal layer with a selected work function to enhance device performance (work function metal layer), a pad, a wetting layer, a first adhesive layer, a metal alloy, or a metal silicide. For example, the gate electrode layer may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof.

[0021] refer to Figures 2A to 2CThe workpiece 200 includes a gate spacer 216 disposed along the sidewall of a combined gate structure 250, which is located above the topmost channel member 208 or isolation member 204. The gate spacer 216 may be a single layer or multiple layers. In some embodiments, the gate spacer 216 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, and / or combinations thereof. Between two adjacent channel members 208, an inner spacer member 228 liner is provided against the sidewall of the gate structure. The inner spacer member 228 may include silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. With respect to each of the first substrate portion 202-1 and the second substrate portion 202-2, each vertical stack of the channel members extends between the source member 230S and the drain member 230D. One end face of each channel member 208 is coupled to a source member 230S, and the other end face of each channel member 208 is coupled to a drain member 230D. Depending on the conductivity type of the MBC transistor to be formed, the source member 230S and the drain member 230D can be n-type or p-type. When they are n-type, they can comprise silicon (Si), phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), antimony-doped silicon (Si:Sb), or other suitable materials, and can be in-situ doped during the epitaxial process by introducing n-type dopants (such as phosphorus (P), arsenic (As), or antimony (Sb)). When they are p-type, they can comprise germanium (Ge), gallium-doped silicon germanium (SiGe:Ga), boron-doped silicon germanium (SiGe:B), or other suitable materials, and can be in-situ doped during the epitaxial process by introducing p-type dopants (such as boron (B) or gallium (Ga)).

[0022] refer to Figure 2A , Figure 2C and Figure 2DEach of the source component 230S and drain component 230D includes a first epitaxial layer 220 and a second epitaxial layer 222 located above the first epitaxial layer 220. In some embodiments, the first epitaxial layer 220 and the second epitaxial layer 222 include dopants. For example, the doping concentration in the second epitaxial layer 222 is greater than the doping concentration in the first epitaxial layer 220. The increased doping concentration in the second epitaxial layer 222 is used to reduce contact resistance. The workpiece 200 also includes a contact etch stop layer (CESL) 232 disposed above the source component 230S and the drain component 230D, and an interlayer dielectric (ILD) layer 234 disposed above the CESL 232. The CESL 232 may include silicon nitride, silicon oxynitride, and / or other materials known in the art. ILD layer 234 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials.

[0023] like Figure 2A , Figure 2C and Figure 2D As shown, at least one of the source components 230S is directly disposed above the semiconductor plug 218. The semiconductor plug 218 extends along the X direction through the substrate 202 and the isolation component 204, sandwiched between the two substrate portions. Along the Y direction, the semiconductor plug 218 is sandwiched between the two portions of the isolation component 204. In some embodiments, the semiconductor plug 218 may be formed of undoped silicon germanium (SiGe). In some embodiments, the composition of the semiconductor plug 218 and the first epitaxial layer 220 is selected such that the first epitaxial layer 220 can be used as an epitaxial etch stop layer. For example, when an n-type MBC transistor is desired, the first epitaxial layer 220 is formed of silicon (Si) doped with an n-type dopant. Due to the reduced germanium content, the etching process of etching the semiconductor plug 218 (formed of silicon germanium) can be slowed down when etching the first epitaxial layer 220. When a p-type MBC transistor is desired, the etching process of etching the semiconductor plug 218 (formed from silicon germanium) can be slowed down when etching the first epitaxial layer 220 because the boron dopant can reduce the etching rate.

[0024] exist Figure 2A , Figure 2B , Figure 2C and Figure 2EIn some embodiments illustrated, a gate self-aligned contact (SAC) dielectric layer 256 is used. In some cases, the gate SAC dielectric layer 256 may be disposed over the combined gate structure 250 and the gate spacer 216. The gate SAC dielectric layer 256 may be a single layer or multiple layers and may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonoxynitride, silicon carbonitride, and / or combinations thereof. The workpiece 200 may also include a front-side source contact 260S located above the source component 230S and a front-side drain contact 260D located above the drain component. The front source contact 260S or the front drain contact 260D may include titanium nitride (TiN), tantalum (Ta), titanium (Ti), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof.

[0025] At box 102, as shown Figures 2A to 2E As shown, the workpiece 200 can be received with its rear side facing upwards. In this upside-down configuration, the substrate 202 is at the bottom, while the gate SAC dielectric layer 256 is at the top.

[0026] refer to Figure 1 and Figures 3A to 3E Method 100 includes block 104, in which workpiece 200 is flipped vertically. To flip workpiece 200 vertically, a carrier substrate (not explicitly shown) is bonded to the front side of workpiece 200, away from substrate 202. In some embodiments, the carrier substrate can be bonded to workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may be formed of a semiconductor material (such as silicon), sapphire, glass, a polymer material, or other suitable material. In embodiments using fusion bonding, the carrier substrate includes a bottom oxide layer, and workpiece 200 includes a top oxide layer. After both the bottom and top oxide layers have been processed, they are placed in fuzzy contact with each other to directly bond at room temperature or elevated temperatures. Figures 3A to 3E As shown, once the carrier substrate is bonded to the workpiece 200, the workpiece 200 is flipped over. After flipping the workpiece 200, the rear side of the workpiece 200 is planarized using chemical mechanical polishing (CMP) until the isolation member 204, the semiconductor plug 218, the first substrate portion 202-1 and the second substrate portion 202-2 are exposed on the now upward-facing rear side of the workpiece 200.

[0027] refer to Figure 1 and Figures 4A to 4EMethod 100 includes block 106, in which a rear contact 270 is formed. Operations at block 106 may include selectively removing a semiconductor plug 218 to form a rear contact opening and forming the rear contact 270 within the rear opening. In some embodiments, because the semiconductor plug 218, formed of silicon germanium (SiGe), is disposed between an isolation member 204 (formed of a dielectric material), a first substrate portion 202-1 (formed of silicon (Si) in at least some embodiments), and a second substrate portion 202-2 (formed of silicon (Si) in at least some embodiments), the removal of the semiconductor plug 218 may be self-aligned. In these embodiments, a selective wet etching process may be used to selectively remove the semiconductor plug 218. Example selective wet etching processes may include using a solution of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). Because the selective etching process at frame 106 etches the semiconductor plug 218 faster than the isolation component 204, the first substrate portion 202-1, and the second substrate portion 202-2, the semiconductor plug 218 can be removed with minimal damage. In the described embodiment, selective removal of the semiconductor plug 218 may also remove a portion of the first epitaxial layer 220 beneath the semiconductor plug 218. The removal of the semiconductor plug 218 and the first epitaxial layer 220 forms a rear contact opening to expose the source component 230S.

[0028] Then, a rear contact 270 is formed in the rear contact opening. Although not explicitly shown, each rear contact 270 may include a silicide layer to form an interface with the source component 230S and the metal filler layer. In the example process, a metal precursor is then deposited over the exposed source component 230S, and an annealing process is performed to induce silicide formation between the source component 230S and the metal precursor to form a silicide layer. In some embodiments, the metal precursor may include titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), zirconium (Zr), nickel (Ni), cobalt (Co), manganese (Mn), tungsten (W), iron (Fe), ruthenium (Ru), or platinum (Pt), and the silicide layer may include titanium silicide (TiSi), chromium silicide (CrSi), tantalum silicide (TaSi), molybdenum silicide (MoSi), nickel silicide (NiSi), cobalt silicide (CoSi), manganese silicide (MnSi), tungsten silicide (WSi), iron silicide (FeSi), ruthenium silicide (RuSi), or platinum silicide (PtSi). Figures 4A to 4EAs shown, after forming the silicide layer, a metal filler material can be deposited in the back contact opening to form the back contact 270. The metal filler material may include tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), or aluminum (Al), and can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the back contact 270 may optionally include a barrier layer disposed at its interface with the isolation member 204. Optional barrier layers may include titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), tungsten nitride (WN), titanium (Ti), or tantalum (Ta). A planarization process, such as a CMP process, can be performed after the deposition of the metal filler material to remove excess material and provide a flat top surface. At the end of the operation at block 106, the back contact 270 is coupled to the source member 230S.

[0029] refer to Figure 1 and Figures 5A to 5E Method 100 includes a frame 108 in which a cap layer 272 is formed to cover a first base portion 202-1 and a second base portion 202-2. In some embodiments, operations at frame 108 include selectively recessing the first base portion 202-1 and the second base portion 202-2 to form a recess and forming the cap layer 272 within the recess. Figure 4A As shown, at the end of the operation at frame 106, the first substrate portion 202-1 and the second substrate portion 202-2 are surrounded by an isolation member 204 and a rear contact member 270 formed of different materials. In some embodiments, selective wet etching or selective dry etching processes can be used to perform selective recessing of the first substrate portion 202-1 and the second substrate portion 202-2. Example selective wet etching processes may include using ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etchant. Example selective dry etching processes may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrofluoric acid (HF), carbon tetrafluoride (CF4), argon, or mixtures thereof. After recessing the first substrate portion 202-1 and the second substrate portion 202-2 to form a groove, metal or metal oxide may be deposited in the groove to form a cap layer 272. In some embodiments, the cap layer 272 may include alumina, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), or tungsten (W). In one embodiment, the cap layer 272 includes hafnium oxide. A planarization process is then performed to provide a flat rear-side surface. Figure 5A , Figure 5C , Figure 5D and Figure 5E As shown, the cap layer 272 may be adjacent to one or more rear contact members 270 and isolation members 204.

[0030] refer to Figure 1 , Figures 6A to 6E and Figures 7A to 7E Method 100 includes block 110, wherein an isolation member 204 is selectively etched to form a guide opening 282 exposing a combined gate structure 250. Operations at block 110 include a patterned hard mask 280 (e.g., ...). Figures 6A to 6E The formation and guiding opening 282 (as shown) Figures 7A to 7E The formation of the hard mask (shown) is as follows. In the example process, a hard mask layer is blanket-deposited over workpiece 200 using CVD. The hard mask layer can be a single layer or multiple layers. When the hard mask layer is multilayered, it may include a silicon oxide layer and a silicon nitride layer. After depositing the hard mask layer, photolithography and etching processes can be performed to pattern the hard mask layer to form a patterned hard mask. In some cases, a photoresist layer is deposited over the hard mask layer. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected from or transmitted through the photomask, baked in a post-exposure bake process, and developed in a developer. The patterned photoresist layer is then used as an etching mask to etch the hard mask layer, thereby forming the patterned hard mask 280. Reference Figures 6A to 6E The patterned hard mask 280 includes a mask opening 281 substantially aligned with the guide opening 282 to be formed. According to the invention, the patterned hard mask 280 is used to mask the portion of the isolation member 204 that is not etched at the frame 114. Whether a portion of the cap layer 272 is exposed in the mask opening 281 is irrelevant. Figure 6E As shown, the mask opening 281 can share an end with a portion of the cap layer 272 on the first base portion 202-1 and the second base portion 202-2. This is because the etching process at frame 114 is selective for the isolation member 204 and substantially does not etch the cap layer 272. Even when the mask opening 281 is larger than the guide opening 282 or misaligned (e.g. Figure 6E When the dotted line in the diagram is shown, the guide opening 282 can still be successfully formed.

[0031] Then refer to Figure 7A and Figure 7E With the patterned hard mask 280 in place, the isolation component 204 is selectively and anisotropically etched to form the guide opening 282. In some embodiments, the isolation component 204 can be etched using a dry etching process (e.g., reactive ion etching (RIE)) that uses chlorine (Cl2), oxygen (O2), boron trifluoride (BCl3), carbon tetrafluoride (CF4), or combinations thereof. Figure 7AAs shown, the guide opening 282 may terminate on the top surface of the gate dielectric layer 254, the gate spacer 216, and the CESL 232, without extending into the gate electrode layer of the combined gate structure 250. Because the spacing between the mask opening 281 and the cap layer 272 is not common, the width of the guide opening 282 between the first base portion 202-1 and the second base portion 202-2 is smaller than the width of the mask opening 281 along the X direction. Note that, for better illustration of the guide opening 282, in... Figure 7A The structure intersecting with the cross section D-D' is omitted. Figure 7D The structure along the cross section D-D' is shown.

[0032] refer to Figure 1 and Figures 8A to 8E Method 100 includes a frame 112 in which a pad 284 is deposited along the sidewall of a guide opening 282. The pad 284 protects the first substrate portion 202-1 and the second substrate portion 202-2 from etching processes at frame 114. The pad 284 may also be referred to as a cut metal gate cap layer. The pad 284 may be a single layer or multiple layers. In the example process, such as... Figure 8A , Figure 8B and Figure 8E As shown, at least one dielectric material is deposited over the back side of workpiece 200, and then the deposited dielectric material is anisotropically etched back to expose the gate dielectric layer 254. In some cases, the at least one dielectric material used for pad 284 may include silicon, oxygen, nitrogen, or carbon. For example, at least one dielectric material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, or silicon oxynitride. After the etch-back process, pad 284 may have a thickness between about 6 nm and about 10 nm. Note that, for better illustration of pad 284, [the following text is missing]. Figure 8A The structure intersecting with the cross section D-D' is omitted. Figure 8D The structure along the cross section D-D' is shown.

[0033] refer to Figure 1 and Figures 9A to 9E Method 100 includes block 114, wherein a guide opening 282 extends through the combined gate structure 250 to form a gate dicing opening 286. At block 114, an anisotropic etching process is performed to extend the guide opening 282 to form the gate dicing opening 286. In some embodiments, the gate dicing opening 286 terminates on or in the gate SAC dielectric layer 256. Figure 9A , Figure 9B and Figure 9EAs shown, because the anisotropic etching process etches the pad 284, gate spacer 216, and gate SAC dielectric layer 256 at a slower rate, these structures limit the etching process at frame 114 and define the boundary of the gate cut opening 286. In some embodiments, the anisotropic etching process at frame 114 may be a dry etching process using chlorine (Cl2), oxygen (O2), boron trifluoride (BCl3), carbon tetrafluoride (CF4), or combinations thereof. Note that for better illustration of the components in the gate cut opening 286, Figure 9A The structure intersecting with the cross section D-D' is omitted. Figure 9D The structure along the cross-section D-D' is shown. (As shown) Figure 9A and Figure 9E As shown, the gate cutting opening 286 divides the combined gate structure 250 into a first gate segment 250-1 and a second gate segment 250-2.

[0034] refer to Figure 1 and Figures 10A to 10E Method 100 includes block 116, wherein a dielectric material is deposited in a gate dicing opening 286 to form a gate dicing portion 288. In some embodiments, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), or CVD deposition may be used to deposit the dielectric material for the gate dicing portion 288. In some cases, the dielectric material for the gate dicing portion 288 may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, or silicon oxynitride. Between the gate dicing portion 288 and the pad 284, the gate dicing portion 288 is formed of a low-k dielectric material to reduce parasitic capacitance, and the pad 284 is more etch-resistant to protect the gate electrode layer, such as the work function layer therein. In some alternative embodiments, the gate dicing portion 288 may be a single layer or multiple layers. When the gate dicing portion 288 is multilayer, the gate dicing portion 288 may include a dielectric pad in contact with a gate segment and a dielectric filler spaced apart from the gate segment by the dielectric pad. The dielectric pad and the dielectric filler may be formed of different materials. For example, the dielectric pad is oxygen-free, while the dielectric filler includes oxygen. As another example, the dielectric constant of the dielectric pad can be greater than that of the dielectric filler. When the gate dicing component 288 is multilayered, the thickness of the dielectric pad can be between about 1 nm and about 6 nm. Note that, for better illustration of the components in the gate dicing component 288, Figure 10A The structure intersecting with the cross section D-D' is omitted. Figure 10D The structure along the cross section D-D' is shown.

[0035] refer to Figure 1 and Figures 11A to 11EMethod 100 includes block 118, wherein the first substrate portion 202-1 and the second substrate portion 202-2 are replaced with a rear-side dielectric layer 290. For example... Figure 10A , Figure 10C , Figure 10D and Figure 10E As shown, at the end of the operation at frame 116, the first substrate portion 202-1 and the second substrate portion 202-2 are surrounded by components formed of different materials, including an isolation component 204, a gasket 284, and a rear contact 270. This arrangement allows for the selective removal of the first substrate portion 202-1 and the second substrate portion 202-2. In some embodiments, selective wet etching or selective dry etching can be used to selectively remove the first substrate portion 202-1 and the second substrate portion 202-2. Example selective wet etching processes may include the use of ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or a suitable wet etchant. Example selective dry etching processes may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrofluoric acid (HF), carbon tetrafluoride (CF4), argon, or mixtures thereof. Then, a rear dielectric layer 290 is deposited to replace the removed first substrate portion 202-1 and second substrate portion 202-2. The rear dielectric layer 290 may comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbonitride, and may be deposited using spin coating, CVD, FCVD, or plasma-enhanced CVD (PECVD). In some embodiments, the rear dielectric layer 290 may be formed of a high-k dielectric material to provide sufficient protection for the gate structure, even though a high-k dielectric material may slightly increase parasitic capacitance. In some embodiments, if the rear dielectric layer 290 comprises oxygen, a protective liner may be deposited over the rear side of the workpiece 200 using CVD, ALD, or a suitable deposition technique prior to depositing the rear dielectric layer 290. The protective liner serves to space the rear dielectric layer 290 from adjacent structures and may comprise silicon nitride. A planarization process, such as CMP, can be performed to remove excess material, ensuring that the top surfaces of the back dielectric layer 290, isolation member 204, gate dicing member 288, pad 284, and back contact 270 are coplanar. Note that, for better illustration of the components in the back dielectric layer 290, Figure 11A The structure intersecting with the cross section D-D' is omitted. Figure 11D The structure along the cross section D-D' is shown.

[0036] refer to Figure 1 and Figures 11A to 11E Method 100 includes block 120, in which a rear power rail 292 is formed. The formation of the rear power rail 292 may include depositing an insulating layer 294 (on...). Figure 11AIt is not explicitly stated in the text, but in Figures 11B to 11E As shown in the diagram, an insulating layer 294 is patterned to form power rail trenches and a rear power rail 292 is formed within the power rail trenches. The insulating layer 294 may have a composition similar to that of the ILD layer 234. The insulating layer 294 is deposited over the rear side of the workpiece 200, including the rear dielectric layer 290, the rear contact 270, the isolation member 204, the pad 284, and the gate dicing member 288. The power rail trenches are then patterned in the insulating layer 294. The rear contact 270 is exposed in one or more power rail trenches. Subsequently, a metal filler material is deposited into the power rail trenches to form a rear power rail 292 electrically coupled to the rear contact 270. In some embodiments, the metal filler material in the rear power rail may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), or combinations thereof. In some embodiments, a barrier layer may be optionally deposited before the deposition of the metal filler material to separate the metal filler material from the insulating layer. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), or tungsten nitride (WN). When the barrier layer is formed, both the barrier layer and the metal filler material can be considered as part of the back power rail 292. The barrier layer and the metal filler layer can be deposited using PVD, CVD, ALD, or electroless plating. A planarization process, such as CMP, can be performed to remove excess material over the insulating layer. Although not explicitly shown, further interconnect structures may be formed over the insulating layer 294 and the back power rail 292.

[0037] exist Figure 11B In this design, the gate dicing member 288 includes a lower portion disposed along the X-direction between gate spacers 216 and an upper portion disposed between pads 284. Along the X-direction, the lower portion includes a first width W1, and the upper portion includes a second width W2. In some cases, the first width W1 can be between about 6 nm and about 22 nm, and the second width W2 can be between about 4 nm and about 22 nm. The lower portion includes a first height H1 along the Z-direction, and the upper portion includes a second height H2 along the Z-direction. The sum of the first height H1 and the second height H2 can be between about 10 nm and about 80 nm. (Reference) Figure 11C At the end of operation at frame 120, the rear contact 270 may include a third height H3 between approximately 20 nm and approximately 40 nm. (Reference) Figure 10E Along the Y direction, the lower portion of the gate cutting member is disposed between the gate electrode portions of the gate segment, while the upper portion is disposed between the pads 284. Figures 11A to 11E The workpiece 200 is inverted. When... Figures 11A to 11EWhen the workpiece 200 is flipped back to the upright position, the isolation layer 294 will be at the bottom and the gate SAC dielectric layer 256 will be at the top.

[0038] Although Figure 7A , Figure 7B and Figure 7E The result of the operation at box 110 is shown, with guide opening 282 comprising substantially vertical sidewalls, and a guide opening with tapered sidewalls is anticipated. (Reference) Figure 12 When the etching process at frame 110 lacks sufficient anisotropy and selectivity, the cap layer 272, the first base portion 202-1, and the second base portion 202-2 are also etched at frame 110 to obtain a tapered guide opening 2820. (Reference) Figure 13 The tapered guide opening 2820 can have a corrugated effect on subsequent processes. For example... Figure 13 As shown, the pad 284 and the tapered gate cut-out portion 2880 deposited in the tapered guide opening 2820 also inherit the tapered profile. When viewed along the X direction, the rear dielectric layer 290, which replaces the current wedge-shaped base portion, may also include a wedge shape. Figure 13 An alternative embodiment is also shown, wherein the gate dicing opening or tapered gate dicing portion 2880 extends completely through the gate SAC dielectric layer 256. (See also...) Figure 13 As shown, the tapered gate dicing member 2880 may include a tapered tip portion that penetrates the gate SAC dielectric layer 256 into the etch stop layer (ESL) 212 and the top interlayer dielectric (ILD) layer 210. The ESL 212 and the top ILD layer 210 may be portions of a front-side interconnect structure. The composition of the ESL 212 may be similar to that of the ESL 232, and the composition of the top ILD layer 210 may be similar to that of the ILD layer 234. Figure 13 As shown, the tapered gate dicing component 2880 may have an over-etch depth D between about 3 nm and about 100 nm.

[0039] The gate dicing component of this invention can span more than one combined gate structure. (See reference...) Figure 14 A first slot guide opening 2822 can be formed at block 110 of method 100, spanning the first joint gate structure 2500 and the second joint gate structure 2502. Then refer to... Figure 15 After the pad 284 is formed, the first slot guide opening 2822 extends downward through the first combined gate structure 2500 and the second combined gate structure 2502 to form a first slot gate dicing opening 2860. The first slot gate dicing opening 2860 divides not only the first combined gate structure 2500 into two gate segments, but also the second combined gate structure 2502 into two gate segments. Figure 15In some embodiments illustrated, the etching process that forms the first slot gate dicing opening 2860 can etch the combined gate structure faster than etching CESL 232 and ILD layer 234. As a result, dielectric islands 298 can be formed. Figure 15 It is also shown that the first slot gate dicing opening 2860 may include an overshoot portion 2830 extending through the ESL 212 and the top ILD layer 210 beneath the gate SAC dielectric layer 256. In these alternative embodiments, such as Figure 16 As shown, the operation at block 116 can form a first slot gate dicing component 2880, which typically follows the shape of the first slot gate dicing opening 2860. When viewed from the Y direction, the first slot gate dicing component 2880 includes legs 300 and spans dielectric island 298. The composition of the first slot gate dicing component 2880 can be similar to that of the gate dicing component 288 described above. Figure 16 The workpiece 200 is flipped up and down. When Figure 16 When the workpiece 200 is flipped back to the upright position, the isolation component 204 will be at the bottom and the two legs 300 will point upwards.

[0040] The gate dicing component of this invention can span the gap between the source / drain contacts. (See reference) Figure 17 A second slot guide opening 2824 can be formed at block 110 of method 100, spanning the first combined gate structure 2500, the second combined gate structure 2502, and the slot source / drain contact 302. Then refer to... Figure 18 After the pad 284 is formed, the second slot guide opening 2824 extends downward through the first combined gate structure 2500 and the second combined gate structure 2502 to form a second slot gate dicing opening 2862. The second slot gate dicing opening 2862 divides not only the first combined gate structure 2500 into two gate segments aligned along the Y direction, but also the second combined gate structure 2502 into two gate segments aligned along the Y direction. Figure 18 In some embodiments shown, the etching process that forms the second slot gate dicing opening 2862 can etch the combined gate structure faster than the slot source / drain contact 302. As a result, a metal island 304 can be formed. Figure 18 It is also shown that the second slot gate dicing opening 2862 may include an overshoot portion 2830 that extends through the ESL 212 beneath the gate SAC dielectric layer 256 and the top ILD layer 210. In these alternative embodiments, such as Figure 19As shown, the operation at block 116 can form a second slot gate dicing member 2882, which typically follows the shape of the second slot gate dicing opening 2862. When viewed from the Y direction, the second slot gate dicing member 2882 includes legs 300 and spans the metal island 304. The composition of the second slot gate dicing member 2882 can be similar to that of the gate dicing member 288 described above. Figure 19 The workpiece 200 is flipped up and down. When... Figure 19 When the workpiece 200 flips back to the upright position, the isolation component 204 will be at the bottom and the two legs 300 will point upwards.

[0041] Embodiments of the present invention offer advantages. For example, the method of the present invention forms the gate dicing portion from the back side of the workpiece. Using a structure on the back side of the workpiece and on the cap layer, the formation of the gate dicing opening of the present invention is self-aligned and does not depend on the high resolution or high coverage accuracy of the photolithography process.

[0042] In one exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a first gate structure disposed over a first rear-side dielectric member; a second gate structure disposed over a second rear-side dielectric member; a gate dicing member extending continuously from between the first gate structure and the second gate structure to between the first rear-side dielectric member and the second rear-side dielectric member; and a pad disposed between the gate dicing member and the first rear-side dielectric member, and between the gate dicing member and the second rear-side dielectric member.

[0043] In some embodiments, the first gate structure and the second gate structure are disposed above the pad. In some embodiments, the semiconductor device may further include a gate spacer extending from the sidewall of the first gate structure to the sidewall of the second gate structure, and a gate dicing member contacts the gate spacer. In some cases, the gate dicing member is in direct contact with the first gate structure and the second gate structure. In some cases, the semiconductor device may further include: a self-aligned contact (SAC) dielectric layer disposed above the first gate structure and the second gate structure; an etch stop layer located above the SAC dielectric layer; and a dielectric layer located above the etch stop layer. The gate dicing member extends into the SAC dielectric layer, the etch stop layer, and the dielectric layer. In some embodiments, the first back-side dielectric member includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbonitride. In some embodiments, the pad includes silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, or silicon oxynitride. In some cases, the gate dicing member includes silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, or silicon oxynitride.

[0044] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a dielectric layer; a contact etch stop layer (CESL) disposed above the dielectric layer; an isolation member disposed above the CESL; and a gate dicing member extending through the isolation member, the CESL, and the dielectric layer. The gate dicing member is disposed between a first gate structure and a second gate structure, and between a third gate structure and a fourth gate structure.

[0045] In some embodiments, the first gate structure and the second gate structure are aligned along one direction, and the third gate structure and the fourth gate structure are aligned along that direction. In some embodiments, the gate dicing member is spaced apart from the isolation member by a pad. In some cases, a dielectric layer is disposed above an etch stop layer and a top dielectric layer, and the gate dicing member includes two legs, each extending into the etch stop layer and the top dielectric layer. In some embodiments, the semiconductor structure may further include a metal member disposed between the two legs, such that the gate dicing member spans the metal member. In some embodiments, the semiconductor structure may further include a dielectric member disposed between the two legs, such that the gate dicing member spans the dielectric member.

[0046] In yet another exemplary aspect, the invention relates to a method. The method includes forming a first plurality of channel members over a first substrate portion of a workpiece and forming a second plurality of channel members over a second substrate portion of the workpiece, the first substrate portion and the second substrate portion being spaced apart by an isolation member; forming a joint gate structure to enclose each of the first plurality of channel members and each of the second plurality of channel members; flipping the workpiece; after flipping, forming a guide opening through the isolation member; extending the guide opening through the joint gate structure to form a gate dicing opening that divides the joint gate structure into a first gate structure and a second gate structure; and after the extension, depositing a dielectric material in the gate dicing opening to form a gate dicing member.

[0047] In some embodiments, the method may further include recessing a first substrate portion and a second substrate portion before forming the guide opening, and depositing a cap layer over the first substrate portion and the second substrate portion after recessing. In some embodiments, forming the guide opening includes depositing a hard mask over the cap layer and the isolation member, patterning the hard mask to expose portions of the isolation member and the cap layer, and etching the isolation member using the patterned hard mask and the cap layer as an etch mask. In some cases, the cap layer includes alumina, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), or tungsten (W). In some embodiments, the method may further include depositing a pad over the sidewalls of the guide opening after forming the guide opening. In some cases, the method may further include forming a self-aligned contact (SAC) dielectric layer over the joint gate structure before flipping. This extension also causes the guide opening to extend through the SAC dielectric layer.

[0048] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: The first gate structure is disposed above the first rear-side dielectric component; The second gate structure is disposed above the second rear dielectric component; A gate dicing component extends continuously from between the first gate structure and the second gate structure to between the first rear dielectric component and the second rear dielectric component; A pad is disposed between the gate dicing component and the first rear dielectric component, and between the gate dicing component and the second rear dielectric component; A self-aligned contact dielectric layer is disposed above the first gate structure and the second gate structure; An etch stop layer is located above the self-aligned contact dielectric layer; as well as A dielectric layer is located above the etch stop layer. The gate dicing component includes two separated legs, each extending into the etch stop layer and the dielectric layer.

2. The semiconductor device according to claim 1, wherein, The first gate structure and the second gate structure are disposed above the pad.

3. The semiconductor device according to claim 1, further comprising: A gate spacer extending from the sidewall of the first gate structure to the sidewall of the second gate structure. The gate cutting component is in contact with the gate spacer.

4. The semiconductor device according to claim 1, wherein, The gate cutting component is in direct contact with the first gate structure and the second gate structure.

5. The semiconductor device according to claim 1, wherein, The gate dicing component also extends through the self-aligned contact dielectric layer.

6. The semiconductor device according to claim 1, wherein, The first rear dielectric component includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, or silicon carbonitride.

7. The semiconductor device according to claim 1, wherein, The gasket includes silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

8. The semiconductor device according to claim 1, wherein, The gate dicing component includes silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride.

9. A semiconductor structure, comprising: Dielectric layer; A contact etch stop layer is disposed above the dielectric layer; An isolation component is disposed above the contact etch stop layer; as well as A gate dicing component extends through the isolation component, the contact etch stop layer, and the dielectric layer, wherein the gate dicing component is disposed between the first gate structure and the second gate structure, and between the third gate structure and the fourth gate structure. The dielectric layer is disposed above the etch stop layer and the top dielectric layer. The gate dicing component includes two separated legs, each extending into the etch stop layer and the top dielectric layer.

10. The semiconductor structure according to claim 9, in, The first gate structure and the second gate structure are aligned in one direction. The third gate structure and the fourth gate structure are aligned along the direction.

11. The semiconductor structure according to claim 9, wherein, The gate dicing component is spaced apart from the isolation component by a pad.

12. The semiconductor structure according to claim 9, wherein the isolation component comprises silicon oxide.

13. The semiconductor structure according to claim 9, further comprising: A metal component is disposed between the two legs such that the gate cutting component spans the metal component.

14. The semiconductor structure according to claim 9, further comprising: A dielectric component is disposed between the two legs such that the gate-cutting component spans the dielectric component.

15. A method of forming a semiconductor device, comprising: A first plurality of channel members are formed above a first substrate portion of the workpiece, and a second plurality of channel members are formed above a second substrate portion of the workpiece, wherein the first substrate portion and the second substrate portion are separated by an isolation member; A combined gate structure is formed to enclose each of the first plurality of channel members and each of the second plurality of channel members; Flip the workpiece; After the flipping, a guide opening is formed through the isolation component; The guide opening extends through the combined gate structure to form a gate cleaving opening, the gate cleaving opening dividing the combined gate structure into a first gate structure and a second gate structure; and Following the extension, dielectric material is deposited in the gate dicing opening to form a gate dicing feature.

16. The method of claim 15, further comprising: Before forming the guide opening, the first substrate portion and the second substrate portion are recessed; as well as After the recess, a cap layer is deposited over the first substrate portion and the second substrate portion.

17. The method according to claim 16, wherein, The formation of the guide opening includes: A hard mask is deposited over the cap layer and the isolation component; Pattern the hard mask to expose portions of the isolation component and portions of the cap layer; and The isolation component is etched using a patterned hard mask and the cap layer as an etching mask.

18. The method according to claim 16, wherein, The capping layer includes aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), or tungsten (W).

19. The method of claim 15, further comprising: After the guide opening is formed, a liner is deposited above the sidewall of the guide opening.

20. The method of claim 15, further comprising: Prior to the flip, a self-aligned contact dielectric layer is formed over the combined gate structure. The extension further extends the guide opening through the self-aligned contact dielectric layer.

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