Methods of forming devices and related devices, memory devices, and electronic systems

Abstract

The present application relates to methods of forming devices and related devices, memory devices, and electronic systems. The methods of forming devices include forming a columnar structure extending vertically through a first isolation material, forming a conductive line operably coupled to the columnar structure, forming a dielectric structure overlying the conductive line, and forming an air gap between adjacent conductive lines. The air gap is laterally adjacent to the conductive lines, where portions of the air gap extend above a plane of upper surfaces of the laterally adjacent conductive lines, and portions of the air gap extend below a plane of lower surfaces of the laterally adjacent conductive lines.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 990,463, filed August 11, 2020, for “Methods of Forming Apparatuses Including Air Gaps Between Conductive Lines and Related Apparatuses, Memory Devices, and Electronic Systems”. Technical Field

[0003] The embodiments disclosed herein relate to the field of microelectronic device design and fabrication. More specifically, embodiments of this disclosure relate to methods of forming devices that include air gaps between conductive lines (e.g., data lines, also known as bit lines), and relate to related devices, memory devices, methods of forming memory devices, and electronic systems. Background Technology

[0004] A continuous goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., "NAND" flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as "three-dimensional (3D) memory array") architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more conductive stack structures, which include layers of conductive and insulating structures. Each vertical memory string may contain at least one selection device that is series-coupled to a series combination of vertically stacked memory cells. Compared to a conventional planar (e.g., two-dimensional) arrangement with transistors, this configuration allows for the placement of a greater number of switching devices (e.g., transistors) within the die region cells (i.e., the length and width of the consumed operating surface) by constructing the array upwards (e.g., vertically) on the die.

[0005] As the size and spacing of conductive features decrease, multi-level wiring structures have been used in memory devices (e.g., 3D NAND flash memory devices) to electrically connect conductive features to each other. Memory devices contain different levels of wiring structures, where the wiring structures are formed of conductive material to provide conductive paths through the memory device. As the size and spacing of conductive features continue to decrease, parasitic (e.g., stray) capacitance between adjacent conductive features within the memory device increases. This increased parasitic capacitance leads to higher power demands and latency in the memory device. Air gaps have been used to electrically isolate conductive features, such as conductive lines. Summary of the Invention

[0006] The embodiments described herein include methods of forming a device comprising air gaps between conductive lines, and related devices, memory devices, methods of forming memory devices, and electronic systems. According to one embodiment described herein, the method of forming a device includes forming a columnar structure extending vertically through a first insulating material; forming conductive lines operatively coupled to the columnar structure; forming a dielectric structure covering the conductive lines; and forming air gaps between adjacent conductive lines, the air gaps being laterally adjacent to the conductive lines, wherein a portion of the air gap extends above a plane of an upper surface of a laterally adjacent conductive line and a portion of the air gap extends below a plane of a lower surface of a laterally adjacent conductive line.

[0007] According to an additional embodiment described herein, the device includes a columnar structure extending vertically through an insulating material; conductive lines operatively coupled to the columnar structure; a dielectric structure covering the conductive lines; and an air gap between laterally adjacent conductive lines, the air gap being laterally adjacent to the conductive lines, wherein an upper portion of the air gap extends laterally adjacent to the dielectric structure and a lower portion of the air gap extends laterally adjacent to a segment of the insulating material.

[0008] According to additional embodiments described herein, a method of forming a memory device includes forming a columnar structure in an opening extending vertically through a stack of alternating conductive and dielectric materials; forming at least one stepped structure comprising a stack of alternating conductive and dielectric materials, the at least one stepped structure being laterally adjacent to the columnar structure; forming conductive lines covering the columnar structure; forming an electrically insulating material covering at least a portion of the stack; forming additional openings extending at least partially vertically through the stack; and forming a dielectric material adjacent to the electrically insulating material to form air gaps within the additional openings, the air gaps being inserted between laterally adjacent conductive lines and between portions of the electrically insulating material covering the conductive lines.

[0009] Furthermore, according to additional embodiments described herein, the memory device includes at least one memory cell array comprising: access lines extending along a first horizontal direction; data lines extending along a second horizontal direction generally transverse to the first horizontal direction; interconnect structures operatively connected to the data lines; dielectric structures adjacent to the data lines on their sides opposite to the interconnect structures; and air gaps extending perpendicularly between laterally adjacent dielectric structures, data lines, and interconnect structures.

[0010] According to other embodiments described herein, an electronic system includes at least one input device; at least one output device; at least one processor device operatively coupled to the at least one input device and the at least one output device; and a memory device operatively coupled to the at least one processor device, the memory device including: a conductive line extending in a horizontal direction; and an air gap separating horizontally adjacent conductive lines, wherein the ratio of the width of the conductive line to the width of the air gap is less than 1. Attached Figure Description

[0011] Figures 1A to 1F A simplified partial cross-sectional view illustrating a method of forming an apparatus according to embodiments of the present disclosure;

[0012] Figure 2 According to embodiments of this disclosure Figures 1A to 1F A simplified cross-sectional view of the device;

[0013] Figure 3 A schematic block diagram illustrating a microelectronic device according to embodiments of the present disclosure; and

[0014] Figure 4 A schematic block diagram illustrating an electronic system according to embodiments of the present disclosure is provided. Detailed Implementation

[0015] This document describes methods for forming devices (e.g., microelectronic devices, semiconductor devices, memory devices) that include air gaps (e.g., voids, unfilled volumes) between conductive lines (e.g., data lines, bit lines), and related devices, memory devices, methods for forming memory devices, and electronic systems. In some embodiments, a method of forming a device includes forming a columnar structure extending vertically through a first insulating material (e.g., a single dielectric material, a stack of alternating dielectric materials), forming conductive lines operatively coupled to the columnar structure, forming a dielectric structure (e.g., a mask material) covering the conductive lines, and forming air gaps between the conductive lines. The air gaps are laterally adjacent to the conductive lines, wherein a portion of the air gap extends above a plane of an upper surface laterally adjacent to the conductive line, and a portion of the air gap extends below a plane of a lower surface laterally adjacent to the conductive line. Thus, the air gaps extend a distance above and below a midpoint of the air gap, wherein the midpoint of the air gap is positioned laterally adjacent to the midpoint of the conductive line. In some embodiments, contact structures (e.g., contacts, bitline contacts) are formed adjacent to the columnar structure, and interconnect structures (e.g., contact vias, bitline vias) are directly formed between and operatively coupled to the contact structures and conductive lines. The interconnect structures can be formed using a single damascene process, and the conductive lines can be formed using a single subtractive patterning process. A portion of the air gap may be laterally adjacent to the interconnect structure. Furthermore, the opening of the air gap may be formed to extend a vertical distance laterally adjacent to portions of the dielectric structure, conductive lines, and interconnect structures. The opening may be formed using a single material removal process within a single chamber of a material removal apparatus. By using a subtractive patterning process, the critical dimension (e.g., width) of the conductive lines can be relatively smaller than the critical dimension (e.g., width) of the air gap laterally inserted between adjacent conductive lines, thereby reducing the parasitic capacitance between adjacent conductive lines. By reducing parasitic capacitance, devices containing conductive lines according to embodiments of this disclosure can operate with less power and at higher speeds.

[0016] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a comprehensive description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without using these specific details. In fact, the embodiments can be practiced in conjunction with conventional fabrication techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not constitute a complete description of a microelectronic device or a complete process flow for manufacturing a microelectronic device, and the structures described below do not constitute a complete microelectronic device. Only the processing actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete microelectronic device can be performed using conventional techniques.

[0017] The materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, or physical vapor deposition (PVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material can be selected by one of ordinary skill in the art. Removal of the material can be accomplished by any suitable technique, including but not limited to etching, abrasive planarization (e.g., chemical mechanical planarization), or other known methods, unless the context otherwise indicates.

[0018] The drawings presented herein are for illustrative purposes only and are not intended to represent actual views of any particular material, component, structure, device, or system. Deviations in the shapes depicted in the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape deviations, for example, due to manufacturing processes. For instance, areas illustrated or described as box-shaped may have rough and / or non-linear characteristics, and areas illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Thus, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas, nor do they limit the scope of the claims. The drawings are not necessarily scaled. Additionally, elements shared between figures may retain the same numerical designations.

[0019] As used herein, unless the context clearly indicates otherwise, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well.

[0020] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] As used herein, for a particular parameter, “about” or “approximately” includes a value whose variation would be understood by one of ordinary skill in the art to be within the acceptable tolerance range of the particular parameter. For example, “about” or “approximately” may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0022] As used herein, spatial relative terms, such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “back,” “left,” “right,” etc., are used for ease of description to describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to encompass different orientations of material other than those depicted in the figures. For example, if the material in the figures were reversed, an element described as “below,” “under,” “below,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of that element or feature. Thus, depending on the context in which the term is used, the term “below” can encompass both the above and below orientations, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0023] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of a structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is generally parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is generally perpendicular to the principal plane of the structure. The principal plane of a structure is defined by its surfaces, which have a relatively large area compared to the other surfaces of the structure.

[0024] As used herein, the term “configured” refers to the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device that facilitates the operation of one or more of the structure and device in a predetermined manner.

[0025] As used herein, features described as “adjacent” to each other (e.g., region, material, structure, device) refer to and include the features located closest to each other (e.g., closest to) the disclosed identities (or identities). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identities (or identities) of “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features are inserted between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one “adjacent” feature is positioned between “adjacent” features. As used herein, features described as “vertically adjacent” to each other refer to and include the features located most vertically adjacent to each other (e.g., vertically closest to) the disclosed identities (or identities). Furthermore, features described as “horizontally adjacent” to each other refer to the features located most horizontally adjacent to each other (e.g., horizontally closest to) the disclosed identities (or identities).

[0026] As used in this article, the term "pitch" refers to the distance between identical points in two adjacent (i.e., neighboring) features.

[0027] As used herein, referring to an element as "on" or "above" another element means and includes that the element is directly on top of the other element, directly adjacent to (e.g., directly laterally adjacent to, directly perpendicularly adjacent to) the other element, directly below the other element, or in direct contact with the other element. It also includes that the element is indirectly on top of, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly perpendicularly adjacent to) the other element, indirectly below the other element, or near the other element, wherein other elements exist between them. In contrast, when an element is referred to as "directly on" or "directly adjacent" to another element, there are no intermediate elements.

[0028] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., via another structure) electrical connection.

[0029] As used herein, the term "selective etching" means and includes a material that exhibits a greater etching rate relative to another material exposed to a given etching chemical in response to exposure to the same etching chemical. For example, the material may exhibit an etching rate at least about three times (3x) greater than that of another material, such as about five times (5x), or about ten times (10x), about twenty times (20x), or about forty times (40x) greater than that of another material. Those skilled in the art can select the etching chemicals and etching conditions used to selectively etch the desired material.

[0030] As used herein, “subtractive patterning” refers to one or more processing actions in which a structure to be defined is formed by removing material. For example, a “subtractive patterning process” may involve forming an etch mask structure over an area to be patterned, followed by etching, such that material in the exposed area is removed by the etching removal process while material in the area masked by the mask structure is protected.

[0031] As used herein, the term "air gap" refers to a volume that extends into or through another region or material, or between regions or materials, leaving a void within or between said other region or material, without solid and / or liquid material. An "air gap" does not necessarily contain no gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or combinations thereof) and does not necessarily contain "air". An "air gap" may be, but is not necessarily, a void (e.g., an unfilled volume, a vacuum).

[0032] As used herein, the term "generally" in relation to a given parameter, property, or condition means and includes, as would be understood by one of ordinary skill in the art, the degree to which a given parameter, property, or condition satisfies variance, such as being within an acceptable tolerance range. For example, depending on the specific parameter, property, or condition that is generally satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0033] As used herein, the term "substrate" means and includes the material (e.g., base material) on which additional material is formed or the structure thereon. A substrate can be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. Materials on a semiconductor substrate may include, but are not limited to, semiconducting materials, insulating materials, conductive materials, etc. A substrate can be a conventional silicon substrate or other bulk substrate that includes layers of semiconducting material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator (SOI) substrates (e.g., silicon-on-sapphire (SOS) and silicon-on-glass (SOG) substrates), epitaxial silicon layers on a base semiconductor substrate, and other semiconductor or optoelectronic materials (e.g., silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). Substrates may be doped or undoped.

[0034] Figures 1A to 1F A method for forming a device is described according to embodiments of this disclosure, wherein the device comprises an air gap between conductive lines (e.g., data lines, also referred to as bit lines) at various stages of the method, and is a device structure (e.g., a microelectronic device structure). For simplicity, the formation of a single device structure is described, but those skilled in the art will understand that the method may include simultaneously forming multiple (e.g., more than one, an array) device structures. For ease of description... Figures 1A to 1F The first direction can be defined as the direction, in Figures 1A to 1F The X direction is shown in the diagram. A second direction, which is laterally (e.g., perpendicular) to the first direction, can be defined as the Y direction, and a third direction, which is laterally (e.g., perpendicular) to each of the first and second directions, can be defined as the Z direction. For example, in... Figure 2 As shown in the figure, similar directions are defined, which will be discussed in more detail below.

[0035] refer to Figure 1A This illustrates a partial fabrication apparatus structure 100 for a device (e.g., a microelectronic device, a memory device). Figure 1A The device structure 100, partially fabricated at the process stage shown herein, can be formed using conventional techniques not described in detail herein. The device structure 100 includes a first insulating material 102 overlaid with a substrate material (not shown). In some embodiments, the first insulating material 102 comprises a single insulating material (e.g., a dielectric material). In other embodiments, the first insulating material 102 comprises a stack of alternating materials. For example, the stack of alternating materials may comprise alternating layers of a first dielectric material and a second dielectric material that are different from each other. Prior to forming the device structure 100, at least some of the alternating layers of dielectric materials in the first insulating material 102 may be replaced with a conductive material. Therefore, the stack of alternating materials may comprise alternating dielectric and conductive materials.

[0036] The first insulating material 102 (e.g., an insulating structure of alternating stacked materials) may be formed of and comprise at least one dielectric material, such as one or more of the following: dielectric oxide materials (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of them), dielectric nitride materials (e.g., SiN) y ), dielectric oxide nitride materials (e.g., SiO2) x N y ) and dielectric carboxynitride materials (e.g., SiO2) x C z N y In some embodiments, the first isolation material 102 is formed of and contains SiO2. The first isolation material 102 may be formed using one or more conventional deposition techniques, including, but not limited to, one or more of conventional CVD or conventional ALD processes.

[0037] As in Figure 1A As shown, the columnar structure 104 may extend vertically through the first insulating material 102. The columnar structure 104 may be formed in the array region and may be configured as a memory columnar structure (e.g., a channel columnar structure). The columnar structure 104 may exhibit a generally rectangular cross-sectional shape (e.g., a generally square cross-sectional shape). However, this disclosure is not limited thereto. As a non-limiting example, in an additional embodiment, the columnar structure 104 exhibits a generally circular cross-sectional shape. Additionally, the pitch between horizontally adjacent columnar structures 104 may range from about 50 nm to about 200 nm, for example, from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm. In some embodiments, for example, the critical dimension of the individual columnar structure 104 along the horizontal direction is in the range of about 20 nm to about 200 nm, for example, from about 20 nm to about 50 nm, from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm.

[0038] The columnar structure 104 may be formed in an opening extending vertically (e.g., along the Z direction) through the first insulating material 102. For example, the columnar structure 104 may be formed in a high aspect ratio (HAR) opening, such as having an aspect ratio of at least about 20:1, at least about 40:1, at least about 50:1, at least about 60:1, at least about 80:1, or at least about 100:1. In some embodiments, the opening of the columnar structure 104 may have an aspect ratio in the range of about 20:1 to about 40:1. Individual columnar structures 104 include channel material surrounding a unit membrane 104a of the filling material 104b. For example, the unit membrane 104a may include unit material formed within the opening, and channel material forming adjacent unit material (e.g., above it). For convenience, the unit material and channel material are... Figure 1A The description refers to a single material (e.g., unit film 104a). However, unit film 104a is understood to include both unit material and channel material. The unit material and channel material are formed using conventional techniques (e.g., by CVD or ALD). For example, the unit material may be an oxide-nitride-oxide (ONO) material, such as silicon oxide-silicon nitride-silicon oxide, which is conformally formed above the sidewalls of the columnar structure 104. The unit material may be formed with a smaller relative thickness than the channel material. The channel material may be conformally formed adjacent to (e.g., above) the unit material. For example, the channel material may be polycrystalline silicon. The filler material 104b may substantially fill the openings near (e.g., above) the channel material forming adjacent unit film 104a. The filler material 104b may be an insulating material, such as a high-quality silicon oxide material. For example, the filler material 104b may be a highly uniform and highly conformal silicon oxide material (e.g., a highly uniform and highly conformal silicon dioxide material). The filler material 104b can be highly uniform and highly conformal during deposition. The filler material 104b can be formed using conventional techniques, such as ALD. In some embodiments, the filler material 104b is ALD SiO. x The filler material 104b may initially be formed in an opening in the first insulating material 102 and above an exposed horizontal surface, wherein the filler material 104b above the first insulating material 102 is subsequently removed, for example by an abrasive planarization process (e.g., chemical mechanical planarization (CMP)). Thus, the filler material 104b is surrounded by the unit material of the unit membrane 104a and the channel material. At least a portion of the unit membrane 104a and the filler material 104b of the columnar structure 104 are operatively coupled (e.g., electrically connected) to the source structure underlying the first insulating material 102, as described below. Figure 2 Further detailed description.

[0039] Continue to refer to Figure 1AA conductive plug structure 106 (e.g., a drain contact plug material) may be formed within the upper portion of the columnar structure 104. The conductive plug structure 106 may be formed via a channel material adjacent to (e.g., on or above) the filler material 104b and laterally adjacent to the unit cell film 104a. The conductive plug structure 106 may be electrically coupled to the channel material of the unit cell film 104a. The conductive plug structure 106 may include a semiconductor material, such as one or more of polysilicon, silicon-germanium, and germanium. The conductive plug structure 106 may be conductively doped. The process for forming the conductive plug structure 106 may be, for example, CVD or ALD.

[0040] Contact structure 110 (e.g., contact point, bit line contact) may be formed by forming adjacent to (e.g., on or above) the uppermost surface of conductive plug structure 106. Contact structure 110 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional process equipment not described in detail herein. For example, a portion of the dielectric material (e.g., first insulating material 102) covering conductive plug structure 106 may be removed (e.g., by conventional optical lithography patterning and etching processes) to form plug openings of conductive plug structure 106, conductive material may be deposited into plug openings, and a portion of the conductive material may be removed (e.g., by CMP process) to form contact structure 110.

[0041] Contact structure 110 may be formed of at least one conductive material and includes at least one conductive material, such as one or more of the following: metal, alloy, conductive metal oxide, conductive metal nitride, conductive metal silicide, and conductive doped semiconductor material. By non-limiting example, contact structure 110 may be formed of one or more of the following and includes one or more of the following: tungsten (W), tungsten nitride (WN) y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x ), titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z ) and conductive doped silicon. In some embodiments, the contact structure 110 is formed of and contains tungsten (W).

[0042] The outer surface (e.g., sidewall) of the contact structure 110 may exhibit a tapered profile, wherein the upper portion of an individual contact structure 110 has a larger critical dimension (e.g., width) than its lower portion, as in Figure 1A As shown in the illustration. In other embodiments, the contact structure 110 has different profiles, such as a generally orthogonal (e.g., generally rectangular) profile, a disc-shaped profile, or any other three-dimensional recessed shape, such that at least a portion of the contact structure 110 (e.g., the lateral extent of the upper surface 112) extends beyond the sidewalls of the columnar structure 104 in at least one lateral direction (e.g., the X direction). Additional portions of the dielectric material, collectively referred to as the first insulating material 102, may be formed adjacent to (e.g., on or above) the upper surface 112 of the contact structure 110.

[0043] Next reference Figure 1B Interconnect structures 114 (e.g., contact vias, bitline vias) may be formed adjacent to (e.g., on or above) an upper surface 112 adjacent to the contact structure 110. Interconnect structures 114 may be formed using one or more conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional process equipment not described in detail herein. For example, a portion of the first insulating material 102 covering the contact structure 110 may be removed (e.g., by conventional optical lithography patterning and etching processes) to form via openings on the upper surface 112 of the contact structure 110, conductive material may be deposited into the via openings, and a portion of the conductive material may be removed (e.g., by CMP processes) to form the interconnect structure 114.

[0044] Interconnect structure 114 can be formed via a damascene process without using one or more subtractive patterning (e.g., etching) processes. In some embodiments, interconnect structure 114 is formed using a single damascene process, wherein a portion of the first insulating material 102 can be selectively removed to expose a corresponding portion of the upper surface 112 of the contact structure 110 and form a via opening extending through the first insulating material 102. The via opening is defined by the sidewalls of the first insulating material 102 and can be formed using conventional photolithography techniques. One or more dry etching processes can be used to form the via opening. For example, the conductive material of interconnect structure 114 can be formed within the via opening using, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Interconnect structure 114 can alternatively or additionally be formed using conventional techniques using selective CVD deposition. Subsequently, the upper portion of interconnect structure 114 on the upper surface of the first insulating material 102 can be removed (e.g., by CMP treatment).

[0045] In an additional embodiment, the interconnect structure 114 is formed during the formation of the contact structure 110. For example, the interconnect structure 114 may be formed substantially simultaneously with the formation of the contact structure 110 to simplify the manufacturing process. In other words, conductive material of each of the contact structure 110 and the interconnect structure 114 may be deposited in a single deposition operation to substantially fill the extended opening in the first insulating material 102. In such embodiments, the outer surface (e.g., sidewall) of the interconnect structure 114 is initially formed to exhibit a tapered profile, wherein the upper portion of the individual interconnect structure 114 has a critical dimension (e.g., width) larger than its lower portion and / or has a critical dimension (e.g., width) larger than that of the contact structure 110. For example, the interconnect structure 114 may be initially formed to exhibit a lateral extent larger than that of the contact structure 110. A portion of the outer surface of the initial material of the interconnect structure 114 may be removed (e.g., etched) in one or more material removal processes such that the final dimension (e.g., final width) of the interconnect structure 114 is relatively smaller than the dimension of the contact structure 110, as referenced. Figure 1F To elaborate further.

[0046] Interconnect structure 114 may be configured to be positioned above (e.g., directly perpendicularly aligned with) contact structure 110 such that at least a portion of the outer surface of each of interconnect structure 114 and contact structure 110 is aligned with each other. In other words, the outer surface of each of interconnect structure 114 and contact structure 110 may be an elongated continuous portion of conductive material along at least one side thereof. Figure 1B As shown, the interconnect structure 114 may be laterally offset (e.g., positioned off-center or staggered) to facilitate electrical connection with the contact structure 110.

[0047] The interconnect structure 114 may be formed of at least one conductive material and includes at least one conductive material, such as one or more of the following: metal, alloy, conductive metal oxide, conductive metal nitride, conductive metal silicide, and conductive doped semiconductor material. By non-limiting example, the interconnect structure 114 may be formed of one or more of the following and includes one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x ), titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z The interconnect structure 114 is formed of and contains tungsten (W). The interconnect structure 114 may or may not contain a material composition substantially the same as that of the contact structure 110.

[0048] refer to Figure 1C The conductive material 116 may be formed on the upper surface (e.g., on or above) adjacent to each of the first insulating material 102 and the interconnect structure 114. The conductive material 116 may be formed using one or more conventional deposition processes, such as conventional ALD, conventional CVD, and conventional PVD processes. For example, the conductive material 116 may be formed to exhibit a generally continuous, flat material surface above the upper surface of the first insulating material 102 and above the exposed upper surface of the interconnect structure 114. In other words, the conductive material 116 may be formed as a generally continuous portion of material, without separation and without openings (e.g., trenches) formed in the first insulating material 102. See reference... Figure 1D In more detail, the conductive material 116 may be generally planar and may exhibit the desired thickness of the subsequently formed conductive lines. By initially forming the conductive material 116 as a continuous portion of conductive material, the subsequently formed conductive lines (e.g., data lines, bit lines) can be formed without using one or more damascene processes (e.g., single damascene or dual damascene processes).

[0049] The conductive material 116 may be formed of at least one conductive material and may include at least one conductive material, such as one or more of the following: metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. By way of non-limiting examples, the conductive material 116 may be formed of one or more of the following and may include one or more of the following: tungsten (W), tungsten nitride (WN) y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x ), titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO)z ), Ruthenium (Ru), Ruthenium oxide (RuO) z The conductive material 116 is formed of and contains tungsten (W). The conductive material 116 may or may not contain a material composition substantially the same as that of the contact structure 110 and / or the interconnect structure 114.

[0050] Continue to refer to Figure 1C The dielectric material 118 may be formed on an upper surface adjacent to (e.g., on or above) the conductive material 116. The dielectric material 118 may be selectively etched relative to the conductive material 116 and / or subsequently formed material during common (e.g., collectively, mutually) exposure to a first etchant, and the conductive material 116 and / or subsequently formed material may be selectively etched relative to the dielectric material 118 during common exposure to a second different etchant.

[0051] In some embodiments, dielectric material 118 may also be used as a mask material (e.g., a mask, a photoresist material, an anti-reflective coating). Dielectric material 118 may also be referred to herein as a hard mask. By way of non-limiting examples, dielectric material 118 may be formed from and comprise at least one of the following: amorphous carbon, silicon, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, and silicon oxynitride. In some embodiments, dielectric material 118 is formed from and comprises at least one dielectric oxide material (e.g., one or more of silicon dioxide and aluminum oxide). In other embodiments, dielectric material 118 is formed from and comprises silicon nitride. Dielectric material 118 may be homogeneous (e.g., may comprise a single material) or heterogeneous (e.g., may comprise a stack comprising at least two different materials). Dielectric material 118 may be formed using one or more conventional processes (e.g., conventional deposition processes) and conventional process equipment not described in detail herein. For example, dielectric material 118 may be deposited (e.g., by one or more of CVD, PVD, ALD, spin coating) above the upper surface of conductive material 116. In some embodiments, dielectric material 118 is formed to have a dielectric structure 124 formed from dielectric material 118 ( Figure 1D The final height of the structure is larger than the initial height so that the desired height of its individual parts (e.g., individual structures) can be achieved after subsequent processing actions, as described in further detail below.

[0052] Next reference Figure 1D The device structure 100 may be patterned to form an opening 120 having an elongated portion extending along a second direction (e.g., the Y direction). The opening 120 may extend vertically (e.g., along the Z direction) through the dielectric material 118. Figure 1C ), conductive material 116 ( Figure 1CEach of the first insulating material 102 and at least a portion thereof. For example, the opening 120 can be formed by transferring a pattern of the opening and features of the dielectric material 118 into the conductive material 116 covering the first insulating material 102. The patterned dielectric material 118 can be used to selectively remove (e.g., selective etching, selective dry etching) the underlying material in one or more etching processes (e.g., a single etching process) to form the opening 120. The opening 120 can be formed to have a desired depth, which can be selected at least in part based on the desired height of the air gap to be formed by subsequent processing of the device structure 100, as referenced below. Figure 1E Further details are described below.

[0053] In some embodiments, dielectric material 118 ( Figure 1C ), conductive material 116 ( Figure 1C A portion of each of the conductive material 116 and the first insulating material 102 is removed by exposing the respective material to wet etching and / or dry etching chemicals, for example, in one or more material removal processes. The formation of the opening 120 can be used to separate the conductive material 116 into individual portions to form conductive lines 122 (e.g., data lines, bit lines) having elongated portions extending in a second direction, and to separate the dielectric material 118 into individual portions (e.g., segments) to form a dielectric structure 124 covering the conductive lines 122 and having elongated portions extending in a second direction. The conductive lines 122 include an upper surface 122a perpendicularly adjacent to the dielectric structure 124 and a lower surface 122b perpendicularly adjacent to the first insulating material 102. Therefore, the opening 120 can be positioned horizontally adjacent to each of the portions of the dielectric structure 124, the conductive lines 122, and the first insulating material 102. The formation of the opening 120 can also separate the remaining portion of the first insulating material 102 covering the conductive lines 122 into segments 108. In other words, the remaining portion of the first insulating material 102, which is perpendicular to (e.g., under) the conductive wire 122 and separated on both lateral sides (e.g., along the Y direction) by the opening 120, is designated as the first insulating material 102 by the segment 108, as in Figure 1D As shown in the diagram. By controlling the amount of material removed, the opening 120 can extend into a portion of the first insulating material 102, thereby creating an air gap 132 ( Figure 1E It can then form a segment 108 adjacent to the dielectric structure 124, the conductive line 122 and the first insulating material 102.

[0054] In order to form the opening 120, the device structure 100 (in) Figure 1DThe processing stages described herein can be housed in conventional semiconductor tools (e.g., a single chamber of a material removal apparatus or an etching apparatus). Conventional processes (e.g., spin coating, spray coating, dip coating, vapor phase coating, immersion coating, or combinations thereof) and conventional processing equipment not described in detail herein can be used to expose the device structure 100 to one or more etchants. The total depth of the opening 120 can generally correspond to the final height of the dielectric material 118 plus the height of the conductive material 116 plus the height of the segment 108 of the first insulating material 102. Similarly, the height of the air gap 132 can generally correspond to the height of the dielectric structure 124 plus the height of the conductive line 122 plus the height of the segment 108 of the first insulating material 102. Since the dielectric material 118 (…) can be reduced during the formation of the opening 120 due to one or more material removal actions… Figure 1C The dielectric material 118 can be initially formed to have an initial height (e.g., thickness) greater than the final height of the dielectric structure 124 formed from the dielectric material 118, so as to achieve the desired height of the dielectric structure 124.

[0055] Forming opening 120 includes pairs Figure 1C The device structure 100 is subtractively patterned to form conductive lines 122 extending along a second direction (e.g., the Y direction), a dielectric structure 124 covering the conductive lines 122, and segments 108 underlying the conductive lines 122. The opening 120 can be formed by providing an etch mask pattern comprising one or more of a resist, a hard mask, and an anti-reflective coating. For example, the resist can be patterned using an optical lithography process, and the pattern can be transferred to the underlying hard mask and / or anti-reflective layer. Alternative lithography techniques are also possible, including processes without a hard mask layer. If one or more hard mask layers are included, the resist can be removed before using the hard mask during etching of the underlying material. Therefore, the etch mask pattern can be provided by the resist and / or hard mask layer when transferring the pattern to the underlying material. In some cases, the areas blocked by the etching mask pattern are covered by the mask pattern to protect the underlying material from etching (e.g., wet or dry etching), while the exposed areas of the etching mask pattern are areas not covered by the mask pattern to etch the exposed areas of the material to be etched.

[0056] In some embodiments, a subtractive patterning process is performed in a single chamber of a conventional semiconductor tool (e.g., a material removal apparatus, an etching apparatus) with one or more (e.g., a single) material removal actions. An opening 120 is formed through a single etching action, passing through dielectric material 118, conductive material 116, and first insulating material 102. The opening 120 extends vertically adjacent (latitudinally adjacent) to a segment 108 of dielectric structure 124, conductive line 122, and first insulating material 102. For example, by utilizing a subtractive process, the opening 120 and conductive line 122 can be formed without using one or more damascene processes and without forming additional material adjacent to (e.g., underlay) the conductive line 122, which would be necessary to facilitate damascene processes. Conventional device structures typically include another material, such as an etch-stop material (e.g., a nitride material), located between conventional conductive lines (e.g., bit lines) and conventional insulating materials (e.g., oxide materials). Such nitride materials are typically positioned adjacent to conventionally formed bit line vias and can be characterized as so-called "nitride-stop etch" materials. According to embodiments of this disclosure, the interconnect structure 114 may be formed laterally adjacent to the first insulating material 102 (e.g., an oxide material), rather than laterally adjacent to the nitride material. Therefore, forming the opening 120 and conductive line 122 of the apparatus structure 100 using a subtractive patterning process provides an improvement over conventional processes (e.g., a single damascene process) by enabling the opening 120 to be formed to the desired depth in a single processing operation, thus eliminating processing operations and avoiding unnecessary waste of additional insulating material (e.g., nitride material). The interconnect structure 114 may be directly located between and operatively coupled to the contact structure 110 and the conductive line 122.

[0057] In some embodiments, at least a portion of the interconnect structure 114 may be removed during a subtractive patterning process. In such embodiments, the dielectric structure 124 and / or the conductive line 122 are formed to self-align with the underlying conductive material (e.g., the interconnect structure 114) using a so-called “assisted self-alignment” process. Thus, the dielectric structure 124 and the conductive line 122 may be positioned above (e.g., directly perpendicularly aligned with) the interconnect structure 114 such that one of the outer surfaces of each of the dielectric structure 124, the conductive line 122, and the interconnect structure 114 is perpendicularly aligned with each other. In other words, the outer surfaces of each of the dielectric structure 124, the conductive line 122, and the interconnect structure 114 may be directly perpendicularly aligned along at least one side. Alternatively or additionally, at least some of the outer surfaces of the interconnect structure 114 may be adjacent to a first residual portion 126 (e.g., a remaining portion) of the first insulating material 102, which is laterally positioned along a first direction (e.g., the X direction) toward the adjacent interconnect structure 114 and the opening 120 (e.g., therebetween).

[0058] The opening 120 may extend vertically from the upper surface of the dielectric structure 124 to the first insulating material 102, but not to the upper vertical boundary of the contact structure 110 (e.g., the upper surface 112). Therefore, the lower portion of the outer surface of the interconnect structure 114 may laterally face the second residual portion 128 (e.g., the remaining portion) of the adjacent first insulating material 102, which is positioned perpendicular to the adjacent conductive line 122 and the upper surface 112 of the contact structure 110 (e.g., between them) in a vertical direction (e.g., the Z direction). In other words, the remaining portions of the first insulating material 102 (e.g., the first residual portion 126 and the second residual portion 128) may approach the upper surface 112 of the contact structure 110 and the interconnect structure 114 to form an “L-shaped” structure of the first insulating material 102, and define at least some of the openings 120 on at least two consecutive sides. The first residual portion 126 and the second residual portion 128 may protect the contact structure 110 and the interconnect structure 114 from subsequent processing actions, such as material removal actions.

[0059] Individual columnar structures 104, together with corresponding individual contact structures 110 and individual interconnect structures 114, are associated with a single (e.g., one) conductive line 122. For clarity and ease of understanding of the diagrams and associated descriptions, Figure 1D There are no additional columnar structures 104 and corresponding individual contact structures 110 and individual interconnection structures 114. In other words, from Figure 1D From the perspective of the four (4) columnar structures 104 in each group, each of the three (3) additional columnar structures 104 is positioned half a pitch depth in the page plane (e.g., along the Y direction) and associated with three (3) conductive lines 122 in each group of four (4) conductive lines 122. However, this disclosure is not limited thereto, and additional configurations of the columnar structures 104, contact structures 110, interconnect structures 114, and conductive lines 122 may be considered.

[0060] Next, refer to Figure 1EThe second insulating material 130 may be formed adjacent to (e.g., on or above) an exposed upper surface of the dielectric structure 124 to substantially cover the opening 120 and the dielectric structure 124. A portion of the second insulating material 130 may be formed in the opening 120, for example, on the sidewalls of the dielectric structure 124, the conductive line 122, and the segment 108. However, a significant portion of the volume of the opening 120 may be substantially free of the second insulating material 130. The second insulating material 130 may be formed near the top of the opening 120 to seal any unfilled space in its central portion, forming one or more air gaps 132 (e.g., voids, unfilled volumes) within the central portion of the opening 120. In some embodiments, at least some of the air gaps 132 comprise a gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or combinations thereof). In other embodiments, the air gaps 132 comprise a vacuum (e.g., a space completely devoid of matter). Air gap 132 is defined by a portion of a second insulating material 130 within and adjacent to (e.g., above) opening 120. The upper surface of air gap 132 is defined by the lower surface of the second insulating material 130 above opening 120. The lower surface of air gap 132 is defined by the surface of the first insulating material 102 within opening 120, such as the horizontal surface of the first insulating material 102 at the bottom of opening 120. The sidewalls of air gap 132 are defined by the second insulating material 130 within opening 120, for example, on the sidewalls of the dielectric structure 124, conductive line 122, and section 108 of the first insulating material 102. Figure 1F As shown in more detail, the air gap 132 has a height H3 that extends from the upper surface of the dielectric structure 124 to the surface of the first insulating material 102 at the bottom of the opening 120.

[0061] Air gap 132 is laterally adjacent to a first residual portion 126 of dielectric structure 124, conductive line 122, and first insulating material 102. For example, air gap 132 is laterally adjacent to conductive line 122, wherein a portion of air gap 132 extends over a plane of the upper surface 122a of the laterally adjacent conductive line 122 (e.g., laterally adjacent dielectric structure 124), and a portion of air gap 132 extends below a plane of the lower surface 122b of the laterally adjacent conductive line 122 (e.g., laterally adjacent interconnect structure 114 and / or first insulating material 102). In other words, one or more (e.g., a single) air gaps 132 extend laterally between adjacent conductive lines 122, wherein the vertical extent of air gap 132 exceeds the vertical extent of conductive line 122 (e.g., perpendicular to it above and perpendicular to it below). Since a portion of the air gap 132 extends above the midpoint of the air gap 132 and a portion of the air gap 132 extends below the midpoint of the air gap 132 of the conductive wire 122, the air gap 132 can be laterally inserted between adjacent conductive wires 122 and can exhibit a height relatively larger than the height of the conductive wire 122 in the vertical direction, as shown in the reference. Figure 1FTo describe in more detail.

[0062] An air gap 132 may be formed in the central portion of the opening 120 and extend substantially through the height of the opening 120 after the formation of the second insulating material 130. An elongated portion of the air gap 132 may extend in a second direction (e.g., the Y direction), wherein at least a portion of the air gap 132 is positioned close to adjacent conductive lines 122. Furthermore, the air gap 132 may be directly perpendicularly aligned with at least a portion of the contact structure 110, such that at least a portion of the air gap 132 is directly above (e.g., perpendicularly aligned with) a portion of the contact structure 110. In some cases, the air gap 132 may be used as an insulating material having a dielectric constant (k) of about 1. The air gap 132 may limit capacitance (e.g., parasitic capacitance, stray capacitance) and increase short-circuit tolerance between laterally adjacent conductive lines 122, and may reduce crosstalk between them.

[0063] In some embodiments, a portion of the second insulating material 130 may be formed within the opening 120 and adjacent to the side surface (e.g., sidewall) of the dielectric structure 124, the conductive line 122, and / or the segment 108 of the first insulating material 102. The second insulating material 130 may also contact the surface of the first insulating material 102 within the bottom portion of the opening 120. In other words, at least a portion of the second insulating material 130 may be formed in the opening 120 and adjacent (e.g., laterally adjacent to) the dielectric structure 124 and the first residual portion 126, as in... Figure 1E As shown in the diagram. Therefore, in some embodiments, at least a portion of the second insulating material 130 is laterally adjacent to the first insulating material 102. In other embodiments, at least some (e.g., each) openings 120 are substantially without (e.g., substantially absent, substantially completely absent) the second insulating material 130, such that the lower vertical boundary of the second insulating material 130 is positioned at or above the upper surface of the dielectric structure 124, wherein no second insulating material 130 is located within the opening 120. The air gap 132 within the opening 120 may be configured (e.g., sized, shaped, etc.) to reduce parasitic (e.g., stray) capacitance between adjacent conductive lines 122. In some embodiments, the air gap 132 exhibits a generally rectangular profile along at least one horizontal direction (e.g., the X direction), for example, when the opening 120 is without the second insulating material 130. In other embodiments, the air gap 132 exhibits a generally disc-shaped profile, such as a "V-shaped" or "U-shaped" profile, in embodiments containing portions of the second insulating material 130 within the opening 120. In other embodiments, the air gap 132 exhibits a generally conical (e.g., truncated cone, inverted truncated cone, generally Y-shaped) profile or, for example, a so-called "hourglass" (e.g., concave bow) profile.

[0064] The second insulating material 130 may be formed of at least one dielectric material and may contain at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), at least one dielectric oxide nitride material (e.g., SiO2) x N y and at least one dielectric carboxynitride material (e.g., SiO2) x C z N y The second insulating material 130 is formed of and contains SiO2. In some embodiments, the second insulating material 130 is formed of and contains a low-k dielectric material. The second insulating material 130 may or may not contain a material composition substantially the same as at least one dielectric material of the first insulating material 102 (e.g., an insulating structure of alternating stacked materials). The second insulating material 130 may be substantially homogeneous or heterogeneous. If the second insulating material 130 is heterogeneous, the amount of one or more elements contained in the second insulating material 130 may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly, parabolically) throughout different portions of the second insulating material 130. In some embodiments, the second insulating material 130 is substantially homogeneous. In further embodiments, the second insulating material 130 is heterogeneous. The second insulating material 130 may be, for example, a stack of at least two different dielectric materials (e.g., a lamination) and contain a stack of at least two different dielectric materials (e.g., a lamination).

[0065] The second insulating material 130 can be formed using conventional processes (e.g., conventional deposition processes, such as spin coating, blanket coating, CVD, and PVD; conventional material removal processes, such as conventional CMP processes) and conventional processing equipment for realizing the air gap 132, which are not described in detail herein. For example, the second insulating material 130 can be formed on or over a portion of the exposed surface of the dielectric structure 124 using one or more conventional non-conformal deposition processes (e.g., at least one conventional non-conformal PVD process). Thereafter, the second insulating material 130 can undergo at least one conventional planarization process (e.g., at least one conventional CMP process) to promote or enhance the planarity of the upper boundary (e.g., upper surface) of the second insulating material 130. After the formation of the second insulating material 130, the dielectric structure 124 can be retained in the device structure 100 to facilitate the formation of the air gap 132 adjacent to the conductive line 122. By using the dielectric material 118 of the dielectric structure 124 during the subtractive patterning process ( Figure 1C As a mask and by allowing the formation of an air gap 132 adjacent to the conductive line 122, the dielectric structure 124 serves more than one (e.g., dual) purpose by allowing the device structure 100 to be formed with fewer processing steps and less material than conventional device structures.

[0066] Figure 1F for Figure 1E An enlarged view of part of the device structure 100. (As shown in...) Figure 1F As shown, each air gap 132 may include an upper portion 132a, a central portion 132b (e.g., a midpoint), and a lower portion 132c. For illustrative purposes, the upper portion 132a is separated from the lower portion 132c by the central portion 132b. The central portion 132b may be laterally adjacent to the midpoint 134 (e.g., the midpoint in the vertical direction) of the conductive line 122, wherein a portion of the air gap 132 extends above the central portion 132b of the air gap 132 and a portion of the air gap 132 extends below the central portion 132b of the air gap 132 relative to the vertical midpoint 134 of the conductive line 122. In some embodiments, the upper portion 132a and the lower portion 132c are substantially the same height, such that the vertical height of the upper portion 132a of the air gap 132 is substantially the same (e.g., substantially equal) as the vertical height of the lower portion 132c of the air gap 132.

[0067] Although the device structure 100 is in Figure 1FThe illustration shows a specific (e.g., symmetrical) orientation of the upper portion 132a and lower portion 132c of the air gap 132 relative to the vertical midpoint 134 of the conductive line 122. This arrangement is shown for illustrative purposes only, and any configuration of the device structure 100 including other (e.g., asymmetrical) orientations of the upper portion 132a and lower portion 132c of the air gap 132 relative to the vertical midpoint 134 of the conductive line 122 can be considered. For example, the upper portion 132a and lower portion 132c may extend to unequal heights above and below the central portion 132b, such that the height of at least some of the upper portions 132a of the air gap 132 is different from (e.g., substantially not equal to) the height of the lower portion 132c. For example, in at least some of the air gaps 132, the height of the upper portion 132a may be greater than or alternatively less than the height of the lower portion 132c. The height of the upper portion 132a and lower portion 132c of the air gap 132 relative to the central portion 132b can be at least partially attributed to the height of the dielectric structure 124 above the central portion 132b and the height of the opening 120 within the first insulating material 102. The vertical orientation of the air gap 132 can be tailored (e.g., selected) to meet the design criteria of a particular device structure.

[0068] Conductive material 116 of conductive wire 122 Figure 1C The conductive material 116 can be formed to have a desired height H1. The height H1 of the conductive material 116 can be selected at least in part based on the desired height of the conductive line 122. By way of non-limiting examples, the height H1 of the conductive line 122 can be in the range of about 5 nm to about 50 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm.

[0069] Dielectric material 118 of dielectric structure 124 Figure 1C It can be formed to have the desired height H2. (See above for reference.) Figure 1DAs discussed, the dielectric material 118 may initially be formed to have a greater height in order to achieve the desired height H2 of the dielectric structure 124. The height H2 of the dielectric structure 124 may be selected at least in part based on the desired vertical offset (e.g., along the Z direction) between the conductive lines 122 and additional structures formed on or above the dielectric structure 124 by subsequent processing of the device structure 100 to be passed through. The height H2 of the dielectric structure 124 may be selected at least in part based on the desired height of the air gap 132 located between adjacent conductive lines 122 and extending above the central portion 132b. By non-limiting example, the height H2 of the dielectric structure 124 may be in the range of about 5 nm to about 50 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 40 nm, or from about 40 nm to about 50 nm. In some embodiments, the height H2 of the dielectric structure 124 is substantially equal to the height H1 of the conductive line 122.

[0070] As referenced above Figure 1E As discussed, the air gap 132 is laterally adjacent to the conductive line 122, wherein the upper portion 132a of the air gap 132 extends over the plane of the upper surface 122a of the laterally adjacent conductive line 122 (e.g., laterally adjacent dielectric structure 124), and the lower portion 132c of the air gap 132 extends below the plane of the lower surface 122b of the laterally adjacent conductive line 122 (e.g., laterally adjacent interconnect structure 114 and / or the segment 108 of the first insulating material 102). Therefore, the upper portion 132a of each air gap 132 extends laterally to the adjacent dielectric structure 124 and laterally to the upper portion of the adjacent conductive line 122 (e.g., above its vertical midpoint 134), and the lower portion 132c extends laterally to the adjacent interconnect structure 114 and / or the segment 108 of the first insulating material 102 and laterally to the lower portion of the adjacent conductive line 122 (e.g., below its vertical midpoint 134). The opening 120 may be formed to have a desired height H3. The height H3 of the opening 120 may be selected at least in part based on the desired height of the air gap 132 formed therein. In some embodiments, the height H3 of the air gap 132 corresponds to the height H3 of the opening 120. By non-limiting example, the height H3 of the opening 120 and therefore the air gap 132 may be in the range of about 30 nm to about 200 nm, for example, from about 30 nm to about 50 nm, from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm. In some embodiments, the height H3 of the air gap 132 is in the range of about 50 nm to about 100 nm.

[0071] The height H3 of the air gap 132 can be relatively larger than the height H1 of the conductive wire 122 or the height H2 of the dielectric structure 124. Furthermore, the height H3 of the air gap 132 can be relatively larger than the combined height of the conductive wire 122 height H1 and the dielectric structure 124 height H2, such as... Figure 1F As shown in the diagram. In some embodiments, the opening 120 has an aspect ratio (e.g., high aspect ratio (HAR)) in the range of about 5:1 to about 40:1, such as between about 5:1 and about 10:1, between about 10:1 and about 20:1, or between about 20:1 and about 40:1. The height H3 of the opening 120 and therefore the air gap 132 may be relatively smaller than the depth D1 of the contact structure 110 within the device structure 100. The depth D1 may correspond to the distance (e.g., along the Z direction) between the upper surface of the dielectric structure 124 and the upper surface 112 of the contact structure 110, such that at least some of the first insulating material 102 (e.g., its second residual portion 128) extends between the air gap 132 and the upper surface 112 of the contact structure 110. In other words, the second residual portion 128 separates the air gap 132 from the upper surface 112 of the contact structure 110.

[0072] Continue to refer to Figure 1F The interconnect structure 114 may have a width W1 (e.g., a horizontal dimension along the X direction), and the contact structure 110 may have a width W2 larger than the width W1 of the interconnect structure 114 (e.g., obtained from its upper surface 112). By non-limiting example, the width W1 of the interconnect structure 114 may be in the range of about 10 nm to about 100 nm, for example, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 50 nm, or from about 50 nm to about 100 nm, and the width W2 of the contact structure 110 may be in the range of about 20 nm to about 200 nm, for example, from about 20 nm to about 50 nm, from about 50 nm to about 100 nm, or from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm. In some embodiments, the width W1 of the interconnect structure 114 is in the range of about 10 nm to about 50 nm, and the width W2 of the contact structure 110 is in the range of about 50 nm to about 150 nm.

[0073] The opening 120 and therefore the air gap 132 (e.g., at its maximum horizontal extent) may have a width W3, and the conductive line 122 may have a width W4 that is relatively smaller than the width W3 of the air gap 132. By way of non-limiting examples, the width W3 of the air gap 132 may be in the range of about 10 nm to about 100 nm, for example from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 30 nm to about 50 nm, or from about 50 nm to about 100 nm, and the width W4 of the conductive line 122 may be in the range of about 10 nm to about 100 nm, for example from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 50 nm, or from about 50 nm to about 100 nm. In some embodiments, the width W3 of the air gap 132 is in the range of about 20 nm to about 100 nm, and the width W4 of the conductive line 122 is in the range of about 10 nm to about 60 nm. Furthermore, the width W3 of the air gap 132 may, for example, be larger than the width W4 of the conductive line 122 by about 1% to about 500% (e.g., from about 10% to about 250%, from about 25% to about 125%, from about 50% to about 100%). In other embodiments, the width W4 of the conductive line 122 is greater than or alternatively subsequently equal to the width W3 of the air gap 132.

[0074] Furthermore, the pitch 136 between horizontally adjacent conductive lines 122 can range from about 20 nm to about 200 nm, for example from about 20 nm to about 50 nm, from about 50 nm to about 100 nm, or from about 100 nm to about 200 nm. The pitch 136 includes a first width 136a corresponding to the width W4 of the conductive line 122 and a second width 136b corresponding to the width W3 of the air gap 132. In some embodiments, the line width:space width ratio (e.g., the ratio of the width of the conductive line 122 to the width of the air gap 132) is less than one (1). In other words, the width W4 of the conductive line 122 is relatively smaller than the width W3 of the air gap 132. In other words, the lateral extent of the conductive line 122 along at least one horizontal direction (e.g., along the X direction) is a small fraction of the extent of the opening 120 and therefore the air gap 132. In some embodiments, the line:space ratio (e.g., W4:W3 ratio) is substantially uniform (e.g., 1:1). In other embodiments, the line-to-space ratio is greater than 1:1 (e.g., 60:40, 70:30, or 80:20). The line-to-space ratio can be tailored to have a desired value between the width W4 of the conductive line 122 and the width W3 of the air gap 132, which can be selected at least in part based on the design requirements of the device structure 100.

[0075] Several advantages are achieved by forming the device structure 100 using the processes described above (e.g., the subtractive patterning process for the conductive lines 122). By using the subtractive process, the critical dimension (e.g., width) of the conductive lines 122 can be relatively smaller than the critical dimension (e.g., width) of the air gap 132 laterally between them, thereby reducing the parasitic capacitance between adjacent conductive lines 122. Because the opening 120 is laterally adjacent to the conductive line 122, with a portion of the opening 120 extending over the plane of the upper surface 122a of the laterally adjacent conductive line 122 (e.g., the plane of the laterally adjacent dielectric structure 124) and a portion of the opening 120 extending below the plane of the lower surface 122b of the laterally adjacent conductive line 122 (e.g., the plane of the laterally adjacent interconnect structure 124 and the first insulating material 102), and an air gap 132 located within the opening 120 is laterally adjacent to the conductive line 122, with a portion of the air gap 132 extending over the plane of the upper surface 122a of the laterally adjacent conductive line 122 and a portion of the air gap 132 extending below the plane of the lower surface 122b of the laterally adjacent conductive line 122, the parasitic capacitance between adjacent conductive lines 122 is further reduced. The air gap 132 according to embodiments of this disclosure can reduce the capacitance between adjacent conductive lines 122 by up to 65%. In some cases, the reduced capacitance can then provide a reduction in programming time of between about 5% and about 10%. Extending the air gap 132 below the conductive line 122 also allows for a reduction in parasitic capacitance between laterally adjacent interconnect structures 114. This is because the conductive line 122 is created by removing a portion of the conductive material 116 (…). Figure 1C The air gap 132 can be formed by removing not only a portion of the conductive material 116 but also a portion of the first insulating material 102 beneath the conductive material 116. Therefore, a subtractive process can be used to open 120 and subsequently form the air gap 132 to a depth extending beneath the conductive material 116. The subtractive patterning process of the conductive line 122 further allows the interconnect structure 114 to self-align with the conductive line 122, allowing for a further reduction in the dimensions (e.g., pitch) between adjacent interconnect structures 114.

[0076] Furthermore, the air gap 132 in the device structure 100 according to embodiments of the present disclosure allows for the use of a low-resistivity conductive material for the conductive line 122. For example, a subtractive patterning process allows the conductive line 122 to be formed from and contain tungsten (e.g., tungsten nitride) material formed using a PVD process, rather than tungsten material formed using a CVD process. Moreover, by using the subtractive method and the resulting material, at least one critical dimension (e.g., width, height) of the conductive line 122 can be relatively smaller than the dimensions of conventional conductive lines (e.g., bit lines) in conventional device structures. Therefore, the RC (resistance-capacitance product) of the conductive line 122 can be optimized, which can be associated with increased performance of a device containing the device structure 100 by allowing a reduction in operating speed (e.g., programming time). Furthermore, the methods of the present disclosure can reduce or eliminate process behaviors, such as the formation of etch-stop materials, for forming many conventional devices that can be used for operations similar to the device structure 100. The device structure 100 according to embodiments of the present disclosure is formed using fewer processing actions than conventional device structures by employing a single material removal action within a single chamber. In some cases, the processing actions can be reduced by half compared to conventional processing actions.

[0077] The apparatus structure according to embodiments of the present disclosure (e.g., in previous references) Figures 1A to 1F The device structure 100 following the described processing stage may be included in a microelectronic device (e.g., a memory device such as a 3D NAND flash memory device). For example, Figure 2 A simplified partial cross-sectional view of a device 201 (e.g., a microelectronic device) including a device structure 200 (e.g., a microelectronic device structure). The device structure 200 may be substantially similar to the previously referenced... Figures 1A to 1F The device structure 100 following the described processing stage. Throughout the entire... Figure 2 And in the related descriptions below, it is functionally similar to the previous reference. Figures 1A to 1F Features (e.g., structure, material, region) of one or more of the described device structures 100 are referred to by similar reference numerals incrementing by 100. To avoid duplication, features are not described in detail herein. Figure 2 All features shown in [the document]. Rather, unless otherwise described below, [the following is not included]. Figure 2 In, by reference number (which is a previous reference) Figures 1A to 1F The feature specified (incremented by 100 from the reference number of one or more of the described features) will be understood as being substantially similar to the previously described features and formed in substantially the same manner as the previously described features.

[0078] As in Figure 2 As shown, the device structure 200 of device 201 (including the previously referenced) Figures 1A to 1FOne or more of the components described herein may be operatively associated with the stacked structure 242 of device 201. The stacked structure 242 includes a vertically alternating (e.g., along the Z direction) sequence of conductive structures 244 (e.g., access lines, word lines) and insulating structures 246 arranged in layers 248. Additionally, as in Figure 2 As shown, the stacked structure 242 includes a memory array region 242A and a stepped region 242B that is horizontally adjacent (e.g., along the X direction) to the memory array region 242A. As described in further detail below, the device 201 further includes additional components (e.g., features, structures, devices) within the horizontal boundaries of the different regions (e.g., memory array region 242A and stepped region 242B) of the stacked structure 242.

[0079] Each layer 248 of the stacked structure 242 of device 201 may individually include at least one of the conductive structures 244 that are perpendicularly adjacent to at least one of the insulating structures 246. The stacked structure 242 may include a desired number of layers 248. For example, the stacked structure 242 may include conductive structures 244 and insulating structures 246 of ten (8), sixteen (16), thirty-two (32), sixty-four (64), one hundred and twenty-eight (128), or two hundred and fifty-six (256) layers 248 or more.

[0080] The conductive structure 244 of layer 248 of stacked structure 242 may be formed of at least one conductive material and may contain at least one conductive material, such as one or more of the following: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, and Al), at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low-carbon steel, stainless steel), at least one conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped Ge, conductive doped SiGe), and at least one material containing a conductive metal (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structure 244 is formed of and comprises a metallic material (e.g., a metal, such as W; an alloy). In additional embodiments, the conductive structure 244 is formed of and comprises conductive doped polysilicon. Each of the conductive structures 244 may be generally homogeneous, or one or more of the conductive structures 244 may be generally heterogeneous. In some embodiments, each of the conductive structures 244 of the stacked structure 242 is generally homogeneous. In additional embodiments, at least one (e.g., each) of the conductive structures 244 of the stacked structure 242 is heterogeneous. Individual conductive structures 244 may be formed, for example, by and comprise stacks of at least two different conductive materials. The conductive structures 244 of each of the layers 248 of the stacked structure 242 may each be generally planar and may each exhibit a desired thickness.

[0081] The insulating structure 246 of layer 248 of stacked structure 242 may be formed of at least one dielectric material and includes at least one dielectric material, such as one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phosphorosilicate glass, borosilicate glass, borosilicate-phosphorosilicate glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), at least one dielectric oxide nitride material (e.g., SiO2) x N yand at least one dielectric carboxynitride material (e.g., SiO2) x C z N y In some embodiments, the insulating structure 246 is formed of and contains SiO2. Each of the insulating structures 246 may be generally homogeneous, or one or more of the insulating structures 246 may be generally heterogeneous. In some embodiments, each of the insulating structures 246 of the stacked structure 242 is generally homogeneous. In additional embodiments, at least one (e.g., each) of the insulating structures 246 of the stacked structure 242 is heterogeneous. Individual insulating structures 246 may be formed, for example, by a stack of at least two different dielectric materials and contain said stack. The insulating structure 246 of each of the layers 248 of the stacked structure 242 may each be generally planar and may each individually exhibit the desired thickness.

[0082] At least one lower conductive structure 244 of the stacked structure 242 may serve as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the device 201. In some embodiments, a single (e.g., only one) conductive structure 244 of the vertically bottommost layer 248 of the stacked structure 242 may serve as the lower select gate (e.g., SGS) of the device 201. In some embodiments, the upper conductive structure 244 of the stacked structure 242 may serve as the upper select gate (e.g., drain-side select gate (SGD)) of the device 201. In some embodiments, the horizontally adjacent (e.g., along the Y direction) conductive structure 244 of the vertically topmost layer 248 of the stacked structure 242 may serve as the upper select gate (e.g., SGD) of the device 201. In other embodiments, the upper select gate of the device 201 may be vertically positioned on top of the stacked structure 242 (e.g., within an additional stacked structure (not shown) of multiple stacked devices), covering the stacked structure 242.

[0083] Still referencing Figure 2 Within the horizontal boundaries of the memory array region 242A of the stacked structure 242 (e.g., along the X and Y directions), the device 201 may include a columnar structure 204 extending vertically through the stacked structure 242. (As in...) Figure 2 As shown, the columnar structure 204 can be formed to extend substantially perpendicularly through the stacked structure 242. The columnar structure 204, comprising channel material of the unit membrane 204a surrounding the filler material 204b, can correspond to the columnar structure 104, comprising channel material of the unit membrane 104a surrounding the filler material 104b, previously referenced herein. Figure 1A As described. For clarity and ease of understanding of the diagrams and associated descriptions, the conductive plug structure 206 is... Figure 2 The above reference does not exist. Figure 1A The conductive plug structure 106 is depicted and described.

[0084] The device structure 200 can be formed to include a desired quantity (e.g., number, amount) of columnar structures 204. Although Figure 2 Device structure 200 is depicted as being formed to include three (3) columnar structures 204, but device structure 200 may be formed to include more than three (3) (e.g., greater than or equal to eight (8)), greater than or equal to sixteen (16), greater than or equal to thirty-two (32), greater than or equal to sixty-four (64), greater than or equal to one hundred and twenty-eight (128), greater than or equal to two hundred and fifty-six (256)) columnar structures 204. The intersection of the columnar structures 204 and conductive structures 244 of the layers 248 of the stacked structure 242 may define a vertically extending string of memory cells 256 coupled in series with each other within the memory array region 242A of the stacked structure 242. In some embodiments, the memory cells 256 formed at the intersection of the conductive structures 244 and columnar structures 204 within each layer 248 of the stacked structure 242 include so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In an additional embodiment, memory cell 256 includes so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells or so-called "BETANOS" (band / barrier engineered TANOS) memory cells, each being a subgroup of MONOS memory cells. In other embodiments, memory cell 256 includes so-called "floating gate" memory cells, which include a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate may be horizontally inserted between the central structure of pillar structure 204 and the conductive structures 244 of different layers 248 of stacked structure 242. Device 201 may include any desired number and distribution of pillar structures 204 within the memory array region 242A of stacked structure 242.

[0085] The device 201 may further include conductive lines 222 (e.g., data lines, bit lines) vertically above the stacked structure 242, at least one source structure 260 (e.g., source line, source plate) vertically below the stacked structure 242, and at least one control device 258 for the vertically below source structure 260. A columnar structure 204 may extend vertically between the conductive lines 222 and the source structure 260 (e.g., along the Z direction). The source structure 260 may extend vertically between the stacked structure 242 and the control device 258. The conductive lines 222 and the source structure 260 may each be individually formed of and contain at least one conductive material, such as one or more of the following: metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. By non-limiting example, the conductive lines 222 and / or the source structure 260 may be formed of and contain one or more of the following: tungsten (W), tungsten nitride (WN). y Nickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x ), titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z The device 201 may further include a dielectric structure 224 adjacent to (e.g., on or above) the conductive line 222 and an air gap 232 horizontally adjacent to the adjacent conductive line 222. The dielectric structure 224 and the air gap 232 may correspond to previously referenced materials. Figure 1D to 1F The dielectric structure 124 and air gap 132 are described.

[0086] Continue to refer to Figure 2 The control device 258 may include means and circuitry for various operations of other components of the control device structure 200. By way of non-limiting example, the control device 258 may include one or more of the following (e.g., each): a charge pump (e.g., V... CCP Charge pump, V NEGWLCharge pumps (e.g., DVC2 charge pumps); Delay-locked loop (DLL) circuit systems (e.g., ring oscillators); Drain supply voltage (V dd The control device 258 includes: a regulator; means and circuitry for controlling column operations of an array (e.g., a vertical memory string array) subsequently formed within the device structure 200, such as decoders (e.g., column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry (e.g., column repair circuitry), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), and error checking (ECC) devices; and means and circuitry for controlling row operations of an array (e.g., a vertical memory string array) within the memory region of the device structure 200, such as decoders (e.g., row decoders), drivers (e.g., word line (WL) drivers), repair circuitry (e.g., row repair circuitry), memory test devices, MUX, ECC devices, and self-refresh / loss equalization devices. In some embodiments, the control device 258 includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control device 258 may be characterized as having a “CMOS array under” (“CuA”) configuration.

[0087] Within the horizontal boundary of the stepped region 242B of the stacked structure 242, the stacked structure 242 may include at least one stepped structure 250. The stepped structure 250 includes a step 252 at least partially defined by the horizontal end of the layer 248 (e.g., along the X direction). The step 252 of the stepped structure 250 can serve as a contact area to electrically couple the conductive structure 244 of the layer 248 of the stacked structure 242 to other components (e.g., features, structures, devices) of the device 201, as described in further detail below. The stepped structure 250 may include the desired number of steps 252. Furthermore, as in... Figure 2 As shown, in some embodiments, the steps 252 of each of the stepped structures 250 are arranged in sequence such that steps 252 that are directly horizontally adjacent to each other (e.g., along the X direction) correspond to layers 248 of stacked structures 242 that are directly vertically adjacent to each other (e.g., along the Z direction). In additional embodiments, the steps 252 of the stepped structures 250 are arranged in random order such that at least some steps 252 of the stepped structures 250 that are directly horizontally adjacent to each other (e.g., along the X direction) correspond to layers 248 of stacked structures 242 that are not directly vertically adjacent to each other (e.g., along the Z direction).

[0088] Still referencing Figure 2The device 201 may further include a lower conductive structure 254 that physically and electrically contacts at least some (e.g., each) of the steps 252 of the stepped structure 250 of the stacked structure 242 to provide electrical access to the conductive structure 244 of the stacked structure 242. The lower conductive structure 254 may be coupled at the steps 252 of the stepped structure 250 to the conductive structure 244 of the layer 248 of the stacked structure 242. (As in...) Figure 2 As shown, the lower conductive structure 254 can physically contact and extend vertically upward (e.g., along the positive Z direction) from the conductive structure 244 at the step 252 of the stepped structure 250 to the lower contact structure 262 of an additional structure (e.g., an access device, a vertical transistor) that may be adjacent to the lower contact structure 262 (e.g., on or above it).

[0089] The device 201 may further include a first insulating material 202 adjacent to (e.g., on or above) the stacked structure 242 and a second insulating material 230 adjacent to (e.g., on or above) the first insulating material 202. The first insulating material 202 and the second insulating material 230 may correspond to previously referenced materials. Figures 1A to 1F The first isolation material 102 and the second isolation material 130 are described. (As in...) Figure 2As shown, a first insulating material 202 may be vertically inserted (e.g., along the Z-direction) between the stacked structure 242 and the second insulating material 230. The first insulating material 202 may substantially cover the stepped structure 250 within the stepped region 242B of the stacked structure 242 and may substantially surround the side surface (e.g., sidewall) of the lower conductive structure 254 on the step 252 of the stepped structure 250. The first insulating material 202 may exhibit a generally planar upper vertical boundary and a generally non-planar lower vertical boundary that complements the morphology of at least the stacked structure 242 (including its stepped structure 250) below it. The second insulating material 230 may substantially cover the upper surface of the dielectric structure 224 within the memory array region 242A of the stacked structure 242. The second insulating material 230 may be formed to seal unfilled spaces between adjacent conductive lines 222 to form an air gap 232 therebetween (e.g., void, unfilled volume). Air gap 232 is laterally adjacent to conductive line 222, with a portion of air gap 232 extending above a plane of the upper surface of the laterally adjacent conductive line 222 (e.g., laterally adjacent dielectric structure 224), and a portion of air gap 232 extending below a plane of the lower surface of the laterally adjacent conductive line 222 (e.g., laterally adjacent interconnect structure 214 and / or a segment of the first insulating material 202). In some embodiments, a portion of the second insulating material 230 may be laterally adjacent to a side surface (e.g., a sidewall) of the first insulating material 202. Contact structure 210 may be located via the uppermost surface (e.g., on or above) of a conductive plug structure 206 (not shown) positioned adjacent to the upper portion of the columnar structure 204. Contact structure 210 may correspond to references previously included herein. Figure 1A The contact structure 110 is described.

[0090] Therefore, according to embodiments of this disclosure, a method of forming a device includes forming a columnar structure extending vertically through a first insulating material, forming conductive lines operatively coupled to the columnar structure, forming a dielectric structure covering the conductive lines, and forming air gaps between adjacent conductive lines. The air gaps are laterally adjacent to the conductive lines, wherein a portion of the air gap extends above a plane of an upper surface of the laterally adjacent conductive line, and a portion of the air gap extends below a plane of a lower surface of the laterally adjacent conductive line.

[0091] Furthermore, according to an additional embodiment of this disclosure, a device includes a columnar structure extending vertically through an insulating material, conductive lines operatively coupled to the columnar structure, a dielectric structure covering the conductive lines, and air gaps between laterally adjacent conductive lines. The air gaps are laterally adjacent to the conductive lines, wherein an upper portion of the air gap extends laterally adjacent to the dielectric structure, and a lower portion of the air gap extends laterally adjacent to a segment of the insulating material.

[0092] The microelectronic device embodiments disclosed herein may use device structures 100, 200 (e.g., Figures 1A to 1F and Figure 2 One or more of the devices shown in the diagram. Figure 3 This is a block diagram of an illustrative microelectronic device 300 (e.g., a 3D NAND flash memory device) according to embodiments of the present disclosure. The microelectronic device 300 may include at least one memory cell array 302, such as multiple memory arrays. The microelectronic device 300 may further include at least one peripheral circuit 304 that receives data from an external source, thus providing access to the at least one memory cell array 302. The microelectronic device 300 may further include a charge pump circuit 306 for generating an input voltage. The peripheral circuit 304 and the charge pump circuit 306 may include one or more capacitors. The peripheral circuit 304 and the charge pump circuit 306 may be electrically connected to the at least one memory cell array 302 via capacitors. For example, the microelectronic device 300 may include a memory cell array 302 that may include a complementary metal-oxide-semiconductor (CMOS) region, such as the under-CMOS (CuA) region 308 of the under-memory cell array 302. Memory cell array 302 may include memory cells connected to access lines (e.g., word lines) and data lines (e.g., bit lines). Furthermore, CuA region 308 may underlie memory cell array 302 and include its supporting circuitry. The supporting circuitry may support one or more additional memory cell arrays present in a stacked configuration. For example, microelectronic device 300, including memory cell array 302 with memory cells, may be two-dimensional (2D) to represent a single stack (e.g., single layer, single level) of memory cells, or may be three-dimensional (3D) to represent multiple stacks (e.g., multiple levels, multiple layers) of memory cells. In a stacked configuration, CuA region 308 may facilitate access to one or more memory cells in each array. For example, CuA region 308 may facilitate data transfer between memory cells coupled to channels of memory cell array 302, memory cells coupled to channels of additional memory cell array 302 (which are coupled to memory cell array 302), and a controller.

[0093] Therefore, according to embodiments of this disclosure, a method of forming a memory device includes forming a columnar structure in an opening extending vertically through a stack of alternating conductive and dielectric materials, and forming at least one stepped structure of material comprising the stack of alternating conductive and dielectric materials. The at least one stepped structure is laterally adjacent to the columnar structure. The method includes forming conductive lines covering the columnar structure, forming an electrically insulating material covering at least a portion of the stack, and forming air gaps within additional openings extending at least partially vertically through the stack. The air gaps are inserted between laterally adjacent conductive lines and between portions of the electrically insulating material covering the conductive lines.

[0094] Furthermore, according to an additional embodiment of this disclosure, a memory device including at least one memory cell array is disclosed. The at least one memory cell array includes access lines extending along a first horizontal direction and data lines extending along a second horizontal direction generally transverse to the first horizontal direction. The at least one memory cell array includes an interconnect structure operatively connected to the data lines, a dielectric structure adjacent to the data lines on its side opposite to the interconnect structure, and an air gap extending vertically between the laterally adjacent dielectric structure, the data lines, and the interconnect structure.

[0095] The apparatus structure according to embodiments of this disclosure (e.g., previously referenced) Figures 1A to 1F The described device structure 100) and microelectronic devices (e.g., previously referenced) Figure 2 The described device structure 200) discloses embodiments that can be used in the electronic systems disclosed herein. For example, Figure 4 This is a block diagram of an illustrative electronic system 400 according to embodiments of the present disclosure. The electronic system 400 may include, for example, a computer or computer hardware component, a server, or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, Wi-Fi, or a tablet with cellular functionality, such as... or Tablets, e-books, navigation devices, etc. Electronic system 400 includes at least one memory device 420. Memory device 420 may include embodiments of microelectronic devices (e.g., device structures 100, 200) previously described herein. Electronic system 400 may further include at least one electronic signal processor device 410 (generally referred to as a “microprocessor”). Electronic signal processor device 410 may, as appropriate, include embodiments of microelectronic devices (e.g., device structures 100, 200) previously described herein. Electronic system 400 may further include one or more input devices 430 for inputting information by a user into electronic system 400, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 400 may further include one or more output devices 440 for outputting information to a user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 430 and output device 440 may include a single touchscreen device that can be used to both input information into electronic system 400 and output visual information to a user. The input device 430 and the output device 440 may be electrically connected to one or more of the memory device 420 and the electronic signal processor device 410.

[0096] Therefore, according to embodiments of this disclosure, an electronic system includes at least one input device, at least one output device, at least one processor device operatively coupled to the at least one input device and the at least one output device, and a memory device operatively coupled to the at least one processor device. The memory device includes conductive lines extending in a horizontal direction and air gaps separating horizontally adjacent conductive lines, wherein the ratio of the width of the conductive lines to the width of the air gaps is less than 1.

[0097] Compared to conventional structures, devices, and systems, the structures, devices, and systems of this disclosure advantageously promote one or more of the following: improved simplicity of components, greater packaging density, and increased miniaturization. Compared to conventional devices (e.g., conventional equipment, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems), the methods and structures of this disclosure promote the formation of devices (e.g., equipment, microelectronic devices, memory devices) and systems (e.g., electronic systems) having one or more of the following: improved performance, reliability and durability, lower cost, increased yield, increased component miniaturization, improved pattern quality, and greater packaging density.

[0098] Embodiments of this disclosure may be further characterized without limitation, as set forth below.

[0099] Example 1: A method of forming a device, comprising: forming a columnar structure extending vertically through a first insulating material; forming conductive lines operatively coupled to the columnar structure; forming a dielectric structure covering the conductive lines; and forming air gaps between adjacent conductive lines, the air gaps being laterally adjacent to the conductive lines, wherein a portion of the air gap extends above a plane of an upper surface of the laterally adjacent conductive line, and a portion of the air gap extends below a plane of a lower surface of the laterally adjacent conductive line.

[0100] Example 2: The method according to Example 1 further includes: forming a contact structure adjacent to the columnar structure; and forming an interconnect structure directly between the contact structure and the conductive line and operably coupling thereto.

[0101] Example 3: The method according to Example 2, wherein forming the interconnect structure includes forming the interconnect structure in a single damascene process.

[0102] Example 4: The method according to Example 2 or Example 3, wherein forming the air gap between the conductive lines includes forming an opening extending vertically between each of the dielectric structure, the conductive lines and the interconnect structure in a single chamber of a material removal apparatus during a single material removal process.

[0103] Example 5: According to any one of Examples 1 to 4, at least some of the air gaps are generally symmetrical about the vertical midpoint of the conductive wire.

[0104] Example 6: The method according to any one of Examples 1 to 5, wherein forming the air gap includes forming a second insulating material adjacent to the upper surface of the dielectric structure, at least a portion of the second insulating material being laterally adjacent to the first insulating material.

[0105] Example 7: The method according to any one of Examples 1 to 6, wherein forming the air gap includes extending the air gap between laterally adjacent dielectric structures and extending the air gap between laterally adjacent segments of the first insulating material.

[0106] Example 8: The method according to any one of Examples 1 to 7, wherein forming the conductive line includes forming a continuous portion of conductive material adjacent to the first insulating material, and removing a portion of the conductive material to form the conductive line in a single subtractive patterning process.

[0107] Example 9: A device comprising: a columnar structure extending vertically through an insulating material; conductive wires operatively coupled to the columnar structure; a dielectric structure covering the conductive wires; and an air gap between laterally adjacent conductive wires, the air gap being laterally adjacent to the conductive wires, wherein an upper portion of the air gap extends laterally adjacent to the dielectric structure and a lower portion of the air gap extends laterally adjacent to a segment of the insulating material.

[0108] Example 10: The device according to Example 9, wherein the width of the air gap in the horizontal direction is relatively greater than the width of the conductive wire in the horizontal direction.

[0109] Example 11: The device according to Example 9 or Example 10, wherein the height of the air gap in the vertical direction is relatively greater than the combined height of the conductive wire and the dielectric structure in the vertical direction.

[0110] Example 12: The device according to any one of Examples 9 to 11 further includes an interconnect structure that lies beneath the conductive line and is operatively coupled to the conductive line, the air gap being between laterally adjacent interconnect structures.

[0111] Example 13: The device according to any one of Examples 9 to 12, wherein the dielectric structure includes segmented portions of hard mask material.

[0112] Example 14: The device according to any one of Examples 9 to 13, wherein the height of the air gap is substantially equal to the combined height of the section of the dielectric structure, the conductive wire and the insulating material.

[0113] Example 15: The device according to any one of Examples 9 to 14, wherein a portion of the insulating material forms an L-shaped structure surrounding the air gap on at least two consecutive sides.

[0114] Example 16: A method of forming a memory device, comprising: forming a columnar structure in an opening extending vertically through a stack of alternating conductive and dielectric materials; forming at least one stepped structure comprising materials of the stack of alternating conductive and dielectric materials, the at least one stepped structure being laterally adjacent to the columnar structure; forming conductive lines covering the columnar structure; forming an electrically insulating material covering at least a portion of the stack; forming an additional opening extending at least partially vertically through the stack; and forming a dielectric material adjacent to the electrically insulating material to form an air gap within the additional opening, the air gap being inserted between laterally adjacent conductive lines and between portions of the electrically insulating material covering the conductive lines.

[0115] Example 17: The method according to Example 16 further includes: forming the additional opening to extend vertically through at least each of the electrical insulating material, the conductive wire, and the stacked dielectric material, wherein forming the additional opening includes removing material from each of the electrical insulating material, the conductive wire, and the stacked dielectric material in a single material removal procedure.

[0116] Example 18: The method according to Example 16 or Example 17 further includes forming a conductive via structure under the conductive wire, wherein forming the air gap includes separating laterally adjacent conductive via structures from each other with one or more of the air gaps.

[0117] Example 19: According to the method of Example 18, forming the conductive via structure includes forming the conductive via structure to self-align with the conductive line along at least one side surface of the conductive via structure.

[0118] Example 20: The method according to any one of Examples 16 to 19, wherein forming the air gap within the additional opening includes forming a single air gap between the laterally adjacent conductive lines, the single air gap extending above a plane of the upper surface of the laterally adjacent conductive line and a portion of the air gap extending below a plane of the lower surface of the laterally adjacent conductive line.

[0119] Example 21: The method according to any one of Examples 16 to 20, wherein forming the columnar structure includes forming a memory columnar structure, the memory columnar structure including channel material surrounding a unit film of filling material.

[0120] Example 22: The method according to any one of Examples 16 to 21, wherein the stack of alternating conductive and dielectric materials is formed by vertically forming the stack above a control device comprising a complementary metal-oxide-semiconductor (CMOS) circuit system.

[0121] Example 23: The method according to Example 22 further includes forming a source layer vertically between the control device and the stack.

[0122] Example 24: A memory device comprising: at least one memory cell array including: access lines extending along a first horizontal direction; data lines extending along a second horizontal direction, generally transverse to the first horizontal direction; interconnect structures operatively connected to the data lines; dielectric structures adjacent to the data lines on their sides opposite to the interconnect structures; and air gaps extending perpendicularly between laterally adjacent dielectric structures, data lines, and interconnect structures.

[0123] Example 25: The memory device according to Example 24, wherein the interconnect structure is laterally oriented toward adjacent oxide material but not laterally toward adjacent nitride material.

[0124] Example 26: The memory device according to Example 24 or Example 25, wherein the height of the air gap is in the range of about 50 nm to about 100 nm.

[0125] Example 27: A memory device according to any one of Examples 24 to 26, wherein the width of the data line along the first horizontal direction is relatively smaller than the width of the air gap along the first horizontal direction.

[0126] Example 28: A memory device according to any one of Examples 24 to 27, further comprising: a columnar structure extending vertically through the at least one memory cell array; a source structure underlying the at least one memory cell array; and control means electrically coupled to the data line and the source structure, wherein the columnar structure comprises a string of memory cells electrically coupled to the data line and the source structure.

[0127] Example 29: A memory device according to any one of Examples 24 to 28, wherein the height of the air gap is substantially equal to the combined height of portions of the dielectric structure, the data line, and the interconnect structure.

[0128] Example 30: An electronic system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the at least one input device and the at least one output device; and a memory device operatively coupled to the at least one processor device, the memory device comprising: a conductive line extending in a horizontal direction; and an air gap separating horizontally adjacent conductive lines, wherein the ratio of the width of the conductive line to the width of the air gap is less than 1.

[0129] Example 31: The electronic system according to Example 30 further includes an interconnect structure under the conductive wire and a contact structure under the interconnect structure, wherein the air gap is positioned directly and perpendicularly aligned with at least a portion of the contact structure.

[0130] Example 32: An electronic system according to Example 30 or Example 31, wherein the conductive line includes a bit line and an elongated portion of the air gap extending along the horizontal direction, wherein at least a portion of the air gap is positioned adjacent to the bit line.

[0131] Example 33: An electronic system according to any one of Examples 30 to 32, wherein the memory device includes a 3D NAND flash memory device.

[0132] While specific illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments encompassed by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure (such as those claimed below, including legal equivalents). Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being encompassed within the scope of this disclosure.

Claims

1. A method for forming a microelectronic device, comprising: Forming a columnar structure that extends vertically through the first insulating material; Forming a contact structure adjacent to the columnar structure; An interconnect structure is formed adjacent to the contact structure; A conductive line is formed that is operatively coupled to the columnar structure, and the interconnect structure is directly between and operatively coupled to the contact structure and the conductive line; A dielectric structure is formed covering the conductive lines; and In a single material removal process, an opening extending vertically between each of the dielectric structure, the conductive line, and the interconnect structure is formed in a single chamber of the material removal apparatus to form an air gap between adjacent conductive lines, the air gap being laterally adjacent to the conductive line, wherein a portion of the air gap extends above a plane on the upper surface of the conductive line and a portion of the air gap extends below a plane on the lower surface of the conductive line.

2. The method of claim 1, wherein forming the interconnect structure comprises forming the interconnect structure in a single damascene process.

3. The method according to any one of claims 1 to 2, wherein at least some of the air gaps are substantially symmetrical about the vertical midpoint of the conductive wire.

4. The method according to any one of claims 1 to 2, wherein forming the air gap includes forming a second insulating material adjacent to the upper surface of the dielectric structure, at least a portion of the second insulating material being laterally adjacent to the first insulating material.

5. The method according to any one of claims 1 to 2, wherein forming the air gap includes extending the air gap between laterally adjacent dielectric structures and extending the air gap between laterally adjacent segments of the first insulating material.

6. The method according to any one of claims 1 to 2, wherein forming the conductive line includes forming a continuous portion of conductive material adjacent to the first insulating material, and removing a portion of the conductive material to form the conductive line in a single subtractive patterning process.

7. A microelectronic device comprising: A columnar structure that extends vertically through the insulating material; A conductive plug structure is located within the upper portion of the columnar structure; Conductive wires that are operatively coupled to the columnar structure; A dielectric structure covered with the conductive lines; and An air gap, located between laterally adjacent conductive lines, is perpendicularly aligned with and laterally adjacent to a portion of the conductive plug structure, wherein the upper portion of the air gap extends laterally adjacent to the dielectric structure, and the lower portion of the air gap extends laterally adjacent to a section of the insulating material.

8. The microelectronic device according to claim 7, wherein the width of the air gap in the horizontal direction is relatively greater than the width of the conductive line in the horizontal direction.

9. The microelectronic device of claim 7, wherein the height of the air gap in the vertical direction is relatively greater than the combined height of the conductive line and the dielectric structure in the vertical direction.

10. The microelectronic device according to any one of claims 7 to 9, further comprising an interconnect structure underlying and operatively coupled to the conductive line, the air gap being laterally adjacent to the interconnect structure.

11. The microelectronic device according to any one of claims 7 to 9, wherein the dielectric structure comprises segmented portions of hard mask material.

12. The microelectronic device according to any one of claims 7 to 9, wherein the height of the air gap is substantially equal to the combined height of the section of the dielectric structure, the conductive line and the insulating material.

13. The microelectronic device according to any one of claims 7 to 9, wherein a portion of the insulating material forms an L-shaped structure surrounding the air gap on at least two consecutive sides.

14. The microelectronic device of claim 7, wherein the conductive plug structure is laterally adjacent to and electrically coupled to the channel material of the columnar structure.

15. A method of forming a memory device, comprising: A columnar structure is formed in an opening that extends vertically through an alternating stack of conductive and dielectric materials; At least one stepped structure is formed, the at least one stepped structure comprising stacked materials of alternating conductive and dielectric materials, the at least one stepped structure being laterally adjacent to the columnar structure; A contact structure formed above the columnar structure; A generally continuous portion of the conductive material formed above the contact structure; An electrically insulating material formed over at least a portion of the stack; Additional openings extending at least partially vertically through the stack are formed by removing portions of the generally continuous portion of the conductive material to form conductive lines; and A dielectric material is formed adjacent to the electrical insulating material to form an air gap within the additional opening, the air gap being inserted between laterally adjacent conductive lines and perpendicularly aligned with a portion of the contact structure, and the air gap being between portions of the electrical insulating material covering the conductive lines.

16. The method of claim 15, further comprising forming the additional opening to extend vertically through at least each of the electrical insulating material, the conductive wire, and the stacked dielectric material, wherein forming the additional opening includes removing material from each of the substantially continuous portions of the electrical insulating material, the conductive material, and the stacked dielectric material in a single material removal procedure.

17. The method of claim 15 or claim 16, further comprising forming a conductive via structure underlying the conductive wire, wherein forming the air gap comprises separating laterally adjacent conductive via structures from each other using one or more of the air gaps.

18. The method of claim 17, wherein forming the conductive via structure comprises forming the conductive via structure to self-align with the conductive line along at least one side surface of the conductive via structure.

19. The method of claim 15 or claim 16, wherein forming the air gap within the additional opening comprises forming a single air gap between the laterally adjacent conductive lines, the single air gap extending above a plane of the upper surface of the laterally adjacent conductive line and a portion of the air gap extending below a plane of the lower surface of the laterally adjacent conductive line.

20. The method of claim 15 or claim 16, wherein forming the columnar structure comprises forming a memory columnar structure, the memory columnar structure comprising a channel material surrounding a unit membrane of a filling material.

21. The method of claim 15 or claim 16, wherein the stack of alternating conductive and dielectric materials comprises forming the stack vertically above a control device comprising a complementary metal-oxide-semiconductor (CMOS) circuit system.

22. The method of claim 21, further comprising forming a source layer perpendicularly between the control device and the stack.

23. The method of claim 15, wherein a portion of the stacked dielectric material is vertically inserted between the air gap and the contact structure.

24. A memory device comprising: At least one memory cell array, comprising: Access lines extend along a first horizontal direction; The data cable extends along a second horizontal direction that is generally transverse to the first horizontal direction; An interconnection structure operatively connected to the data line; A contact structure adjacent to the interconnect structure on its side opposite to the data line; A dielectric structure adjacent to the data line on its side opposite to the interconnect structure; and An air gap extends vertically between laterally adjacent dielectric structures, data lines, and interconnect structures, the air gap being perpendicularly aligned with a portion of the contact structure, wherein the width of the data lines along the first horizontal direction is relatively smaller than the width of the air gap along the first horizontal direction.

25. The memory device of claim 24, wherein the interconnect structure is laterally oriented toward adjacent oxide material but not laterally toward adjacent nitride material.

26. The memory device of claim 24, wherein the height of the air gap is in the range of 50 nm to 100 nm.

27. The memory device according to any one of claims 24 to 26, further comprising: A columnar structure that extends vertically through the at least one memory cell array; A source structure, beneath which lies at least one memory cell array; and A control device electrically coupled to the data line and the source structure, wherein the columnar structure includes a string of memory cells electrically coupled to the data line and the source structure.

28. The memory device according to any one of claims 24 to 26, wherein the height of the air gap is substantially equal to the combined height of portions of the dielectric structure, the data line, and the interconnect structure.

29. An electronic system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the at least one input device and the at least one output device; and A memory device operatively coupled to the at least one processor device, the memory device comprising: Conductive wires that extend horizontally; An interconnect structure, beneath which the conductive lines lie; Contact structure, beneath which lies the interconnect structure; and An air gap separates horizontally adjacent conductive lines and is directly and perpendicularly aligned with at least a portion of the contact structure, wherein the ratio of the width of the conductive line to the width of the air gap is less than 1.

30. The electronic system of claim 29, wherein the conductive line includes a bit line and an elongated portion of the air gap extending along the horizontal direction, wherein at least a portion of the air gap is positioned adjacent to the bit line.

31. The electronic system of claim 29, wherein the memory device comprises a 3D NAND flash memory device.

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