Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments of the present application provide a semiconductor storage device capable of forming columnar bodies that penetrate a specified film without enlarging a cross-sectional area, and a manufacturing method of the semiconductor storage device. The semiconductor storage device of the embodiments includes a plurality of columnar bodies that penetrate a specified film, and a beam portion that reaches a specified depth shallower than the plurality of columnar bodies to the specified film, and links the plurality of columnar bodies with a width narrower than the plurality of columnar bodies.

Description

[0001] [Cross-reference to related applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-139687 (filed on August 20, 2020). This application incorporates all the contents of the basic application by reference to that basic application. Technical Field

[0003] The present invention relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. Background Technology

[0004] A type of semiconductor memory device includes a columnar structure that penetrates a designated film, such as a contact connecting upper and lower layer wirings. To reliably penetrate the designated film, sometimes during the design phase of the semiconductor memory device, the cross-sectional area of ​​the columnar structure is increased by making its aspect ratio smaller than a specified value. This results in an increase in the size of the semiconductor memory device. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can form a columnar body through a specified film without increasing the cross-sectional area.

[0006] The semiconductor memory device of the embodiment includes: a plurality of pillars penetrating a designated film; and a beam portion reaching a designated depth in the designated film that is shallower than the plurality of pillars, connecting the plurality of pillars with a width narrower than the plurality of pillars. Attached Figure Description

[0007] Figure 1 (a) and (b) are diagrams illustrating a schematic configuration example of a semiconductor memory device according to an embodiment.

[0008] Figure 2 (a) to (h) are diagrams showing detailed configuration examples of the semiconductor memory device according to the embodiments.

[0009] Figure 3 (A) to (C) are diagrams illustrating an example of the sequence of a method for manufacturing a semiconductor memory device according to an embodiment.

[0010] Figure 4 (c) to (h) are diagrams illustrating an example of the sequence of the manufacturing method of the semiconductor memory device according to the embodiments.

[0011] Figure 5 (A) to (C) are diagrams illustrating an example of the sequence of a method for manufacturing a semiconductor memory device, which is a variation of the implementation. Detailed Implementation

[0012] The present invention will now be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the constituent elements in the following embodiments include elements that are readily conceived by the practitioner or substantially the same elements.

[0013] (Example of a semiconductor memory device)

[0014] Figure 1 This is a diagram illustrating a schematic configuration example of the semiconductor memory device 1 according to an embodiment. Figure 1 (a) is a schematic cross-sectional view along the X direction showing the overall configuration of the semiconductor memory device 1. Figure 1 (b) is a cross-sectional view of semiconductor memory device 1.

[0015] like Figure 1 As shown, the semiconductor memory device 1 has a peripheral circuit CUA, a memory region MR, a through-connect region TPc, and a stepped region SR on a substrate SB.

[0016] The substrate SB is, for example, a semiconductor substrate such as a silicon substrate. Peripheral circuitry CUA, including transistors TR and wiring, is disposed on the substrate SB. The peripheral circuitry CUA facilitates the operation of the memory cells described below.

[0017] The peripheral circuitry CUA is covered by an insulating layer 50. Source lines SL are disposed on the insulating layer 50. Multiple word lines WL are stacked on the source lines SL.

[0018] Multiple word lines WL are divided by multiple contacts LI in the Y direction. That is, each of the multiple contacts LI has a length direction in the X direction along the surface of the word line WL, and extends through the word line WL in the stacking direction.

[0019] Between multiple nodes LI, there are storage regions MR, through-node regions TPc, and stepped regions SR located at both ends of word lines WL. These configurations between multiple nodes LI are called blocks BLK.

[0020] In the storage region MR, multiple pillars PL are arranged in a matrix, extending through word lines WL in the stacking direction. Multiple memory cells are formed at the intersections of the pillars PL and word lines WL. Thus, the semiconductor memory device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are arranged in three dimensions in the storage region MR. A plug connecting the pillars PL to upper-layer wiring such as bit lines is disposed at the upper end of the pillars PL.

[0021] The stepped area SR has multiple word lines WL extended in a stepped manner. At each terrace of the stepped word lines WL, a connection point CC is arranged to connect the word line WL to the upper-level wiring, etc. Furthermore, in this specification, the direction in which the terrace surface of each step of the stepped area SR faces is defined as the upward direction.

[0022] The through-connect region TPc has an insulating region NR sandwiched between two barrier layers BR arranged in the Y direction. Each barrier layer BR has a length direction in the X direction and a word line WL passing through it in the stacking direction. Due to the obstruction of the barrier layers BR, the word line WL is not located in the insulating region NR. Multiple contacts C4 are arranged in the insulating region NR to connect the peripheral circuitry CUA located on the underlying substrate SB to various upper-layer wirings.

[0023] A beam portion BM is disposed between multiple joints C4, connecting the multiple joints C4. The beam portion BM has a width narrower than the width of the joints C4 in the Y direction, for example, connecting multiple joints C4 arranged in the X direction and extending along the X direction. The beam portion BM may also be disposed outside the joints C4 at the ends in the X direction.

[0024] In the area of ​​the through-connect region TPc, excluding the insulating region NR, multiple columnar portions HR are arranged in a matrix, passing through the word lines WL in the stacking direction. The columnar portions HR are also arranged in the stepped region SR. In the manufacturing process of the semiconductor memory device 1, the columnar portions HR function as pillars supporting the semiconductor memory device 1.

[0025] Secondly, utilize Figure 2 A detailed configuration example of semiconductor memory device 1 will be described. Figure 2 This is a diagram showing a detailed configuration example of the semiconductor memory device 1 according to the embodiment.

[0026] Figure 2 (a) is a cross-sectional view of the face along the specified word line WL that runs through the contact area TPc. Figure 2 (b) is a cross-sectional view of the surface of the storage region MR along the specified word line WL.

[0027] Figure 2 (c) is Figure 2 (a) is a longitudinal section view of the barrier layer BR along line a-a'. Figure 2 (d) is Figure 2 (a) is a longitudinal section view of the beam BM on line b-b'. Figure 2 (e) is Figure 2 (a) Longitudinal sectional view of the junction C4 on line c-c'. Figure 2 (f) is Figure 2 (a) Longitudinal sectional view of the junction LI on the d-d' line. Figure 2 (g) is Figure 2 (a) Longitudinal sectional view of the columnar portion HR on the e-e' line. Figure 2 (h) is Figure 2 (b) Longitudinal sectional view of the support PL on line f-f'.

[0028] Among them, Figure 2 In (c) to (h), the structure below the insulating layer 50, such as the substrate SB and the peripheral circuit CUA, and the upper layer wiring are omitted.

[0029] like Figure 2 As shown, the semiconductor memory device 1 includes a multilayer LM, such as a polysilicon layer, disposed on the source line SL.

[0030] The stacked body LM, which is the second stacked body, has a structure in which word lines WL and insulating layers OL are stacked alternately in multiple layers. The word lines WL are the first conductive layer, which is a tungsten layer or a molybdenum layer, etc., and the insulating layer OL is the second insulating layer, which is a SiO2 layer, etc.

[0031] The stacked matrix (LM) features: a memory region (MR) with multiple memory cells arranged in three dimensions; and a stepped region (SR) (see reference). Figure 1 (a) The word lines WL of each layer are stepped at both ends of the laminate LM; and the through-connection region TPc contains multiple contacts C4 and beams BM connecting them. In the through-connection region TPc, the laminate LM surrounds the insulation region NR. The insulation region NR has a laminated structure with alternating layers of different types of insulating layers, such as multiple SiN layers and SiO2 layers, as the first laminate. That is, no word lines WL are arranged in the insulation region NR.

[0032] The barrier layer BR, which is the first plate-shaped portion, has a length direction in the X direction, and its width in the Y direction is approximately equal to the width of the junction LI in the Y direction. Furthermore, the barrier layer BR extends through the laminate LM to reach the source line SL, in contact with the insulating region NR. Thus, the barrier layer BR separates the insulating region NR from the laminate LM surrounding the insulating region NR, at least in the Y direction. An insulating layer 36, such as a SiO2 layer, is filled inside the barrier layer BR.

[0033] The beam portion BM extends along the X-direction within the insulating region NR, and also extends along the depth direction of the insulating region NR. However, the beam portion BM does not penetrate the laminated structure of the insulating region NR, and the bottom of the beam portion BM is, for example, located shallower than the bottom of the contact C4 described below. The width of the beam portion BM in the Y-direction is narrower than the width of the barrier layer BR and the contact LI in the Y-direction. An insulating layer 35, such as a SiO2 layer, is filled inside the beam portion BM as a third insulating layer.

[0034] The contact C4, being a columnar body, has a shape such as a cylinder, elliptical cylinder, or polygonal cylinder, and its width in the Y direction is at least approximately 1.3 times wider than the width of contact LI in the Y direction. Contact C4 penetrates the stacked structure of the insulating region NR and is connected to wiring D2 disposed within the insulating layer 50 below the source line SL. Wiring D2 is electrically connected to the transistor TR of the peripheral circuit CUA via multiple contacts including contact C2 and other wiring.

[0035] Contact C4 has an insulating layer 35, such as a SiO2 layer, covering the sidewalls of contact C4, and a conductive layer 25, such as a tungsten layer, filling the inner side of the insulating layer 35. Thus, contact C4 electrically connects the lower layer wiring D2 of the multilayer assembly LM to the upper layer wiring.

[0036] Contact C4 is positioned within an insulated region NR that does not have a word line WL, thus suppressing electrical connections with the word line WL. Furthermore, the sidewalls of contact C4 are covered by an insulating layer 35, thereby suppressing leakage current and other issues between the multiple contacts C4. Moreover, because the beam portion BM connecting the multiple contacts C4 is filled with the insulating layer 35, the beam portion BM does not affect the insulation performance between the multiple contacts C4.

[0037] The junction LI, which is the second plate-shaped part, has a length direction in the X direction, penetrates the stacked body LM, and reaches the source line SL. Thus, multiple junctions LI divide the stacked body LM in the Y direction.

[0038] The contact LI has an insulating layer 34, such as a SiO2 layer, covering the sidewalls of the contact LI, and a conductive layer 24, such as a tungsten layer, filling the inner side of the insulating layer 34. Thus, the contact LI is electrically connected to the source line SL and functions as a source line contact.

[0039] The columnar portion HR has a shape such as a cylinder or an elliptical cylinder, and extends through the stacked body LM to the source line SL in the through-connection region TPc and the stepped region SR. The interior of the columnar portion HR is filled with an insulating layer 37 such as a SiO2 layer.

[0040] The strut PL has a shape such as a cylinder or elliptical cylinder, and extends through the stacked volume LM to reach the source line SL. From its outer periphery, the strut PL sequentially comprises a storage layer ME, a channel layer CN, and a core layer CR. Within the storage layer ME, from the outer periphery of the strut PL, a block insulating layer (not shown), a charge storage layer, and a tunnel insulating layer are sequentially stacked. The channel layer CN is also disposed on the bottom surface of the strut PL.

[0041] The block insulating layer, tunnel insulating layer, and core layer (CR) are, for example, SiO2 layers. The charge storage layer is, for example, SiN layers. The channel layer (CN) is, for example, an amorphous silicon layer or a polycrystalline silicon layer.

[0042] With these configurations, multiple memory cells are formed at the intersections of the pillar PL and multiple word lines WL, arranged along the height direction of the pillar PL. The memory cells store data by storing charge or the like in a charge storage layer. Data is written to and read from the memory cells by applying a specified voltage from a specified word line WL to the memory cells located at the height of that word line WL.

[0043] (Manufacturing method of semiconductor memory device)

[0044] Secondly, utilize Figure 3 and Figure 4 An example of a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described. Figure 3 and Figure 4 This is a diagram illustrating an example of the sequence of manufacturing methods for the semiconductor memory device 1 according to an embodiment.

[0045] Figure 3 (A) to (C) indicate the status of the processing in sequence. Figure 3 The figures labeled 'a' in (A) to (C) are partial cross-sectional views of the through-joint region TPc in this process. The figures labeled 'c' to 'e' are longitudinal sectional views of line a-a', line b-b', and line c-c' in the figures labeled 'a', respectively. In other words, Figure 3 The figures marked c to e in (A) to (C) are consistent with the above. Figure 2 (c) to (e) correspond.

[0046] Figure 4 (c)~(h) are 1 process related to the above. Figure 2 (c)~(h) are the longitudinal sectional views.

[0047] In the manufacturing method of semiconductor memory device 1, firstly, a peripheral circuit CUA including a transistor TR is formed on a substrate SB. Furthermore, an insulating layer 50 covers the peripheral circuit CUA, and multiple contacts and multiple wirings are formed, with contact C2 and wiring D2 formed on the uppermost layer. A source line SL is then formed on these components.

[0048] A stacked body LMs is formed on the source line SL, forming multiple struts PL and multiple columnar sections HR that run through the stacked body LMs.

[0049] like Figure 3 As shown in (A), the stacked body LMs, which is the first stacked body, has a structure in which multiple insulating layers NL and OL are stacked alternately. The insulating layer NL is the first insulating layer, such as a SiN layer, and the insulating layer OL is the second insulating layer, such as a SiO2 layer. After approximately the entire insulating layer NL, it is replaced with a conductive material, etc., and functions as a sacrificial layer to become the word line WL.

[0050] A mask layer 60, including a carbon layer with a pattern of barrier layer BR, beam portion BM, and junctions C4 and LI, is formed on the stacked matrix LMs. The stacked matrix LMs are then etched to a specified depth. The carbon layer is a carbon-based layer formed by methods such as CVD (Chemical Vapor Deposition) or spin coating.

[0051] Thus, in the laminated body LMs, there are slits STr with a pattern of barrier layer BR transferred, grooves TRm with a pattern of beam BM transferred, holes HL with a pattern of contact C4 transferred, and slits (not shown) with a pattern of contact LI transferred.

[0052] Furthermore, the slits with the pattern of the contact LI transferred and the slits with the pattern of the barrier layer BR transferred have roughly the same structure. Additionally, in Figure 3 In (A) to (C), these slits are treated in roughly the same way. Therefore, in Figure 3 The slit STr is shown only as an example.

[0053] Here, the width of the aperture HL in the Y direction is wider than the width of the slot STr in the Y direction. Furthermore, the aperture HL connects to the trench TRm. Consequently, the apparent aspect ratio of the aperture HL decreases, and the etching rate increases. Therefore, the depth of the aperture HL in the stacked matrix LMs is, for example, deeper than the slot STr.

[0054] Furthermore, the width of the trench TRm in the Y direction is narrower than the width of the slit STr in the Y direction. Therefore, the aspect ratio of the trench TRm is higher than that of the slit STr, the etching rate is reduced, and the depth of the trench TRm in the stacked matrix LMs is located, for example, shallower than that of the slit STr.

[0055] like Figure 3 As shown in (B), a carbon layer 31 of a specified thickness is formed on the sidewalls of the slit STr, the groove TRm, and the hole HL as a sidewall layer. As a result, at least the upper part of the narrower groove TRm in the Y direction is closed by the carbon layer 31.

[0056] like Figure 3 As shown in (C), the stacked matrix LMs are re-etched. As a result, the carbon layer 31 is largely removed in the slot STr, and the bottom of the slot STr reaches the source line SL. Furthermore, the carbon layer 31 is largely removed in the via HL, and the bottom of the via HL reaches the wiring D2. On the other hand, because the trench TRm is closed by the carbon layer 31, no further etching is performed in the trench TRm, and the depth of the trench TRm in the stacked matrix LMs remains approximately unchanged.

[0057] Additionally, it is desirable for the slot STr and via HL to finish etching approximately simultaneously. This is to prevent excessive over-etching or reduced throughput of the other while waiting for one to finish etching. However, generally, the aspect ratio of a single via HL will be higher, and the etching rate will be lower compared to the slot STr, which has a lower aspect ratio and is easier to etch.

[0058] Therefore, in the semiconductor memory device 1 of the embodiment, the trench TRm is connected to the via HL to reduce the apparent aspect ratio. At this time, in order to allow the via HL to reach the lower-layer wiring D2 compared to the slit STr, which has a depth above the source line SL, it is preferable to also consider increasing the etching depth of the via HL by, for example, about 1 μm compared to the slit STr, and to adjust the etching rate of the via HL to be slightly higher than the etching rate of the slit STr. For this purpose, it is preferable, for example, to make the width of the via HL in the Y direction approximately 1.3 times the width of the slit STr in the Y direction.

[0059] On the other hand, the groove TRm communicating with the hole HL is preferably adjusted in the Y direction in such a way that it does not penetrate the laminate LMs, for example, to the extent that it can be closed by the carbon layer 31. This is to suppress interference with the underlying structure caused by the groove TRm penetrating the laminate LMs. Therefore, the width of the groove TRm in the Y direction is preferably, for example, narrower than the width of the slit STr in the Y direction.

[0060] After the etching process of the stacked matrix LMs is completed, the mask layer 60 and the carbon layer 31 are removed by ashing.

[0061] like Figure 4 As shown, the sidewalls of the slit STr are covered by an insulating layer 36. Furthermore, an insulating layer 35 is filled inside the groove TRm to form the beam portion BM. At this time, an insulating layer 35 is also formed on the sidewalls of the hole HL. A sacrificial layer 55 is filled inside the insulating layer 35 formed in the hole HL. The sacrificial layer 55 is an amorphous silicon layer, etc., which is subsequently replaced by the conductive layer 25.

[0062] Through the slit ST, which later becomes the contact LI, the removal fluid for the insulating layer NL permeates into the laminated LMs, removing the insulating layer NL. At this point, the laminated LMs become a fragile state with gaps between the insulating layers OL due to the removal of the insulating layer NL. The strut PL functions as a support for the laminated LMs in the storage region MR. The columnar portion HR functions as a support for the laminated LMs in the penetrating contact region TPc and the stepped region SR.

[0063] Furthermore, the removal fluid entering from the slit ST is blocked by the slit STr having the insulating layer 36 and does not reach the region between the two slit STr. In other words, the process of removing the insulating layer NL ends before the removal fluid enters the region between the slit STr from the X direction side. As a result, the insulating layer NL is not removed and remains in the laminate LMs between the two slit STr.

[0064] Conductive material gas is introduced into the laminates LMs via slits ST, filling the gaps where the insulating layer NL has been removed. Word lines WL are thus formed within these gaps, creating a laminate LM with alternating layers of word lines WL and insulating layers OL. However, because the insulating layer NL remains in the laminates LMs between the two slits STr, no word lines WL are formed. Thus, an insulating region NR is formed by maintaining the laminates LMs, which serve as the first laminate, between the slits STr.

[0065] As described above, the process of replacing the insulating layer NL of a multilayer LMs with a word line WL to form a multilayer LM is sometimes referred to as a replacement process.

[0066] Subsequently, the interior of the slit STr is filled with insulating layer 36 to form barrier layer BR. Furthermore, the sacrificial layer 55 inside the hole HL is removed, and conductive layer 25 is filled inside insulating layer 35 to form contact C4. Additionally, insulating layer 34 is formed on the sidewall of slit ST, and conductive layer 24 is filled inside insulating layer 34 to form contact LI. Furthermore, upper-layer wiring is connected to contacts C4, LI, and support PL via plugs or the like.

[0067] Through the above operations, the semiconductor memory device 1 of the embodiment is manufactured.

[0068] (Summary)

[0069] In the manufacturing process of semiconductor memory devices, contacts are sometimes formed, such as wiring connecting upper and lower layers through a specified film. To ensure that the contacts reliably penetrate the specified film, the cross-sectional area of ​​the contacts is sometimes set to be slightly larger than the area required for electrical characteristics. As a result, when etching the specified film to form contact holes for forming the contacts, the aspect ratio of the contact holes is reduced, and the specified film can be reliably formed.

[0070] Furthermore, in semiconductor memory devices such as three-dimensional non-volatile memory, slits used for displacement processing, slits that serve as barriers to maintain insulation in the through-contact region, and contact holes used to form connections between upper and lower layers are sometimes etched together. In this case, the etching rate of contact holes, which have a higher aspect ratio and are easier to etch, will decrease compared to slits, which have a low aspect ratio and are easier to etch. Alternatively, etching may terminate without further etching.

[0071] Therefore, designing a larger cross-sectional area for the contact hole becomes more important. For example, when forming a cylindrical contact, the diameter of the contact hole is set to approximately three times the width of the short side of the slit.

[0072] However, the size of semiconductor memory devices can sometimes increase when the cross-sectional area of ​​the contact hole is enlarged.

[0073] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a groove TRm is formed that connects the multiple holes HL with a width narrower than that of the multiple holes HL. This allows for a reduction in the apparent aspect ratio of the holes HL without increasing their cross-sectional area, resulting in a more reliable connection point C4 that penetrates the laminated layers LMs. Furthermore, even when slits ST, STr, and holes HL are processed together, the width of the holes HL in the Y direction can be suppressed to within 1.3 times the width of the slits ST, STr in the Y direction.

[0074] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a carbon layer 31 is formed on the sidewalls of the plurality of holes HL and the sidewalls of the trenches TRm by CVD or spin coating, thereby sealing the trenches TRm. In this way, since the trenches TRm are sealed during the etching process, it is possible to prevent the trenches TRm from penetrating the stacked layers LMs and interfering with the underlying structure.

[0075] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, the width of the trench TRm is narrower than the width of the slits ST and STr. Therefore, when the trench TRm, slits ST and STr and via HL are processed together, the etching rate of the trench TRm can be reduced, and the penetration of the stacked layer LMs before the trench TRm is closed can be suppressed.

[0076] According to the semiconductor memory device 1 of the embodiment, the beam portion BM is a groove TRm that is connected to a plurality of contacts C4 and filled with an insulating layer 35. This suppresses the influence of the beam portion BM on the insulation performance between the plurality of contacts C4.

[0077] (Example of variation)

[0078] Secondly, utilize Figure 5 A semiconductor memory device with variations of the implementation will be described. In this variation, the method of sealing the trench TRm differs from that in the implementation described above.

[0079] Figure 5 This is a diagram illustrating an example of the sequence of a method for manufacturing a semiconductor memory device, representing a variation of the implementation. Figure 5 (A) through (C) sequentially represent the processing status, which is consistent with the implementation method described above. Figure 3 The corresponding processing steps (A) to (C) are as follows. Figure 5 The figures labeled 'a' in (A) to (C) are partial cross-sectional views of the through-joint region TPc in this process. The figures labeled 'c' to 'e' are longitudinal sectional views of line a-a', line b-b', and line c-c' in the figures labeled 'a', respectively. In other words, Figure 5 The figures marked c to e in (A) to (C) are consistent with the embodiments described. Figure 3 The figures marked c to e in (A) to (C) correspond to each other.

[0080] In progress Figure 5 Prior to the processing shown, the semiconductor memory device 1 of the described embodiment undergoes the same processing up to the formation of pillars PL and columnar portions HR in the multilayer LMs. Furthermore, Figure 5 The processing and the implementation methods shown in (A) and (B) are described above. Figure 3 The processes shown in (A) and (B) are the same.

[0081] Among them, such as Figure 5 As shown in (B), the sidewalls of the slit STr, groove TRm, and hole HL are formed with a ratio greater than that described in the embodiment. Figure 3 The carbon layer 31 formed by the treatment in (B) is a thin carbon layer 31. As a result, the groove TRm, the slit STr, and the hole HL are not closed and remain open at the top.

[0082] like Figure 5 As shown in (C), the stacked layers LMs are re-etched. At this time, as the etching gas, fluorocarbon (CxFy) based gases such as C4F8, C4F6, and C5F8 are used, and etching conditions are used to facilitate the deposition of CxFy layer 32 in slits STr, trenches TRm, and holes HL.

[0083] Fluorocarbon gases dissociate into CxFy radicals (CxFy) in the plasma during etching processes. ＊ The etchant acts as an etchant, adsorbed within the slits (STr), trenches (TRm), and holes (HL), and etched by the energy of ion bombardment. However, some of the etchant is not bombarded by ions and thus does not contribute to etching; in this way, some or all of the carbon polymerizes and is deposited as the CxFy layer 32. Therefore, the CxFy layer 32 is sometimes referred to as a deposition layer, deposit layer, or fluorocarbon layer. However, this does not mean that the CxFy layer 32 is composed of chemically classifiable fluorocarbons.

[0084] As described above, by performing etching under conditions where CxFy layer 32 is easy to deposit, CxFy layer 32, which serves as a sidewall layer, is continuously deposited in the slot STr, trench TRm, and hole HL, where the aspect ratio is higher and ions have difficulty reaching the interior. At least the upper part of the trench TRm is sealed by CxFy layer 32.

[0085] After this, no further etching is performed within the trench TRm. The depth of the trench TRm is slightly deeper than before the re-etching process, but the etching ends without the trench TRm penetrating the stacked matrix LMs. On the other hand, etching continues in the slit STr and the via HL. The slit STr reaches the source line SL, and the via HL reaches the wiring D2, at which point the etching ends.

[0086] After the etching process of the stacked matrix LMs is completed, the mask layer 60, carbon layer 31 and CxFy layer 32 are removed by ashing.

[0087] Subsequently, the implementation method described above is performed. Figure 4 The same process is used, in addition to forming a barrier layer BR and contacts C4 and LI, and connecting the upper layer wiring to contacts C4, LI and support PL via plugs, etc.

[0088] Based on the above operations, a modified semiconductor memory device is manufactured.

[0089] The variations also achieve the same effect as the semiconductor memory device 1 and the manufacturing method of the semiconductor memory device 1 described in the embodiments.

[0090] Furthermore, according to the semiconductor memory device manufacturing method of the variation example, a CxFy layer 32 is formed by etching on the sidewalls of the multiple holes HL and the sidewalls of the trenches TRm, thereby sealing the trenches TRm. Therefore, it is unnecessary to form a thicker carbon layer 31, which shortens the processing time and reduces costs.

[0091] (Other variations)

[0092] In the described embodiments and variations, the trench TRm is sealed by a carbon-containing layer such as carbon layer 31 or CxFy layer 32. However, the trench TRm may also be sealed by a silicon-containing layer such as an amorphous silicon layer or a metal-containing layer. In this case, the metal-containing layer is preferably an insulating layer such as a metal oxide layer like an Al2O3 layer. In this case, even if conductive components remain in the trench TRm, the trench TRm will only reach a specified depth within the laminate LMs, and the possibility of electrical conduction with other components is extremely low.

[0093] In the described embodiment and its variations, a contact C4 is formed as a columnar body, which penetrates the laminate LM, which serves as a designated membrane. However, the method of connecting multiple columnar bodies by beams can also be applied to other configurations. That is, the designated membrane is not limited to a laminated membrane such as the laminate LM, but can be composed of a single type of membrane, and the columnar body is not limited to the contact C4, but can be other components penetrating the designated membrane.

[0094] In the described embodiments and variations, the etching processes for forming the contact C4 as a columnar body, the contact LI as a plate-like portion, and the barrier layer BR are performed simultaneously. However, the method of connecting multiple columnar bodies by beams can also be applied to other configurations. That is, the plate-like portion is not limited to the contact LI and the barrier layer BR, but can also be other slit-like components that penetrate a specified film and have a relatively low aspect ratio.

[0095] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the invention described in the claims and their equivalents.

[0096] [Explanation of Symbols]

[0097] 1: Semiconductor memory devices

[0098] 31: Carbon layer

[0099] 32:CxFy layer

[0100] BM: Beam Section

[0101] BR: barrier layer

[0102] C4: Contact

[0103] LI: contact

[0104] LM, LMs: laminates

[0105] MR: Storage Area

[0106] NL, OL: Insulation layer

[0107] NR: Insulation area

[0108] PL: pillar

[0109] SB: Substrate

[0110] SR: Stepped Area

[0111] TPc: Through-connection area

[0112] WL: Word line.

Claims

1. A method for manufacturing a semiconductor memory device, comprising: A designated film is formed as a first laminate, wherein a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated in the first laminate; Forming multiple pores that penetrate the designated membrane; The plurality of holes and the grooves connecting the plurality of holes with a width narrower than the plurality of holes are etched to a specified depth of the specified film; A sidewall layer is formed on the sidewalls of the plurality of holes and the sidewalls of the groove to seal the groove; The plurality of holes are further etched to make them penetrate the designated membrane; in When forming the plurality of pores penetrating the designated membrane, a pair of first slits and a pair of second slits are formed to penetrate the first laminate. The sidewall of the first slit is covered with a third insulating layer, and the removal liquid for the first insulating layer permeates into the first stacked layer through the second slit to remove the first insulating layer. The removal of the first insulating layer is terminated before the removal liquid reaches the area between the two first slits. The first insulating layer remains in the first laminate between the two first slits without being removed. A conductive material gas is filled into the gaps where the first insulating layer was removed to form a first conductive layer. This forms a second laminate with alternating layers of the first conductive layer and the second insulating layer. A fourth insulating layer is formed on the sidewall of the second slit, and a second conductive layer is filled inside the fourth insulating layer to form a contact. The interior of the first slit is filled with the third insulating layer to form a barrier layer. The pair of first slits have a length along the surface of each layer of the first laminate, and have a width wider than the width of the slot. The pair of second slits have a length direction in the first direction, and at positions separated from and located on either side of the pair of first slits, they have a width wider than the width of the groove.

2. The method for manufacturing a semiconductor memory device according to claim 1, wherein... When forming the plurality of holes penetrating the designated membrane, the plurality of holes are made to reach a position deeper than the pair of first slits and the pair of second slits.

3. The method for manufacturing a semiconductor memory device according to claim 1, wherein... When forming the plurality of pores that penetrate the designated membrane, This allows the plurality of holes to reach the wiring disposed below the first laminate, and The pair of first slits and the pair of second slits are brought to the source line located above the wiring.

4. The method for manufacturing a semiconductor memory device according to claim 1, wherein... The sidewall layer is a carbon layer formed by CVD or spin coating, or a CxFy layer produced by etching.

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