Light-emitting element, method for manufacturing light-emitting element, and display device

Abstract

A light-emitting element, a method for manufacturing the light-emitting element, and a display device are disclosed. The light-emitting element includes: a first semiconductor layer, which is doped to have a first polarity; a second semiconductor layer, which is doped to have a second polarity different from the first polarity; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a shell layer formed on the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer, the shell layer comprising a divalent metal element; and an insulating film covering the outer surface of the shell layer and surrounding the side surfaces of the light-emitting layer.

Description

Technical Field

[0001] The disclosure relates to a light-emitting element, a method for manufacturing the light-emitting element, and a display device. Background Technology

[0002] With the development of multimedia, display devices have become increasingly important. Therefore, various types of display devices, such as organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs), are being used.

[0003] A display device is a device for displaying images and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. As a light-emitting display panel, the display panel may include a light-emitting element such as a light-emitting diode (LED). For example, the LED may be an organic light-emitting diode (OLED) that uses organic materials as fluorescent materials, or it may be an inorganic LED that uses inorganic materials as fluorescent materials. Summary of the Invention

[0004] The disclosed embodiments provide a light-emitting element and a method of manufacturing the light-emitting element, the light-emitting element comprising a semiconductor layer and a shell layer formed on the outer surface of the semiconductor layer to compensate for any defects in the semiconductor layer.

[0005] The disclosed embodiments also provide a display device that includes a light-emitting element to have improved emission efficiency.

[0006] However, the disclosed embodiments are not limited to those described herein. The above and other disclosed embodiments will become more apparent to those skilled in the art by referring to the detailed description of the disclosure given below.

[0007] According to the disclosed embodiments, the light-emitting element may include: a first semiconductor layer, which is doped to have a first polarity; a second semiconductor layer, which is doped to have a second polarity different from the first polarity; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a shell layer formed on the side surfaces of the first semiconductor layer, the side surfaces of the light-emitting layer and the second semiconductor layer, wherein the shell layer includes a divalent metal element, or the shell layer is formed as a region in which the first semiconductor layer, the light-emitting layer and the second semiconductor layer are doped with a divalent metal element; and an insulating film covering the outer surface of the shell layer and surrounding the side surfaces of the light-emitting layer.

[0008] The light-emitting element may further include an electrode layer disposed on the second semiconductor layer, wherein the insulating film may surround at least a portion of the outer surface of the electrode layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0009] The shell can be directly disposed on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer, so as to form a physical interface with at least the first semiconductor layer.

[0010] The shell may include at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe.

[0011] The shell can have a thickness of about 0.5 nm to about 10 nm.

[0012] The shell can be formed as a region doped with divalent metal elements in the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0013] Divalent metal elements can be one of Be, Mg, Ca, Sr, Ba, Zn, and Cd.

[0014] The shell can be doped with approximately 10 10 / cm 3 To about 10 18 / cm 3 The amount of divalent metal elements within the range.

[0015] The shell can have approximately to approximately The thickness is within the range.

[0016] The insulating film can be formed as a single layer or multiple layers including silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, zirconium oxide and hafnium oxide, and has a thickness in the range of about 10 nm to about 200 nm.

[0017] The insulating film may include: a first layer disposed directly on the shell layer; and a second layer disposed directly on the first layer, wherein the first layer may include silicon oxide and the second layer may include aluminum oxide.

[0018] The light-emitting element may further include: a third semiconductor layer disposed between the first semiconductor layer and the light-emitting layer; a fourth semiconductor layer disposed between the second semiconductor layer and the light-emitting layer; and a fifth semiconductor layer disposed between the second semiconductor layer and the fourth semiconductor layer, wherein a shell layer may be formed on the side surfaces of the third semiconductor layer, the fourth semiconductor layer and the fifth semiconductor layer.

[0019] According to the disclosed embodiments, a method for manufacturing a light-emitting element may include the following steps: forming a plurality of element rods spaced apart from each other on a target substrate; forming a shell layer comprising a divalent metal element on a portion of the outer surface of the plurality of element rods, and forming an insulating film on the shell layer; and separating the plurality of element rods on which the insulating film is formed from the target substrate.

[0020] The formation of multiple component rods may include the following steps: forming a semiconductor structure by forming multiple semiconductor layers on a target substrate; and etching the semiconductor structure in a direction perpendicular to the top surface of the target substrate.

[0021] The formation of the shell and insulating film may include the following steps: forming a shell material layer surrounding the multiple element rods by immersing a target substrate on which a plurality of element rods are formed into a solution in which a precursor material for forming the shell is mixed; forming an insulating layer on the shell material layer; and forming the shell and insulating film by partially removing the shell material layer and the insulating layer to expose the top surface of the multiple element rods.

[0022] The formation of multiple component bars may include forming multiple component bars, each of the multiple component bars including: a first semiconductor layer, the first semiconductor layer being doped to have a first polarity; a second semiconductor layer, the second semiconductor layer being doped to have a second polarity different from the first polarity; and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and the formation of a shell layer may include forming a shell layer on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0023] According to the disclosed embodiments, the display device may include: a first substrate; a first electrode disposed on the first substrate; a second electrode separated from the first electrode; a first insulating layer disposed on the first substrate and superimposed on portions of the first electrode and the second electrode; and a plurality of light-emitting elements disposed on the first insulating layer, each of the plurality of light-emitting elements including a first end disposed on the first electrode and a second end disposed on the second electrode, wherein each of the plurality of light-emitting elements may include: a first semiconductor layer doped to have a first polarity; a second semiconductor layer doped to have a second polarity different from the first polarity; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a shell layer formed on the side surfaces of the first semiconductor layer, the side surfaces of the light-emitting layer and the second semiconductor layer, the shell layer including a divalent metal element, or the shell layer being formed as a region in which a divalent metal element is doped in the first semiconductor layer, the light-emitting layer and the second semiconductor layer; and an insulating film configured to cover the outer surface of the shell layer and at least surround the side surface of the light-emitting layer.

[0024] The display device may further include: a first contact electrode that electrically contacts a first end of a first electrode and each of a plurality of light-emitting elements; and a second contact electrode that electrically contacts a second electrode and a second end of each of a plurality of light-emitting elements.

[0025] The shell can be directly disposed on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer to form a physical interface with at least the first semiconductor layer, and the shell can include at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe.

[0026] The shell can be formed as a region doped with divalent metal elements in the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0027] According to the above and other disclosed embodiments, a light-emitting element is provided that includes a shell for compensating for any defects in the semiconductor layer, thereby preventing the emission efficiency from being reduced due to these defects.

[0028] A display device including a light-emitting element is provided, thereby improving the emission efficiency per unit area.

[0029] Other features and embodiments may be apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0030] The above and other embodiments and features will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a schematic plan view of a display device according to a disclosed embodiment;

[0032] Figure 2 yes Figure 1 A schematic plan view of the pixels of a display device;

[0033] Figure 3 It is along Figure 2 A schematic cross-sectional view taken by lines Q1-Q1', Q2-Q2', and Q3-Q3';

[0034] Figure 4 This is a schematic perspective view of a light-emitting element according to a disclosed embodiment;

[0035] Figure 5 yes Figure 4 A schematic plan view of the light-emitting element;

[0036] Figure 6 yes Figure 4 A schematic cross-sectional view of the light-emitting element;

[0037] Figure 7 This is a schematic cross-sectional view of a light-emitting element according to another disclosed embodiment;

[0038] Figure 8This is a schematic flowchart illustrating a method for manufacturing a light-emitting element according to a disclosed embodiment;

[0039] Figures 9 to 18 It shows Figure 8 A schematic diagram of the method;

[0040] Figure 19 This is a schematic perspective view of a light-emitting element according to another disclosed embodiment;

[0041] Figure 20 yes Figure 19 A schematic cross-sectional view of the light-emitting element;

[0042] Figure 21 This is a schematic perspective view of a light-emitting element according to another disclosed embodiment;

[0043] Figure 22 yes Figure 21 A schematic cross-sectional view of the light-emitting element;

[0044] Figure 23 This is a schematic perspective view of a light-emitting element according to another disclosed embodiment; and

[0045] Figure 24 yes Figure 23 A schematic cross-sectional view of the light-emitting element. Detailed Implementation

[0046] The disclosure will now be described more fully below with reference to the accompanying drawings, in which some embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will convey the scope of the disclosure to those skilled in the art.

[0047] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals denote the same components.

[0048] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0049] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B or A and B”.

[0050] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in the disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] The disclosed embodiments will be described below with reference to the accompanying drawings.

[0052] Figure 1 This is a schematic plan view of a display device according to an embodiment.

[0053] Reference Figure 1 The display device 10 can display moving or still images. The display device 10 can refer to any type of electronic device that provides a display screen. Examples of display devices 10 may include televisions (TVs), laptops, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, head-mounted displays (HMDs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, camcorders, etc.

[0054] Display device 10 may include a display panel that provides a display screen. Examples of the display panel of display device 10 may include an inorganic light-emitting diode (ILED) display panel, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a plasma display panel (PDP), a field emission display (FED) panel, etc. The display panel of display device 10 will be described below as, for example, an ILED display panel, but the disclosure is not limited thereto. For example, the disclosure may be applied to various other display panels, provided that the same technical concept is applicable.

[0055] The shape of the display device 10 can vary. For example, the display device 10 can have a rectangular shape that extends longer in the horizontal direction than in the vertical direction, a rectangular shape that extends longer in the vertical direction than in the horizontal direction, a square shape, a quadrilateral shape with rounded corners, a non-quadrilateral polygonal shape, or a circular shape. The shape of the display area DPA of the display device 10 can be similar to the shape of the display device 10. Figure 1 The display device 10 and the display area DPA are shown to have a rectangular shape that extends longer in the horizontal direction than in the vertical direction.

[0056] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area in which an image is displayed, and the non-display area NDA may be an area in which no image is displayed. The display area DPA may also be referred to as the active area, and the non-display area NDA may also be referred to as the inactive area. The display area DPA may occupy the middle portion of the display device 10.

[0057] The display area DPA may include pixels PX. Pixels PX may be arranged in both row and column directions. Pixels PX may have a rectangular or square shape in a planar view, but are not limited thereto. As another example, pixels PX may have a rhombus shape including sides tilted relative to a particular direction. Pixels PX may be arranged alternately in a striped or pen-tile manner. Each of the pixels PX may include one or more light-emitting elements 30 that emit light within a specific wavelength range (see...). Figure 2 ).

[0058] The non-display area NDA can be disposed around the display area DPA. The non-display area NDA can surround the entire display area DPA or a portion of the display area DPA. The display area DPA can have a rectangular shape, and the non-display area NDA can be positioned adjacent to the four sides of the display area DPA. The non-display area NDA can form the frame of the display device 10. Wiring or circuit drivers included in the display device 10 can be disposed in the non-display area NDA, or external devices can be mounted in the non-display area NDA.

[0059] Figure 2 yes Figure 1 A schematic plan view of the pixels of a display device.

[0060] Reference Figure 2A pixel PX may include sub-pixels PXn (where n is an integer in the range of 1 to 3). For example, a pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may emit light of a first color, a second color, and a third color, respectively. For example, the first color, the second color, and the third color may be blue, green, and red, respectively, but the disclosure is not limited thereto. As another example, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may emit light of the same color. Figure 2 The illustration shows that pixel PX comprises three sub-pixels PXn, but the disclosure is not limited thereto. For example, pixel PX may include more than three sub-pixels PXn.

[0061] Each sub-pixel PXn may include an emitting region EMA and a non-emitting region. The emitting region EMA may be a region in which a light-emitting element 30 is disposed and which can emit light within a specific wavelength range, while the non-emitting region may be a region in which no light-emitting element 30 is disposed and which has no light output because the light emitted from the light-emitting element 30 does not reach it. The emitting region EMA may include the region in which the light-emitting element 30 is disposed and the region adjacent to or around the light-emitting element 30 from which light emitted by the light-emitting element 30 is output.

[0062] However, the disclosure is not limited thereto. As another example, the emission region EMA may also include the region from which light is emitted by the light-emitting element 30 and then reflected or refracted by other components. The light-emitting element 30 may be disposed in each of the sub-pixels PXn, and each of the sub-pixels PXn may include a region in which the light-emitting element 30 is disposed and a region adjacent to that region to form the emission region EMA.

[0063] Each sub-pixel PXn may further include a cut-out region CBA disposed in a non-emitting region. The cut-out region CBA may be disposed on one side of the emitting region EMA in the second direction DR2. The cut-out region CBA may be disposed between the emitting regions EMA of two adjacent sub-pixels PXn along the second direction DR2. For example, the emitting regions EMA and the cut-out region CBA may be arranged in the display area DPA of the display device 10. For example, the emitting regions EMA may be arranged in a row in the first direction DR1, the cut-out regions CBA may be arranged in a row in the first direction DR1, and the emitting regions EMA and cut-out regions CBA may be arranged alternately in the second direction DR2. The distance between the cut-out regions CBA in the first direction DR1 may be smaller than the distance between the emitting regions EMA in the first direction DR1. A second embankment BNL2 may be disposed between the cut-out regions CBA and the emitting regions EMA, and the distances between the cut-out regions CBA, between the emitting regions EMA, and between the cut-out regions CBA and the emitting regions EMA may vary depending on the width of the second embankment BNL2. Since the light-emitting element 30 is not disposed in the cut-out region CBA, light may not be output from the cut-out region CBA. Conversely, portions of electrodes 21 and 22 can be disposed within the cutting region CBA. Electrodes 21 and 22 can be divided or separated from each other within the cutting region CBA.

[0064] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from lines Q1-Q1', Q2-Q2', and Q3-Q3'. Figure 3 It shows from Figure 2 A schematic cross-sectional view of one of the light-emitting elements 30 in the first sub-pixel PX1, taken from one end to the other (or other ends).

[0065] Reference Figure 3 And further refer to Figure 2 The display device 10 may include a first substrate 11 and a semiconductor layer, a conductive layer, and an insulating layer disposed on the first substrate 11. The semiconductor layer, conductive layer, and insulating layer may form the circuit layer and the light-emitting layer of the display device 10.

[0066] The first substrate 11 may be an insulating substrate. The first substrate 11 may be formed of an insulating material such as glass, quartz, or polymer resin. The first substrate 11 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0067] A light-blocking layer BML may be disposed on the first substrate 11. The light-blocking layer BML is configured to be stacked with the active layer ACT1 of the first transistor T1. The light-blocking layer BML may include a material capable of blocking light, and thus prevent light from incident on the active layer ACT1 of the first transistor T1. For example, the light-blocking layer BML may be formed of an opaque metallic material capable of blocking light transmission, but the disclosure is not limited thereto. In some embodiments, the light-blocking layer BML may not be disposed.

[0068] The buffer layer 12 can be disposed on the entire surface of the first substrate 11. For example, the buffer layer 12 can be configured to cover the top surface of the light-blocking layer BML and the first substrate 11, or be stacked with the light-blocking layer BML and the top surface of the first substrate 11. The buffer layer 12 can be formed on the moisture-sensitive first substrate 11 to protect the first transistor T1 from moisture and can perform a surface planarization function.

[0069] The active layer ACT1 can be disposed on the buffer layer 12. The active layer ACT1 can be configured to partially overlap with the gate electrode G1 of the first conductive layer, which will be described below.

[0070] Figure 3 Only the first transistor T1, which is included in the first sub-pixel PX1, is shown, but the disclosure is not limited thereto. The display device 10 may include more than one transistor in each of the sub-pixels PXn. For example, the display device 10 may include two or three transistors in each of the sub-pixels PXn, in addition to the first transistor T1.

[0071] The active layer ACT1 may include polycrystalline silicon, monocrystalline silicon, or an oxide semiconductor. When the active layer ACT1 includes an oxide semiconductor, it may include a conductor region and a channel region disposed between the conductor regions. The oxide semiconductor may be an indium (In)-containing oxide semiconductor. For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0072] As another example, the active layer ACT1 may comprise polycrystalline silicon, which can be formed by crystallizing amorphous silicon. In this case, the conductive region of the active layer ACT1 may be a region doped with impurities.

[0073] The first gate insulating layer 13 can be disposed on the active layer ACT1 and the buffer layer 12. For example, the first gate insulating layer 13 can cover the entire surface of the active layer ACT1 and the buffer layer 12, or be stacked on the entire surface of the active layer ACT1 and the buffer layer 12. The first gate insulating layer 13 can be used as a gate insulating film for each transistor.

[0074] A first conductive layer may be disposed on the first gate insulating layer 13. The first conductive layer may include the gate electrode G1 of the first transistor T1 and the first capacitor electrode CSE1 of the storage capacitor. The gate electrode G1 may be configured to be stacked with the channel region ACT_c of the active layer ACT1 in the thickness direction. The first capacitor electrode CSE1 may be configured to be stacked with a second capacitor electrode CSE2, which will be described below, in the thickness direction. For example, the first capacitor electrode CSE1 may be integral with and / or connected to the gate electrode G1. The first capacitor electrode CSE1 and the second capacitor electrode CSE2 may be formed to be stacked on top of each other in the thickness direction to form a storage capacitor.

[0075] The first interlayer insulating layer 15 may be disposed on the first conductive layer. The first interlayer insulating layer 15 may serve as an insulating film between the first conductive layer and the layer disposed on the first conductive layer. The first interlayer insulating layer 15 may be configured to cover the first conductive layer or be stacked with the first conductive layer, and to protect the first conductive layer.

[0076] The second conductive layer may be disposed on the first interlayer insulating layer 15. The second conductive layer may include the first source electrode S1 and the first drain electrode D1 of the first transistor T1, the data line DTL, and the second capacitor electrode CSE2.

[0077] The first source electrode S1 and the first drain electrode D1 of the first transistor T1 can contact the doped regions ACT_a and ACT_b of the active layer ACT1 through contact holes penetrating the first interlayer insulating layer 15 and the first gate insulating layer 13. The first source electrode S1 of the first transistor T1 can contact the light-blocking layer BML through another contact hole.

[0078] The data line DTL can apply data signals to other transistors included in the first sub-pixel PX1. Although not specifically shown, the data line DTL can be connected to the source / drain electrodes of other transistors and can transmit data signals applied to them.

[0079] The second capacitor electrode CSE2 is configured to be stacked on top of the first capacitor electrode CSE1 in the thickness direction. For example, the second capacitor electrode CSE2 may be integral with and / or connected to the first source electrode S1.

[0080] The second interlayer insulating layer 17 can be disposed on the second conductive layer. The second interlayer insulating layer 17 can serve as an insulating film between the second conductive layer and the layer disposed on the second conductive layer. The second interlayer insulating layer 17 can be stacked with the second conductive layer and protect the second conductive layer.

[0081] A third conductive layer may be disposed on the second interlayer insulating layer 17. The third conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high potential voltage (or a first power supply voltage) to be provided to the first transistor T1 may be applied to the first voltage line VL1, and a low potential voltage (or a second power supply voltage) to be provided to the second electrode 22 may be applied to the second voltage line VL2. During the manufacture of the display device 10, an alignment signal for aligning the light-emitting element 30 may be applied to the second voltage line VL2.

[0082] The first conductive pattern CDP can be electrically connected to the second capacitor electrode CSE2 through contact holes formed in the second interlayer insulating layer 17. The second capacitor electrode CSE2 can be integrated with the first source electrode S1 of the first transistor T1, and the first conductive pattern CDP can be electrically connected to the first source electrode S1 of the first transistor T1. The first conductive pattern CDP can electrically contact the first electrode 21, which will be described below, and the first transistor T1 can transmit the first power supply voltage applied to it from the first voltage line VL1 to the first electrode 21 via the first conductive pattern CDP. The third conductive layer is in... Figure 3 The diagram is shown to include a first voltage line VL1 and a second voltage line VL2, but the disclosure is not limited thereto. As another example, the third conductive layer may include more than one first voltage line VL1 and more than one second voltage line VL2.

[0083] Each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may comprise alternately stacked inorganic films. For example, each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may be formed in which silicon oxide (SiO2) is alternately stacked. x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y A multilayer of one or more inorganic layers of at least one of the following. As another example, each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may be formed as a single inorganic layer comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] The first planarization layer 19 may be disposed on the third conductive layer. The first planarization layer 19 may include an organic insulating material such as polyimide (PI) and may perform a surface planarization function.

[0085] The first diaphragm BNL1, electrodes 21 and 22, light-emitting element 30, contact electrodes CNE1 and CNE2, and the second diaphragm BNL2 can be disposed on the first planarization layer 19. Insulating layers PAS1, PAS2, PAS3, and PAS4 can also be disposed on the first planarization layer 19.

[0086] The first dam BNL1 can be directly disposed on the first planarization layer 19. Each of the first dams BNL1 can have a predetermined width in each sub-pixel PXn to extend in the second direction DR2, but may not extend to other adjacent sub-pixels PXn in the second direction DR2, and can be disposed within the emission region EMA. The first dams BNL1 can be disposed separately from each other in the first direction DR1.

[0087] Multiple first dams BNL1 can be set in sub-pixels PXn. Figure 3 Two first dams BNL1 are shown disposed in each sub-pixel PXn to form a linear pattern in the display area DPA, but the disclosure is not limited thereto. The number of first dams BNL1 disposed in the sub-pixel PXn can vary depending on the number of electrodes 21 and 22 disposed in the sub-pixel PXn and the arrangement of the light-emitting elements 30 in the sub-pixel PXn. The first dams BNL1 can form an island pattern instead of a linear pattern.

[0088] The first dam BNL1 may protrude at least partially from the top surface of the first planarization layer 19. Each of the protruding portions of the first dam BNL1 may have a sloping side surface, allowing light emitted from the light-emitting element 30 to be reflected by electrodes 21 and 22 disposed on the first dam BNL1 and emitted upward from the first planarization layer 19. The first dam BNL1 may provide an area in which the light-emitting element 30 is disposed and may serve as a reflective wall for upward reflection of light emitted from the light-emitting element 30. The side surface of each of the first dams BNL1 may be linearly sloping, but the disclosure is not limited thereto. Each of the first dams BNL1 may have a semi-circular or semi-elliptical shape with a curved outer surface. The first dam BNL1 may comprise an organic insulating material such as polyimide, but the disclosure is not limited thereto. In some embodiments, the first dam BNL1 may not be provided.

[0089] Electrodes 21 and 22 can be configured to extend in one direction within each sub-pixel PXn. Electrodes 21 and 22 can extend in a second direction DR2 and can be configured to be spaced apart from each other in a first direction DR1. For example, the first electrode 21 and the second electrode 22 can be configured to be spaced apart from each other in the first direction DR1 within the sub-pixel PXn, but the disclosure is not limited thereto. For example, the number and position of electrodes 21 and 22 disposed in each sub-pixel PXn can vary depending on the number of light-emitting elements 30 disposed in each sub-pixel PXn.

[0090] The first electrode 21 and the second electrode 22 can be disposed in the emission region EMA of each sub-pixel PXn, and can be partially disposed outside the emission region EMA to overlap with the second embankment BNL2 in the thickness direction. Electrodes 21 and 22 can extend in the sub-pixel PXn in the second direction DR2, and can be separated from the electrodes 21 and 22 of the upper adjacent sub-pixel PXn in the second direction DR2 in the cutting region CBA.

[0091] The first electrode 21 and the second electrode 22 may extend in each sub-pixel PXn along the second direction DR2 and may be separated from other first electrodes 21 and other second electrodes 22 in the cut region CBA. For example, the cut region CBA may be located between the emission regions EMA of two adjacent sub-pixels PXn along the second direction DR2, and the first electrode 21 and the second electrode 22 of one of the two adjacent sub-pixels PXn may be separated from the first electrode 21 and the second electrode 22 of the other sub-pixel PXn in the cut region CBA. However, the disclosure is not limited to this example. As another example, some of the electrodes 21 and 22 may extend beyond each pair of adjacent sub-pixels PXn along the second direction DR2, instead of being divided between each pair of adjacent sub-pixels PXn along the second direction DR2, or only one of the first electrode 21 and the second electrode 22 may be divided between each pair of adjacent sub-pixels PXn along the second direction DR2.

[0092] Electrodes 21 and 22 can be obtained by forming electrode lines extending in the second direction DR2 and by dividing the electrode lines after the light-emitting element 30 is arranged. During the manufacture of the display device 10, the electrode lines can be used to form an electric field in the sub-pixel PXn to align the light-emitting element 30. For example, the light-emitting element 30 can be jetted onto the electrode lines by an inkjet printing process, and once the ink including the light-emitting element 30 is jetted onto the electrode lines, an electric field can be formed by applying an alignment signal to the electrode lines. The light-emitting element 30, which is scattered or dispersed in the ink, can receive a dielectric force from the electric field and can therefore be arranged on the electrodes 21 and 22. After the light-emitting element 30 is arranged, some of the electrode lines can be divided to form electrodes 21 and 22 disposed in each of the sub-pixels PXn.

[0093] Electrodes 21 and 22 can be connected to a third conductive layer, allowing a signal for causing the light-emitting element 30 to emit light to be applied to electrodes 21 and 22. The first electrode 21 can electrically contact the first conductive pattern CDP through a first contact hole CT1 penetrating the first planarization layer 19. The second electrode 22 can electrically contact the second voltage line VL2 through a second contact hole CT2 penetrating the first planarization layer 19. The first electrode 21 can be electrically connected to the first transistor T1 via the first conductive pattern CDP, allowing a first power supply voltage to be applied to the first electrode 21. The second electrode 22 can be electrically connected to the second voltage line VL2, allowing a second power supply voltage to be applied to the second electrode 22.

[0094] Electrodes 21 and 22 can be electrically connected to the light-emitting element 30. Electrodes 21 and 22 can be connected to the ends of each of the light-emitting elements 30 via contact electrodes CNE1 and CNE2, and can transmit electrical signals received from the third conductive layer to the light-emitting element 30. Since electrodes 21 and 22 are divided between different sub-pixels PXn, the light-emitting element 30 of one sub-pixel PXn can emit light separately from the light-emitting element 30 of another sub-pixel PXn.

[0095] The first contact hole CT1 and the second contact hole CT2 are shown to be formed at a location overlapping with the second dam BNL2, but the disclosure is not limited thereto. For example, the first contact hole CT1 and the second contact hole CT2 may be located in the emission area EMA surrounded by the second dam BNL2.

[0096] Electrodes 21 and 22 may be disposed on a pair of first dams BNL1 spaced apart from each other. Electrodes 21 and 22 may be disposed on the side surfaces of the first dams BNL1 in a first direction DR1, arranged on the inclined side surfaces of the first dams BNL1. For example, the width of electrodes 21 and 22 in the first direction DR1 may be greater than the width of the first dams BNL1 in the first direction DR1. Electrodes 21 and 22 may be configured to overlap with at least one side surface of each of the first dams BNL1 to reflect light emitted from the light-emitting element 30.

[0097] The distance between electrodes 21 and 22 in the first direction DR1 can be smaller than the distance between the first diaphragms BNL1 in the first direction DR1. At least a portion of electrodes 21 and 22 can be directly disposed on the first planarization layer 19 and can be disposed on the same plane (or layer).

[0098] Electrodes 21 and 22 may comprise conductive materials with high reflectivity. For example, electrodes 21 and 22 may comprise metals with high reflectivity such as silver (Ag), Cu, or Al, or alloys of Al, Ni, or lanthanum (La). Electrodes 21 and 22 may reflect light emitted from the light-emitting element 30 and traveling toward the side of the first embankment BNL1 upward from each sub-pixel PXn.

[0099] However, the disclosure is not limited thereto, and electrodes 21 and 22 may also comprise transparent conductive materials. For example, electrodes 21 and 22 may comprise materials such as ITO, IZO, or indium tin zinc oxide (ITZO). In some embodiments, each of electrodes 21 and 22 may be formed into a structure in which the transparent conductive material and a highly reflective metal are stacked in more than one layer, or may be formed into a single layer comprising the transparent conductive material and a highly reflective metal. For example, each of electrodes 21 and 22 may have a stack of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0100] A first insulating layer PAS1 may be disposed on electrodes 21 and 22 and a first dam BNL1. The first insulating layer PAS1 may be stacked with the first dam BNL1 and the first electrode 21 and the second electrode 22, and may expose portions of the top surfaces of the first electrode 21 and the second electrode 22. An opening OP may be formed in the first insulating layer PAS1 to expose portions of the top surfaces of electrodes 21 and 22 disposed on the first dam BNL1, and contact electrodes CNE1 and CNE2 may electrically contact electrodes 21 and 22 through the opening OP.

[0101] For example, the first insulating layer PAS1 can be formed with a recessed top surface between the first electrode 21 and the second electrode 22. Since the first insulating layer PAS1 can be stacked with the first electrode 21 and the second electrode 22, it can be formed with a recess between the first electrode 21 and the second electrode 22, but the disclosure is not limited thereto. The first insulating layer PAS1 can protect the first electrode 21 and the second electrode 22, and can insulate the first electrode 21 and the second electrode 22 from each other. The first insulating layer PAS1 can prevent the light-emitting element 30 from being damaged by direct contact with other elements.

[0102] A second dam BNL2 may be disposed on the first insulating layer PAS1. In a plan view, the second dam BNL2 may include portions extending in a first direction DR1 and portions extending in a second direction DR2, and thus may be arranged in a grid pattern. The second dam BNL2 may be disposed along the boundary of each of the sub-pixels PXn to define each of the sub-pixels PXn. The second dam BNL2 may be configured to surround the emission region EMA and the cut region CBA of each of the sub-pixels PXn to separate the emission region EMA and the cut region CBA of each of the sub-pixels PXn. The portion of the second dam BNL2 extending in the second direction DR2 between the emission regions EMA of the sub-pixels PXn may have a width greater than the width of the portion of the second dam BNL2 extending in the second direction DR2 between the cut regions CBA of the sub-pixels PXn. The distance between the cut regions CBA of the sub-pixels PXn may be smaller than the distance between the emission regions EMA of the sub-pixels PXn.

[0103] The second barrier BNL2 can be formed to have a greater height than the first barrier BNL1. The second barrier BNL2 can prevent ink spillage between adjacent sub-pixels PXn during the inkjet printing process during the manufacture of the display device 10, and can separate the ink between different sub-pixels PXn and in which the light-emitting element 30 is dispersed to prevent ink mixing. Similar to the first barrier BNL1, the second barrier BNL2 may include polyimide, but the disclosure is not limited thereto.

[0104] The light-emitting element 30 may be disposed on the first insulating layer PAS1. The light-emitting element 30 may be spaced apart from each other in the direction along which the electrodes 21 and 22 extend (e.g., in the second direction DR2), and may be arranged substantially parallel to each other. The light-emitting element 30 may extend in one direction, and the direction along which the electrodes 21 and 22 extend may form substantially right angles with the direction along which the light-emitting element 30 extends. However, the disclosure is not limited thereto. As another example, the light-emitting element 30 may be arranged diagonally relative to the direction along which the electrodes 21 and 22 extend.

[0105] Each of the light-emitting elements 30 may include a semiconductor layer doped with dopants of different conductivity types. Because each of the light-emitting elements 30 includes a semiconductor layer, the light-emitting elements 30 can be aligned such that the first end of each of the light-emitting elements 30 faces a specific direction depending on the direction of the electric field formed on electrodes 21 and 22. Each of the light-emitting elements 30 may include a light-emitting layer 36 (see...). Figure 4 And thus can emit light within a specific wavelength range. The light-emitting element 30 can emit light within different wavelength ranges depending on its material, but the disclosure is not limited thereto. As another example, the light-emitting element 30 can emit light of the same color.

[0106] Layers can be arranged in each of the light-emitting elements 30 in a direction perpendicular to the top surface of the first substrate 11. The light-emitting elements 30 can be arranged such that the direction in which the light-emitting elements 30 extend is parallel to the first substrate 11, and the semiconductor layers included in each of the light-emitting elements 30 can be sequentially arranged in a direction parallel to the top surface of the first substrate 11. However, the disclosure is not limited thereto. As another example, in cases where the light-emitting elements 30 have different structures, the layers included in each of the light-emitting elements 30 can be arranged in a direction perpendicular to the first substrate 11.

[0107] The light-emitting element 30 can be disposed on electrodes 21 and 22 between the first electrode 21 and the second electrode 22. For example, the first end of the light-emitting element 30 can be disposed on the first electrode 21, and the second end of the light-emitting element 30 can be disposed on the second electrode 22. The length of the light-emitting element 30 can be greater than the distance between the first electrode 21 and the second electrode 22, and the two ends of each of the light-emitting elements 30 can be disposed on the first electrode 21 and the second electrode 22, respectively.

[0108] Each of the light-emitting elements 30 has two ends that can electrically contact contact electrodes CNE1 and CNE2. This is due to the insulating film 38 (see...). Figure 6 It is not necessary to form portions of the semiconductor layer of each of the light-emitting elements 30 at both ends to expose a portion of the semiconductor layer of each of the light-emitting elements 30, so that the exposed semiconductor layer can electrically contact the contact electrodes CNE1 and CNE2, but the disclosure is not limited thereto. As another example, at least a portion of the insulating film 38 may be removed, such that portions of the side surfaces of the semiconductor layer of each of the light-emitting elements 30 can be exposed. The exposed side surfaces of the semiconductor layer can directly contact the contact electrodes CNE1 and CNE2.

[0109] The second insulating layer PAS2 may be partially disposed on the first insulating layer PAS1 and the light-emitting element 30. For example, the second insulating layer PAS2 may be disposed around the outer surface of the light-emitting element 30 and may not cover the first and second ends of the light-emitting element 30. During the manufacture of the display device 10, the second insulating layer PAS2 may be initially disposed on the first insulating layer PAS1 (or the entire first insulating layer PAS1) and may then be partially removed to expose the two ends of each of the light-emitting elements 30.

[0110] The portion of the second insulating layer PAS2 disposed on the light-emitting element 30 can extend in the second direction DR2 above the first insulating layer PAS1, and thus can form a linear pattern or island pattern in each sub-pixel PXn. The second insulating layer PAS2 can protect and fix the light-emitting element 30 during the manufacture of the display device 10. The second insulating layer PAS2 can be configured to fill the space between the light-emitting element 30 and the first insulating layer PAS1.

[0111] Contact electrodes CNE1 and CNE2, and a third insulating layer PAS3, can be disposed on the second insulating layer PAS2. The first contact electrode CNE1 and the second contact electrode CNE2 can be partially disposed on the first electrode 21 and the second electrode 22, respectively. The first contact electrode CNE1 can be disposed on the first electrode 21, and the second contact electrode CNE2 can be disposed on the second electrode 22. The first contact electrode CNE1 and the second contact electrode CNE2 can be separated from each other and face each other in the first direction DR1, and can form a linear pattern in the emission region EMA of each sub-pixel PXn.

[0112] Contact electrodes CNE1 and CNE2 can electrically contact the light-emitting element 30 and electrodes 21 and 22. Each of the light-emitting elements 30 can have a semiconductor layer exposed at its two ends, and the first contact electrode CNE1 and the second contact electrode CNE2 can electrically contact the light-emitting element 30 at its two ends, wherein the semiconductor layer of each of the light-emitting elements 30 is exposed at said two ends. A first end of the light-emitting element 30 can be electrically connected to the first electrode 21 via the first contact electrode CNE1, and a second end of the light-emitting element 30 can be electrically connected to the second electrode 22 via the second contact electrode CNE2.

[0113] Figure 3 The diagram shows a first contact electrode CNE1 and a second contact electrode CNE2 disposed in each of the sub-pixels PXn, but the disclosure is not limited thereto. For example, the number of first contact electrodes CNE1 and second contact electrodes CNE2 disposed in each of the sub-pixels PXn can vary depending on the number of first electrodes 21 and second electrodes 22 disposed in each of the sub-pixels PXn.

[0114] Contact electrodes CNE1 and CNE2 may comprise conductive materials. For example, contact electrodes CNE1 and CNE2 may comprise ITO, IZO, ITZO, or aluminum (Al). For example, contact electrodes CNE1 and CNE2 may comprise transparent conductive materials, allowing light emitted from the light-emitting element 30 to travel through contact electrodes CNE1 and CNE2 toward electrodes 21 and 22. However, the disclosure is not limited to this example.

[0115] A third insulating layer, PAS3, can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2. The third insulating layer, PAS3, can be disposed on the first contact electrode CNE1 and / or the second insulating layer, in areas other than the region where the second contact electrode CNE2 is disposed. The third insulating layer, PAS3, insulates the first contact electrode CNE1 and the second contact electrode CNE2 from each other, preventing them from directly contacting each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on different layers. The first contact electrode CNE1 can be directly disposed on the second insulating layer, and the second contact electrode CNE2 can be partially directly disposed on the third insulating layer, PAS3.

[0116] A third insulating layer, PAS3, can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2, thereby insulating the first contact electrode CNE1 and the second contact electrode CNE2 from each other. As described above, in some embodiments, the third insulating layer, PAS3, may not be provided, in which case the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer.

[0117] A fourth insulating layer, PAS4, can be disposed within the entire display area DPA of the first substrate 11. The fourth insulating layer, PAS4, can protect the components disposed on the first substrate 11 from the influence of the external environment. Alternatively, the fourth insulating layer, PAS4, can be omitted.

[0118] The first insulating layer PAS1, the second insulating layer PAS2, the third insulating layer PAS3, and the fourth insulating layer PAS4 may comprise inorganic or organic insulating materials. For example, the first insulating layer PAS1, the second insulating layer PAS2, the third insulating layer PAS3, and the fourth insulating layer PAS4 may comprise materials such as silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (Al2O3 (or Al x O y The disclosure may include inorganic insulating materials such as aluminum nitride (AlN) or aluminum nitride (AlN), but is not limited thereto. In another example, the first insulating layer PAS1, the second insulating layer PAS2, the third insulating layer PAS3, and the fourth insulating layer PAS4 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene resin, polyphenylene sulfide resin, benzocyclobutene, caloric resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, or polymethyl methacrylate-polycarbonate synthetic resin, but is not limited thereto.

[0119] Figure 4 This is a schematic perspective view of the light-emitting element according to an embodiment. Figure 5 yes Figure 4 A schematic plan view of the light-emitting element. Figure 6 yes Figure 4 A schematic cross-sectional view of the light-emitting element. Figure 4 A light-emitting element 30 including an insulating film 38 is shown, with a portion of the insulating film 38 removed to reveal a semiconductor layer surrounded by the insulating film 38.

[0120] Reference Figures 4 to 6 The light-emitting element 30 can be a light-emitting diode (LED), specifically an ILED having a size from micrometers to nanometers and formed of inorganic materials. If an electric field is formed in a specific direction between two opposing electrodes, the ILED can be aligned between the two polarized electrodes. The light-emitting element 30 can be aligned by the electric field formed between the two electrodes.

[0121] The light-emitting element 30 can have a shape extending in one direction. The light-emitting element 30 can have a cylindrical, rod-like, wire-like, or tube-like shape, but there are no particular limitations on its shape. As another example, the light-emitting element 30 can have a polygonal prism shape such as a cube, cuboid, or hexagonal prism, or it can have a shape extending in one direction and including a partially inclined outer surface. The semiconductors included in the light-emitting element 30 can be sequentially arranged or stacked along the direction in which the light-emitting element 30 extends.

[0122] The light-emitting element 30 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer can receive electrical signals from an external power source and emit light within a specific wavelength range.

[0123] Reference Figures 4 to 6 The light-emitting element 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 36, an electrode layer 37, an insulating film 38, and a shell layer 39.

[0124] The first semiconductor layer 31 may include an n-type semiconductor. When the light-emitting element 30 emits light in the blue wavelength range, the first semiconductor layer 31 may include the semiconductor material Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). Semiconductor material Al x Ga y In 1-x-yN can be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The first semiconductor layer 31 can be doped with an n-type dopant, which can be Si, Ge, Se, or Sn. For example, the first semiconductor layer 31 can be n-GaN doped with n-type Si. The first semiconductor layer 31 can have a length of about 1.5 μm to about 5 μm, but the disclosure is not limited thereto.

[0125] The second semiconductor layer 32 may be disposed on the light-emitting layer 36. The second semiconductor layer 32 may include a p-type semiconductor. When the light-emitting element 30 emits light in the blue wavelength range or the green wavelength range, the second semiconductor layer 32 may include the semiconductor material Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). For example, semiconductor material Al. x Ga y In 1-x-y N can be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The second semiconductor layer 32 can be doped with a p-type dopant, which can be Mg, Zn, Ca, or Ba. For example, the second semiconductor layer 32 can be p-GaN doped with p-type Mg. The second semiconductor layer 32 can have a length of about 0.05 μm to about 0.10 μm, but the disclosure is not limited thereto.

[0126] Figures 4 to 6 The first semiconductor layer 31 and the second semiconductor layer 32 are shown to be formed as a single layer, but the disclosure is not limited thereto. As another example, depending on the material of the light-emitting layer 36, each of the first semiconductor layer 31 and the second semiconductor layer 32 may include more than one layer such as a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0127] A light-emitting layer 36 may be disposed between a first semiconductor layer 31 and a second semiconductor layer 32. The light-emitting layer 36 may comprise a material having a single quantum well structure or a multiple quantum well structure. When the light-emitting layer 36 comprises a material having a multiple quantum well structure, the light-emitting layer 36 may have a structure in which multiple quantum layers and multiple well layers are alternately stacked. The light-emitting layer 36 may emit light by recombination of electron-hole pairs in response to an electrical signal applied thereto via the first semiconductor layer 31 and the second semiconductor layer 32. When the light-emitting layer 36 emits light in the blue wavelength range, the quantum layers may comprise materials such as AlGaN or AlGaInN. When the light-emitting layer 36 has a multiple quantum well structure in which multiple quantum layers and multiple well layers are alternately stacked, the quantum layers may comprise materials such as AlGaN or AlGaInN, and the well layers may comprise materials such as GaN or AlInN. For example, when the light-emitting layer 36 comprises AlGaInN as its quantum layer and AlInN as its well layer, the light-emitting layer 36 may emit blue light having a center wavelength in the range of about 450 nm to about 495 nm.

[0128] However, the disclosure is not limited thereto. As another example, the light-emitting layer 36 may have a structure in which semiconductor materials with large bandgap energy and semiconductor materials with small bandgap energy are alternately stacked, or may include group III to group V semiconductor materials depending on the wavelength of the light to be emitted. There is no particular limitation on the type of light emitted by the light-emitting layer 36. In some embodiments, the light-emitting layer 36 may emit light in the red or green wavelength range as needed, instead of blue light. The light-emitting layer 36 may have a length of about 0.05 μm to about 0.10 μm, but the disclosure is not limited thereto.

[0129] Light can be emitted not only from the circumferential surface along the length of the light-emitting element 30, but also from both sides of the light-emitting element 30. The directionality of the light emitted from the light-emitting layer 36 is not particularly limited.

[0130] Electrode layer 37 may be an ohmic contact electrode, but the disclosure is not limited thereto. As another example, electrode layer 37 may be a Schottky contact electrode. Light-emitting element 30 may include at least one electrode layer 37. Figure 4 The illustration shows a light-emitting element 30 including an electrode layer 37, but the disclosure is not limited thereto. As another example, the light-emitting element 30 may include more than one electrode layer 37, or may not have an electrode layer 37. The following description of the light-emitting element 30 can also be directly applied to elements including more than one electrode layer 37 or having an electrode layer 37. Figures 4 to 6 The light-emitting element 30 has different structures.

[0131] When the light-emitting element 30 is electrically connected to electrodes 21 and 22 (or contact electrodes CNE1 and CNE2), the electrode layer 37 can reduce the resistance between the light-emitting element 30 and electrodes 21 and 22 (or contact electrodes CNE1 and CNE2). The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of Al, Ti, In, gold (Au), Ag, ITO, IZO, and ITZO. The electrode layer 37 may include a semiconductor material doped with an n-type dopant or a p-type dopant. However, the disclosure is not limited thereto.

[0132] The insulating film 38 may be configured to surround the first semiconductor layer 31, the second semiconductor layer 32, and the electrode layer 37. For example, the insulating film 38 may be configured to at least surround the light-emitting layer 36 and may extend in the direction along which the light-emitting element 30 extends. The insulating film 38 may protect the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 32, and the electrode layer 37. For example, the insulating film 38 may be formed around the sides of the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 32, and the electrode layer 37, and may expose the two ends of the light-emitting element 30 in the longitudinal direction.

[0133] Figures 4 to 6 The diagram shows an insulating film 38 extending in the longitudinal direction of the light-emitting element 30 to cover the sides of the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 32, and the electrode layer 37, but the disclosure is not limited thereto. The insulating film 38 may cover only some of the sides of the light-emitting layer 36 and some of the first semiconductor layer 31 and the second semiconductor layer 32, or it may cover only a portion of the sides of the electrode layer 37, such that the sides of the electrode layer 37 can be partially exposed. The insulating film 38 may be formed circular in cross-sectional view in a region adjacent to at least one end of the light-emitting element 30. The thickness WB of the insulating film 38 is... Figure 6 The thickness of the insulating film 38 is shown as uniform, but the disclosure is not limited thereto. As another example, the thickness WB of the insulating film 38 can vary partially from one region to another. For example, the insulating film 38 can typically have a uniform thickness, but on the side surface of the electrode layer 37, the thickness WB of the insulating film 38 can gradually decrease towards the top surface of the electrode layer 37, such that the top surface of the insulating film 38 can be circular in cross-sectional view.

[0134] The thickness WB of the insulating film 38 can be from about 10 nm to about 200 nm, but the disclosure is not limited thereto. The thickness WB of the insulating film 38 can be from about 40 nm to about 120 nm.

[0135] The insulating film 38 may include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N yAluminum nitride (AlN), aluminum oxide (Al) x O y Titanium oxide (TiO) x Zirconium oxide (ZrO) x or hafnium oxide (HfO) x The insulating film 38 is made of an insulating material. Therefore, the insulating film 38 can prevent short circuits that may occur when the light-emitting layer 36 is in direct contact with the electrodes that transmit electrical signals directly to the light-emitting element 30. Since the insulating film 38 covers the outer surface of the light-emitting layer 36 to protect the outer surface of the light-emitting element 30, it can prevent the degradation of the emission efficiency of the light-emitting element 30.

[0136] The outer surface of the insulating film 38 can be surface-treated. The light-emitting element 30 can be sprayed onto the electrode while being dispersed in a predetermined ink. Here, the surface of the insulating film 38 can be hydrophobic or hydrophilic treated to keep the light-emitting element 30 dispersed in the ink without agglomerating with other adjacent light-emitting elements 30. For example, the insulating film 38 can be surface-treated with materials such as stearic acid or 2,3-naphthalenedicarboxylic acid.

[0137] The light-emitting element 30 may include a shell layer 39 formed on the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32. The shell layer 39 may be formed as a separate layer and may be configured to surround the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32. For example, the shell layer 39 may be disposed on the sides of the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 32, and the electrode layer 37 to form a physical interface between the insulating film 38 and the first semiconductor layer 31 and the second semiconductor layer 32, but the disclosure is not limited thereto. In another example, the shell layer 39 may not be formed as a separate layer, but rather as a specific region with a uniform thickness adjacent to the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32, as will be described below.

[0138] The light-emitting element 30 can be obtained by epitaxial growth, which involves forming a semiconductor layer on a target substrate and etching the grown semiconductor layer in a direction perpendicular to the top surface of the target substrate. Depending on the growth conditions, the semiconductor layer can be grown smoothly on the target substrate without any intercrystalline lattice defects, but defects will appear on the etched surface of the semiconductor layer during etching. For example, if the first semiconductor layer 31 is obtained by growing a semiconductor layer including n-GaN on the target substrate and etching the semiconductor layer, defects such as gallium (Ga) vacancies or dangling bonds will be formed on the outer surface of the first semiconductor layer 31. Such defects cause electrons to leak from the first semiconductor layer 31, thus increasing the number of non-luminescent electrons in the light-emitting layer 36. As another example, electrons can be trapped on surfaces with such defects, causing non-emissive bonding, whereby the electrons are converted into heat instead of light. Therefore, the heat generated by the light-emitting element 30 will increase, or fluorescence quenching may occur, thus reducing the emission efficiency of the light-emitting element 30.

[0139] To prevent this, the light-emitting element 30 may include a shell layer 39 formed on the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32, thereby compensating for any defects formed on the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32 after the etching process during the manufacture of the light-emitting element 30. When the shell layer 39 is formed on the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32 exposed by etching, the shell layer 39 can be used to fill any Ga vacancies formed after etching. Therefore, the light-emitting element 30 can prevent the flow of electrons due to such defects or non-emissive bonding, thereby improving light conversion efficiency.

[0140] The shell 39 of the light-emitting element 30 may include a divalent metal element. For example, the shell 39 may include at least one of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), and cadmium (Cd). The divalent metal element of the shell 39 can compensate for defects in the first semiconductor layer 31 and the second semiconductor layer 32 by filling Ga vacancies formed on the outer surfaces of the first semiconductor layer 31 and the second semiconductor layer 32. For example, the number of defects in the first semiconductor layer 31 can be reduced by filling the defects in the first semiconductor layer 31 with a divalent group II or group XII metal element. Specifically, when the first semiconductor layer 31 is doped with n-type impurities, due to the compensating doping effect caused by filling the vacancies in the first semiconductor layer 31 with the divalent metal element of the shell 39, the electron concentration on the outer surface of the first semiconductor layer 31 can become lower than the electron concentration on the inner surface of the first semiconductor layer 31, and most of the electrons injected into the light-emitting element 30 can flow on the inner surface of the light-emitting element 30 instead of the outer surface of the light-emitting element 30. For example, it can prevent electron leakage caused by defects in the first semiconductor layer 31 or prevent non-emission binding caused by trapped electrons. Therefore, the emission efficiency of the light-emitting element 30 can be improved, and the heat generated by the light-emitting element 30 can be reduced.

[0141] Conversely, when a semiconductor layer other than the first semiconductor layer 31 (e.g., the second semiconductor layer 32) is doped with p-type impurities, the doping concentration of the p-type impurities in the second semiconductor layer 32 can vary from one location to another because the vacancies in the second semiconductor layer 32 are filled with divalent metal elements forming a shell layer 39 on the outer surface of the second semiconductor layer 32. The shell layer 39 can serve as an insulating layer surrounding the second semiconductor layer 32 and can protect the second semiconductor layer 32 rather than providing a doping compensation effect. For example, when the shell layer 39 of the light-emitting element 30 includes a divalent metal element, the shell layer 39 can provide a doping compensation effect on the first semiconductor layer 31, allowing the electron density in the first semiconductor layer 31 to change. Due to the change in the doping concentration of impurities in the second semiconductor layer 32, the shell layer 39 can serve as an insulating layer. Since the light-emitting element 30 includes a shell layer 39 to compensate for any defects in the first semiconductor layer 31 and the second semiconductor layer 32 during the manufacturing of the light-emitting element 30, the light conversion efficiency and emission characteristics of the light-emitting element 30 can be improved.

[0142] For example, shell 39 may include an inorganic compound having a divalent metal element and may be configured to surround the first semiconductor layer 31 and the second semiconductor layer 32. Shell 39 may be formed from an inorganic compound in which a divalent cationic metal and a divalent anionic nonmetal are combined. For example, shell 39 may include at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe. When shell 39 is formed from an inorganic compound such as ZnS, ZnSe, MgS, MgSe, ZnMgS, or ZnMgSe as a separate layer from the first semiconductor layer 31 and the second semiconductor layer 32 to form a physical interface with the first semiconductor layer 31 and the second semiconductor layer 32, the divalent cationic metal element of shell 39 can compensate for defects in the first semiconductor layer 31 and the second semiconductor layer 32 by filling vacancies formed on the surfaces of the first semiconductor layer 31 and the second semiconductor layer 32. In this case, insulating film 38 can be formed by direct bonding with the inorganic compound of shell 39. The insulating film 38, including inorganic insulating materials such as silicon dioxide, can form chemical bonds with the shell 39, which is formed by divalent cationic metal elements and divalent anionic nonmetal elements.

[0143] In some embodiments, the shell layer 39, formed as a single layer, may have a thickness WC of about 0.5 nm to about 10 nm. The shell layer 39 may be formed as a multilayer (e.g., five layers) in which single layers of inorganic compound particles are stacked, but the disclosure is not limited thereto. When the thickness WC of the shell layer 39 is about 0.5 nm to about 10 nm, the shell layer 39 can compensate for defects in the first semiconductor layer 31 using compensating doping effects without degrading the electrical properties of the first semiconductor layer 31. Since the light-emitting element 30 also includes the shell layer 39 disposed between the insulating film 38 and the semiconductor layer of the light-emitting element 30, defects formed in the semiconductor layer of the light-emitting element 30 during the manufacture of the light-emitting element 30 can be compensated, and the optical efficiency of the light-emitting element 30 can be improved.

[0144] The height h of the light-emitting element 30 can be in the range of about 1 μm to about 10 μm, about 2 μm to about 6 μm, or about 3 μm to about 5 μm, but the disclosure is not limited thereto. The diameter WA of the light-emitting element 30 can be about 30 nm to about 700 nm, and the aspect ratio of the light-emitting element 30 can be about 1.2 to about 100, but the disclosure is not limited thereto. As another example, the light-emitting element 30 included in the display device 10 can have different diameters depending on the differences in the composition of the light-emitting layer 36. The light-emitting element 30 can have a diameter of about 500 nm.

[0145] Figure 7 This is a schematic cross-sectional view of a light-emitting element according to another embodiment.

[0146] Reference Figure 7 The insulating film 38_1 of the light-emitting element 30_1 may include multiple layers 38A and 38B. The insulating film 38_1 may include a first layer 38A that directly contacts the shell layer 39 and a second layer 38B that surrounds the first layer 38A. Figure 7 Implementation examples and Figure 6 The difference in the embodiments lies at least in that the insulating film 38_1 is formed as a multilayer. The insulating film 38_1 can be formed of an inorganic insulating material to protect the light-emitting layer 36, the first semiconductor layer 31, the second semiconductor layer 32, and the electrode layer 37 of the light-emitting element 30_1, but the amount of light generated by the light-emitting layer 36 is affected by the type of inorganic insulating material. The light-generating efficiency of the light-emitting layer 36 is reduced due to the electric field caused by the fixed charge in the portion of the insulating film 38_1 adjacent to the light-emitting layer 36. To prevent this, the first layer 38A, which contacts the shell layer 39 on the outer surface of the light-emitting layer 36, and the second layer 38B, which is disposed on the outermost side of the light-emitting element 30_1, are formed of different materials. Therefore, the light-emitting layer 36 can be protected, and the optical efficiency of the light-emitting element 30_1 can be improved.

[0147] For example, the first layer 38A of the insulating film 38_1 may include silicon oxide, and the second layer 38B of the insulating film 38_1 may include aluminum oxide. When the first layer 38A, which directly contacts the shell layer 39 inside the insulating film 38_1, contains silicon oxide, the light generation efficiency of the light-emitting layer 36 can be prevented from decreasing due to the fixed charge in the first layer 38A. When the second layer 38B, disposed on the outer surface of the first layer 38A, contains aluminum oxide, the light-emitting element 30_1 can be safely protected. The first layer 38A and the second layer 38B are in... Figure 7 The layers are shown to have the same thickness, but the disclosure is not limited thereto. As another example, the first layer 38A may be thicker than the second layer 38B.

[0148] Will be described below Figure 4 Manufacturing of the light-emitting element 30.

[0149] Figure 8 This is a schematic flowchart illustrating a method for manufacturing a light-emitting element according to an embodiment.

[0150] Reference Figure 8The method may include the following steps: forming a component rod ROD on a target substrate 100 (S100); forming a shell layer 39 on the outer surface of the component rod ROD (S200); forming an insulating film 38 to surround the shell layer 39 of the component rod ROD (S300); and separating the component rod ROD having the insulating film 38 therein from the target substrate 100 (S400). In S100, the component rod ROD can be formed by an etching process in which a semiconductor layer is vertically etched, and then the shell layer 39 can be formed to compensate for any defects formed on the outer surface of the component rod ROD. Reference will be made below. Figures 9 to 18 To describe in further detail Figure 8 The method.

[0151] Figures 9 to 18 It shows Figure 8 A schematic diagram of the method.

[0152] Reference Figure 9 A target substrate 100 can be prepared, comprising a substrate 110 and a buffer material layer 120 formed on the substrate 110. The substrate 110 may include a transparent substrate such as a sapphire (Al2O3) substrate or a glass substrate, but the disclosure is not limited thereto. As another example, the substrate 110 may be a conductive substrate formed of, for example, GaN, SiC, ZnO, Si, GaP, or GaAs. The substrate 110 will be described below as, for example, a sapphire substrate. The thickness of the substrate 110 is not particularly limited, but the substrate 110 may have a thickness of about 400 μm to about 1500 μm.

[0153] A semiconductor layer can be formed on the substrate 110. The semiconductor layer can be formed by epitaxial growth through seed crystal growth. The semiconductor layer can be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-mode thermal evaporation, sputtering, or metal-organic chemical vapor deposition (MOCVD), but the disclosure is not limited thereto.

[0154] There are no particular limitations on the type of precursor material used to form the semiconductor layer. For example, the precursor material may include a metal precursor having an alkyl group (such as methyl or ethyl). For example, the metal precursor may be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4), but the disclosure is not limited thereto. The semiconductor layer can be formed by using deposition processes using both metal and non-metal precursors. A description of how and under what conditions the semiconductor layer is formed will be omitted; instead, the sequence in which the light-emitting element 30 is fabricated and the stacked structure of the light-emitting element 30 will be described below.

[0155] A buffer material layer 120 can be formed on the substrate 110. Figure 9 The illustration shows the deposition of a single buffer material layer 120 on a substrate 110, but the disclosure is not limited thereto. As another example, multiple buffer material layers 120 may be formed. The buffer material layers 120 may be configured to reduce the difference in lattice constant between the first semiconductor material layer 310 and the substrate 110.

[0156] For example, the buffer material layer 120 may include an undoped semiconductor. The buffer material layer 120 may include the same material as the first semiconductor material layer 310, and may include a material undoped of n-type or p-type impurities. For example, the buffer material layer 120 may include at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but the disclosure is not limited thereto. The buffer material layer 120 may be omitted depending on the type of the substrate 110. The buffer material layer 120 will be described below as being formed of an undoped semiconductor on the substrate 110.

[0157] Subsequently, refer to Figure 10 A semiconductor structure 300 can be formed on the target substrate 100. The semiconductor structure 300 may include a first semiconductor material layer 310, a light-emitting material layer 360, a second semiconductor material layer 320, and an electrode material layer 370. The material layers of the semiconductor structure 300 can be formed by the typical process described above, and the material layers of the semiconductor structure 300 may correspond to the layers of each of the light-emitting elements 30 to be formed. For example, the first semiconductor material layer 310, the light-emitting material layer 360, the second semiconductor material layer 320, and the electrode material layer 370 may each include the same material as the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 320, and the electrode layer 370 of each of the light-emitting elements 30.

[0158] Subsequently, refer to Figure 11 The semiconductor structure 300 is etched to form spaced element rods (RODs). The semiconductor structure 300 can be etched using typical patterning methods. For example, the semiconductor structure 300 can be etched by forming an etching mask layer on the semiconductor structure 300 and etching the semiconductor structure 300 in a direction perpendicular to the target substrate 100 using the etching mask layer.

[0159] For example, the etching of the semiconductor structure 300 can be performed by dry etching, wet etching, reactive ion etching (RIE), or inductively coupled plasma reactive ion etching (ICP-RIE). Dry etching, as anisotropic etching, can be suitable for vertically etching the semiconductor structure 300. During the etching of the semiconductor structure 300, Cl2 or O2 can be used as an etchant, but the disclosure is not limited thereto. In some embodiments, the etching of the semiconductor structure 300 can be performed by both dry etching and wet etching. For example, the semiconductor structure 300 can be first etched in the depth direction by dry etching, and then the semiconductor structure 300 can be etched by wet etching, as isotropic etching, such that the etched sidewalls can fall on a plane (or multiple planes) perpendicular to the surface of the semiconductor structure 300.

[0160] As a result of etching the semiconductor structure 300, holes can be formed in the semiconductor structure 300. A first semiconductor material layer 310, a light-emitting material layer 360, a second semiconductor material layer 320, and an electrode material layer 370 can form element rods (RODs). Each element rod ROD may include a first semiconductor layer 31, a light-emitting layer 36, a second semiconductor layer 32, and an electrode layer 37. The element rods RODs can be separated from each other, and holes are located between the element rods RODs. The buffer material layer 120 of the target substrate 100 can be partially exposed in or through the holes, and the element rods RODs are separated from each other by the holes.

[0161] As a result of etching the semiconductor structure 300, defects will form on the outer surface of the component rod ROD. (Refer to...) Figure 12 , showed Figure 11 The enlarged view of region A illustrates defect DFTs, such as vacancies, that can form on the outer surface of the first semiconductor layer 31 exposed by etching of the semiconductor structure 300. As described above, defect DFTs can lead to leakage of injected electrons or non-emission bonding and reduce the optical efficiency of the light-emitting element 30. To prevent this, an element rod ROD can be formed by etching the semiconductor structure 300 during the fabrication of the light-emitting element 30, and then a shell layer 39 can be formed to compensate for the defect DFTs formed in the first semiconductor layer 31.

[0162] Reference Figure 13 and Figure 14A shell material layer 390 can be formed around the outer surface of the element rod ROD by immersing the target substrate 100 on which the element rod ROD is formed into a solution S containing a first precursor material P1 and a second precursor material P2. The shell material layer 390 will form a shell layer 39. For example, the shell layer 39 included in the light-emitting element 30 can be formed using a wet process using a solution S in which the first precursor material P1 and the second precursor material P2 are mixed. When the target substrate 100 on which the element rod ROD is formed is immersed in the solution S, the first precursor material P1 and the second precursor material P2 in the solution S can react with the outer surface of the element rod ROD to form the shell material layer 390. The first precursor material P1 may include a divalent cationic metal, and the second precursor material P2 may include a divalent anionic nonmetal. The shell material layer 390 can be formed not only on the side and top surfaces of the element rod ROD, but also on the buffer material layer 120 of the target substrate 100. During the formation of the insulating film 38, the shell material layer 390 can be partially removed, thereby forming a shell layer 39 surrounding the side surface of the element rod ROD.

[0163] Subsequently, refer to Figures 15 to 17 An insulating film 38 can be formed to surround a portion of the side surface of the component rod ROD, and a shell material layer 390 is formed on the portion of the side surface of the component rod ROD. For example... Figure 16 As indicated by "etching", the insulating film 38 and the shell layer 39 can be formed by forming an insulating layer 380 on the shell material layer 390 and partially removing the insulating layer 380 and the shell material layer 390 to expose the first end of the element rod ROD (e.g., the top surface of the electrode layer 37 of the element rod ROD). Therefore, the shell material layer 390 and the insulating layer 380 can be formed as the shell layer 39 and the insulating film 38, respectively.

[0164] An insulating layer 380, which is an insulating material formed on the outer surface of a component rod ROD, can be formed by coating an insulating material onto a vertically etched component rod ROD or by immersing the component rod ROD in an insulating material, but the disclosure is not limited thereto. For example, the insulating layer 380 can be formed by atomic layer deposition (ALD) or CVD.

[0165] Similar to the shell material layer 390, an insulating layer 380 can be formed on the side and top surfaces of the component rod ROD and on the portions of the target substrate 100 exposed between the component rod RODs. The insulating layer 380 and the shell material layer 390 can be partially removed by a dry etching or etch-back process, which is anisotropic etching. When removing the portion of the insulating layer 380 on the top surface of the component rod ROD, the electrode layer 37 can be exposed and partially removed. For example, the thickness of the electrode layer 37 of the finally manufactured light-emitting element 30 can be smaller than the thickness of the electrode material layer 370 formed during the manufacturing of the light-emitting element 30.

[0166] The top surface of electrode layer 37 is shown as exposed, and the top surface of insulating film 38 is shown as flat. However, the disclosure is not limited thereto. As another example, insulating film 38 may be formed with a partially curved outer surface in the region surrounding electrode layer 37. During partial removal of insulating layer 380, the top and side surfaces of insulating layer 380 may be partially removed, such that insulating film 38 surrounding layers included in each of the element rod RODs may be formed with partially etched side surfaces. Specifically, when the top surface of insulating layer 380 is removed, insulating film 38 may be formed such that portions of its outer surface adjacent to electrode layer 37 may be partially removed.

[0167] Subsequently, refer to Figure 18 The element rod ROD, in which the shell layer 39 and the insulating film 38 are formed, can be separated from the target substrate 100, thereby obtaining the light-emitting element 30. The light-emitting element 30 may include the shell layer 39 to compensate for defects in the semiconductor layer of the semiconductor structure 300 formed due to vertical etching. Figure 8 The method includes forming a shell 39 through a wet process, thereby producing the light-emitting element 30 while preventing a decrease in the optical efficiency of the light-emitting element 30.

[0168] Figure 4 The shape and material of the light-emitting element 30 are not particularly limited. For example, the light-emitting element 30 may include materials larger than those used in the past. Figure 4 Multiple layers, and with Figure 4 Different shapes.

[0169] Figure 19 This is a schematic perspective view of a light-emitting element according to another embodiment. Figure 20 yes Figure 19 A schematic cross-sectional view of the light-emitting element. Figure 20 It shows Figure 19 A schematic longitudinal cross-sectional view of the light-emitting element 30_2 is shown, and a semiconductor layer is stacked in the light-emitting element 30_2.

[0170] Reference Figure 19 and Figure 20The light-emitting element 30_2 may further include a third semiconductor layer 33_2, a fourth semiconductor layer 34_2, and a fifth semiconductor layer 35_2. The third semiconductor layer 33_2 is disposed between the first semiconductor layer 31_2 and the light-emitting layer 36_2, and the fourth semiconductor layer 34_2 and the fifth semiconductor layer 35_2 are disposed between the light-emitting layer 36_2 and the second semiconductor layer 32_2. Figure 4 The difference in the light-emitting element 30 may be at least that the light-emitting element 30_2 further includes a third semiconductor layer 33_2, a fourth semiconductor layer 34_2, and a fifth semiconductor layer 35_2, as well as an electrode layer (e.g., a first electrode layer 37A_2 and a second electrode layer 37B_2), and the light-emitting layer 36_2 includes... Figure 4 The light-emitting layer has 36 different elements. The following discussion will focus primarily on the elements related to... Figure 4 The difference between the light-emitting elements 30 and 30 is used to describe the light-emitting element 30_2.

[0171] Figure 4 The light-emitting layer 36 of the light-emitting element 30 may include nitrogen (N) and can therefore emit blue or green light. Conversely, the light-emitting layer 362 and semiconductor layer of the light-emitting element 30_2 may include a semiconductor containing at least phosphorus (P). The light-emitting element 30_2 can emit red light having a center wavelength range of about 620 nm to about 750 nm. However, the center wavelength range of the red light emitted by the light-emitting element 30_2 is not particularly limited and should be understood to cover all wavelengths that can be perceived as red.

[0172] Specifically, the first semiconductor layer 31_2 may be an n-type semiconductor layer and may include layers having the chemical formula In. x Al y Ga 1-x-y The semiconductor material P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1) may be used. The first semiconductor layer 31_2 may include one of InAlGaP, GaP, AlGaP, InGaP, AlP, and InP doped with an n-type dopant. For example, the first semiconductor layer 31_2 may be n-AlGaInP doped with n-type Si.

[0173] The second semiconductor layer 32_2 may be a p-type semiconductor layer, and may include a semiconductor layer having the chemical formula In. x Al y Ga 1-x-y The second semiconductor layer 32_2 may include one of the following: InAlGaP, GaP, AlGaNP, InGaP, AlP, and InP, all doped with p-type dopants. For example, the second semiconductor layer 32_2 may be p-GaP doped with p-type Mg.

[0174] A light-emitting layer 36_2 may be disposed between a first semiconductor layer 31_2 and a second semiconductor layer 32_2. The light-emitting layer 36_2 may comprise a material having a single quantum well structure or a multiple quantum well structure, and thus may emit light within a specific wavelength range. In the case where the light-emitting layer 36_2 has a structure in which quantum layers and well layers are alternately stacked, the quantum layers may comprise AlGaP or AlInGaP, and the well layers may comprise GaP or AlInP. For example, the light-emitting layer 36_2 may comprise AlGaInP as a quantum layer and AlInP as a well layer, and thus may emit red light with a center wavelength range of approximately 620 nm to approximately 750 nm.

[0175] Figure 19 The light-emitting element 30_2 may include a covering layer disposed adjacent to the light-emitting layer 36_2. For example... Figure 19 As shown, the third semiconductor layer 33_2 and the fourth semiconductor layer 34_2 disposed between the first semiconductor layer 31_2 and the second semiconductor layer 32_2 can be cladding layers.

[0176] The third semiconductor layer 33_2 can be disposed between the first semiconductor layer 31_2 and the light-emitting layer 36_2. Similar to the first semiconductor layer 31_2, the third semiconductor layer 33_2 can be an n-type semiconductor and can include components having the chemical formula In. x Al y Ga 1-x-y A semiconductor material P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). For example, the first semiconductor layer 31_2 can be n-AlGaInP, and the third semiconductor layer 33_2 can be n-AlInP. However, the disclosure is not limited to this example.

[0177] A fourth semiconductor layer 34_2 can be disposed between the light-emitting layer 36_2 and the second semiconductor layer 32_2. Similar to the second semiconductor layer 32_2, the fourth semiconductor layer 34_2 can be a p-type semiconductor and can include components having the chemical formula In. x Al y Ga 1-x-y A semiconductor material of type P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ x + y ≤ 1). For example, the second semiconductor layer 32_2 can be p-GaP, and the fourth semiconductor layer 34_2 can be p-AlInP.

[0178] A fifth semiconductor layer 35_2 may be disposed between the second semiconductor layer 32_2 and the fourth semiconductor layer 34_2. Similar to the second semiconductor layer 32_2 and the fourth semiconductor layer 34_2, the fifth semiconductor layer 35_2 may include a semiconductor doped with a p-type dopant. In some embodiments, the fifth semiconductor layer 35_2 may be disposed to reduce the difference in lattice constant between the second semiconductor layer 32_2 and the fourth semiconductor layer 34_2. The fifth semiconductor layer 35_2 may be a TSBR layer. For example, the fifth semiconductor layer 35_2 may include p-GaInP, p-AlInP, or p-AlGaInP, but the disclosure is not limited thereto. The third semiconductor layer 33_2, the fourth semiconductor layer 34_2, and the fifth semiconductor layer 35_2 may have a length of about 0.08 μm to about 0.25 μm, but the disclosure is not limited thereto.

[0179] The first electrode layer 37A_2 and the second electrode layer 37B_2 can be respectively disposed on the first semiconductor layer 31_2 and the second semiconductor layer 32_2. The first electrode layer 37A_2 can be disposed on the bottom surface of the first semiconductor layer 31_2, and the second electrode layer 37B_2 can be disposed on the top surface of the second semiconductor layer 32_2. However, the disclosure is not limited thereto, and one of the first electrode layer 37A_2 and the second electrode layer 37B_2 may not be disposed. For example, the light-emitting element 30_2 may not have the first electrode layer 37A_2 on the bottom surface of the first semiconductor layer 31_2, but may only include the second electrode layer 37B_2 on the top surface of the second semiconductor layer 32_2.

[0180] Shell layer 39_2 can be disposed on the side surfaces of the first semiconductor layer 31_2, the third semiconductor layer 33_2, the light-emitting layer 36_2, the fourth semiconductor layer 34_2, the fifth semiconductor layer 35_2, the second semiconductor layer 32_2, the first electrode layer 37A_2, and the second electrode layer 37B_2. Insulating film 38_2 can cover shell layer 39_2 or be stacked with shell layer 39_2. Figure 4 Similar to the light-emitting element 30, the light-emitting element 30_2 can be formed by vertically etching the semiconductor structure 300, and a shell layer 39_2 can be formed to compensate for defects that may form in the semiconductor layer of the light-emitting element 30_2 during the etching of the semiconductor structure 300. The light-emitting element 30_2 may include more than Figure 4 The light-emitting element 30 has multiple semiconductor layers and can emit red light.

[0181] Figure 4The shell layer 39 of the light-emitting element 30 (used to compensate for defects formed in the semiconductor layer of the light-emitting element 30 (specifically, in the first semiconductor layer 31 of the light-emitting element 30)) does not necessarily need to be formed as a separate layer. As another example, the shell layer 39 can be formed by doping the semiconductor layer of the light-emitting element 30 with a divalent cationic metal, and a portion of the semiconductor layer of the light-emitting element 30 can be formed as the shell layer 39. In this case, the shell layer 39 can be formed as a doped region in the semiconductor layer of the light-emitting element 30, and the insulating film 38 can be directly disposed on the outer surface of the semiconductor layer of the light-emitting element 30.

[0182] Figure 21 This is a schematic perspective view of a light-emitting element according to another embodiment. Figure 22 yes Figure 21 A schematic cross-sectional view of the light-emitting element. Figure 21 A portion of the insulating film 38_3 is shown to be removed to reveal the light-emitting element 30_3, which is surrounded by a semiconductor layer of insulating film 38_3.

[0183] Reference Figure 21 and Figure 22 The light-emitting element 30_3 may include a shell layer 39_3, which is formed as a region doped with a divalent metal element in portions of the first semiconductor layer 31_3, the light-emitting layer 36_3, and the second semiconductor layer 32_3. The shell layer 39_3 may be formed with a predetermined thickness WC from the side surfaces of the first semiconductor layer 31_3, the light-emitting layer 36_3, and the second semiconductor layer 32_3. The light-emitting element 30_3 and... Figures 4 to 6 The difference in the light-emitting element 30 can be at least in that the shell layer 39_3 is not formed as a separate layer disposed on the side surface of the semiconductor layer of the light-emitting element 30_3, but is formed as a region in the semiconductor layer doped with divalent metal elements, so that the shell layer 39_3 is formed without a physical boundary with the semiconductor layer. The following will mainly focus on the relationship with... Figures 4 to 6 The differences in the light-emitting element 30 are used to describe the light-emitting element 30_3.

[0184] The divalent metal can have a size similar to the lattice size of the Ga-containing semiconductor layer crystal, and the Ga vacancies formed in the first semiconductor layer 31_3 can be compensated by directly doping the first semiconductor layer 31_3 with a specific metal element. During the fabrication of the light-emitting element 30_3, the element rod ROD can be formed by etching the semiconductor structure 300, and the side surfaces of the element rod ROD can be doped with divalent metal by immersing the semiconductor structure 300 in a solution S in which divalent cationic metal is dispersed. The divalent cationic metal included in the solution S can directly fill the Ga vacancies and can form a shell layer 39_3, which is a doped region with a predetermined thickness from the outer surface of the semiconductor layer of the light-emitting element 30_3. The divalent cationic metal can be doped into the first semiconductor layer 31_3, the second semiconductor layer 32_3, and the light-emitting layer 36_3, but not into the electrode layer 37_3. For example, shell layer 39_3 may be formed in the first semiconductor layer 31_3, the second semiconductor layer 32_3, and the light-emitting layer 36_3, but not in the electrode layer 37_3. The first semiconductor layer 31_3, the second semiconductor layer 32_3, and the light-emitting layer 36_3 may include Ga, In, and N, or Ga, In, and P, and may be formed by epitaxial growth and selectively doped with divalent cationic metals. Conversely, electrode layer 37_3 comprising a material different from the first semiconductor layer 31_3, the second semiconductor layer 32_3, and the light-emitting layer 36_3 (e.g., a material such as ITO) may not be doped with divalent cationic metals, and shell layer 39_3 may not be formed in electrode layer 37_3.

[0185] The shell 39_3, which serves as the doped region formed in the semiconductor layer of the light-emitting element 30_3, can provide [something related to the doped region]. Figure 4 The effect is similar to that when the shell 39 is formed as a separate layer. For example, with Figure 4 Similar to shell 39, shell 39_3 formed of divalent cationic metal can compensate for defects in semiconductor layer, and divalent cationic metal doped into second semiconductor layer 32_3 can be used as insulating layer.

[0186] and Figure 4 Unlike the light-emitting element 30, the light-emitting element 30_3 can have a relatively small diameter WA, and the shell layer 39_3 can be formed as a doped region with a predetermined thickness from the side surface of the semiconductor layer. For example, the shell layer 39_3 of the light-emitting element 30_3 can include a divalent cationic metal such as beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zinc (Zn), or cadmium (Cd). The shell layer 39_3 formed as a doped region can have approximately to approximately The thickness of WC, and can be doped with about 10 10 / cm 3 To about 1018 / cm 3 The amount of divalent cationic metal doped in the shell 39_3 is disclosed, but is not limited thereto. The thickness WC of the shell 39_3 and the amount of divalent cationic metal doped in the shell 39_3 can be controlled according to the number or density of defects formed in the semiconductor layer of the light-emitting element 30_3. Since the light-emitting element 30_3 includes a shell 39_3 doped with a divalent metal element, defects that may form in the semiconductor layer during the manufacturing of the light-emitting element 30_3 can be compensated, and the emission efficiency of the light-emitting element 30_3 can be improved.

[0187] Figure 23 This is a schematic perspective view of a light-emitting element according to another embodiment. Figure 24 yes Figure 23 A schematic cross-sectional view of the light-emitting element.

[0188] Reference Figure 23 and Figure 24 ,and Figure 19 Similar to the light-emitting element 30_2, the light-emitting element 30_4 may include a semiconductor layer containing P and emits red light. (And...) Figure 21 Similar to the shell 39_3 of the light-emitting element 30_3, the shell 39_4 of the light-emitting element 30_4 can be formed as a doped region on the outer surface of the semiconductor layer of the light-emitting element 30_4. The shell 39_4, which is a region formed in the first semiconductor layer 31_4, the second semiconductor layer 32_4, the third semiconductor layer 33_4, the fourth semiconductor layer 34_4, the fifth semiconductor layer 35_4, and the light-emitting layer 36_4 and doped with group II or group XII metal elements, can be formed to have a predetermined thickness WC from the side surface of the semiconductor layer of the light-emitting element 30_4. The shell 39_4 may not be formed in the first electrode layer 37A_4 and the second electrode layer 37B_4, and the insulating film 38_4 can be formed to cover the shell 39_4 and the side surfaces of the first electrode layer 37A_3 and the second electrode layer 37B_4. The light-emitting element 30_4 can be... Figure 19 The light-emitting element 30_2 and Figure 21 The combination of light-emitting elements 30_3 is omitted in its detailed description.

[0189] Will be described below Figure 4 Production examples of the light-emitting element 30 and evaluation of the production examples.

[0190] <Production Example 1: Manufacturing of a light-emitting element including a shell formed of inorganic compounds>

[0191] according to Figure 4The embodiments of the invention fabricate a light-emitting element 30 comprising a shell 39 formed as a layer separate from the semiconductor layer. Specifically, light-emitting element samples SAMPLE#1 to SAMPLE#8 are obtained by epitaxially growing a first semiconductor layer 31 comprising GaN, a second semiconductor layer 32, a light-emitting layer 36, and an electrode layer 37 on a sapphire (Al2O3) substrate, and by varying the type of inorganic compound used therein and the thickness of the shell 39.

[0192] In the light-emitting element samples SAMPLE#1 to SAMPLE#8, the type of precursor used to form the shell 39 can be varied from one sample to another depending on the type of metal element. Zinc nitrate was used as the precursor for the shell 39 containing Zn, and sodium sulfide was used as the precursor for the shell 39 containing sulfur (S). Each precursor was dissolved in distilled water at a concentration of about 0.01 mol to about 1.0 mol to prepare a precursor solution. The temperature of the precursor solution was about 60°C when impregnating each element rod ROD, and each element rod ROD was impregnated for about 1 hour. Afterward, each element rod ROD was removed from the precursor solution, washed with distilled water, and dried, and in subsequent processes, light-emitting element samples SAMPLE#1 to SAMPLE#8 were obtained.

[0193] and Figure 7 Similar to the light-emitting element 30_1, each of the light-emitting element samples SAMPLE#1 to SAMPLE#8 may include a multilayer insulating film 38, the multilayer insulating film 38 including a first layer 38A having a thickness of about 80 nm and formed of silicon oxide (SiO2) and a second layer 38B having a thickness of about 40 nm and formed of aluminum oxide (Al2O3). As a control group for comparison with light-emitting element samples SAMPLE#1 to SAMPLE#8, light-emitting element samples SAMPLE#9 to SAMPLE#11 were manufactured without at least one of the shell layer 39 and insulating film 38. Table 1 below shows examples of... Production Example 1 Samples of the manufactured light-emitting elements, SAMPLE#1 to SAMPLE#11.

[0194] Table 1

[0195] Light-emitting element sample Shell (composition / thickness) <![CDATA[Insulating film (SiO2 / Al2O3)]]> SAMPLE#1 ZnS / 1nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #2 ZnS / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #3 ZnS / 3nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #4 ZnSe / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #5 MgS / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#6 MgSe / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #7 ZnMgS / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#8 ZnMgSe / 2nm <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#9 - - SAMPLE #10 - <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#11 ZnS / 2nm -

[0196] <Production Example 2: Fabrication of a light-emitting element including a shell formed as a doped region>

[0197] according to Figure 21The embodiment fabricates a light-emitting element 30_3 having a shell layer 39_3 formed as a doped region on the outside of the semiconductor layer. A first semiconductor layer 31_3, a second semiconductor layer 32_3, a light-emitting layer 36_3, and an electrode layer 37_3 comprising GaN are formed on a sapphire (Al2O3) substrate by epitaxial growth, and each element rod ROD is immersed in a solution containing a precursor for forming the shell layer 39_3, and light-emitting element samples SAMPLE#12 to SAMPLE#18 are obtained.

[0198] In the light-emitting element samples SAMPLE#12 to SAMPLE#18, the type of precursor used to form the shell 39_3 can vary depending on the type of metal element used to form the shell 39_3. Zinc nitrate was used as the precursor for the Zn-containing shell 39_3, and sodium sulfide was used as the precursor for the sulfur (S)-containing shell 39_3. Each precursor was dissolved in distilled water at a concentration of about 0.01 mol to about 1.0 mol to prepare a precursor solution. The temperature of the precursor solution was about 60°C when impregnating each element rod ROD, and each element rod ROD was impregnated for about 1 hour. Afterward, each element rod ROD was removed from the precursor solution, washed with distilled water, and dried, and in subsequent processes, light-emitting element samples SAMPLE#12 to SAMPLE#18 were obtained.

[0199] and Figure 7 Similar to the light-emitting element 30_1, each of the light-emitting element samples SAMPLE#12 to SAMPLE#18 may include a multilayer insulating film 38, the multilayer insulating film 38 including a first layer 38A having a thickness of about 80 nm and formed of SiO2 and a second layer 38B having a thickness of about 40 nm and formed of Al2O3. As a control group for comparison with the light-emitting element samples SAMPLE#12 to SAMPLE#18, light-emitting element samples SAMPLE#19 to SAMPLE#21 were manufactured without at least one of the shell layer 39_3 and the insulating film 38_3. Table 2 below shows examples of... Production Example 2 Samples of the manufactured light-emitting elements, SAMPLE#12 to SAMPLE#21.

[0200] Table 2

[0201] Light-emitting element sample Shell (metal atoms) <![CDATA[Insulating film (SiO2 / Al2O3)]]> SAMPLE #12 Be <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#13 Mg <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#14 Ca <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE #15 Sr <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#16 Ba <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#17 Zn <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#18 Cd <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#19 - - SAMPLE#20 - <![CDATA[SiO2(80nm) / Al2O3(40nm)]]> SAMPLE#21 Zn -

[0202] <Experimental Example 1: Evaluation of the Emission Characteristics of a Light-Emitting Element>

[0203] The emission characteristics of the light-emitting element samples SAMPLE#1 to SAMPLE#11 prepared in Production Example 1 were evaluated. Specifically, the photoluminescence of the light-emitting element samples SAMPLE#1 to SAMPLE#11 was evaluated, and the intensity of light with a center wavelength of approximately 445 nm and light with a center wavelength of approximately 560 nm in the light beam emitted from each of the light-emitting element samples SAMPLE#1 to SAMPLE#11 were measured. The measurement results were expressed relative to the intensity of light emitted from the light-emitting element sample SAMPLE#9, as shown in Table 3 below.

[0204] Table 3

[0205] Light-emitting element sample Intensity of 445nm light Intensity of 560nm light SAMPLE#1 25 0.49 SAMPLE #2 25 0.45 SAMPLE #3 26 0.55 SAMPLE #4 25 0.56 SAMPLE #5 24 0.51 SAMPLE#6 25 0.59 SAMPLE #7 24 0.52 SAMPLE#8 25 0.57 SAMPLE#9 1 1 SAMPLE #10 25 1 SAMPLE#11 1 0.45

[0206] <Experimental Example 2: Evaluation of the Emission Characteristics of Light-Emitting Elements>

[0207] The emission characteristics of the light-emitting element samples SAMPLE#12 to SAMPLE#21 prepared in Production Example 2 were evaluated. (Compared with...) Experimental Example 1 The photoluminescence of light-emitting element samples SAMPLE#12 to SAMPLE#21 was evaluated in the same manner. The intensity of light emitted from each of the light-emitting element samples SAMPLE#12 to SAMPLE#21 was measured, and the results were expressed relative to the intensity of light emitted from light-emitting element sample SAMPLE#19, as shown in Table 4 below.

[0208] Table 4

[0209]

[0210]

[0211] The light-emitting element samples SAMPLE#1 to SAMPLE#21 prepared according to Production Example 1 and Production Example 2 can generate blue light with a center wavelength of approximately 445 nm. The light-emitting element samples SAMPLE#1 to SAMPLE#21 prepared according to Production Example 1 and Production Example 2 are all light-emitting elements 30 comprising a first semiconductor layer 31, a nitrogen (N)-containing light-emitting layer 36, and a second semiconductor layer 32. The 445 nm light measured in Experimental Example 1 and Experimental Example 2 can be light within the target wavelength range, and the 560 nm light measured in Experimental Example 1 and Experimental Example 2 can be light within a non-target wavelength range generated by utilizing Ga vacancies formed in the semiconductor layer of each of the light-emitting element samples SAMPLE#1 to SAMPLE#21.

[0212] Assuming the intensity of the 445nm and 560nm light emitted by the light-emitting element sample SAMPLE#9 or SAMPLE#19 is 1, Tables 3 and 4 show the intensity of the 445nm and 560nm light emitted by each of the light-emitting element samples SAMPLE#1 to #21, relative to the intensity of the 445nm and 560nm light emitted by the light-emitting element sample SAMPLE#9 or SAMPLE#19.

[0213] Referring to Table 3, the light-emitting element samples SAMPLE#1 to SAMPLE#8, which include a shell 39 formed of inorganic compounds, have a 445nm light intensity of approximately 25, meaning that the light-emitting element samples SAMPLE#1 to SAMPLE#8 produce 445nm light with a intensity stronger than that of light-emitting element sample SAMPLE#9. Conversely, the light-emitting element samples SAMPLE#1 to SAMPLE#8 have a 560nm light intensity of approximately 0.5, meaning that the light-emitting element samples SAMPLE#1 to SAMPLE#8 produce 560nm light with a intensity weaker than that of light-emitting element sample SAMPLE#9. The light-emitting element sample SAMPLE#10, which only includes an insulating film 38, has a 445nm light intensity of 25 and a 560nm light intensity of 1, while the light-emitting element sample SAMPLE#11, which only includes a shell 39, has a 445nm light intensity of 1 and a 560nm light intensity of 0.45. For example, the light-emitting element sample including the shell 39 formed of inorganic compounds has a strong target light intensity, such as a strong 445 nm light intensity and a weak 560 nm light intensity, which indicates that the shell 39 formed of inorganic compounds can suppress the generation of undesirable 560 nm light by compensating for defects formed in the semiconductor layer.

[0214] Referring to Table 4, the light-emitting element samples SAMPLE#12 to SAMPLE#18, which include a shell layer 39 formed as a doped region, have a 445nm light intensity of approximately 25, meaning that the light-emitting element samples SAMPLE#12 to SAMPLE#18 produce 445nm light with a intensity stronger than that of the light-emitting element sample SAMPLE#19. Conversely, the light-emitting element samples SAMPLE#12 to SAMPLE#18 have a 560nm light intensity of approximately 0.5, meaning that the light-emitting element samples SAMPLE#12 to SAMPLE#18 produce 560nm light with a intensity weaker than that of the light-emitting element sample SAMPLE#19. The light-emitting element sample SAMPLE#20, which only includes an insulating film 38, has a 445nm light intensity of approximately 27 and a 560nm light intensity of approximately 1, while the light-emitting element sample SAMPLE#21, which only includes a shell layer 39, has a 445nm light intensity of approximately 0.9 and a 560nm light intensity of approximately 0.35. For example, the light-emitting element sample including the shell 39 formed as a doped region has a strong target light intensity, such as a strong 445 nm light intensity and a weak 560 nm light intensity, which indicates that the shell 39 formed as a doped region can suppress the generation of undesirable 560 nm light by compensating for defects formed in the semiconductor layer.

[0215] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the disclosed embodiments without substantially departing from the principles disclosed. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A light-emitting element, the light-emitting element comprising: A first semiconductor layer, wherein the first semiconductor layer is doped to have a first polarity; A second semiconductor layer, wherein the second semiconductor layer is doped to have a second polarity different from the first polarity; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; A shell layer is formed on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer. The shell layer includes a divalent metal element, or the shell layer is formed as a region in the first semiconductor layer, the light-emitting layer, and the second semiconductor layer doped with the divalent metal element. as well as An insulating film covers the outer surface of the shell and surrounds the side surface of the light-emitting layer. The shell layer includes at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe.

2. The light-emitting element according to claim 1, further comprising: An electrode layer is disposed on the second semiconductor layer. The insulating film surrounds at least a portion of the outer surface of the electrode layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

3. The light-emitting element according to claim 2, wherein, The shell layer is directly disposed on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer, so as to form a physical interface with at least the first semiconductor layer.

4. The light-emitting element according to claim 3, wherein, The shell has a thickness of 0.5 nm to 10 nm.

5. The light-emitting element according to claim 2, wherein, The shell is formed as a region in which the divalent metal element is doped in the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

6. The light-emitting element according to claim 5, wherein, The divalent metal element is one of Be, Mg, Ca, Sr, Ba, Zn, and Cd.

7. The light-emitting element according to claim 5, wherein, The shell layer is doped with 10 10 / cm 3 Up to 10 18 / cm 3 The amount of the divalent metal element within the specified range.

8. The light-emitting element according to claim 7, wherein, The shell has a thickness ranging from 0.1 Å to 50 Å.

9. The light-emitting element according to claim 2, wherein, The insulating film is formed as a single layer or multiple layers comprising one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, zirconium oxide and hafnium oxide, and has a thickness in the range of 10 nm to 200 nm.

10. The light-emitting element according to claim 9, wherein, The insulating film comprises: a first layer, directly disposed on the shell layer; and a second layer, directly disposed on the first layer. The first layer comprises silicon oxide, and The second layer comprises aluminum oxide.

11. The light-emitting element according to claim 2, further comprising: A third semiconductor layer is disposed between the first semiconductor layer and the light-emitting layer. A fourth semiconductor layer is disposed between the second semiconductor layer and the light-emitting layer, and A fifth semiconductor layer is disposed between the second semiconductor layer and the fourth semiconductor layer. The shell layer is formed on the side surfaces of the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer.

12. A method for manufacturing a light-emitting element, the method comprising the following steps: Multiple component rods, spaced apart from each other, are formed on the target substrate; A shell layer comprising a divalent metal element is formed on a portion of the outer surface of the plurality of element rods, and an insulating film is formed on the shell layer; as well as Separate the plurality of element rods on which the insulating film is formed from the target substrate. The shell layer includes at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe.

13. The method according to claim 12, wherein, The formation of the plurality of component bars includes the following steps: A semiconductor structure is formed by forming multiple semiconductor layers on the target substrate; and The semiconductor structure is etched in a direction perpendicular to the top surface of the target substrate.

14. The method according to claim 13, wherein, The formation of the shell and the insulating film includes the following steps: A shell material layer is formed around the plurality of element rods by immersing the target substrate on which the plurality of element rods are formed into a solution in which a precursor material for forming the shell layer is mixed. An insulating layer is formed on the shell material layer; and The shell layer and the insulating film are formed by partially removing the shell material layer and the insulating layer to expose the top surface of the plurality of element rods.

15. The method according to claim 14, wherein, The formation of the plurality of element bars includes forming the plurality of element bars, each of the plurality of element bars comprising: a first semiconductor layer, the first semiconductor layer being doped to have a first polarity; a second semiconductor layer, the second semiconductor layer being doped to have a second polarity different from the first polarity; and a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer, and The formation of the shell layer includes forming a shell layer on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

16. A display device, the display device comprising: First base; The first electrode is disposed on the first substrate; The second electrode is separated from the first electrode; A first insulating layer is disposed on the first substrate and overlapped with portions of the first electrode and the second electrode. as well as A plurality of light-emitting elements are disposed on the first insulating layer, each of the plurality of light-emitting elements including a first end disposed on the first electrode and a second end disposed on the second electrode. Each of the plurality of light-emitting elements comprises: a first semiconductor layer, the first semiconductor layer being doped to have a first polarity; a second semiconductor layer, the second semiconductor layer being doped to have a second polarity different from the first polarity; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; a shell layer formed on the side surfaces of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer, the shell layer comprising a divalent metal element, or the shell layer being formed as a region in which the divalent metal element is doped in the first semiconductor layer, the light-emitting layer, and the second semiconductor layer; and an insulating film configured to cover the outer surface of the shell layer and at least surround the side surface of the light-emitting layer, and The shell layer includes at least one of ZnS, ZnSe, MgS, MgSe, ZnMgS, and ZnMgSe.

17. The display device according to claim 16, further comprising: A first contact electrode is electrically connected to the first end of the first electrode and each of the plurality of light-emitting elements; as well as The second contact electrode makes electrical contact with the second electrode and the second end of each of the plurality of light-emitting elements.

18. The display device according to claim 17, wherein, The shell layer is directly disposed on the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer, so as to form a physical interface with at least the first semiconductor layer.

19. The display device according to claim 17, wherein, The shell is formed as a region in which the divalent metal element is doped in the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

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