Semiconductor device and method of forming the same

Abstract

The semiconductor device includes: a bottom electrode; a magnetic tunnel junction (MTJ) element located above the bottom electrode; a top electrode located above the MTJ element; and sidewall spacers adjacent to the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacers includes a magnetic material. Embodiments of the present invention also relate to a method of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each having smaller and more complex circuits than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling down process generally provides benefits by increasing production efficiency and decreasing related costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] One advancement in some IC designs and manufacturing is the development of non-volatile memory (NVM), especially magnetic random access memory (MRAM). In some embodiments, MRAM can provide performance comparable to volatile static random access memory (SRAM), and has density comparable to volatile dynamic random access memory (DRAM) and lower power consumption. Compared to NVM flash memory, MRAM can provide faster access speeds and undergoes less degradation over time. An MRAM cell is formed by a magnetic tunnel junction (MTJ) including two ferromagnetic layers separated by a thin insulating barrier and operates by electron tunneling through the insulating barrier between the two ferromagnetic layers. While existing methods in forming MRAM devices have generally been sufficient for their intended purposes, they are not entirely satisfactory in all respects. For example, it is desirable to provide improved shielding against magnetic interference for MRAM devices. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, comprising: a bottom electrode; a magnetic tunnel junction (MTJ) element located above the bottom electrode; a top electrode located above the MTJ element; and sidewall spacers adjacent to the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacers comprises a magnetic material.

[0005] Another embodiment of the present invention provides a semiconductor device, comprising: a bottom electrode; a magnetic tunnel junction (MTJ) element located above the bottom electrode; a top electrode located above the MTJ element; and sidewall spacers adjacent to the MTJ element, wherein the sidewall spacers comprise a magnetic material.

[0006] Another embodiment of the present invention provides a method of forming a semiconductor device, comprising: forming a first viaduct in a first dielectric layer; forming a first barrier layer in the first viaduct; forming a first conductive layer above the first barrier layer and in the first viaduct; depositing a magnetic tunnel junction (MTJ) stack above the first conductive layer, the first barrier layer, and the first dielectric layer, wherein the magnetic tunnel junction stack is electrically connected to the first conductive layer; patterning the magnetic tunnel junction stack to produce a patterned magnetic tunnel junction stack; depositing a nitride spacer above sidewalls of the patterned magnetic tunnel junction stack; depositing a protection spacer above the nitride spacer; depositing an oxide spacer above the protection spacer; depositing a second dielectric layer above the oxide spacer and the patterned magnetic tunnel junction stack; forming a second viaduct in the second dielectric layer; forming a second barrier layer in the second viaduct; and forming a second conductive layer above the second barrier layer and in the second viaduct, wherein the second conductive layer is electrically connected to the patterned magnetic tunnel junction stack, wherein at least one of the first barrier layer, the first conductive layer, the protection spacer, the second barrier layer, and the second conductive layer comprises a magnetic material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1B shows a perspective view of a semiconductor device in which an MRAM is integrated. Figure 1C shows, according to an embodiment, Figure 1A and Figure 1B a cross-sectional view of the semiconductor device in

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H show cross-sectional views of portions of the semiconductor device in Figures 1A to 1C according to various embodiments.

[0010] Figure 3A and Figure 3B shows a flowchart of a method for forming a semiconductor device in which an MRAM array is integrated according to an embodiment of the present invention.

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4K-1 , Figure 4L , Figure 4L-1 , Figure 4M , Figure 4M-1 , Figure 4N and Figure 4N-1 illustrate cross-sectional views of semiconductor structures during a manufacturing process of a method in accordance with Figures 3A to 3B in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Further, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Still further, when a numerical value or numerical range is described with "about", "approximate", etc., unless otherwise stated, in light of the knowledge of those skilled in the art and the specific technology disclosed herein, the term covers values within certain variations (such as + / −10% or other variations) of the described numerical value. For example, the term "about 5 nm" may cover a size range from 4.5 nm to 5.5 nm, from 4.0 nm to 5.0 nm, etc.

[0014] The present invention generally relates to semiconductor devices and manufacturing methods. More specifically, the present invention relates to a semiconductor device providing an array of MRAM devices (or cells), where each MRAM device includes a magnetic shield for improving the anti-magnetic interference performance of the MRAM device. The magnetic shield can be provided as a magnetic material in a bottom electrode, a magnetic material in a sidewall spacer, and / or a magnetic material in a top electrode.

[0015] In some embodiments, MRAM devices are provided in a memory device region (or MRAM region) of the semiconductor device, and logic devices are provided in a logic device region (or logic region) of the semiconductor device. The memory device region can include an array of MRAM devices arranged in rows and columns. MRAM devices in the same row are connected to a common word line, and MRAM devices in the same column are connected to a common bit line. The array can be connected to and controlled by the logic devices in the logic region.

[0016] The MRAM devices of the present invention can be formed above a semiconductor structure including a semiconductor substrate. Certain devices, such as field effect transistors (FETs) having associated gate components, source components, and drain components, can be formed on the semiconductor substrate. One or more layers of a multi-layer interconnect (or MLI) including horizontally extending wires (e.g., metallization layers) and vertically extending conductive vias can also be provided on the semiconductor structure. The MLI can interconnect one or more devices (e.g., FETs) formed on the substrate. In an embodiment, at least one metallization layer of the MLI is formed on the semiconductor structure, while other metallization layers of the MLI can be formed after (e.g., above) the fabricated MRAM devices as discussed below. In other words, the MRAM devices are disposed within the metallization layers of the MLI.

[0017] Figure 1A and Figure 1B A perspective view of a semiconductor device 200 having an MRAM array 250 is shown. In particular, Figure 1A a building block of the MRAM array 250 - an MRAM cell 249 having an MTJ 150 (or MTJ stack 150) is shown. The MTJ 150 includes an upper ferromagnetic plate 152 and a lower ferromagnetic plate 154, which are separated by a thin insulating layer 156 (also referred to as a tunnel barrier layer). One of the two ferromagnetic plates (e.g., the lower ferromagnetic plate 154) is a magnetic layer pinned to an antiferromagnetic layer, while the other ferromagnetic plate (e.g., the upper ferromagnetic plate 152) is a "free" magnetic layer, and the magnetic field of the "free" magnetic layer can be changed to one of two or more values to store one of two or more corresponding data states.

[0018] The MTJ 150 uses tunneling magnetoresistance (TMR) to store a magnetic field on the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154. For an insulating layer 156 that is thin enough (e.g., a thickness of about 10 nm or less), electrons can tunnel from the upper ferromagnetic plate 152 to the lower ferromagnetic plate 154. Data can be written to the cell in a variety of ways. In one method, a current is transmitted between the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154, which induces a magnetic field stored in the free magnetic layer (e.g., the upper ferromagnetic plate 152). In another method, spin transfer torque (STT) is utilized, where a spin-aligned or polarized electron current is used to change the magnetic field within the free magnetic layer relative to the pinned magnetic layer. Other methods of writing data can be used. However, all data writing methods involve changing the magnetic field within the free magnetic layer relative to the pinned magnetic layer.

[0019] Due to the magneto-tunneling effect, the resistance of the MTJ 150 varies according to the magnetic fields stored on the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154. For example, when the magnetic fields of the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154 are aligned (or in the same direction), the MTJ 150 is in a low-resistance state (i.e., the logic "0" state). When the magnetic fields of the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154 are in opposite directions, the MTJ 150 is in a high-resistance state (i.e., the logic "1" state). The magnetic field direction of the upper ferromagnetic plate 152 can be changed by passing a current through the MTJ 150. By measuring the resistance between the upper ferromagnetic plate 152 and the lower ferromagnetic plate 154, a read circuit coupled to the MTJ 150 can identify the "0" and "1" states. Figure 1A It is also shown that the upper ferromagnetic plate 152 of the MTJ 150 is coupled to a bit line, the lower ferromagnetic plate 154 of the MTJ 150 is coupled to the source (or drain) of a transistor in the transistor structure 101, the drain (or source) of the transistor is coupled to a power supply line (SL), and the gate of the transistor is coupled to a word line (WL). The MTJ 150 can be accessed (such as read or written) through the bit line, word line, and power supply line. Since the MTJ 150 uses magnetization to store binary digital information, there is a risk that its data may be adversely disturbed by a large external magnetic field. The object of the present invention is to provide a structure that can prevent the MTJ 150 from being affected by an external magnetic field.

[0020] Figure 1B An MRAM array 250 is shown, and the MRAM array 250 includes M rows (words) and N columns (bits) of MRAM cells (or MRAM devices) 249. Each MRAM cell 249 includes an MTJ 150. Word lines WL1, WL2…WL M extend across the corresponding rows of the MRAM cells 249, and bit lines BL1, BL2...BL N extend along the columns of the MRAM cells 249.

[0021] Figure 1C A cross-sectional view of a semiconductor device 200 along the bit line direction of the MRAM array 250 (i.e., line B-B in Figure 1B ) according to some embodiments of the present invention is shown, with the MRAM array 250 and the logic device 252 shown in the same figure. Referring to Figure 1C , the MRAM array 250 is provided in the MRAM region 100A, while the logic device 252 is provided in the logic region 100B. The logic device 252 can be used to implement write / read logic for accessing the MRAM array 250 or performing other functions. The MRAM region 100A and the logic region 100B have a common transistor structure 101 in or on the semiconductor substrate 100.

[0022] In some embodiments, the semiconductor substrate 100 can be, but is not limited to, a silicon substrate (such as a silicon wafer). Optionally, the substrate 100 includes another elemental semiconductor, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, the semiconductor substrate 100 is a semiconductor-on-insulator (SOI). In other alternatives, the semiconductor substrate 100 can include a doped epitaxial layer, a graded semiconductor layer, and / or a semiconductor layer located on top of another semiconductor layer of a different type, such as a silicon layer on a silicon-germanium layer. The semiconductor substrate 100 may or may not include doped regions such as p-wells, n-wells, or combinations thereof.

[0023] The semiconductor substrate 100 further includes heavily doped regions, such as source 103 and drain 105, at least partially located in the semiconductor substrate 100. A gate 107 is located above the top surface of the semiconductor substrate 100 and between the source 103 and the drain 105. A contact plug 108 is formed in the interlayer dielectric (ILD) 109 and can be electrically coupled to the transistor structure 101. In some embodiments, the ILD 109 is formed on the semiconductor substrate 100. The ILD 109 can be formed by various techniques for forming such a layer, for example, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), thermal growth, etc. The ILD 109 can be formed of various dielectric materials, such as oxides, oxynitrides, silicon dioxide (SiO2), oxynitrides containing nitrogen (e.g., nitrogen-containing SiO2), nitrogen-doped oxides (e.g., N2-implanted SiO2), silicon oxynitride (Si x O y N z) etc. The transistors in the transistor structure 101 can be planar transistors or non-planar transistors, such as FinFETs or gate-all-around (GAA) transistors.

[0024] In some embodiments, shallow trench isolation (STI) 111 is provided to define and electrically isolate adjacent transistors. A plurality of STIs 111 are formed in the semiconductor substrate 100. The STI 111 can include, for example, oxides, oxynitrides, silicon dioxide (SiO2), oxynitrides containing nitrogen (e.g., nitrogen-containing SiO2), nitrogen-doped oxides (e.g., N2-implanted SiO2), silicon oxynitride (Si x O y N z ) etc. The STI 111 can also be formed of any suitable "high dielectric constant" or "high-k" material, where k is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g., TiO2), tantalum oxide (Ta x O y , e.g., Ta2O5), etc. Optionally, the STI 111 can also be formed of any suitable "low dielectric constant" or "low-k" dielectric material, where k is less than or equal to about 4.

[0025] Figure 1C Also shown is that the semiconductor device 200 includes a multi-layer interconnect (MLI) structure 308 located above the transistor structure 101. The interconnect structure 308 includes three adjacent metal layers 302, 304, and 306 and other metal layers not shown. For example, in some embodiments, there is a metal layer above the metal layer 306. For example, in some embodiments, there is one or more metal layers below the metal layer 302. The metal layer 302 is the Nth metal layer located above the top surface of the transistor structure 101, while the metal layers 304 and 306 are the (N + 1)th metal layer and the (N + 2)th metal layer, respectively. Thus, in some embodiments, the metal layers 302, 304, and 306 are also referred to as metal layers M N , M N+1 and M N+2 . The number N can be any natural number. For example, N can be 3, 4, 5, 6, or other natural numbers. In this embodiment, the MRAM cell 249 is implemented in the metal layer 304.

[0026] The metal layer 302 includes an inter-metal dielectric (IMD) layer 206 and metal lines 208 located in both the MRAM region 100A and the logic region 100B. The IMD layer 206 can be an oxide (such as silicon dioxide), a low-k dielectric material (such as carbon-doped oxide), or an extremely low-k dielectric material (such as porous carbon-doped silicon dioxide). The metal lines 208 can be made of a metal such as aluminum, copper, or a combination thereof.

[0027] The metal layer 304 includes a barrier layer 210 that extends through the MRAM region 100A and the logic region 100B. For example, in various embodiments, the barrier layer 210 may include one or more dielectric materials such as Si3N4, SiON, SiC, SiCN, or combinations thereof. In the MRAM region 100A, the metal layer 304 further includes an MRAM cell 249 surrounded by one or more dielectric layers 210, 212, 214, and 216. In the logic region 100B, the metal layer 304 further includes a metal via 213 and a metal line 217 surrounded by one or more dielectric layers 210 and 215. The various components in the metal layer 304 are further described below.

[0028] In an embodiment, the dielectric layer 212 includes a metal-based dielectric material such as aluminum oxide (i.e., AlO x , such as Al2O3). In an embodiment, the dielectric layer 214 includes a low-k dielectric material such as a silicon oxide-based low-k dielectric material. For example, the dielectric layer 214 may include undoped silicate glass (USG) or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. In an embodiment, the dielectric layer 216 includes one or more oxide-based dielectric materials such as silicon dioxide, oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials.

[0029] In the present embodiment, each MRAM cell 249 includes a bottom electrode (BE) 221. The BE 221 includes a bottom electrode via (BEVA) 220 and a conduction barrier layer 218 located on the sidewalls and bottom surface of the BEVA 220. In an alternative embodiment, the BE 221 may include other layers. The conduction barrier layer 218 may be directly disposed on one of the metal lines 208 in the metal layer 302, and the metal line 208 is connected to a via on one of the source and drain components of the transistor in the transistor structure 101 (such a connection is not shown in Figure 1C but see Figure 1A)。The BEVA 220 may include a magnetic material (such as a ferromagnetic material or other types of magnetic materials) or a non-magnetic material (such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, combinations thereof, or other suitable metals or metal compounds). Examples of ferromagnetic materials include iron, nickel, cobalt, or their compounds. The barrier layer 218 may include a magnetic material (such as iron, nickel, cobalt, or their compounds) or a non-magnetic material (such as titanium nitride, tantalum nitride, and / or other suitable conductive diffusion barriers). The barrier layer 218 is disposed between the BEVA 220 and the surrounding dielectric layers 210, 221, and 214. Having a magnetic material in either the barrier layer 218, the BEVA 220, or both the barrier layer 218 and the BEVA 220 effectively shields the MTJ150 against a perpendicular external magnetic field (i.e., a magnetic field that is up and down along the "z" direction).

[0030] In this embodiment, each MRAM cell 249 further includes a bottom conductive hard mask (HM) 222 disposed on the BE 221, a MTJ (or MTJ stack) 150 disposed on the HM 222, and a top conductive HM 228 disposed on the MTJ 150. In an embodiment, each of the HM 222 and the HM 228 may include a metal nitride, such as TaN, TiN, Ti / TiN, TaN / TiN, Ta, or combinations thereof. In some embodiments, the MTJ 150 may include a ferromagnetic layer, a MTJ spacer, and a capping layer. The capping layer is formed on the ferromagnetic layer. Each ferromagnetic layer may include a ferromagnetic material, which may be a metal or a metal alloy, for example, Fe, Co, Ni, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, etc. The MTJ spacer may include a non-ferromagnetic metal, for example, Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, etc. Another MTJ spacer may also include an insulator, such as Al2O3, MgO, TaO, RuO, etc. The capping layer may include a non-ferromagnetic material, which may be a metal or an insulator, for example, Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, Ir, Re, Os, Al2O3, MgO, TaO, RuO, etc. The capping layer may reduce the write current of its associated MRAM cell. The ferromagnetic layer may be used as the free layer 152 ( Figure 1A ), during the write operation of its associated MRAM cell 249, the magnetic polarity or magnetic orientation of the free layer 152 may be changed. The ferromagnetic layer and the MTJ spacer may be used as the fixed layer or pinned layer 154 ( Figure 1A), whose magnetic orientation does not change during the operation of its associated MRAM cell 249. It is contemplated that, according to other embodiments, the MTJ 150 may include an antiferromagnetic layer.

[0031] In this embodiment, each MRAM cell 249 further includes dielectric spacers 224 located on the sidewalls of the MTJ 150 and the HM 222. The spacer 224 may include one or more dielectric materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (Si x O y N z ), etc. In this embodiment, a protective spacer 226 is disposed above the dielectric spacer 224 and above the sidewalls of the HM 228. In an embodiment, when viewed from a top view, the dielectric spacer 224, the protective spacer 226, and the dielectric layer 216 surround the MTJ 150 360 degrees. In an embodiment, the dielectric spacer 224, the protective spacer 226, and the dielectric layer 216 are collectively referred to as the sidewall spacers of the MRAM cell 249. In some embodiments, the protective spacer 226 includes a magnetic material such as cobalt or NiFe. The presence of a magnetic material in the protective spacer 226 effectively shields the MTJ 150 from the influence of a horizontal external magnetic field (such as a magnetic field in the "xy" plane). In some embodiments, the protective spacer 226 includes a non-magnetic material such as aluminum oxide (Al2O3).

[0032] In this embodiment, the metal layer 304 in the logic region 100B includes metal vias 213, metal lines 217, and dielectric layers 210 and 215. The metal vias 213 are electrically connected to some of the metal lines 208 in the metal layer 302. The dielectric layer 215 may be an oxide such as silicon dioxide; a low-k dielectric material such as carbon-doped oxide; or an extremely low-k dielectric material such as porous carbon-doped silicon dioxide. The metal vias 213 and the metal lines 217 may be made of a metal such as aluminum, copper, or a combination thereof.

[0033] The metal layer 306 includes conductive components (or conductive layers) 260 and 262 surrounded by one or more dielectric layers 230, 232, and 234. The dielectric layers 230, 232, and 234 extend across the MRAM region 100A and the logic region 100B. The conductive components 260 and 262 in the MRAM region 100A are disposed on one or more MTJs 150 and are electrically connected to one or more MTJs 150. The conductive components 260 and 262 in the logic region 100B are disposed on one or more metal lines 217 and are electrically connected to one or more metal lines 217. The various components in the metal layer 306 are further described below.

[0034] In an embodiment, the dielectric layer 230 includes the same or similar materials as those in the dielectric layer 210. For example, the dielectric layer 230 may include one or more dielectric materials such as Si3N4, SiON, SiC, SiCN, or a combination thereof. In an embodiment, the dielectric layer 232 includes the same or similar materials as those in the dielectric layer 212. For example, the dielectric layer 232 may include metal-based dielectric materials such as aluminum oxide (i.e., AlO x , such as Al2O3) or other metal oxides. In an embodiment, the dielectric layer 234 includes a low-k dielectric material such as a silicon oxide-based low-k dielectric material. For example, the dielectric layer 234 may include undoped silicate glass (USG) or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials.

[0035] In the present embodiment, the conductive component 260 is a metal via and / or a metal line, and the conductive component 262 is a barrier layer located on the sidewalls and bottom surface of the conductive component 260. In an embodiment, the conductive component 260 includes a magnetic material (such as iron, nickel, cobalt, or a compound thereof) or a non-magnetic material (such as aluminum, copper, or a combination thereof). In an embodiment, the conductive component 262 includes a magnetic material (such as iron, nickel, cobalt, or a compound thereof) or a non-magnetic material (such as titanium nitride, tantalum nitride, and / or other suitable conductive diffusion barriers). Having a magnetic material in either the conductive component 260, the conductive component 262, or both the conductive components 260 and 262 effectively shields the MTJ 150 from the influence of a perpendicular external magnetic field (i.e., an upward and downward magnetic field along the "z" direction).

[0036] In the present embodiment, the conductive components 260 / 262 in the MRAM region 100A are part of the bit lines for the MRAM array 250. Each conductive component 260 may be disposed above the columns of the MRAM cells 249 sharing the same bit line (see Figure 1B ). In some embodiments, each conductive component 260 is disposed above one MRAM cell 249 or a plurality of consecutive MRAM cells 249 (which may be a subset of the columns of the MRAM cells 249) sharing the same bit line. In some embodiments, the conductive components 260 / 262 are directly disposed on the conductive HM 228 of each MRAM cell 249 in the column and are electrically connected to the conductive M 228. In some embodiments, the conductive components 260 / 262 are directly disposed on the MTJ 150 of each MRAM cell 249 in the column and are electrically connected to the MTJ 150, such as Figure 2E , Figure 2F , Figure 2G and Figure 2HAs shown. In some embodiments, the conductive members 260 / 262 are also referred to as the top electrode (TE) 263 of the MRAM cell 249.

[0037] As discussed above, one or more of the layers / components 218, 220, 226, 260, and 262 may include a magnetic material such as cobalt, iron, nickel, or a compound thereof such as NiFe. This shields the MTJ 150 from external magnetic interference, such as from a wireless charger on a mobile phone carrying the semiconductor device 200. In some embodiments, the semiconductor device 200 incorporates a magnetic material in at least one of the layers / components 218, 220, 226, 260, and 262. In some embodiments, the semiconductor device 200 incorporates a magnetic material in at least two of the layers / components 218, 220, 226, 260, and 262. For example, the semiconductor device 200 may include a magnetic material in one of the layers 218 and 220 and another magnetic material in the layer 226. This shields the MTJ 150 from both vertical and horizontal external magnetic fields. Similarly, the semiconductor device 200 may include a magnetic material in one of the layers 260 and 262 and another magnetic material in the layer 226. In some embodiments, the semiconductor device 200 incorporates a magnetic material in at least three of the layers / components 218, 220, 226, 260, and 262. For example, the semiconductor device 200 may include a magnetic material in one of the layers 260 and 262, another magnetic material in the layer 226, and yet another magnetic material in one of the layers 218 and 220. This shields the MTJ 150 from both vertical and horizontal external magnetic fields. In various embodiments, the magnetic materials in the layers / components 218, 220, 226, 260, and 262 may be the same or may be different.

[0038] Figures 2A to 2H Further non-limiting examples of the device 200 are shown, where magnetic materials are included in one or more of the layers / components 218, 220, 226, 260, and 262. Refer to Figure 2A, in this embodiment, the barrier layer 218 includes a sub-layer 218b above the sub-layer 218a. In an embodiment, the sub-layer 218a includes TaN, and the sub-layer 218b includes TiN. The protective spacer 226 includes a magnetic material such as Co, NiFe, or a combination thereof. The protective spacer 226 is sandwiched between the dielectric spacers 224 and 216. In an example, the dielectric spacer 224 includes a nitride such as silicon nitride (Si3N4), and the dielectric spacer (or layer) 216 includes an oxide such as silicon dioxide. Additionally, the barrier layer 262 includes a sub-layer 262b above the sub-layer 262a. In an embodiment, the sub-layer 262a includes Ta, and the sub-layer 262b includes TaN. In an embodiment, the BEVA 220 includes tungsten, and the conductive component 260 includes copper.

[0039] Reference Figure 2B , in this embodiment, the barrier layer 218 includes a sub-layer 218b above the sub-layer 218c, and the sub-layer 218c is above the sub-layer 218a. In an embodiment, the sub-layer 218a includes TaN, the sub-layer 218b includes TiN, and the sub-layer 218c includes a magnetic material such as Co. In an embodiment, the BEVA 220 includes a magnetic material such as Co. In an alternative embodiment, the BEVA 220 includes a non-magnetic material such as tungsten. In an embodiment, the protective spacer 226 includes a magnetic material such as Co, NiFe, or a combination thereof. In an alternative embodiment, the protective spacer 226 includes a non-magnetic material such as Al2O3. Figure 2B Other aspects of the embodiment in Figure 2A are the same as those of the embodiment in

[0040] Reference Figure 2C , in this embodiment, the barrier layer 262 includes a sub-layer 262b above the sub-layer 262c, and the sub-layer 262c is above the sub-layer 262a. In an embodiment, the sub-layer 262a includes Ta, the sub-layer 262b includes TaN, and the sub-layer 262c includes a magnetic material such as Co. In an embodiment, the conductive layer 260 includes a magnetic material such as Co. In an alternative embodiment, the conductive layer 260 includes a non-magnetic material such as copper. In an embodiment, the protective spacer 226 includes a magnetic material such as Co, NiFe, or a combination thereof. In an alternative embodiment, the protective spacer 226 includes a non-magnetic material such as Al2O3. Figure 2C Other aspects of the embodiment in Figure 2A are the same as those of the embodiment in

[0041] Reference Figure 2D, in this embodiment, the barrier layer 218 includes a sub-layer 218b above the sub-layer 218c, and the sub-layer 218c is above the sub-layer 218a. In addition, the barrier layer 262 includes a sub-layer 262b above the sub-layer 262c, and the sub-layer 262c is above the sub-layer 262a. In an embodiment, the sub-layer 218a includes TaN, the sub-layer 218b includes TiN, the sub-layer 218c includes a magnetic material such as Co, the sub-layer 262a includes Ta, the sub-layer 262b includes TaN, the sub-layer 262c includes a magnetic material such as Co, and the protective spacer 226 includes a magnetic material such as Co, NiFe, or a combination thereof. Thus, the MTJ 150 is surrounded by magnetic materials (on the sidewalls as well as the top and bottom surfaces of the MTJ 150). In another embodiment, each of the BEVA 220 and the conductive layer 260 also includes a magnetic material such as Co.

[0042] Figure 2E , Figure 2F , Figure 2G and Figure 2H The embodiments shown in Figure 2A , Figure 2B , Figure 2C and Figure 2D are substantially the same as the embodiments shown in Figure 2E , Figure 2F , Figure 2G and Figure 2H , except that the top HM 228 is removed in the embodiments shown in Figure 2E , Figure 2F , Figure 2G and Figure 2H , and the conductive layer 260 / 262 extends into the space previously occupied by the top HM 228. In the embodiments shown in

[0043] Figure 3A and Figure 3B , the barrier layer 262 is in direct contact with the MTJ 150.

[0043] Figure 3A and Figure 3B show a flowchart of a method 500 for forming a semiconductor device 200 having an integrated MRAM array and logic device according to an embodiment. The method 500 is merely an example and is not intended to limit the present disclosure to what is explicitly recited in the claims. Additional operations may be provided before, during, and after the method 500, and for additional embodiments of the method, some of the described operations may be replaced, eliminated, or repositioned. The method 500 is described below in conjunction with Figures 4A to 4N-1 , Figures 4A to 4N-1 showing various cross-sectional views of the semiconductor device 200 during the manufacturing steps according to the method 500.

[0044] At operation 502, the method 500 ( Figure 3A) provides or provides with a device structure 200, the device structure 200 having a metal layer 302 and respective dielectric layers 210, 212, and 214 disposed above the metal layer 302, such as Figure 4A as shown. Although not shown in Figure 4A , the device structure 200 further includes a transistor structure (such as Figure 1C the transistor structure 101 in Figure 1C ) disposed in or on a substrate (such as Figure 4A , the metal layer 302 is the Nth metal layer above the transistor structure, where N is a natural number. The device structure 200 includes an MRAM region 100A for forming an MRAM array therein and a logic region 100B for forming logic devices therein. The metal layer 302 includes an IMD layer 206 and metal lines 208 located in the MRAM region 100A and the logic region 100B. The IMD layer 206 can be an oxide (such as silicon dioxide), a low-k dielectric material (such as carbon-doped oxide), or an ultra-low-k dielectric material (such as porous carbon-doped silica). The metal lines 208 can be made of a metal such as aluminum, copper, or a combination thereof. The IMD layer 206 can be formed by a deposition process such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) including plasma-enhanced chemical vapor deposition (PECVD). The metal lines 208 are formed by a deposition process such as PVD, CVD, ALD, or plating process. In an embodiment, the dielectric layer 210 can include one or more dielectric materials, such as Si3N4, SiON, SiC, SiCN, or a combination thereof, and can be deposited to a thickness in the range of about 12 nm to about 20 nm using PVD, CVD, ALD, or other suitable processes. In an embodiment, the dielectric layer 212 includes a metal-based dielectric material, such as aluminum oxide, and can be deposited to a thickness in the range of about 2 nm to about 6 nm using CVD, ALD, or other suitable processes. In an embodiment, the dielectric layer 214 includes a silicon oxide-based dielectric material, such as undoped silicate glass (USG), and can be deposited to a thickness in the range of about 40 nm to about 100 nm using CVD, PVD, or other suitable processes. Still referring to

[0045] At operation 504, method 500 ( Figure 3A)The BEVA 220 and the barrier layer 218 are formed in the via 219, and the BEVA 220 and the barrier layer 218 are electrically connected to some of the metal lines 208 in the MRAM region 100A, such as Figure 4B as shown. For example, operation 504 deposits the barrier layer 218 on the surface of the via 219 and deposits the BEVA 220 over the barrier layer 218. Thereafter, operation 504 may perform a chemical mechanical planarization (CMP) process on the BEVA 220 and the barrier layer 218 to remove any excess material located on the top surface of the dielectric layer 214. The barrier layer 218 may include a magnetic material such as Co or a non-magnetic material such as titanium nitride, tantalum nitride, or other suitable conductive diffusion barrier, and may be deposited using ALD, PVD, CVD, or other suitable deposition methods. The BEVA 220 may include a magnetic material such as Co or a non-magnetic material such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, a combination thereof, or other suitable metals or metal compounds, and may be deposited using CVD, PVD, ALD, plating, or other suitable deposition methods.

[0046] At operation 506, method 500 ( Figure 3A ) deposits a bottom conductive HM layer 222, the MTJ stack 150, and a top conductive HM layer 228 over the dielectric layer 214, the barrier layer 218, and the BEVA 220, such as Figure 4C as shown. In particular, the HM layer 222 is electrically connected to the BEVA 220. In an embodiment, the HM layer 222 may include a metal nitride such as TaN, TiN, Ti / TiN, TaN / TiN, Ta, or a combination thereof, and may be deposited using CVD, ALD, or other suitable deposition methods. In some embodiments, the HM layer 222 may be formed to have a thickness in the range of about 1 nm to about 8 nm. In some embodiments, the MTJ stack 150 may be deposited using CVD, PVD, ALD, or other suitable deposition methods and may have a thickness in the range of about 20 nm to about 50 nm. In an embodiment, the HM layer 228 may include a metal nitride such as TaN, TiN, Ti / TiN, TaN / TiN, Ta, or a combination thereof, and may be deposited using CVD, ALD, or other suitable deposition methods. In some embodiments, the HM layer 228 may be formed to have a thickness in the range of about 10 nm to about 25 nm.

[0047] At operation 508, method 500 ( Figure 3A)Pattern the HM layer 222, the MTJ stack 150, and the HM layer 228 into individual MRAM cells 249. For example, using a lithography and etching process, operation 508 can form an etch mask 402 that covers the regions of the HM layer 228 corresponding to the individual MRAM cells 249 and exposes the remainder of the HM layer 228, such as Figure 4D as shown. Then, operation 508 etches through the etch mask 402 the HM layer 228, the MTJ stack 150, the HM layer 222, and the dielectric layer 214 to form individual MRAM cells 249, such as Figure 4E as shown. The etching process can be wet etching, dry etching, reactive ion etching, or other suitable etching methods. Thereafter, the etch mask 402 is removed using etching, stripping, ashing, or other suitable methods.

[0048] At operation 510, method 500 ( Figure 3A ) forms dielectric spacers 224 over the sidewalls of the MRAM cells 249, such as Figure 4F as shown. In some embodiments, the spacers 224 are considered part of the MRAM cells 249. For example, operation 510 can deposit a blanket dielectric layer over the device structures 200 in the MRAM region 100A and the logic region 100B using CVD, ALD, or other suitable methods, and then anisotropically etch the blanket dielectric layer to remove the blanket dielectric layer from the top surfaces of the dielectric layer 214 and the HM 228. The portion of the dielectric layer remaining on the sidewalls of the MRAM cells 249 becomes the spacers 224. The spacers 224 can include one or more dielectric materials, such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (Si x O y N z ), etc. In various embodiments, the spacers 224 can include one or more layers of dielectric material.

[0049] At operation 512, method 500 ( Figure 3A ) forms a protective spacer (or protective layer) 226 over the dielectric spacers 224 and the dielectric layer 214, and forms a dielectric layer (or another dielectric spacer) 216 over the protective spacer 226 in the MRAM region 100A, such as Figure 4GAs shown. For example, operation 512 can deposit protective spacers 226 and dielectric layer 216 in MRAM region 100A and logic region 100B; form an etch mask using photolithography and etching processes, where the etch mask covers MRAM region 100A and exposes logic region 100B; etch protective spacers 226 and dielectric layers 216, 214, and 212 through the etch mask until dielectric layer 210 is exposed in logic region 100B; and remove the etch mask. CVD, ALD, or other suitable methods can be used to deposit protective spacers 226. CVD, PVD, or other suitable methods can be used to deposit dielectric layer 216. Wet etching, dry etching, reactive ion etching, or other suitable methods can be used to etch protective spacers 226 and dielectric layers 216, 214, and 212. In an embodiment, protective spacers 226 can include a magnetic material such as Co or NiFe or a non-magnetic material such as Al2O3.

[0050] After etching protective spacers 226 and dielectric layers 216, 214, and 212, operation 512 further forms dielectric layer 215 in logic region 100B, such as Figure 4H As shown. Dielectric layer 215 can be an oxide (such as silicon dioxide), a low-k dielectric material (such as carbon-doped oxide), or an ultra-low-k dielectric material (such as porous carbon-doped silicon dioxide). CVD, PVD, or other suitable methods can be used to deposit dielectric layer 215. Operation 512 also performs a CMP process to planarize the top surfaces of dielectric layers 215 and 216, protective spacers 226, and HM 228.

[0051] At operation 514, method 500 ( Figure 3A ) forms metal vias 213 and metal lines 217 in logic region 100B, such as Figure 4I As shown. Damascene process, dual damascene process, or other suitable methods can be used to form metal vias 213 and metal lines 217. For example, operation 514 can etch holes and / or trenches in dielectric layer 215 to expose the top surface of metal line 208, deposit one or more metals into the holes and / or trenches, and perform a CMP process on the one or more metals. The portions of the one or more metals remaining in the holes and / or trenches become metal vias 213 and metal lines 217. Metal vias 213 and metal lines 217 can include aluminum, copper, or other suitable low-resistance metals, and can be deposited using PVD, CVD, ALD, plating, or other suitable methods. After operation 514 is completed, the top surface of metal line 217 is substantially coplanar with the top surface of HM 228. Using operations 504 to 514, metal layer 304 is formed above metal layer 302.

[0052] At operation 516, method 500 ( Figure 3B)Deposit dielectric layers 230, 232, and 234 over the metal layer 304 in the MRAM region 100A and the logic region 100B, such as Figure 4J as shown. In an embodiment, the dielectric layer 230 may include one or more dielectric materials, such as nitrides (e.g., silicon nitride) or silicon carbide, and may be deposited using ALD, CVD, PVD, or other suitable methods. In some embodiments, the dielectric layer 230 may have a thickness in the range of about 10 nm to about 15 nm. In an embodiment, the dielectric layer 232 may include a metal-based dielectric material, such as aluminum oxide (i.e., AlO x , e.g., Al2O3), and may be deposited using ALD, CVD, PVD, or other suitable methods. In some embodiments, the thickness of the dielectric layer 232 may be in the range of about 4 nm to about 10 nm. In an embodiment, the dielectric layer 234 may include undoped silicate glass (USG) or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials, and may be deposited using CVD, PVD, or other suitable methods. In some embodiments, the dielectric layer 234 may have a thickness in the range of about 40 nm to about 100 nm.

[0053] At operation 518, method 500 ( Figure 3B ) forms an etch mask 404 over the dielectric layer 234, such as Figure 4J as shown. The etch mask 404 provides openings 406 over the MRAM region 100A and the logic region 100B. In an embodiment, the etch mask 404 includes a material that has etch selectivity with respect to the dielectric layers 234, 232, and 230 in an etching process. For example, in an embodiment, the etch mask 404 may include a photoresist pattern and may also include a patterned hard mask located under the photoresist pattern. For example, in an embodiment, the patterned hard mask may include titanium nitride and may have a thickness in the range of about 10 nm to about 40 nm. Operation 518 may include: depositing a hard mask layer over the dielectric layer 234; coating a photoresist over the hard mask layer; performing photolithography (such as exposure and development) on the photoresist layer to form a photoresist pattern; and etching the hard mask layer through the photoresist pattern to form a patterned hard mask. The patterned hard mask and the photoresist pattern together form the etch mask 404.

[0054] At operation 520, method 500 ( Figure 3B ) etches through the etch mask 404 the dielectric layers 234, 232, and 230 to expose the MRAM cells 249 in the MRAM region 100A and the metal lines 217 in the logic region 100B. Figure 4KAnd Figure 4K-1 shows the resulting structure 200 according to an embodiment. Figure 4K shows the structure 200 along Figure 1B the B-B line in (i.e., along the "x" direction), and Figure 4K-1 shows the structure 200 along Figure 1B the A-A line of (i.e., along the "y" direction perpendicular to the "x" direction). In an embodiment, operation 520 may perform multiple etching processes, which are designed to etch each of the dielectric layers 234, 232, and 230, respectively. For example, operation 520 may perform a first etching process that is designed to etch the first dielectric layer 234 with minimal or no etching of the etch mask 404; perform a second etching process that is designed to etch the dielectric layer 232 with minimal or no etching of the etch mask 404; and perform a third etching process that is designed to etch the dielectric layer 230 with minimal or no etching of the etch mask 404. The multiple etching processes may include wet etching, dry etching, or a combination of wet etching and dry etching. In some embodiments, the etching process in operation 520 may etch more than one dielectric layer.

[0055] In some alternative embodiments, HM 228 is also etched and the top surface of the MTJ 150 is exposed, such as Figure 4M and Figure 4M-1 shown, Figure 4M and Figure 4M-1 show the structure 200 along Figure 1B the B-B line and the A-A line in, respectively. As Figure 4K , Figure 4K-1 , Figure 4M and Figure 4M-1 shown, operation 520 extends the opening 406 into the dielectric layers 234 / 232 / 230 to expose the MRAM cell 249 and the metal line 217. Subsequently, the etch mask 404 may be removed.

[0056] At operation 522, method 500 ( Figure 3B ) forms conductive layers 262 and 260 in the opening 406. For example, operation 522 may deposit one or more barrier layers 262 into the opening 406 and deposit one or more metal materials 260 above the barrier layer 262 and in the opening 406, such as Figure 4L and Figure 4L-1 shown, Figure 4L and Figure 4L-1 show the structure 200 along Figure 1B the B-B line and the A-A line in, respectively. In embodiments where HM 228 is partially or completely removed by operation 520 (such as Figure 4M and Figure 4M-1As shown), layers 260 and 262 also fill the space between the protection spacers 226 located directly above the MTJ 150 and on two opposite sidewalls of the MTJ cell 249, such as Figure 4N and Figure 4N-1 shown, Figure 4N and Figure 4N-1 respectively show the structure 200 along the Figure 1B lines B-B and A-A in. In an embodiment, the conductive layer 260 includes a magnetic material (such as cobalt) or a non-magnetic material (such as aluminum, copper, or a combination thereof). In an embodiment, the conductive layer 262 includes a magnetic material (such as cobalt) or a non-magnetic material (such as titanium nitride, tantalum nitride, and / or other suitable conductive diffusion barriers). CVD, PVD, ALD, plating, or other suitable processes can be used to deposit the conductive layers 262 and 260. Subsequently, operation 522 performs a CMP process on the conductive layers 262 and 260 to remove the conductive layers 262 and 260 from the top surface of the dielectric layer 234. In various embodiments, method 500 deposits a magnetic material in at least one of the layers or components 218, 220, 226, 260, and 262.

[0057] At operation 524, method 500 ( Figure 3B ) performs further fabrication on the device 200, such as forming one or more metal layers above the metal layer 306, forming a passivation layer, and performing more back-end processes.

[0058] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. For example, embodiments of the present invention provide a semiconductor device having an array of MRAM cells in an MRAM region. Each MRAM cell includes a magnetic shield that is used to shield the MRAM cell from external magnetic fields, thereby improving the reliability of the MRAM cell. The magnetic shield can be provided as a magnetic material in the bottom electrode, a magnetic material in the sidewall spacer, and / or a magnetic material in the top electrode. The magnetic material in the bottom electrode or the top electrode can block vertical magnetic interference, while the magnetic material in the sidewall spacer can block horizontal magnetic interference. The MRAM cell of the present invention can be implemented as a stand-alone memory device or as an embedded memory integrated with a logic device. In addition, the formation of the semiconductor device can be easily integrated into existing semiconductor manufacturing processes.

[0059] In one exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a bottom electrode; a magnetic tunnel junction (MTJ) element located above the bottom electrode; a top electrode located above the MTJ element; and sidewall spacers adjacent to the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacers includes a magnetic material.

[0060] In an embodiment of a semiconductor device, the top electrode includes a magnetic material. In another embodiment, the magnetic material is formed as a barrier layer located below the conductive layer. In an embodiment, the conductive layer includes copper. In another embodiment, the top electrode includes a barrier layer containing tantalum and a conductive layer of magnetic material formed above the barrier layer.

[0061] In another embodiment of a semiconductor device, the bottom electrode includes a magnetic material. In another embodiment, the bottom electrode includes a barrier layer of magnetic material and a conductive material formed above the barrier layer. In yet another embodiment, the bottom electrode includes a barrier layer that includes at least one of TiN and TaN, and the magnetic material is formed above the barrier layer.

[0062] In an embodiment of a semiconductor device, the sidewall spacer includes multiple layers, and one of the layers includes a magnetic material. In another embodiment, the magnetic material is Co or NiFe. In yet another embodiment, the magnetic material is disposed between a nitride spacer and an oxide spacer.

[0063] In an embodiment of a semiconductor device, at least two of the bottom electrode, the top electrode, and the sidewall spacer include one or more magnetic materials. In another embodiment, all of the bottom electrode, the top electrode, and the sidewall spacer include one or more magnetic materials.

[0064] In another exemplary aspect, the present invention is directed to a semiconductor device that includes: a bottom electrode; a magnetic tunnel junction (MTJ) element located above the bottom electrode; a top electrode located above the MTJ element; and a sidewall spacer adjacent to the MTJ element, the sidewall spacer including a magnetic material.

[0065] In an embodiment of a semiconductor device, the magnetic material is at least one of Co and NiFe. In another embodiment, the sidewall spacer includes a stack of a nitride spacer, a magnetic material, and an oxide spacer. In another embodiment, at least one of the bottom electrode and the top electrode includes another magnetic material.

[0066] In yet another exemplary aspect, the present invention is directed to a method that includes forming a first viaduct in a first dielectric layer; forming a first barrier layer in the first viaduct; forming a first conductive layer over the first barrier layer and in the first viaduct; and depositing a magnetic tunnel junction (MTJ) stack over the first conductive layer, the first barrier layer, and the first dielectric layer, wherein the MTJ stack is electrically connected to the first conductive layer. The method further includes patterning the MTJ stack to produce a patterned MTJ stack; depositing nitride spacers over sidewalls of the patterned MTJ stack; depositing protective spacers over the nitride spacers; depositing oxide spacers over the protective spacers; depositing a second dielectric layer over the oxide spacers and the patterned MTJ stack; forming a second viaduct in the second dielectric layer; forming a second barrier layer in the second viaduct; and forming a second conductive layer over the second barrier layer and in the second viaduct, wherein the second conductive layer is electrically connected to the patterned MTJ stack, wherein at least one of the first barrier layer, the first conductive layer, the protective spacers, the second barrier layer, and the second conductive layer includes a magnetic material.

[0067] In an embodiment of the method, the magnetic material includes Co. In an embodiment, prior to patterning the MTJ stack, the method further includes depositing a hard mask layer having TiN over the MTJ stack, wherein forming the second viaduct includes removing portions of the hard mask layer exposed in the second viaduct to expose a top surface of the MTJ stack.

[0068] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A bottom electrode; A magnetic tunnel junction element located above the bottom electrode; A top electrode located above the magnetic tunnel junction element; And Sidewall spacers adjacent to the magnetic tunnel junction element, wherein the top electrode includes a first conductive layer and a first barrier layer, wherein the first barrier layer includes a first sub-layer, a second sub-layer located on the first sub-layer, and a third sub-layer located on the second sub-layer, wherein each of the first sub-layer, the second sub-layer, and the third sub-layer is disposed on the bottom surface and two sidewall surfaces of the first conductive layer, and wherein the second sub-layer includes a magnetic material.

2. The semiconductor device according to claim 1, wherein, The bottom electrode includes a second conductive layer and a second barrier layer, wherein the second barrier layer includes a fourth sub-layer, a fifth sub-layer located on the fourth sub-layer, and a sixth sub-layer located on the fifth sub-layer, wherein each of the fourth sub-layer, the fifth sub-layer, and the sixth sub-layer is disposed on the bottom surface and two sidewall surfaces of the second conductive layer.

3. The semiconductor device according to claim 2, wherein, The fifth sub-layer includes another magnetic material.

4. The semiconductor device according to claim 3, wherein, The first conductive layer includes copper.

5. The semiconductor device according to claim 2, wherein, The first sub-layer includes tantalum.

6. The semiconductor device according to claim 1, wherein, The third sub-layer includes titanium.

7. The semiconductor device according to claim 1, wherein, The magnetic material includes Co.

8. The semiconductor device according to claim 2, wherein, The fourth sub-layer includes at least one of TiN and TaN.

9. The semiconductor device according to claim 1, wherein, The sidewall spacers include multiple layers, and one of the layers includes another magnetic material.

10. The semiconductor device according to claim 9, wherein, The another magnetic material in the sidewall spacers is Co or NiFe.

11. The semiconductor device according to claim 9, wherein, The another magnetic material in the sidewall spacers is disposed between a nitride spacer and an oxide spacer.

12. The semiconductor device according to claim 1, wherein, At least one of the bottom electrode and the sidewall spacers includes one or more magnetic materials.

13. The semiconductor device according to claim 1, wherein, All of the bottom electrode, the top electrode, and the sidewall spacers include one or more magnetic materials.

14. A semiconductor device, comprising: A bottom electrode; A magnetic tunnel junction element located above the bottom electrode; A top electrode located above the magnetic tunnel junction element; And Sidewall spacers adjacent to the magnetic tunnel junction element, wherein the sidewall spacers include a first magnetic material, wherein the top electrode includes a first conductive layer and a first barrier layer located on the bottom surface and two sidewalls of the first conductive layer, wherein each of the first conductive layer and the first barrier layer includes a second magnetic material, wherein the first barrier layer includes a first sub-layer, a second sub-layer located on the first sub-layer, and a third sub-layer located on the second sub-layer, wherein each of the first sub-layer, the second sub-layer, and the third sub-layer is disposed on the bottom surface and two sidewall surfaces of the first conductive layer, and wherein the second sub-layer includes the second magnetic material.

15. The semiconductor device according to claim 14, wherein, The first magnetic material is at least one of Co and NiFe.

16. The semiconductor device according to claim 14, wherein, The sidewall spacers include a stack of a nitride spacer, the first magnetic material, and an oxide spacer.

17. The semiconductor device according to claim 14, wherein, The bottom electrode includes another magnetic material.

18. A method of forming a semiconductor device, comprising: Forming a first viaduct in a first dielectric layer; Forming a first barrier layer in the first viaduct; Forming a first conductive layer above the first barrier layer and in the first viaduct; Deposit a magnetic tunnel junction stack above the first conductive layer, the first barrier layer, and the first dielectric layer, wherein the magnetic tunnel junction stack is electrically connected to the first conductive layer; Pattern the magnetic tunnel junction stack to produce a patterned magnetic tunnel junction stack; Deposit a nitride spacer above the sidewalls of the patterned magnetic tunnel junction stack; Deposit a protective spacer above the nitride spacer; Deposit an oxide spacer above the protective spacer; Deposit a second dielectric layer above the oxide spacer and the patterned magnetic tunnel junction stack; Form a second via hole in the second dielectric layer; Form a second barrier layer in the second via hole; and Form a second conductive layer above the second barrier layer and in the second via hole, wherein the second conductive layer is electrically connected to the patterned magnetic tunnel junction stack, wherein the first barrier layer includes a first sublayer, a second sublayer located on the first sublayer, and a third sublayer located on the second sublayer, wherein each of the first sublayer, the second sublayer, and the third sublayer is disposed on the bottom surface and two sidewall surfaces of the first conductive layer, and wherein the second sublayer includes a magnetic material.

19. The method according to claim 18, wherein, The magnetic material includes Co.

20. The method according to claim 18, further comprising: Before patterning the magnetic tunnel junction stack, deposit a hard mask layer having TiN above the magnetic tunnel junction stack, wherein forming the second via hole includes removing a portion of the hard mask layer exposed in the second via hole to expose the top surface of the magnetic tunnel junction stack.

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