Resistive random access memory device

Abstract

The present disclosure relates generally to memory devices and methods of forming the same. More specifically, the present disclosure relates to resistive random access (ReRAM) memory devices. The present disclosure provides a memory device comprising a first electrode, a dielectric cap over the first electrode, a second electrode laterally adjacent to the first electrode, wherein an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode at least through the resistive layer.

Description

Technical Field

[0001] The disclosed subject matter generally relates to memory devices and methods of forming the same. More specifically, this disclosure relates to resistive random access (ReRAM) memory devices. Background Technology

[0002] Semiconductor devices and integrated circuit (IC) chips have found widespread application in the fields of physics, chemistry, biology, computing, and memory devices. An example of a memory device is a non-volatile (NV) memory device. NV memory devices are programmable and widely used in electronic products due to their ability to retain data for extended periods, even after power is turned off. Exemplary categories of NV memory can include resistive random access memory (ReRAM), erasable programmable read-only memory (EPROM), flash memory, ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM).

[0003] Resistive memory devices operate by changing (or switching) between two different states: a high-resistance state (HRS), which can represent off or a 0 state; and a low-resistance state (LRS), which can represent on or a 1 state. However, these devices can experience large changes in their resistance switching characteristics, which can lead to large fluctuations in the current flow within the device, degrading its performance and increasing its power consumption.

[0004] Therefore, there is a need to provide improved memory devices that can overcome or at least improve one or more of the disadvantages mentioned above. Summary of the Invention

[0005] In one aspect of this disclosure, a memory device is provided, comprising: a first electrode; a dielectric cap located above the first electrode; a second electrode laterally adjacent to the first electrode, wherein the upper surface of the second electrode is substantially coplanar with the upper surface of the dielectric cap; and a resistive layer located between the first electrode and the second electrode. The edge of the first electrode is electrically coupled to the edge of the second electrode at least through the resistive layer.

[0006] In another aspect of this disclosure, a memory device is provided, comprising: a first electrode; a dielectric cap located above the first electrode; a second electrode laterally adjacent to the first electrode, wherein the upper surface of the second electrode is substantially coplanar with the upper surface of the dielectric cap; a resistive layer located between the first electrode and the second electrode; and an oxygen scavenging layer located between the first electrode and the second electrode. The oxygen scavenging layer is disposed on the resistive layer and comprises a material different from the resistive layer. The edge of the first electrode is electrically coupled to the edge of the second electrode through the resistive layer and the oxygen scavenging layer.

[0007] In another aspect of this disclosure, a method is provided for forming a memory device by: forming a first electrode and a dielectric cap in a dielectric region, wherein the dielectric cap is formed on the first electrode; forming a resistive layer in an opening defined in the dielectric region; and forming a second electrode in the dielectric region, the second electrode being formed laterally adjacent to the first electrode and the dielectric cap, wherein the resistive layer is located between the first electrode and the second electrode, and the upper surface of the second electrode is substantially coplanar with the upper surface of the dielectric cap. Attached Figure Description

[0008] This disclosure can be understood by referring to the following description and the accompanying drawings.

[0009] For the sake of simplicity and clarity, the accompanying drawings illustrate a general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the embodiments described in this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the embodiments of this disclosure. The same reference numerals in different drawings denote the same elements, and similar reference numerals may, but do not necessarily, denote similar elements.

[0010] Figures 1A to 1G This is a cross-sectional view of a memory device according to an embodiment of the present disclosure.

[0011] Figures 2A to 2C Based on this disclosure Figure 1G The diagram shows a plan view of an embodiment and depicts various configurations of electrodes in the device.

[0012] Figures 3 to 8 This is a cross-sectional view illustrating a set of exemplary steps for manufacturing a memory device according to embodiments of the present disclosure.

[0013] Figure 9 Based on this disclosure Figure 7 The diagram shows a plan view of an embodiment and depicts the layout of the crossbar configuration of the memory devices. Detailed Implementation

[0014] Various exemplary embodiments of this disclosure are described below. The embodiments disclosed herein are exemplary and are not intended to be exhaustive or limiting of this disclosure.

[0015] Figure 1A A cross-sectional view of an exemplary memory device according to the present disclosure is shown. The device includes a first electrode 102, a dielectric cap 104 located above the first electrode 102, and a second electrode 106 laterally adjacent to the first electrode 102, wherein the upper surface of the second electrode 106 is substantially coplanar with the upper surface of the dielectric cap 104.

[0016] The first electrode 102 and the second electrode 106 can be connected to various interconnect structures 114, 116, 118, 120 to send or receive electrical signals between other circuitry and / or active components in the memory device. The interconnect structures may include interconnect vias 118, 120 and conductors 114, 116, and may include metals such as copper, cobalt, aluminum, or alloys thereof. Depending on the design requirements of the memory device, conductors 114, 116 may be configured as source lines or word lines. As used herein, the terms "source line" and "bit line" refer to electrical terminal connections that connect elements in the memory device circuitry.

[0017] Examples of active components (not shown) that can be connected to the first electrode 102 and the second electrode 106 may include diodes (e.g., single-photon avalanche diodes) or transistors, such as, but not limited to, planar field-effect transistors, fin field-effect transistors (FinFETs), ferroelectric field-effect transistors (FeFETs), complementary metal-oxide-semiconductor (CMOS) transistors, and bipolar junction transistors (BJTs).

[0018] A resistive layer 108 is located between the first electrode 102 and the second electrode 106. The resistive layer 108 may be conformally fitted to the sidewalls and lower surface of the second electrode 106. The edge of the first electrode 102 is electrically coupled to the edge of the second electrode 106 through the resistive layer 108. Specifically, the resistive layer 108 may include a conductive path 112 configured to be formed between the edge of the first electrode 102 and the edge of the second electrode 106 in response to an electrical signal (e.g., a set voltage or current).

[0019] For example, a set voltage can be applied to one of the wires 114 and 116 to provide a potential difference between the first electrode 102 and the second electrode 106. This potential difference can lead to the formation of a conductive path 112 to allow electrical conduction between the first electrode 102 and the second electrode 106. Specifically, the conductive path 112 can be a filament formed by the diffusion or drift of charges (e.g., ions, electrons) caused by the potential difference.

[0020] The resistive layer 108 may also be configured to have a switchable resistance responsive to changes in an electrical signal. For example, when an electrical signal is applied, the formation of a filament can decrease the resistance of the resistive layer 108. When the electrical signal flows in the reverse direction, the filament can be removed and the resistance of the resistive layer 108 can increase, thereby enabling the controllable resistive properties of the resistive layer 108. The resistive layer 108 may exhibit characteristics characterized by changes in the resistance states of the material forming the layer. These resistance states (e.g., a high resistance state or a low resistance state) can be used to represent one or more bits of information. During an operation switch for changing the stored data, the resistive layer 108 can change its resistance state when a switching electrical signal (e.g., a set voltage or a reset voltage) is applied to the resistive layer 108.

[0021] As shown in the figure, the first electrode 102 may have a corner edge 102a on its upper surface and a corner edge 102b on its lower surface. The second electrode 106 may have a corner edge 106a on its lower surface. When an electrical signal is applied, the corner edges 102a and 102b of the first electrode and the corner edge 106a of the second electrode 106 may have the strongest electric field (i.e., the largest charge concentration). Therefore, the corner edges 102a and 102b of the first electrode 102 may be positioned close to the corner edge 106a of the second electrode 106 so that when an electrical signal is applied, the formed conductive path 112 can be confined to the region between one of the corner edges 102a and 102b of the first electrode 102 and the corner edge 106a of the second electrode 106. The confinement of the conductive path 112 helps reduce the randomness of the formation of the conductive path 112, thereby reducing the cycle time and inter-device variability of the memory device in a high-resistance state. In other words, the variability of the resistance of the resistive layer 108 in a high-resistance state can be reduced. This enables stable switching of the resistor states in resistor layer 108 during device operation and can reduce its total power consumption.

[0022] exist Figure 1A In the illustrated embodiment, the lower surface of the second electrode 106 may be located between the upper surface and the lower surface of the first electrode 102, such that the corner edge 106a of the lower surface of the second electrode 106 is close to either the corner edge 102a or the corner edge 102b of the upper surface of the first electrode 102. In another embodiment (not shown), the lower surface of the second electrode 106 may be positioned above or substantially coplanar with the upper surface of the first electrode 102, such that the corner edge 106a of the lower surface of the second electrode is close to the corner edge 102a of the upper surface of the first electrode 102.

[0023] although Figure 1AA conductive path 112 is shown that connects the corner edge 106a on the lower surface of the second electrode 106 to the corner edge 102b on the lower surface of the first electrode 102. However, it should be understood that the conductive path 112 may also connect the corner edge 106a on the lower surface of the second electrode 106 to the corner edge 102a on the upper surface of the first electrode 102, depending on the proximity of the corner edges 102a, 102b, and 106a.

[0024] The thickness of the resistive layer 108 can be configured such that a relatively low voltage level is sufficient to switch the resistance of the resistive layer 108. In some embodiments, the resistive layer 108 may have a thickness in the range of about 1 nm to about 10 nm. Examples of materials used for the resistive layer 108 may include, but are not limited to, carbon polymers, perovskites, silicon dioxide, metal oxides, or nitrides. Some examples of metal oxides may include lanthanide oxides, tungsten oxide, zinc oxide, nickel oxide, niobium oxide, titanium oxide, hafnium oxide, aluminum oxide, tantalum oxide, zirconium oxide, yttrium oxide, scandium oxide, magnesium oxide, chromium oxide, and vanadium oxide. Examples of nitrides may include boron nitride and aluminum nitride. In some embodiments, metal oxides with a band gap greater than 3 eV may be used. Examples of such oxides may include titanium oxide, tungsten oxide, niobium oxide, nickel oxide, zinc oxide, lanthanide oxides, hafnium oxide, aluminum oxide, tantalum oxide, zirconium oxide, and yttrium oxide.

[0025] The dielectric cap 104 can provide structural protection for the first electrode 102 and may comprise nonmetals, such as, but not limited to, oxides or nitrides. For example, the dielectric cap 104 may comprise silicon dioxide, silicon nitride, titanium oxide, or combinations thereof. The dielectric cap 104 may be disposed on the upper surface of the first electrode 102, and the thickness of the second electrode 106 may be defined by making the upper surface of the second electrode 106 substantially coplanar with the upper surface of the dielectric cap 104. Advantageously, by positioning the dielectric cap 104 on the upper surface of the first electrode 102, the dielectric cap 104 can prevent the formation of any conductive path (or filament) connecting the edge at the upper surface of the first electrode 102 to the edge at the upper surface of the second electrode 106. Thus, the filament may be confined in a preferred region between one of the corner edges 102a, 102b of the first electrode 102 and the corner edge 106a of the second electrode 106. In one embodiment, the second electrode 106 may be configured to have a greater thickness than the first electrode 102.

[0026] In one embodiment, the first electrode 102 may be configured as an active electrode, while the second electrode 106 may be configured as an inert electrode. Alternatively, in another embodiment, the second electrode may be configured as an active electrode, while the first electrode 106 may be configured as an inert electrode.

[0027] As used herein, the term "active electrode" can refer to an electrode having a conductive material capable of being oxidized and / or reduced (i.e., a redox reaction) to generate a charge for forming the conductive path 112 in the resistive layer 108. Examples of conductive materials in an active electrode may include, but are not limited to, tantalum (Ta), hafnium (Hf), titanium (Ti), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), or alloys thereof. Conversely, the term "inert electrode" can refer to a conductive material resistant to redox reactions. Examples of conductive materials for inert electrodes may include, but are not limited to, ruthenium (Ru), platinum (Pt), titanium nitride (TiN), and tantalum nitride (TaN). Preferably, the active electrode may be configured to have a thickness much greater than that of an inert electrode. The greater thickness of the active electrode provides sufficient material for redox reactions between the active electrode and the resistive layer.

[0028] exist Figure 1A In the illustrated embodiment, the conductor 116 may be formed in the first dielectric region 124. The dielectric cap 104, the first electrode 102, the second electrode 106, and the resistive layer 108 may be formed in the second dielectric region 126. The first dielectric region 124 and the second dielectric region 126 may be part of an intermetallic dielectric (IMD) layer or a "metallization level". Examples of dielectric materials in the first dielectric region 124 and the second dielectric region 126 may include, but are not limited to, silicon dioxide, tetraethyl orthosilicate (TEOS), or materials with SiC. x O y H z The chemical composition of the material, where x, y, and z are stoichiometric ratios.

[0029] A dielectric layer 122 may be disposed between a first dielectric region 124 and a second dielectric region 126. Interconnect vias 120 may be formed in the dielectric layer 122. Examples of dielectric materials in the dielectric layer 122 may include, but are not limited to, silicon nitride (SiN), nitrogen-doped silicon carbide (SiCN), and SiC. x H z (i.e., BLoK) TM ) or SiN w C x H z (i.e., NBLOK) TM ), where each of w, x, y, and z independently has a value greater than 0 and less than 0.75.

[0030] refer to Figure 1B Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1AThe memory device may include an oxygen scavenging layer 110 located between a first electrode 102 and a second electrode 106. The edge of the first electrode 102 may be electrically coupled to the edge of the second electrode 106 via a resistive layer 108 and an oxygen scavenging layer 110. For example, a conductive path 112 may be configured to be formed in the resistive layer 108 and the oxygen scavenging layer 110 to electrically couple the edge of the first electrode 102 to the edge of the second electrode 106 in response to an electrical signal (e.g., a set voltage or current).

[0031] As used herein, the terms "oxygen scavenger" or "oxygen remover" can refer to a component, layer, film, or material that consumes or depletes oxygen ions from a given environment or reacts with such oxygen ions. As shown, an oxygen scavenger layer 110 is disposed on a resistive layer 108 and may be conformally oriented to the sidewalls and lower surface of the second electrode 106. The oxygen scavenger layer 110 may comprise a material different from that of the resistive layer 108. In some embodiments, the oxygen scavenger layer 110 may comprise tantalum (Ta), titanium (Ti), tungsten (W), hafnium oxide (HfO2), or aluminum oxide (Al2O3). The oxygen scavenger layer 110 may be arranged to contact the active electrode.

[0032] exist Figure 1B In the illustrated embodiment, the second electrode 106 is configured as an active electrode, while the first electrode 102 is configured as an inert electrode. The active electrode (e.g., the second electrode 106) is disposed on the oxygen scavenging layer 110, which is disposed on the resistive layer 108, and the sidewalls of the inert electrode (e.g., the first electrode 102) are in contact with the resistive layer 108.

[0033] The oxygen scavenging layer 110 can be configured to cause ions to move from the resistive layer 108 toward the oxygen scavenging layer 110 in response to an electrical signal. For example, when a potential difference is applied across an active electrode (e.g., the second electrode 106) and an inert electrode (e.g., the first electrode 102), the oxygen scavenging layer 110 can scavenge oxygen ions from the resistive layer 108 to increase the concentration or density of oxygen vacancies in the resistive layer 108. The oxygen ions scavenged by the oxygen scavenging layer 110 can then drift to the active electrode to complete the conductive path 112 between the first electrode 102 and the second electrode 106.

[0034] Advantageously, the presence of the oxygen removal layer 110 is found to provide additional confinement to the filament in the region between the corner edges 102a, 102b of the first electrode 102 and the corner edge 106a of the second electrode 106, thereby further reducing the variability of the resistance of the resistive layer 108.

[0035] refer to Figure 1C Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1BThe same characteristics as described herein. As described herein, the oxygen scavenging layer 110 can be arranged to contact the active electrode. Figure 1C In the illustrated embodiment, the first electrode 102 is configured as an active electrode, while the second electrode 106 is configured as an inert electrode. The inert electrode (e.g., the second electrode 106) is disposed on the resistive layer 108, which is disposed on the oxygen scavenging layer 110, and the sidewalls of the active electrode (e.g., the first electrode 102) are in contact with the oxygen scavenging layer 110.

[0036] refer to Figure 1D Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1C The same characteristics. Figure 1D The illustrated embodiments are similar to Figure 1C The embodiments shown, except in Figure 1C In this configuration, the lower surface of the second electrode 106 is substantially coplanar with the upper surface of the first electrode 102. For example, the thicknesses of the resistive layer 108 and the oxygen removal layer 110 can be modified such that the corner edge 106a at the lower surface of the second electrode 106 is close to the corner edge 102a at the upper surface of the first electrode 102. When an electrical signal is applied, the conductive path 112 can be confined to the region between the corner edge 102a of the first electrode 102 and the corner edge 106a of the second electrode 106, thereby reducing the variability of the resistance of the resistive layer 108.

[0037] In another embodiment (not shown), the lower surface of the second electrode 106 may be located above the upper surface of the first electrode 102. For example, the thicknesses of the resistive layer 108 and the oxygen scavenging layer 110 may be modified so that the lower surface of the second electrode 106 can be raised above the layer located above the upper surface of the first electrode.

[0038] refer to Figure 1E Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1D The memory device may include a multilayer resistive layer 108 and a multilayer oxygen scavenging layer 110 disposed between a first electrode 102 and a second electrode 106. Depending on the thickness and number of layers used, the lower surface of the second electrode 106 may be substantially coplanar with the upper surface of the first electrode 102, such that the corner edge 106a at the lower surface of the second electrode 106 is close to the corner edge 102a at the upper surface of the first electrode 106. When an electrical signal is applied, the conductive path 112 may be confined in the region between the corner edge 102a of the first electrode 102 and the corner edge 106a of the second electrode 106, thereby reducing the variability of the resistance of the resistive layer 108.

[0039] refer to Figure 1F Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1B The memory device may include a first electrode 102, a first dielectric cap 104 located above the first electrode 102, and a second electrode 106 laterally adjacent to the first electrode 102, wherein the upper surface of the second electrode 106 is substantially coplanar with the upper surface of the first dielectric cap 104. The memory device may also include a third electrode 103 laterally adjacent to the second electrode 106, wherein the second electrode 106 is disposed between the first electrode 102 and the third electrode 103. A second dielectric cap 105 may be disposed above the third electrode 103, and the upper surface of the second electrode 106 may be substantially coplanar with the upper surface of the second dielectric cap 105. In some embodiments, the third electrode 103 may include the same conductive material as the first electrode 102. Alternatively, in other embodiments, the first electrode 102 may include a different conductive material than the third electrode 103.

[0040] The thickness of the third electrode 103 may be substantially similar to the thickness of the first electrode 102 in some embodiments, or different in other embodiments. The first electrode 102 and the third electrode 103 may have substantially similar widths in some embodiments, or different widths in other embodiments. For example, the first electrode 102 and the third electrode 103 may be formed using the same processing steps, which may result in the two electrodes having substantially similar thicknesses or widths. In another example, the first electrode 102 and the third electrode 103 may be formed using different processing steps, which may result in the two electrodes having different thicknesses or widths. The thickness, width, and conductive material of the first electrode 102 and the third electrode 103 may be modified according to the design requirements of the device.

[0041] As described herein, the resistive layer 108 and the oxygen removal layer 110 may be conformally fitted to the sidewalls and lower surface of the second electrode 106. Specifically, the resistive layer 108 and the oxygen removal layer 110 may extend between the second electrode 106 and the third electrode 103, and between the second electrode 106 and the first electrode 102.

[0042] The first electrode 102, the second electrode 106, and the third electrode 103 can be connected to interconnect vias 118 and 120 and wires 114, 116, and 117. Wires 114, 116, and 117 can be configured as source lines or word lines, depending on the design requirements of the memory device. For example, in... Figure 1F In the illustrated embodiment, a bit line (e.g., wire 114) may be positioned above and connected to the second electrode 106. A first source line (e.g., wire 116) may be positioned below and connected to the first electrode 102, while a second source line (e.g., wire 117) may be positioned below and connected to the third electrode 103.

[0043] refer to Figure 1G Another embodiment of the memory device is shown, wherein the same reference numerals indicate Figure 1B The memory device may include a first electrode 102, a dielectric cap 104 located above the first electrode 102, and a second electrode 106 laterally adjacent to the first electrode 102. The memory device may also include a third electrode 107 laterally adjacent to the first electrode 102, wherein the first electrode 102 may be disposed between the second electrode 106 and the third electrode 107. Figure 1G In the illustrated embodiment, the upper surface of the dielectric cap 104 may be substantially coplanar with the upper surfaces of the second electrode 106 and the third electrode 107.

[0044] The second electrode 106 and the third electrode 107 may have substantially similar thicknesses or widths in some embodiments, or different thicknesses or widths in others. In some embodiments, the second electrode 106 may comprise the same conductive material as the third electrode 107. Alternatively, in other embodiments, the second electrode 106 may comprise a different conductive material than the third electrode 107. The thickness, width, and conductive material of the second electrode 106 and the third electrode 107 may be modified according to the design requirements of the device.

[0045] A first resistive layer 108 and a first oxygen scavenging layer 110 may be disposed between a first electrode 102 and a second electrode 106. The first resistive layer 108 and the first oxygen scavenging layer 110 may be conformally oriented to the sidewalls and lower surface of the second electrode 106. A second resistive layer 109 and a second oxygen scavenging layer 111 may be disposed between a first electrode 102 and a third electrode 107. The second resistive layer 109 and the second oxygen scavenging layer 111 may be conformally oriented to the sidewalls and lower surface of the third electrode 107.

[0046] The first electrode 102, the second electrode 106, and the third electrode 107 can be connected to interconnect vias 118 and 120 and wires 114 and 116. Wires 114 and 116 can be configured source lines or word lines, depending on the design requirements of the memory device. For example, in... Figure 1G In the illustrated embodiment, a bit line (e.g., wire 114) may be positioned above the second electrode 106 and the third electrode 107. Both the second and third electrodes 107 may be connected to the bit line. A source line (e.g., wire 116) may be positioned below and connected to the first electrode 102.

[0047] Figures 2A to 2C Various configurations of the first electrode 102, the second electrode 106, and the third electrode 107 are shown. The cross-sectional line X-X' indicates the direction from... Figure 1GThe view shows a cross-section. For simplicity, only the first electrode 102, the second electrode 106, and the third electrode 107 are shown. Although the electrodes shown are generally square, it should be understood that other electrode shapes are also within the scope of this disclosure. For example, due to manufacturing limitations, one or more electrodes may have rounded corners or rounded edges that are not perfectly straight.

[0048] Figure 2A An embodiment in which the first electrode 102, the second electrode 106, and the third electrode 107 have substantially similar widths is depicted. For example... Figure 2A As shown, the side edge of the first electrode 102 is approximately equal to the side edge of the second electrode 106 and the side edge of the third electrode 107.

[0049] Alternatively, Figure 2B and Figure 2C An embodiment is shown in which the first electrode 102, the second electrode 106, and the third electrode 107 have different widths. Figure 2B In the illustrated embodiment, the second electrode 106 has a wider width than the first electrode 102 and the third electrode 107. Since the first electrode 102 has a smaller width than the second electrode 106, the side edge 136a of the first electrode 102 can be positioned close to the side edge 134a of the second electrode 106, while the side edge 136b of the first electrode 102 can be positioned away from the side edge 134b of the second electrode 106.

[0050] exist Figure 2C In the illustrated embodiment, the third electrode 107 may have a smaller width than the first electrode 102 and the second electrode 106. Because the third electrode 107 has a smaller width than the first electrode 102, the side edge 138a of the third electrode 107 may be positioned close to the side edge 136d of the first electrode 102, while the side edge 136c of the first electrode 102 may be positioned away from the side edge 134b of the second electrode 106.

[0051] Advantageously, electrodes of different widths can increase the confinement of the wire by ensuring that conductive paths are formed only at the shortest distance between the edges of the electrodes (i.e., the edges with the closest proximity). Increased confinement of the wire leads to a reduction in the variability of the resistance of the resistive layer, and consequently, a reduction in the voltage level used to switch the resistance of the resistive layer.

[0052] It should be understood that Figure 2B and Figure 2C The different electrode configurations depicted can be conceived as suitable for Figures 1A to 1F Examples of implementations.

[0053] The memory devices described herein can be resistive memory devices. Examples of resistive memory devices may include, but are not limited to, oxide random access memory (OxRAM).

[0054] Figures 3 to 8 A set of steps is shown that can be used to create memory devices as provided in the embodiments of this disclosure.

[0055] As used herein, “deposition technique” refers to a process of applying material onto another material (or substrate). Exemplary techniques for deposition include, but are not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source atomized chemical deposition (LSMCD), and atomic layer deposition (ALD).

[0056] Furthermore, "patterning techniques" include the deposition of materials or photoresists required to form the patterns, structures, or openings; patterning of materials or photoresists; exposure, development, etching, cleaning, and / or removal. Examples of patterning techniques include, but are not limited to, wet etching lithography, dry etching lithography, or direct patterning processes. These techniques may utilize mask sets and mask layers.

[0057] refer to Figure 3 The diagram illustrates a device structure for fabricating the memory device of this disclosure. The device structure may include a first dielectric region 124 having conductors 116, 117. A dielectric layer 122 may be deposited on the first dielectric region 124 using the deposition techniques described herein. Interconnect vias 120 may be formed in the dielectric layer 122, for example by patterning the dielectric layer 122 to define openings in the dielectric layer 122 and then depositing material in the openings to form the interconnect vias 120.

[0058] Figure 4A and Figure 5 A set of steps for forming electrodes 102, 103 and dielectric caps 104, 105 in the second dielectric region 126 is shown.

[0059] like Figure 4A As shown ( Figure 4A Continued Figure 3 In the illustrated embodiment, a dielectric material can be deposited using the deposition techniques described herein to form a second dielectric region 126 on the dielectric layer 122. The second dielectric region 126 can then be patterned using the patterning techniques described herein to define an opening 128 within the second dielectric region 126.

[0060] like Figure 5 As shown ( Figure 5 Continued Figure 4AIn the illustrated embodiment, conductive material can be deposited using the deposition technique described herein to form a first electrode 102 and a third electrode 103 in the opening 128. Subsequently, a first dielectric cap 104 can be deposited on the first electrode 102, and a second dielectric cap 105 can be deposited on the third electrode 103.

[0061] Figure 4B and Figure 5 An alternative set of steps for forming electrodes 102, 103 and dielectric caps 104, 105 in the second dielectric region 126 is shown.

[0062] like Figure 4B As shown ( Figure 4B Continued Figure 3 In the illustrated embodiment, a conductive material layer can be deposited on the dielectric layer 122, and a non-metallic material layer can be deposited on the conductive material layer. A patterning step (using the patterning techniques described herein) can then be performed with respect to the conductive and non-metallic material layers to form a first electrode 102, a third electrode 103, a first dielectric cap 104, and a second dielectric cap 105. The patterning step also defines an opening 128 between the first electrode 102 and the third electrode 103. In this embodiment, the first dielectric cap 104 and the second dielectric cap 105 can be used as masks during the patterning step to form the first electrode 102 and the third electrode 103 from the conductive material layer and to define the opening 128 between the first electrode 102 and the third electrode 103.

[0063] like Figure 5 As shown ( Figure 5 Continued Figure 4B As shown in the embodiment, a dielectric material can be deposited in the opening 128 between the first electrode and the third electrode 103 using the deposition technique described herein, thereby forming a second dielectric region 126.

[0064] refer to Figure 6 ( Figure 6 Continued Figure 5In the illustrated embodiment, the second electrode 106 may be laterally formed between the first electrode 102 and the third electrode 103. For example, an opening (not shown) may be defined in the second dielectric region 126 using the patterning techniques described herein. A resistive layer 108 may be deposited in the opening using the deposition techniques described herein. Preferably, the resistive layer 108 may be formed using a conformal deposition process such as an ALD process or a highly conformal CVD process. An oxygen scavenging layer 110 may be deposited on the resistive layer 108 using the deposition techniques described herein. Preferably, the oxygen scavenging layer 110 may be deposited conformally to the resistive layer 108. Subsequently, the second electrode 106 may be deposited on the oxygen scavenging layer 110. A chemical mechanical planarization process may be performed to planarize the upper surface of the second electrode 106 and the upper surfaces of the dielectric caps 104, 105.

[0065] In an alternative embodiment (not shown), an oxygen removal layer 110 may be deposited in the opening. A resistive layer 108 may then be deposited on the oxygen removal layer 110, followed by the deposition of a second electrode 106 on the resistive layer 108.

[0066] refer to Figure 7 ( Figure 7 Continued Figure 6 In the illustrated embodiment, additional dielectric material can be deposited over the dielectric caps 104, 105 and the second electrode 106. The deposited dielectric material can be patterned to define via openings 132 that expose the upper surface of the second electrode 106.

[0067] refer to Figure 8 ( Figure 8 Continued Figure 7 In the illustrated embodiment, the via opening 132 can be filled with metal using the deposition technique described herein to form the interconnect via 118. A conductor 114 can be formed on the second dielectric region 126 and contact the interconnect via 118. Figure 8 In the illustrated embodiment, wire 114 can be configured as a bit line, while wires 116 and 117 can be configured as source lines.

[0068] Figure 9 yes Figure 8 The diagram shows a plan view of an embodiment and illustrates an exemplary cross-layout configuration of the memory devices. The cross-section line X-X' indicates the direction from... Figure 8 The view shows a cross-section. For simplicity, only the first electrode, second electrode, third electrode, source line, and bit line are shown. Figure 9As shown, bit line 814 is positioned above the first electrode 802, the second electrode 806, and the third electrode 803. Source lines 816 and 817 (delineated by dashed rectangles) are positioned below the first electrode 802, the second electrode 806, and the third electrode 803. Bit line 814 may cross source lines 816 and 817 to provide a cross configuration.

[0069] Throughout this disclosure, it should be understood that if a method is described herein as involving a series of steps, the order of these steps presented herein is not necessarily the only order in which they can be performed, and some said steps may be omitted and / or certain other steps not described herein may be added to the method. Furthermore, the terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article of manufacture, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to those processes, methods, articles of manufacture, or devices. The appearance of the phrase “in one embodiment” does not necessarily indicate the same embodiment.

[0070] The description of various embodiments in this disclosure is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory set forth in the foregoing background or the following detailed description.

[0071] Furthermore, the various tasks and processes described herein can be incorporated into a more comprehensive procedure or process with additional functions not described in detail herein. Specifically, the various processes in the manufacture of integrated circuits are well known; therefore, for the sake of brevity, many processes are only briefly mentioned or omitted entirely without providing well-known process details.

[0072] Those skilled in the art will readily understand, upon fully reading this application, that the disclosed semiconductor devices and their formation methods can be used to manufacture a variety of different integrated circuit products, including but not limited to memory chips, NV memory devices, FinFET transistor devices, CMOS devices, etc.

Claims

1. A memory device, comprising: First electrode; A dielectric cap is located above the first electrode; A second electrode, laterally adjacent to the first electrode, wherein the upper surface of the second electrode is coplanar with the upper surface of the dielectric cap; and A resistive layer is located between the first electrode and the second electrode, wherein the edge of the first electrode is electrically coupled to the edge of the second electrode at least through the resistive layer; An oxygen removal layer is located between the first electrode and the second electrode, wherein the oxygen removal layer is disposed on the resistive layer; and A dielectric layer is located below the first electrode and the oxygen removal layer, wherein the oxygen removal layer is directly on the dielectric layer.

2. The device according to claim 1, wherein, The resistive layer includes conductive paths configured to be formed between the edges of the first electrode and the second electrode in response to changes in an electrical signal.

3. The device according to claim 1, wherein, The resistive layer is conformal to the sidewall and lower surface of the second electrode.

4. The device according to claim 3, wherein, The lower surface of the second electrode is located between the upper and lower surfaces of the first electrode.

5. The device according to claim 3, wherein, The lower surface of the second electrode is coplanar with the upper surface of the first electrode.

6. The device according to claim 1, wherein, The oxygen scavenging layer is disposed on the resistive layer and comprises a material different from that of the resistive layer.

7. The device according to claim 6, wherein, The oxygen scavenging layer is configured to cause ions to move from the resistive layer toward the oxygen scavenging layer in response to an electrical signal.

8. The device according to claim 7, wherein, The first electrode is configured as an active electrode, the second electrode is configured as an inert electrode, and the oxygen scavenging layer contacts the active electrode.

9. The device according to claim 7, wherein, The oxygen removal layer includes tantalum, titanium, tungsten, hafnium oxide, or aluminum oxide.

10. A memory device, comprising: First electrode; A dielectric cap is located above the first electrode; The second electrode is laterally adjacent to the first electrode, wherein the upper surface of the second electrode is coplanar with the upper surface of the dielectric cap; A resistive layer is located between the first electrode and the second electrode; An oxygen removal layer is located between the first electrode and the second electrode, the oxygen removal layer being disposed on the resistive layer and comprising a material different from the resistive layer; and a dielectric layer is located below the first electrode and the oxygen removal layer, wherein the oxygen removal layer is directly on the dielectric layer. The edge of the first electrode is electrically coupled to the edge of the second electrode through the resistive layer and the oxygen scavenging layer.

11. The device according to claim 10, wherein, The resistive layer and the oxygen removal layer are conformally oriented to the sidewalls and lower surface of the second electrode.

12. The device according to claim 11, wherein, The lower surface of the second electrode is located between the upper and lower surfaces of the first electrode.

13. The device according to claim 11, wherein, The lower surface of the second electrode is coplanar with the upper surface of the first electrode.

14. The device according to claim 11, wherein, The dielectric cap located above the first electrode is a first dielectric cap, and the device further includes: A third electrode, which is laterally adjacent to the second electrode, wherein the second electrode is disposed between the first electrode and the third electrode; and A second dielectric cap is located above the third electrode, wherein the upper surface of the second dielectric cap is coplanar with the upper surface of the second electrode.

15. The device according to claim 14, wherein, The resistive layer and the oxygen scavenging layer extend between the third electrode and the second electrode.

16. The device according to claim 15, further comprising: Bit lines are arranged above and connected to the second electrode; A first source line is arranged below the first electrode and connected to the first electrode; as well as A second source line is disposed below and connected to the third electrode, wherein the first source line is parallel to the second source line, and the second electrode is disposed between the first source line and the second source line.

17. The device according to claim 16, wherein, The bit line spans the first source line and the second source line.

18. A method of forming a memory device, comprising: A first electrode and a dielectric cap are formed in a dielectric region on a dielectric layer, wherein the dielectric cap is formed on the first electrode; An oxygen removal layer is formed in an opening defined in the dielectric region, wherein the oxygen removal layer is directly on the dielectric layer; A resistive layer is formed in the opening defined in the dielectric region; and A second electrode is formed in the dielectric region, the second electrode being laterally adjacent to the first electrode and the dielectric cap, wherein the resistive layer is located between the first electrode and the second electrode, and the upper surface of the second electrode is coplanar with the upper surface of the dielectric cap.

19. The method according to claim 18, wherein, Forming the first electrode and the dielectric cap includes patterning the dielectric region to define an opening and depositing the first electrode and the dielectric cap in the opening.

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