Memory device, memory array and method of forming the same

Abstract

The present disclosure relates to a memory device, a memory array and a method for forming the same. A memory device may be provided. The memory device may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory device may also include: a contact element arranged in the well and including a first contact having the first conductivity type; a diode layer arranged in the well and having a second conductivity type opposite to the first conductivity type; and a dummy gate configured to isolate the first contact from the diode layer. The memory device may also include a memory element electrically connected to the diode layer.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices, memory arrays, methods of forming memory devices, and methods of forming memory arrays. Background Art

[0002] Semiconductor memory has a variety of applications, including various consumer electronics and computing devices. Emerging memories include resistive random access memory (ReRAM), phase change random access memory (PCRAM), etc.

[0003] For high-density applications, the memory can be integrated in a cross-point or cross-bar memory architecture. In a 1T1R (one transistor and one resistor) structure, the bit cell has a large cell size and incurs a large area loss. Therefore, a cross-point memory architecture with a 1S1R (one selector and one resistor) structure is proposed to achieve a compact cell size and suppress sneak path current.

[0004] However, various selectors such as BEOL (back-end-of-line) metal-based selectors used in conventional 1S1R structures are not compatible with complementary metal oxide semiconductor (CMOS) processes. These selectors also suffer from low driveability, small on / off ratio, poor durability, and thus require low processing temperatures. Summary of the invention

[0005] According to various non-limiting embodiments, a memory device may be provided. The memory device may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory device may also include: a contact element arranged in the well and including a first contact having the first conductivity type; a diode layer arranged in the well and having a second conductivity type opposite to the first conductivity type; and a dummy gate configured to isolate the first contact from the diode layer. The memory device may also include: a memory element electrically connected to the diode layer.

[0006] According to various non-limiting embodiments, a method of forming a memory device may be provided. The method may include providing a substrate, wherein the substrate includes a well having a first conductivity type. The method may also include: forming a contact element in the well, wherein the contact element includes a first contact having the first conductivity type; forming a diode layer in the well, wherein the diode layer has a second conductivity type opposite to the first conductivity type; forming a dummy gate to isolate the first contact from the diode layer; and electrically connecting a memory element to the diode layer.

[0007] According to various non-limiting embodiments, a memory array may be provided. The memory array may include a substrate, wherein the substrate includes a well having a first conductivity type. The memory array may also include: a plurality of columns including a plurality of memory cells arranged in a matrix form. The plurality of columns may include a first column of memory cells and a second column of memory cells. Each memory cell may include: a diode layer, which is arranged in the well and has a second conductivity type opposite to the first conductivity type; and a memory element, which is electrically connected to the diode layer. The memory array may also include: a contact element column, which includes a contact element arranged in the well, wherein each contact element includes a first contact having the first conductivity type; a dummy gate, which is configured to isolate the contact element column from the diode layer in each memory cell in the first column of memory cells; and another dummy gate, which is configured to isolate the diode layer in the first column of memory cells from the diode layer in the second column of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, the same reference numerals represent the same parts in all the different views. In addition, the drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. Embodiments of the present invention will now be described with reference to the following drawings for purposes of illustration only, wherein:

[0009] Figure 1 Schematic diagrams illustrating cross-sectional views of memory devices are shown in accordance with various non-limiting embodiments.

[0010] Figure 2 A perspective view of a memory array is shown in accordance with various non-limiting embodiments.

[0011] Figure 3A 1 shows a diagram of a circuit along line A-A' according to various non-limiting embodiments. Figure 2 A cross-sectional view of a memory array.

[0012] Figure 3B 1 shows a diagram of a circuit along line B-B' according to various non-limiting embodiments. Figure 2 A cross-sectional view of a memory array.

[0013] Figure 3C shows a diagram along line C-C' according to various non-limiting embodiments. Figure 2 A cross-sectional view of a memory array.

[0014] Figure 4 Shown are representations according to various non-limiting embodiments Figure 2 Equivalent circuit of the memory array.

[0015] Figure 5A perspective view of a memory array is shown in accordance with various non-limiting embodiments.

[0016] Figure 6 and Figure 7 Shown are representations according to various non-limiting embodiments Figure 5 The corresponding equivalent circuit of the memory array.

[0017] Figure 8 A flow chart illustrating a method of forming a memory device according to various non-limiting embodiments is shown.

[0018] Fig. 9 A flow chart illustrating a method of forming a memory array is shown, according to various non-limiting embodiments.

[0019] Figures 10A-10F Methods of forming a memory array according to various non-limiting embodiments are shown.

[0020] Figures 11A-11B A process of forming a memory array according to various non-limiting embodiments is shown.

[0021] Figures 12A-12F Methods of forming a memory array according to various non-limiting embodiments are shown. DETAILED DESCRIPTION

[0022] The various aspects of the present invention and its features, advantages and details are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the details of the present invention. However, it should be understood that while indicating aspects of the present invention, detailed descriptions and specific examples are provided only for illustration and not for limitation. Through this disclosure, various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the following inventive concepts will be apparent to those skilled in the art.

[0023] As used herein throughout the specification and claims, approximate language may be applied to modify any quantitative representation that may be permissibly varied without resulting in a change in the basic function to which it is related. Thus, a value modified by a term or terms such as "about" is not limited to the precise value specified. In some cases, approximate language may correspond to the precision of an instrument used to measure a value or.

[0024] The terms used herein are only for describing specific examples and are not intended to limit the present invention. As used herein, the singular forms "one", "an" and "said" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "include" (and any form of including, such as "include" and "include"), "have" (and any form of having, such as "have" and "have"), "include" (and any form of including, such as "include" and "include") and "contain" (and any form of containing, such as "contain" and "contain") are all open linking verbs. As a result, the method or device of "include", "have", "include" or "contain" one or more steps or elements has these one or more steps or elements, but is not limited to having only these one or more steps or elements. Similarly, the steps of the method or elements of the device of "include", "have", "include" or "contain" one or more features have these one or more features, but are not limited to having only these one or more features. In addition, the device or structure configured in a certain way is configured at least in this way, but can also be configured in an unlisted way.

[0025] The term "connected" (or "coupled") herein, when used to refer to two physical elements, means a direct connection between the two physical elements or a connection through one or more intermediate elements.

[0026] It should be understood that when used in the following description, the terms "upper", "above", "below", "top", "bottom", "lower", "side", "back", "left", "right", "front", "side", "one side", "upward", "downward", etc. are used for convenience and to help understand relative positions or directions, and are not intended to limit the orientation of any device, structure, or any part of any device or structure. In addition, the singular terms "a", "an", and "the" include plural references unless the context clearly indicates otherwise. Similarly, the word "or" is intended to include "and" unless the context clearly indicates otherwise.

[0027] The non-limiting embodiments described below in the context of a device are similarly valid for the corresponding method, and vice versa.In addition, it should be understood that the embodiments described below may be combined; for example, a portion of one embodiment may be combined with a portion of another embodiment.

[0028] It should be understood that any features described herein for a specific device also apply to any device described herein. It should be understood that any features described herein for a specific method also apply to any method described herein. In addition, it should be understood that for any device or method described herein, it is not necessary to include all of the components or steps described in the device or method, but only some (but not all) components or steps may be included.

[0029] Various non-limiting embodiments are directed to a memory device, such as a resistive memory device. Various non-limiting embodiments are also directed to a memory array, such as a cross-point or cross-stripe memory array having a 1S1R (one selector and one resistor) structure or a 2S1R (double selectors and one resistor) structure.

[0030] Figure 1 A schematic diagram illustrating a cross-sectional view of a memory device 100 is shown, according to various non-limiting embodiments.

[0031] like Figure 1 As shown, the memory device 100 may include a substrate 102. The substrate 102 may include a well 104 having a first conductivity type. The memory device 100 may also include a contact element 110 arranged in the well 104, wherein the contact element 110 may include a first contact 112 having the first conductivity type. A diode layer 122 may be arranged in the well 104 and may have a second conductivity type opposite to the first conductivity type. A dummy gate 130 may be configured to isolate the first contact 112 from the diode layer 122. The memory device 100 may also include a memory element 140 electrically connected to the diode layer 122.

[0032] In the memory device 100, the contact element 110 and the diode layer 122 may be arranged or formed in the substrate 102 in a FEOL (front end of line) process. For example, the first contact 112 of the contact element 110 and the diode layer 122 may be formed as a source region or a drain region of a transistor. The dummy gate 130 may be formed as a gate region of a transistor, although the dummy gate 130 is not used as a gate terminal of the transistor, but is used to separate the diode layer 122 from the contact element 110. As used herein, "separation" means isolating the mentioned components. Therefore, a simple and compact diode formed by the diode layer 122 and compatible with a complementary metal oxide semiconductor (CMOS) process may be configured as a selector for the operation of the memory element 140. In addition, the dummy gate 130 may provide a compact isolation structure having a smaller size than a conventional isolation structure such as STI (shallow trench isolation). In a non-limiting example, the dummy gate length may be in a range of approximately 10 nm to 40 nm, which is less than the length of the STI, which may be in a range of approximately 40 nm to approximately 80 nm.

[0033] In some non-limiting embodiments, the first conductivity type may be an N-type and the second conductivity type may be a P-type. In other words, the well 104 may include an N-type dopant and may be referred to as an N-well. The first contact 112 may include an N-type dopant and may be referred to as an n+ contact. The diode layer 122 may include a P-type dopant and may be referred to as a p+ diode layer. The doping concentration of the first contact 112 and the doping concentration of the diode layer 122 may be higher than the doping concentration of the well 104. In a non-limiting embodiment, the doping concentration of the well 104 may be about 1×10 16 cm -3 To about 1×10 17 cm -3 The doping concentration of the first contact 112 and the doping concentration of the diode layer 122 may be within a range of about 1×10 18 cm -3 To about 1×10 20 cm -3 It should be noted that these doping concentration ranges of the well 104, the first contact 112, and the diode layer 122 are only non-limiting examples. It should be understood that any suitable doping concentration for a well in a semiconductor process can be applied to the well 104, and any suitable doping concentration for a source region and a drain region in a semiconductor process can be applied to the first contact 112 and the diode layer 122. In an alternative non-limiting embodiment, the first conductivity type can be a P type and the second conductivity type can be an N type. Therefore, the well 104, the first contact 112, and the diode layer 122 can be a P well 104, a p+ contact 112, and an n+ diode layer 122, respectively.

[0034] The substrate 102 may include a silicon substrate, a SOI (Silicon On Insulator) substrate, a germanium substrate, or any other suitable type of semiconductor substrate. Therefore, the well 104 , the first contact 112 , and the diode layer 122 may be doped regions formed in the substrate 102 .

[0035] According to various non-limiting embodiments, at least a portion of well 104 (e.g., a portion of well 104 adjacent to diode layer 122) and diode layer 122 may form diode 120. Thus, the portion of diode layer 122 and well 104 having opposite conductivity types to each other may form PN diode 120.

[0036] In an exemplary embodiment where diode layer 122 is a p+ diode layer, memory element 140 may be connected to the anode of the p+ diode layer, i.e., PN diode 120, such that diode 120 is configured to allow current to flow in a single direction from memory element 140 to diode 120. In an alternative embodiment where diode layer 122 is an n+ diode layer, memory element 140 may be connected to the cathode of PN diode 120, such that diode 120 is configured to allow current to flow in a single direction from diode 120 to memory element 140. Thus, diode 120 may be a selector configured for unipolar operation of memory element 140, as will be described below with reference to Figure 6 and Figure 7 Detailed description.

[0037] According to various non-limiting embodiments, the memory device 100 may include a channel layer having a second conductivity type (eg, Figure 2 ). The channel layer may be arranged in the well 104. The memory device 100 may include an additional diode layer (eg, Figure 2 ), wherein at least a portion of the channel layer and the further diode layer can form a further diode. In other words, the memory element 140 can also be connected to a further diode layer having a conductivity type opposite to that of the diode layer 122, so that the further diode can be configured to allow current to flow in a direction opposite to that allowed by the diode 120. Thus, the diode 120 and the further diode can be provided as two selectors configured for bipolar operation of the memory element 140, as described below with reference to Figure 2 , Figures 3A-3C and Figure 4 Detailed description.

[0038] In various non-limiting embodiments where the memory device 100 includes an additional diode, the memory device may also include an isolation element (eg, Figure 2 The isolation element may be arranged between the diode layer 122 and the further diode layer, and the isolation well may have the second conductivity type.

[0039] In various non-limiting embodiments where the memory device 100 includes an additional diode, the contact element 110 may also include a second contact (eg, Figure 2 ) and a third contact (as shown) arranged in the well 104 Figure 2 ). The second contact may have the second conductivity type, and the third contact may have the first conductivity type. The dummy gate 130 may be configured to isolate the second contact from the additional diode layer.

[0040] The dummy gate 130 may include a gate dielectric layer, a gate layer disposed above the gate dielectric layer, and an insulating spacer surrounding the gate dielectric layer and the gate layer, as described in detail below in FIG. 3. The gate dielectric layer may include a dielectric material, such as an oxide material, such as silicon oxide. The gate layer may include polysilicon or a metal, such as Al, TaN, or TiN. The insulating spacer may include an insulating material, such as silicon oxide or silicon nitride, or a combination thereof.

[0041] The dummy gate 130 may be configured to separate or isolate the diode 120 from the contact element 110. In an exemplary non-limiting embodiment, no voltage is applied to the dummy gate 130, so that the dummy gate 130 does not serve as a gate terminal of the transistor. The dummy gate 130 can be easily formed in a CMOS process without additional steps or processes, while providing a more compact structure than the STI structure. In an alternative non-limiting embodiment, the dummy gate 130 may be biased to reduce sneak current. Exemplarily, in a memory array including a plurality of memory devices 100, a sneak current may flow through an unselected memory device through a selected word line and a selected bit line. In order to reduce or eliminate the sneak current, a semi-forward bias may be provided to the dummy gate 130 positioned along the current path of the selected memory device to help form a channel under the dummy gate, while a semi-reverse bias is applied to the dummy gate 130 not positioned along the current path of the selected memory device to ensure that the channel under the dummy gate is closed. Therefore, current can only pass through the selected memory device to prevent the sneak current effect.

[0042] The contact element 110 may be electrically connected to a first signal line (eg, Figure 2 and Fig.12F ), for example, a bit line (BL). The memory element 140 may be electrically connected to a second signal line (eg, Figure 2 and Fig.12F ), such as a word line (WL). In an alternative non-limiting embodiment, the first signal line may be a word line and the second signal line may be a bit line.

[0043] When a predetermined bias is applied to the bit line and the word line, the well 104 can be configured to electrically connect the diode 120 to the first signal line through the contact element 110, and the well 104 can also be used as a part of the first signal line. Therefore, the memory element 140 and the diode 120 can be electrically connected in series between the bit line and the word line, so that the predetermined bias can be applied to the memory element 140 and the diode 120 through the bit line and the word line for selection and operation of the memory element 140.

[0044] The memory element 140 may be a resistive memory, such as a resistive random access memory (ReRAM) or a phase change random access memory (PCRAM). The memory element 140 may include an oxide layer or a resistive dielectric layer between two electrodes.

[0045] As described below in various non-limiting embodiments, the memory device 100 may be used as a unit cell or bit cell of a memory array.

[0046] Figure 2 A perspective view of a memory array 200 is shown in accordance with various non-limiting embodiments. Figure 3A 1 shows a diagram of a circuit along line A-A' according to various non-limiting embodiments. Figure 2 2 is a cross-sectional view of a memory array 200. Figure 3B 1 shows a diagram of a circuit along line B-B' according to various non-limiting embodiments. Figure 2 2 is a cross-sectional view of a memory array 200. Figure 3C shows a diagram along line C-C' according to various non-limiting embodiments. Figure 2 2 is a cross-sectional view of a memory array 200. The memory array 200 may include Figure 1 The memory device 100 is similar to multiple memory devices, and thus like features are labeled with like reference numerals. Figure 1 The various embodiments described are similar to Figure 2 as well as Figures 3A-3C of the memory array 200 is valid, and vice versa.

[0047] Similar to the memory device 100, the memory array 200 may include a substrate 102 having a well 104, the well 104 having a first conductivity type. The memory array 200 may also include a plurality of columns including a plurality of memory cells 250 arranged in a matrix form, wherein the plurality of columns include a first column 251 memory cell and a second column 253 memory cell. In other words, the plurality of memory cells 250 may be arranged at the intersection of the rows and columns of the matrix. The memory cell 250 may also be referred to as a unit cell or a bit cell of the memory array 200.

[0048] Each memory cell 250 in the memory array 200 may include a diode layer 122 disposed in the well 104 , wherein the diode layer 122 has a second conductivity type opposite to the first conductivity type. Each memory cell 250 may also include a memory element 140 electrically connected to the diode layer 122 .

[0049] Each memory element 140 may be a resistive memory, such as a resistive random access memory (ReRAM) or a phase change random access memory (PCRAM). The memory element 140 may include an oxide layer or a resistive dielectric layer between two electrodes.

[0050] According to various non-limiting embodiments, at least a portion of the well 104 (e.g., a portion of the well 104 adjacent to the corresponding diode layer 122) and the corresponding diode layer 122 may form a diode 120 for each memory cell 250. Therefore, the corresponding portions of the well 104 and the corresponding diode layer 122 having opposite conductivity types to each other may thereby form a corresponding PN diode 120 for each memory cell 250.

[0051] exist Figure 2 In various non-limiting embodiments, each memory cell 250 in the memory array 200 may further include a channel layer 206 having a second conductivity type. The channel layer 206 may be arranged in the well 104. Each memory cell 250 may further include an additional diode layer 222 arranged in the channel layer 206, wherein the additional diode layer 222 has a first conductivity type and is electrically connected to the corresponding memory element 140. Figure 2 As shown, the memory element 140 may be electrically connected to the further diode layer 222 via corresponding interconnects 242 and metal layers 244 .

[0052] At least a portion of the channel layer 206 (e.g. at least a portion of the channel layer 206 adjacent to the further diode layer 222) and the further diode layer 222 may form a further diode 220 for each memory cell 250. A portion of the channel layer 206 and the further diode layer 222 have opposite conductivity types and thereby form a further PN diode 220.

[0053] In other words, each memory element 140 may be connected not only to the diode layer 122 of the corresponding diode 120, but also to the further diode layer 222 (whose conductivity type is opposite to that of the diode layer 122) of the corresponding further diode 220, such as Figure 3C Thus, the further diode 220 may be configured to allow current to flow in a direction opposite to that allowed by the diode 120. Thus, the diode 120 and the further diode 220 may be provided as two selectors configured for bipolar operation of the memory element 140, as described below with reference to Figure 4 Detailed description.

[0054] exist Figure 2In various non-limiting embodiments, the well 104 may include a portion located at the region of the diode 120 and a portion located at the region of the further diode 220. In alternative non-limiting embodiments, the well 104 may include a deep well located below the channel layer 206 (e.g., as described below in Fig. 11B ), where the deep well may have the same conductivity type as well 104. In a non-limiting embodiment where well 104 is an N-well, the deep well may be a deep N-well (DNW). In other words, well 104 may include a portion located at a region where diode 120 is to be formed, and may include a deep well located at a region where additional diode 220 is to be formed.

[0055] like Figure 2 and Figure 3C As shown, the memory array 200 may include a plurality of isolation elements 260 arranged in columns in the substrate 102 and corresponding isolation wells 262 located below the corresponding isolation elements 260. The corresponding isolation elements 260 may be arranged between the corresponding diode layer 122 and the corresponding additional diode layer 222 in each column of memory cells so as to isolate the diode 120 in each memory cell 250 from the additional diode 220 and to isolate the memory cells 250 in the same column of memory cells from each other. In other words, as shown in FIG. Figure 3C As shown in the non-limiting example, a Figure 2 The line CC' of FIG. 1 is a first memory cell 250a and a second memory cell 250b in the same column, wherein the first memory cell 250a and the second memory cell 250b are adjacent memory cells with an isolation element 260 arranged therebetween. The isolation element 260 may be configured to isolate the diode 120a, 120b in each memory cell 250a, 250b from the other diodes 220a, 220b. The isolation element 260 may also be configured to isolate the diode 120b of the second memory cell 250b from the other diode 220a of the first memory cell 250a, such as Figure 3C As shown. The isolation well 262 may be arranged to separate and isolate a portion of the well layer 104 located below the diodes 120a, 120b from a portion of the well layer 104 located below another diode 220a, 220b. In other words, the isolation well 262 may be configured to isolate a dual channel disposed within each memory cell 250a, 250b, wherein the dual channel includes a first channel formed in the portion of the well layer 104 located below the diodes 120a, 120b and a second channel formed in the portion of the well layer 104 located below another diode 220a, 220b.

[0056] The isolation element 260 may include an STI (shallow trench isolation) extending into the substrate 102. The isolation well 262 may further extend from the bottom of the isolation element 260 into the substrate 102. The isolation well 262 may have a second conductivity type. In a non-limiting embodiment where the well 104 is an N-well, the isolation well 262 may be a P-well, which together with the isolation element 260 may be configured to isolate the diode 120 from an adjacent additional diode 220 arranged in the well 104.

[0057] The memory array 200 may include a contact element column 111 including contact elements 110 arranged in a well 104, wherein each contact element 110 may include a first contact 112 having a first conductivity type. Figure 2 In the non-limiting embodiment shown, the contact element columns 111 may be arranged adjacent to or in parallel with the first column 251 of memory cells 250. Each contact element 110 may be arranged adjacent to a corresponding memory cell in the first column 251 of memory cells 250, such as Figure 2 and Figure 3A shown.

[0058] The contact element column 111 may further include a plurality of second contacts 214 disposed in the channel layer 206 and a plurality of third contacts 216 disposed in the well 104, wherein the plurality of second contacts 214 have the second conductivity type, and the plurality of third contacts 216 have the first conductivity type. Figure 2 and Figure 3B In the non-limiting embodiment shown, each contact element 110 may further include a second contact 214 disposed in the channel layer 206 and a third contact 216 disposed in the well 104 .

[0059] In various non-limiting embodiments, the above reference Figure 1 The memory device 100 described may include Figure 3B The structure shown includes an additional diode 220, a second contact 214 and a third contact 216, as Figure 1 An alternative or supplement to the structure shown includes a diode 120 and a first contact 112 .

[0060] In the memory array 200, the columns 111 of contact elements 110 may be arranged close to or in parallel with the first column 251 of memory cells 250, and each contact element 110 may be arranged close to a memory cell 250 in the first column 251 of memory cells. Figure 2 Only one memory cell 250 of each column 251, 253 of memory cells is shown, therefore, Figure 2Only one contact element 110 is shown including a first contact 112, a second contact 214, and a third contact 216. It should be understood that in various non-limiting embodiments in which the memory array 200 includes a plurality of memory cells 250 in memory cell columns 251, 253, the plurality of contact elements 110 may be arranged in columns to form a contact element column 111, wherein each contact element 110 is arranged proximate to a corresponding memory cell 250 in the first column 251 of memory cells.

[0061] In various non-limiting embodiments, the doping concentration of the second contact 214, the third contact 216, and the further diode layer 222 may be higher than the doping concentration of the channel layer 206 and the well 104. In a non-limiting embodiment, the doping concentration of the channel layer 206 and the well 104 may be about 1×10 16 cm -3 To about 1×10 17 cm -3 The doping concentration of the second contact 214, the third contact 216 and the further diode layer 222 may be approximately 1×10 18 cm -3 To about 1×10 20 cm -3 It should be noted that these doping concentration ranges for the channel layer 206, the well 104, the second contact 214, the third contact 216, and the further diode layer 222 are only non-limiting examples. It should be understood that any suitable doping concentration for the channel layer and the well in the semiconductor process can be applied to the channel layer 206 and the well 104, and any suitable doping concentration for the source region and the drain region in the semiconductor process can be applied to the second contact 214, the third contact 216, and the further diode layer 222.

[0062] In an exemplary non-limiting embodiment where the first conductivity type is N-type, well 104 can be an N-well and channel layer 206 can be a P-channel. First contact 112 can be an n+ contact and diode layer 122 can be a p+ diode layer. Similarly, second contact 214 can be a p+ contact, third contact 216 can be an n+ contact, and additional diode layer 222 can be an n+ diode layer.

[0063] like Figure 2 As shown, each contact element 110 may include a first contact 112 and a second contact 214, wherein the first contact 112 is configured to be electrically connected to a corresponding diode 120 through the well 104, and the second contact 214 is configured to be electrically connected to a corresponding additional diode 220 through the channel layer 206. Figure 3BAs shown, the second contact 214 can be electrically connected to the third contact 216. The second contact 214 and the third contact 216 can also be electrically connected to the first contact 112, as shown in FIG. Figure 2 The three terminals 112 , 214 , and 216 are configured to be at the same bias to ensure that the well layer 104 under the channel layer 206 and the well layer 104 under the first contact 112 have the same bias so that a PN diode is not formed between the channel layer 206 and the well layer 104 .

[0064] The isolation element 260 may extend to the region of the well 104 in which the contact element 110 is arranged to separate the first contact 112 from the second contact 214 and the third contact 216, as shown in FIG. Figure 2 shown.

[0065] The memory array 200 may include a dummy gate 130 configured to isolate the contact element column 111 from the diode layer 122 of each memory cell 250 in the first column 251 of memory cells. In various non-limiting embodiments, the dummy gate 130 may be disposed over a space between the first contact 112 of the contact element column 111 and the diode layer 122 of the first column 251 of memory cells 250 to separate or isolate the first contact 112 of the column from the diode layer 122 of an adjacent column. Figure 2 In the non-limiting embodiment shown, the dummy gate 130 may also be arranged over the space between the second contacts 214 of the contact element column 111 and the additional diode layer 222 in the first column 251 of the memory cells 250. Thus, the dummy gate 130 may be configured to isolate the plurality of second contacts 214 in the contact element column 111 from the additional diode layer 222 in the first column 251 of the memory cells.

[0066] The memory array 200 may also include an additional dummy gate 230 configured to isolate the diode layer 122 of the memory cells in the first column 251 of memory cells from the diode layer 122 of the memory cells in the second column 253 of memory cells. In various non-limiting embodiments, the additional dummy gate 230 may be arranged above the corresponding spaces between the diode layers 122 in the memory cells 250 in adjacent columns 251, 253. The additional dummy gate 230 may also be arranged above the corresponding spaces between the additional diode layers 222 in the memory cells 250 in adjacent columns 251, 253. In other words, the additional dummy gate 230 may be arranged to separate or isolate the memory cells 250 in adjacent columns 251, 253. Although Figure 3A and Figure 3BOnly one further dummy gate 230 is shown arranged between two columns 251 , 253 of memory cells 250 , but it should be understood that more than one further dummy gate 230 may be included when more than two columns of memory cells 250 are included in the memory array 200 .

[0067] like Figure 3A As shown, the dummy gate 130 and the additional dummy gate 230 may each include a gate dielectric layer 132, a gate layer 134 disposed above the gate dielectric layer 132, and an insulating spacer 136 surrounding the gate dielectric layer 132 and the gate layer 134. The gate dielectric layer 132 may be disposed above the well 104 and may include a dielectric material, such as an oxide material, such as silicon oxide. The gate layer 134 may include polysilicon or a metal, such as Al, TaN, or TiN. The insulating spacer 136 may be disposed above the first contact 112 and the diode layer 122 and may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. In a non-limiting embodiment, the insulating spacer 136 may include an inner spacer 137 and an outer spacer 138 at least partially surrounding the inner spacer 137. In a non-limiting example, the inner spacer 137 may include silicon oxide, and the outer spacer 138 may include silicon nitride.

[0068] The dummy gate 130 may be configured to separate or isolate the corresponding contact element 110 in the contact element column 111 from the corresponding diode 120 in the first column 251 memory cell. The additional dummy gate 230 may be configured to separate or isolate the diode 120 in the adjacent columns 251, 253 memory cells. In other words, the additional dummy gate 230 may isolate or separate one or more diodes in the first column 251 memory cell from one or more diodes in the second column 253 memory cell. In an exemplary non-limiting embodiment, no voltage is applied to the dummy gate 130 and the additional dummy gate 230, so that the dummy gate 130 and the additional dummy gate 230 do not serve as the gate terminal of the transistor. The dummy gate 130 and the additional dummy gate 230 can be easily formed in a CMOS process without additional steps or processes, while providing a more compact structure than the STI structure. In an alternative non-limiting embodiment, the dummy gate 130 and the additional dummy gate 230 may be biased to reduce sneak current that may flow through the unselected memory cell 250 through the selected word line and the selected bit line. To reduce or eliminate the sneak current, the dummy gate 130 and / or the additional dummy gate 230 located along the current path of the selected memory cell 250 may be provided with a semi-forward bias to help form a channel under the corresponding dummy gate and / or the corresponding additional dummy gate 230, while the additional dummy gate 230 not located along the current path of the selected memory cell may be provided with a semi-reverse bias to ensure that the channel under the corresponding additional dummy gate is closed. Thus, current can only pass through the selected memory cell to prevent the sneak current effect.

[0069] like Figure 2 and Figures 3A-3C As shown, each contact element 110 can be electrically connected to a corresponding first signal line 272, such as a bit line (BL). Each column of memory elements 140 can be electrically connected to a corresponding second signal line 274, such as a word line (WL). For simplicity, in the following description, the first signal line can be a bit line, and the second signal line can be a word line. However, it should be understood that in alternative non-limiting embodiments, the first signal line 274 can be a word line, and the second signal line 276 can be a bit line.

[0070] because Figure 2 Only one row of memory cells 250 is shown in FIG. 2 , and thus only one bit line 272 is shown for applying voltage to the row of memory cells 250 through the contact elements 110. It should be understood that more than one bit line 272 may be included in the memory array 200.

[0071] exist Figure 3C In the non-limiting embodiment shown, the Figure 2The memory cells 250a, 250b in the same column are connected to the same word line 274 by electrically connecting one terminal of the corresponding memory element 140 to the word line 274. The other terminal of the corresponding memory element 140 can be electrically connected to the corresponding diode layer 122 and the corresponding further diode layer 222 of the corresponding memory cell 250.

[0072] When a predetermined bias is applied to the selected bit line 272 and the selected word line 274, the memory cell 250 connected between the selected bit line and the selected word line may be selected and operated accordingly.

[0073] Figure 4 Shown are representations according to various non-limiting embodiments Figure 2 An equivalent circuit 400 of the memory array 200 is shown.

[0074] according to Figure 2 In the non-limiting embodiment described in , each memory element 140 may be connected not only to the diode layer 122 of the corresponding diode 120, but also to the further diode layer 222 (whose conductivity type is opposite to that of the diode layer 122) of the corresponding further diode 220, such as Figure 3C Thus, the additional diode 220 may be configured to allow current to flow in a direction opposite to that allowed by the diode 120 .

[0075] exist Figure 4 In each memory cell 250 shown, the memory element 140 is electrically connected to both the diode 120 and the further diode 220. In an exemplary embodiment where the respective diode layer 122 is a p+ diode layer and the respective further diode layer 222 is an n+ diode layer, the respective memory element 140 may be connected to the anode of the respective diode 120 and the cathode of the respective further diode 220, so that the diode 120 and the further diode 220 may be configured to allow the respective current to flow in opposite directions. Thus, the diode 120 and the further diode 220 may be provided as two selectors configured for bipolar operation of the memory element 140.

[0076] like Figure 4As shown, the diodes 120 and the additional diodes 220 in the memory cells 250 of the corresponding rows may be electrically connected to the corresponding bit lines 272 (BL1, BL2, BL3, ...) through the corresponding contact elements 110. The memory elements 140 of the corresponding columns in the memory array 200 may be electrically connected to the corresponding word lines 274 (WL1, WL2, WL3, ...). When a predetermined bias is applied to the selected bit line and the selected word line, the memory cell 250 connected between the selected bit line and the selected word line may be selected for the corresponding operation.

[0077] Table 1 below shows the application of Figure 4 Various bias conditions on the circuit 400.

[0078] Table 1

[0079]

[0080] To program a memory cell (e.g., memory cell 250 connected between WL2 and BL2), signal lines WL2 and BL2 may be selected signal lines, and the remaining signal lines WL1, WL3, BL1, BL3 may be unselected signal lines. 设置 A voltage of 0V is applied to the selected WL2, and a voltage of 0V may be applied to the selected BL2, so that the diode 120 in the selected memory cell 250 allows current to flow through the current path 470 to set the selected memory cell 250. In a non-limiting example, V 设置 can be about 2.5V. 禁止 A voltage (if the bias V is set to 3V, the voltage is, for example, 1 / 2V, such as 1.5V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0081] To erase the selected memory cell 250 connected between WL2 and BL2, V 重置 A voltage of 0V may be applied to the selected BL2, and a voltage of 0V may be applied to the selected WL2, so that current may flow from the other diode 220 in the selected memory cell 250 to the memory element 140 in the opposite direction to the current path 470 to reset the selected memory cell 250. In a non-limiting example, V 重置 can be about 1.7V. 禁止 A voltage (eg, 1 / 2 V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0082] In a non-limiting example, the voltage of the memory element 140 in the selected memory cell may be approximately 1.3 V in a set (SET) operation and may be approximately 0.7 V in a reset (RESET) operation. The resistance of the memory element 140 may be approximately 10 kilo-ohms for an LRS (low resistance state) of the memory element 140 and may be approximately 100 kilo-ohms for an HRS (high resistance state) of the memory element 140.

[0083] According to Table 1, to read the selected memory cell 250 connected between WL2 and BL2, V 读取 A voltage of 0V may be applied to the selected WL2, and a voltage of 0V may be applied to the selected BL2, so that current flows through the current path 470 to read the selected memory cell 250. 禁止 A voltage (eg, 1 / 2 V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0084] Therefore, the above Figure 2 , Figures 3A-3C and Figure 4 The memory array 200 shown in the non-limiting embodiment provides a high-density 2S1R (dual selector and one resistor) crosspoint bipolar memory structure. Conventional CMOS technology can be used for the 2S1R crosspoint memory array 200 without the need for additional masks. The diode 120 and the additional diode 220 as selectors for the corresponding memory element 140 can be formed in the source / drain region of the transistor by injection (for example, in the FEOL (front end of line) process). These CMOS-compatible FEOL diode selectors are compact and not limited by thermal budget. In addition, these diodes can be combined or arranged in a simple manner to achieve bipolar operation of the memory element. The memory element 140 can be formed between metal layers, which are arranged above the diode 120 and the additional diode 220. The dummy gate 130 and the additional dummy gate 230 can be formed as the gate region of the transistor, although the dummy gate 130 and the additional dummy gate 230 are not used as the gate terminal of the transistor but separate the diode 120 and the additional diode 220. The dummy gate 130 and the additional dummy gate 230 further provide a compact isolation structure for isolating the memory cell 250. Compared with the conventional 1T1R (one transistor and one resistor) memory structure, the range of about 40F 2 to about 60F 2 Compared to the cell size of 18F, by using the dummy gate 130 and the additional dummy gate 230 for isolation, a range of about 18F can be achieved.2 to about 28F 2 The smaller primitive size. Figure 5 1 shows a perspective view of a memory array 500 according to various non-limiting embodiments. Figure 5 A cross-sectional view of the memory array 500 is similar to Figure 3A , and can refer accordingly Figure 3A Memory array 500 can be connected with Figure 2 The memory array 200 is similar and may include Figure 1 The memory device 100 is similar to multiple memory devices, and thus like features are labeled with like reference numerals. Figure 1-2 The various embodiments described are similar to Figure 5 of the memory array 500 is valid, and vice versa.

[0085] Similar to the memory device 100 and the memory array 200, the memory array 500 may include a substrate 102. The substrate 102 may include a well 104 having a first conductivity type. The memory array 500 may also include a plurality of columns including a plurality of memory cells 250 arranged in a matrix form, wherein the plurality of columns may include a first column 251 memory cell and a second column 253 memory cell. In other words, the plurality of memory cells 250 may be arranged at the intersection of the matrix. Such a memory array 500 may be referred to as a cross-point or cross-bar memory array. The memory cell 250 may also be referred to as a unit cell or a bit cell of the memory array 500.

[0086] Each memory cell 250 may include a diode layer 122 disposed in the well 104 , wherein the diode layer 122 has a second conductivity type opposite to the first conductivity type. Each memory cell 250 may also include a memory element 140 electrically connected to the diode layer 122 .

[0087] The memory array 500 may further include a contact element column 111 including contact elements 110 arranged in the well 104, wherein each contact element 110 may include a first contact 112 having a first conductivity type. Figure 5 In the non-limiting embodiment shown, the contact element columns 111 may be arranged close to or in parallel with the memory cells 250 of the first column 251. Each contact element 110 may be arranged close to a corresponding memory cell in the memory cells 250 of the first column 251, such as Figure 5 and Figure 3A shown.

[0088] The memory array 500 may include a dummy gate 130 configured to isolate the contact element column 111 from the diode layer 122 of each memory cell 250 in the first column 251 of memory cells. The dummy gate 130 may be arranged over a space between the first contact 112 and the diode layer 122 in the first column 251 of memory cells 250. In other words, the dummy gate 130 may be arranged to separate or isolate the first contact 112 of the column from the diode layer 122 of an adjacent column.

[0089] The memory array 500 may further include an additional dummy gate 230 configured to isolate the diode layer 122 of the memory cell 250 in the first column 251 memory cell from the diode layer 122 of the memory cell 250 in the second column 253 memory cell. The additional dummy gate 230 may be arranged above the corresponding space between the diode layer 122 in the first column 251 memory cell and the diode layer 122 in the second column 253 memory cell. In other words, the additional dummy gate 230 may be arranged to separate or isolate the memory cells 250 of adjacent columns 251, 253. Although Figure 5 and Figure 3A Only two columns of memory cells and only one additional dummy gate 230 arranged between the two columns of memory cells 250 are shown, but it should be understood that the memory array 500 may include more than two columns of memory cells, and when the memory array 500 includes more than two columns of memory cells 250, more than one additional dummy gate 230 may be included.

[0090] like Figure 5 As shown, the memory array 500 may further include a plurality of isolation elements 260 arranged in columns in the substrate 102, wherein the isolation elements 260 are configured to isolate the diode layers 122 of memory cells within the same column of memory cells. In other words, the isolation elements 260 may be arranged to separate or isolate the diode layers 122 in adjacent memory cells 250 within the same column. Figure 5 As shown, corresponding isolation elements 260 may also be arranged between adjacent first contacts 112. The isolation elements 260 may include STI (Shallow Trench Isolation) extending into the substrate 102.

[0091] Similar to the non-limiting embodiment described above, the first conductivity type may be an N-type and the second conductivity type may be a P-type. Thus, the well 104 may be an N-well, which may include a plurality of portions separated by the isolation element 260. The first contact 112 may be an n+ contact, and the diode layer 122 may be a p+ diode layer. The doping concentration of the first contact 112 and the doping concentration of the diode layer 122 may be higher than the doping concentration of the well 104. In a non-limiting embodiment, the doping concentration of the well 104 may be about 1×10 16 cm -3 To about 1×10 17 cm -3 The doping concentration of the first contact 112 and the doping concentration of the diode layer 122 may be within a range of about 1×10 18 cm -3 To about 1×10 20 cm -3 It should be noted that these doping concentration ranges for the well 104, the first contact 112, and the diode layer 122 are only non-limiting examples. It should be understood that any suitable doping concentration for a well in a semiconductor process can be applied to the well 104, and any suitable doping concentration for a source region and a drain region in a semiconductor process can be applied to the first contact 112 and the diode layer 122. In an alternative non-limiting embodiment, the first conductivity type can be a P-type and the second conductivity type can be an N-type.

[0092] The substrate 102 may include a silicon substrate, a SOI (Silicon On Insulator) substrate, a germanium substrate, or any other suitable type of semiconductor substrate. Therefore, the well 104 , the first contact 112 , and the diode layer 122 may be doped regions formed in the substrate 102 .

[0093] Each memory element 140 may be a resistive memory, such as a resistive random access memory (ReRAM) or a phase change random access memory (PCRAM). The memory element 140 may include an oxide layer or a resistive dielectric layer between two electrodes.

[0094] According to various non-limiting embodiments, at least a portion of the well 104 (e.g., a portion of the well 104 adjacent to the corresponding diode layer 122) and the corresponding diode layer 122 may form a diode 120 for each memory cell 250. Thus, the corresponding portions of the well 104 and the corresponding diode layer 122 having opposite conductivity types to each other may form a corresponding PN diode 120 for each memory cell 250.

[0095] Unlike memory array 200, memory cell 250 in memory array 500 includes only diode 120 but may not include additional diode 220 shown in memory array 200. Therefore, memory cell 250 in memory array 500 does not include channel layer 206 and additional diode layer 522 shown in memory array 200.

[0096] like Figure 3A As shown in the cross-sectional view of , the dummy gate 130 and the additional dummy gate 230 may each include a gate dielectric layer 132, a gate layer 134 arranged above the gate dielectric layer 132, and an insulating spacer 136 surrounding the gate dielectric layer 132 and the gate layer 134. The gate dielectric layer 132 may be arranged above the well 104 and may include a dielectric material, such as an oxide material, such as silicon oxide. The gate layer 134 may include polysilicon or a metal, such as Al, TaN, or TiN. The insulating spacer 136 may be arranged above the first contact 112 and the diode layer 122, and may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. In a non-limiting embodiment, the insulating spacer 136 may include an inner spacer 137 and an outer spacer 138 at least partially surrounding the inner spacer 137. In a non-limiting example, the inner spacer 137 may include silicon oxide, and the outer spacer 138 may include silicon nitride.

[0097] The dummy gate 130 may be configured to separate or isolate the corresponding contact element 110 in the contact element column 111 from the corresponding diode 120 in the first column 251 memory cell. The additional dummy gate 230 may be configured to separate or isolate the diode 120 in the memory cell of the adjacent column 251, 253. In other words, the additional dummy gate 230 may isolate or separate one or more diodes in the first column 251 memory cell from one or more diodes in the second column 253 memory cell. In an exemplary non-limiting embodiment, no voltage is applied to the dummy gate 130 and the additional dummy gate 230, so that the dummy gate 130 and the additional dummy gate 230 do not serve as the gate terminal of the transistor. The dummy gate 130 and the additional dummy gate 230 can be easily formed in a CMOS process without additional steps or processes, while providing a more compact structure than the STI structure. In an alternative non-limiting embodiment, the dummy gate 130 and the additional dummy gate 230 may be biased to reduce sneak current that may flow through the selected word line and the selected bit line through the unselected memory cell 250. To reduce or eliminate the sneak current, the dummy gate 130 and / or the additional dummy gate 230 positioned along the current path of the selected memory cell 250 may be provided with a semi-forward bias to help form a channel under the corresponding dummy gate and / or the corresponding additional dummy gate 230, while the additional dummy gate 230 not positioned along the current path of the selected memory cell is semi-reverse biased to ensure that the channel under the corresponding additional dummy gate is closed. Therefore, current can only pass through the selected memory cell to prevent the sneak current effect.

[0098] Each contact element 110 may be electrically connected to a corresponding first signal line (eg, Fig.12F Each column of memory elements 140 may be electrically connected to a corresponding second signal line (eg, Fig.12F ), such as a word line (WL). In an alternative non-limiting embodiment, the first signal line may be a word line and the second signal line may be a bit line.

[0099] When a predetermined bias is applied to a selected bit line and a selected word line, a memory cell 250 connected between the selected bit line and the selected word line may be selected and operated accordingly, as described below with reference to Figure 6 and Figure 7 described.

[0100] Figure 6 and Figure 7 Shown are representations according to various non-limiting embodiments Figure 5 Equivalent circuits 600, 700 of the memory array 500.

[0101] exist Figure 6In a non-limiting embodiment in which the corresponding diode layer 122 is a p+ diode layer, the corresponding memory element 140 can be connected to the p+ diode layer, i.e., the anode of the corresponding PN diode 120, so that each diode 120 is configured to allow current to flow in a single direction from the corresponding memory element 140 to the corresponding diode 120.

[0102] exist Figure 7 In an alternative non-limiting embodiment in which the respective diode layer 122 is an n+ diode layer, the respective memory element 140 may be connected to the cathode of the respective PN diode 120 such that each diode 120 is configured to allow current to flow in a single direction from the respective diode 120 to the respective memory element 140. Thus, the respective diode 120 may be a selector configured for unipolar operation of the respective memory element 140.

[0103] Arrange in Figure 5 The diodes 120 in each row of the memory array 500 may be electrically connected to corresponding bit lines (BL1, BL2, BL3, ...) through corresponding contact elements 110, and Figure 2 Each column 251, 253 of the memory element 140 in the memory array 200 may be electrically connected to a corresponding word line (WL1, WL2, WL3, ...) at the other terminal of the memory element 140. When a predetermined bias is applied to a selected bit line and a selected word line, a memory cell 250 connected between the selected bit line and the selected word line may be selected for a corresponding operation.

[0104] Table 2 below shows the various non-limiting embodiments that are applied to Figure 6 and Figure 7 Various bias conditions on circuits 600, 700.

[0105] Table 2

[0106]

[0107] To program a memory cell (e.g., memory cell 250 connected between WL2 and BL2), signal lines WL2 and BL2 may be selected signal lines, and the remaining signal lines WL1, WL3, BL1, BL3 may be unselected signal lines. 设置 A voltage of 0V may be applied to the selected WL2, and a voltage of 0V may be applied to the selected BL2, so that current flows through the current paths 670, 770 to set the selected memory cell 250. In a non-limiting example, in Figure 6 In the embodiment, V 设置 can be approximately 2.5V, and Figure 7 In the embodiment, V 设置 can be approximately -2.5V. 禁止 A voltage (if the bias V is set to 3V, the voltage is, for example, 1 / 2V, such as 1.5V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0108] Similarly, to erase the selected memory cell 250 connected between WL2 and BL2, V 重置 A voltage of 0V may be applied to the selected WL2, and a voltage of 0V may be applied to the selected BL2, so that current flows through the current paths 670, 770 to reset the selected memory cell 250. In a non-limiting example, in Figure 6 In the embodiment, V 重置 can be approximately 1.7V, and Figure 7 In the embodiment, V 重置 can be approximately -1.7V. 禁止 A voltage (eg, 1 / 2 V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0109] Similarly, to read the selected memory cell 250 connected between WL2 and BL2, V 读取 A voltage of 0V may be applied to the selected WL2, and a voltage of 0V may be applied to the selected BL2, so that current flows through the current paths 670, 770 to read the selected memory cell 250. 禁止 A voltage (eg, 1 / 2 V) is applied to the unselected signal lines WL1, WL3, BL1, BL3 to ensure that the memory cells 250 connected to these unselected signal lines are not selected.

[0110] Therefore, the above Figure 5The memory array 500 shown in the non-limiting embodiment provides a high-density 1S1R (one selector and one resistor) cross-point unipolar memory structure. Conventional CMOS technology can be used for the 1S1R cross-point memory array 500 without the need for additional masks. The diode 120 as a selector for the corresponding memory element can be formed in the source / drain region of the transistor by injection (for example, in a FEOL (front-end process) process). These CMOS-compatible FEOL diode selectors are compact and not limited by thermal budgets. In addition, these diodes can be combined or arranged in a simple manner to achieve unipolar operation of the memory element. The memory element 140 can be formed between metal layers that are arranged above the diode 120. The dummy gate 130 and the additional dummy gate 230 can be formed as the gate region of the transistor, although the dummy gate 130 and the additional dummy gate 230 are not used as the gate terminal of the transistor but separate the diode 120. The dummy gate 130 and the additional dummy gate 230 further provide a compact isolation structure for isolating the memory cell 250. Compared with the conventional 1T1R (one transistor and one resistor) memory structure, the range is about 40F. 2 to about 60F 2 Compared to the cell size of 8F, by using the dummy gate 130 and the additional dummy gate 230 for isolation, a range of about 8F can be achieved. 2 to about 27F 2 The smaller primitive size.

[0111] Figure 8 800 illustrating a method of forming a memory device according to various non-limiting embodiments. The method may be used to form the memory device 100 described in the various non-limiting embodiments above. The various non-limiting embodiments described in the context of the memory device 100 are similarly directed to Figure 8 The method is valid and vice versa.

[0112] At 802, a substrate may be provided. The substrate may include a well having a first conductivity type.

[0113] At 804, a contact element may be formed in the well. The contact element may include a first contact having a first conductivity type.

[0114] A diode layer can be formed in the well at 806. The diode layer can have a second conductivity type opposite to the first conductivity type.

[0115] At 808 , a dummy gate may be formed to isolate the first contact from the diode layer.

[0116] At 810, a memory element can be electrically connected to the diode layer.

[0117] It should be understood that according to various embodiments, the method may not be performed in the order of 802 - 810 . For example, according to a non-limiting embodiment, forming a dummy gate at 808 may be performed before forming a diode layer at 806 .

[0118] According to various non-limiting embodiments, the method may further include forming a channel layer in the well, wherein the channel layer may have the second conductivity type.

[0119] According to various non-limiting embodiments, the method may further include forming an additional diode layer in the channel layer and electrically connecting the additional diode layer to the memory element. The additional diode layer may have a first conductivity type. At least a portion of the channel layer and the additional diode layer may form an additional diode.

[0120] According to various non-limiting embodiments, the method may further include forming a second contact in the channel layer and forming a third contact in the well. The second contact may have the second conductivity type, and the third contact may have the first conductivity type.

[0121] According to various non-limiting embodiments, the method may further include forming an isolation element in the substrate. The isolation element may be arranged between the diode layer and the other diode layer. In a non-limiting example, the isolation element may include an STI (shallow trench isolation) extending into the substrate. The method may further include forming an isolation well below the isolation element, wherein the isolation well may have a second conductivity type. The isolation well may further extend from the bottom of the isolation element into the substrate.

[0122] exist Figure 8 In the method, the contact element and the diode layer can be formed similarly to the source region and the drain region of the transistor, and the dummy gate can be formed similarly to the gate region of the transistor. Therefore, the process of forming the contact element, the diode layer and the dummy gate can be similar to the process of forming the transistor, and is therefore compatible with the CMOS process.

[0123] Fig. 9 A flowchart 900 illustrating a method of forming a memory array according to various non-limiting embodiments is shown. The method may be used to form the memory arrays 200, 500 described in the various non-limiting embodiments above. The various non-limiting embodiments described in the context of the memory arrays 200, 500 are similarly described for Fig. 9 The method is valid and vice versa.

[0124] At 902, a substrate may be provided, wherein the substrate includes a well having a first conductivity type.

[0125] At 904, a plurality of columns including a plurality of memory cells arranged in a matrix may be formed, wherein the plurality of columns include a first column of memory cells and a second column of memory cells. Each memory cell may include a diode layer arranged in a well and a memory element electrically connected to the diode layer. The diode layer may have a second conductivity type opposite to the first conductivity type.

[0126] At 906 , a column of contact elements including contact elements may be formed in the well, wherein each contact element includes a first contact having a first conductivity type.

[0127] At 908, a dummy gate can be formed to isolate the column of contact elements from the diode layer in each memory cell in the first column of memory cells.

[0128] At 910, additional dummy gates may be formed to isolate the diode layer in the first column of memory cells from the diode layer in the second column of memory cells.

[0129] It should be understood that according to various embodiments, the method may not be performed in the order of 902 - 910 . For example, according to a non-limiting embodiment, forming a dummy gate at 908 and forming an additional dummy gate at 910 may be performed before forming a contact element at 906 .

[0130] Forming each of the dummy gate and the additional dummy gates may include forming a gate dielectric layer, forming a gate layer over the gate dielectric layer, and forming insulating spacers surrounding the gate dielectric layer and the gate layer.

[0131] In various non-limiting embodiments, the method may further include forming a plurality of isolation elements in a column in the substrate. The isolation elements may be configured to isolate diode layers in memory cells within the same column of memory cells.

[0132] According to various non-limiting embodiments, the method may further include forming a channel layer in the well, wherein the channel layer may have a second conductivity type. The method may further include forming an additional diode layer in the channel layer and electrically connecting the additional diode layer to the memory element. The additional diode layer may have a first conductivity type. At least a portion of the channel layer and the additional diode layer may form an additional diode.

[0133] The method may also include forming a plurality of isolation elements in columns in the substrate and forming corresponding isolation wells below the corresponding isolation elements. The corresponding isolation elements may be arranged between the diodes in each column of memory cells and the other diodes. In a non-limiting example, the isolation element may include an STI extending into the substrate. The isolation well may have a second conductivity type. The isolation well may further extend from the bottom of the isolation element into the substrate.

[0134] According to various non-limiting embodiments, forming the column of contact elements may include forming a plurality of second contacts in the channel layer and forming a plurality of third contacts in the well. The second contacts may have the second conductivity type, and the third contacts may have the first conductivity type.

[0135] The dummy gate may be configured to isolate a plurality of second contacts in the column of contact elements from an additional diode layer in the first column of memory cells. In a non-limiting embodiment, the dummy gate may be arranged over a space between a second contact in the column of contact elements and an additional diode layer in the first column of memory cells. Additional dummy gates may be configured to isolate an additional diode layer in the first column of memory cells from an additional diode layer in the second column of memory cells. Additional dummy gates may be arranged over corresponding spaces between additional diode layers in memory cells of adjacent columns.

[0136] In various non-limiting embodiments, the method may further include electrically connecting each contact element to a corresponding first signal line, and electrically connecting each column of memory elements to a corresponding second signal line.

[0137] Various non-limiting embodiments of methods of forming the memory device 100 and memory arrays 200 , 500 are described in further detail below.

[0138] Figures 10A-10F Methods of forming a memory array according to various non-limiting embodiments are shown. Figures 10A-10F In the non-limiting embodiment of FIG. 1 , a method of forming a memory array 200 is shown. In the above memory array 200 and Fig. 9 The various non-limiting embodiments described in the context of the method are similarly Figures 10A-10F The method is valid and vice versa. It should be understood that Figures 10A-10F The method can be similarly used to form Figure 1 The memory device 100 includes a single memory cell of the memory array 200. In the above memory device 100 and Figure 8 The various non-limiting embodiments described in the context of the method are similarly Figures 10A-10F The method is valid and vice versa.

[0139] exist Fig. 10A In the embodiment of the present invention, a substrate 102 may be provided. The substrate 102 may include a silicon substrate, an SOI (silicon on insulator) substrate, a germanium substrate, or any other suitable type of semiconductor substrate. A plurality of isolation elements 260 may be formed in columns in the substrate 102. The isolation elements 260 may be formed as STI and may be similar to Figure 2 The structure is arranged in columns.

[0140] exist Fig. 10BIn the embodiment of the present invention, a well 104 having a first conductivity type may be formed in the substrate 102, for example by ion implantation. The well 104 may include one or more portions separated by isolation elements 260. A channel layer 206 having a second conductivity type may be formed in the well 104, for example in selected portions of the well 104 where additional diodes may be formed.

[0141] exist Fig. 10B In the process of , a plurality of isolation wells 262 can be formed under the corresponding isolation element 260, and can also be arranged in a column. The isolation well 262 can extend further from the bottom of the isolation element 260 into the substrate 102. The isolation well 262 can have a second conductivity type. In a non-limiting embodiment in which the well 104 is an N-well, the isolation well 262 can be a P-well, which together with the isolation element 260 can be configured to isolate the diode 120 from another adjacent diode 220 arranged in the well 104, as shown above Figure 2 shown.

[0142] exist Fig. 10C In the embodiment of the present invention, a dummy gate 130 and an additional dummy gate 230 may be formed above the well 104 and the channel layer 206. The dummy gate and the additional dummy gate 230 may each include a gate dielectric layer 132 disposed above the well 104, a gate layer 134 disposed above the gate dielectric layer 132, and an insulating spacer 136 surrounding the gate dielectric layer 132 and the gate layer 134. The gate dielectric layer 132 may include a dielectric material, such as an oxide material, such as silicon oxide. The gate layer 134 may include polysilicon or a metal, such as Al, TaN, or TiN. The insulating spacer 136 may be disposed above the well 104 and may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. In a non-limiting embodiment, the insulating spacer 136 may include an inner spacer 137 and an outer spacer 138 at least partially surrounding the inner spacer 137. In a non-limiting example, the inner spacer 137 may include silicon oxide, and the outer spacer 138 may include silicon nitride.

[0143] like Fig. 10C As shown, the isolation element 260 may extend in a first direction, while the dummy gate 130 and the additional dummy gate 230 may extend in a second direction perpendicular to the first direction. In this way, the isolation element 260 may be configured to isolate the diodes of the memory cells arranged along the second direction from the additional diodes, while the dummy gate 130 and the additional dummy gate 230 may be configured to isolate the memory cells arranged along the first direction.

[0144] exist Fig. 10D In the embodiment, a plurality of contact elements 110, a diode 120 and an additional diode 220 may be formed. Fig. 10DIn the non-limiting embodiment shown, only one contact element 110 corresponding to a single row of memory cells is shown. It should be understood that Figures 10A-10F The method can be used to form a memory array including a plurality of rows of memory cells and a plurality of contact elements corresponding thereto.

[0145] The formation of the contact element 110 may include forming a first contact 112 in the well 104. The formation of the contact element 110 may also include forming a second contact 214 in the channel layer 206 and forming a third contact 216 in the well 104. The first contact 112 and the third contact 216 may have a first conductivity type, and the second contact 214 may have a second conductivity type.

[0146] The formation of the diode 120 may include forming a plurality of diode layers 122 in the well 104. The diode layers 122 may have the second conductivity type. The formation of the further diode 220 may include forming a plurality of further diode layers 222 in the channel layer 206, wherein the further diode layers 222 have the first conductivity type.

[0147] In a non-limiting embodiment where the first conductivity type is N-type, the well 102 can be an N-well and the channel layer 206 can be a P-channel. The first contact 112, the second contact 214, and the third contact 216 can be formed as an n+ contact, a p+ contact, and an n+ contact, respectively. The diode layer 122 and the additional diode layer 222 can be formed as a p+ diode layer and an n+ diode layer, respectively. The corresponding contacts 112, 214, 216 and the corresponding diode layers 122, 222 can be formed as doped regions in the well 102 and the channel layer 206, for example, by ion implantation.

[0148] like Fig. 10D As shown, the first contact 112 and the second contact 214 may be spaced apart from the diode layer 122 and the further diode layer 222, so that the dummy gate 130 may be arranged over the space between the first contact 112 and the diode layer 122, and over the space between the second contact 214 and the further diode layer 222. Thus, the dummy gate 130 may be arranged to separate the contact element 110 from adjacent memory cells 250. The further dummy gate 230 may be arranged over the space between the diode layers 122 from adjacent columns, and over the space between the further diode layers 222 from adjacent columns. Thus, the further dummy gate 230 may be arranged to separate the memory cells 250 from adjacent columns.

[0149] The isolation element 260 may extend to a region of the well 104 in which the contact element 110 is arranged, so as to separate the first contact 112 from the second contact 214 and the third contact 216 .

[0150] exist Fig.10E In the embodiment, interconnect 242 may be formed over first contact 112, second contact 214, and third contact 216. A metal layer may also be formed over interconnect 242 to serve as a first signal line 272, such as a bit line or a word line. Interconnect 242 may also be formed over diode layer 122 and further diode layer 222, and a metal layer 244 may also be formed over interconnect 242 for electrical connection to a memory element, as shown below. Fig.10F shown.

[0151] In the contact element 110, the first contact 112 may be configured to be electrically connected to the corresponding diode 120 through the well 104. The second contact 214 may be configured to be electrically connected to the corresponding additional diode 220 through the channel layer 206. Fig.10E As shown, the second contact 214 may be electrically connected to the third contact 216. This is to ensure that the channel layer 206 and the well 104 having different conductivity types and in which the second contact 214 and the third contact 216 are respectively arranged are at the same bias so that no diode is formed therebetween.

[0152] exist Fig.10F In the embodiment, a plurality of memory elements 140 may be arranged or formed above a corresponding diode layer 122 and a corresponding additional diode layer 222, and may be electrically connected to the corresponding diode layer 122 and the corresponding additional diode layer 222 via one or more interconnects. Each memory element 140 may have one terminal connected to both a diode 120 and an additional diode 220, wherein the diode 120 and the additional diode 220 are electrically connected in parallel. Thus, a corresponding memory cell 250 including the memory element 140, the diode 120 and the additional diode 220 may be formed. Metal layers 274 may be formed on the corresponding memory elements 140, which may be used as second signal lines 274, such as word lines or bit lines. Thus, in Fig.10F The structure formed in can be a 2S1R memory array, similar to the above Figure 2 The memory array 200 described in .

[0153] By applying a predetermined voltage to the selected first signal line 272 and the selected second signal line 274, the corresponding diode 120 and the further diode 220 can be configured to select the memory element 140 for bipolar operation of the memory element 140, as described above with reference to Figure 4 described.

[0154] Additional interlayer dielectrics can be formed ( Fig.10F2 (not shown) to isolate the memory elements 140 from each other, and to isolate the interconnects 242, metal layers 244, and signal lines 272, 274 from each other. Conventional BEOL processes may also be performed to fabricate other interconnects and metal layers.

[0155] Figures 11A-11B A process of forming a memory array according to various non-limiting embodiments is shown.

[0156] Fig.11A Shown as Fig. 10B An alternative non-limiting embodiment of the non-limiting embodiment of . Fig.11A In a non-limiting alternative embodiment of , forming well 104 may include forming a deep well 1104 below channel layer 206, wherein deep well 1104 may have the same conductivity type as well 104. In a non-limiting embodiment where well 104 is an N-well, deep well 1104 may be a deep N-well (DNW). Well 104 may include a portion located at a region where diode 120 is to be formed, and may include a deep well 104 located at a region where additional diode 220 is to be formed (as shown below). Fig. 11B As shown), wherein the above-mentioned portion of the well 104 and the deep well 104 are separated via an isolation element 260. Fig. 10B The isolation well 262 in the non-limiting embodiment of Fig.11A In the non-limiting embodiment, may not exist.

[0157] Can be Fig.11A The structure obtained in is similarly executed Figures 10C-10F process to form Fig. 11B The memory array structure in Fig. 11B The memory array formed in may be a 2S1R memory array, similar to that in Fig.10F The memory array formed in FIG. 1 is similar to the memory array formed in FIG. 1 , but the difference is that the well 104 may include a portion located at the region of the diode 120 and may include a deep well 1104 located at the region of the further diode 220. Fig. 11B In the 2S1R memory array, the deep well 1104 can be used to separate the channel layer 206 (e.g., P-type channel) that can be used as a bit line connected to another diode 220 from the well layer 104 (e.g., N-well) that can be used as a bit line connected to the diode 120.

[0158] Figures 12A-12F Methods of forming a memory array according to various non-limiting embodiments are shown. Figures 12A-12F In the non-limiting embodiment of FIG. 5 , a method of forming a memory array 500 is shown. In the above memory array 500 and Fig. 9 The various non-limiting embodiments described in the context of the method are similarly Figures 12A-12FThe method is valid and vice versa. It should be understood that Figures 12A-12F The method can be similarly used to form Figure 1 The memory device 100 includes a single memory cell of the memory array 500. In the above memory device 100 and Figure 8 The various non-limiting embodiments described in the context of the method are similarly Figures 12A-12F The method is valid and vice versa.

[0159] exist Fig. 12A In the embodiment of the present invention, a substrate 102 may be provided. The substrate 102 may include a silicon substrate, an SOI (silicon on insulator) substrate, a germanium substrate, or any other suitable type of semiconductor substrate. A plurality of isolation elements 260 may be formed in columns in the substrate 102. The isolation elements 260 may be formed as STI and may be similar to Figure 5 Arrange in columns.

[0160] exist Fig. 12B In the embodiment of the present invention, a well 104 having a first conductivity type may be formed in the substrate 102, for example, by ion implantation. The well 104 may include one or more portions separated by isolation elements.

[0161] exist Fig. 12C In the embodiment of the present invention, a dummy gate 130 and an additional dummy gate 230 may be formed above the well 104. The dummy gate and the additional dummy gate 230 may each include a gate dielectric layer 132 disposed above the well 104, a gate layer 134 disposed above the gate dielectric layer 132, and an insulating spacer 136 surrounding the gate dielectric layer 132 and the gate layer 134. The gate dielectric layer 132 may include a dielectric material, such as an oxide material, such as silicon oxide. The gate layer 134 may include polysilicon or a metal, such as Al, TaN, or TiN. The insulating spacer 136 may be disposed above the well 104 and may include an insulating material, such as silicon oxide, silicon nitride, or a combination thereof. In a non-limiting embodiment, the insulating spacer 136 may include an inner spacer 137 and an outer spacer 138 at least partially surrounding the inner spacer 137. In a non-limiting example, the inner spacer 137 may include silicon oxide, and the outer spacer 138 may include silicon nitride.

[0162] The isolation element 260 may extend in a first direction, and the dummy gate 130 and the further dummy gate 230 may extend in a second direction perpendicular to the first direction. In other words, the dummy gate 130 and the further dummy gate 230 may intersect the isolation element 260, but not at the same surface level, such as Fig. 12CIn this way, the isolation element 260 may be configured to isolate the memory cells arranged along the second direction, while the dummy gate 130 and the further dummy gate 230 may be configured to isolate the memory cells arranged along the first direction.

[0163] exist Fig.12D 104, a plurality of contact elements 110 and a plurality of diodes 120 may be formed. The formation of the contact elements 110 may include forming a plurality of first contacts 112 in the well 104. The formation of the diodes 120 may include forming a plurality of diode layers 122 in the well 104. The first contacts 112 and the diode layers 122 may be formed as doped regions in the well 102, for example, by implantation. The first contacts 112 may have a first conductivity type, and the diode layers 122 may have a second conductivity type. In a non-limiting embodiment where the well 102 is an N-well, the first contacts 112 may be formed as n+ contacts, and the diode layers 122 may be formed as p+ diode layers.

[0164] like Fig.12D As shown, respective first contacts 112 may be spaced apart from respective diode layers 122 such that dummy gates 130 may be disposed over spaces between first contacts 112 and diode layers 122. Additional dummy gates 230 may be disposed over spaces between diode layers 122 from adjacent columns.

[0165] exist Fig.12E In the embodiment, an interconnect 242 may be formed over the first contact 112, and a metal layer may be formed over the interconnect 242 to serve as a first signal line 272, such as a bit line or a word line. An interconnect 242 may also be formed over the diode layer 122, and a metal layer 244 may be formed over the interconnect 242 for electrical connection to a memory element, as shown below. Fig.12F shown.

[0166] exist Fig.12F In the embodiment, a plurality of memory elements 140 may be arranged or formed above a corresponding diode layer 122 and may be electrically connected to the corresponding diode layer 122 through one or more interconnects. Each memory element 140 and a corresponding diode 120 are electrically connected in series and form a corresponding memory cell 250, such as Figure 5 As shown. Metal layers 274 may be formed on corresponding memory elements 140, and these metal layers may be used as second signal lines 274, such as word lines or bit lines. Therefore, Fig.12F The structure formed in can be a 1S1R memory array, similar to the above Figure 5 The memory array 500 described in .

[0167] By applying a predetermined voltage to the selected first signal line 272 and the selected second signal line 274, the corresponding diode 120 can be configured to select the memory element 140 for unipolar operation of the memory element 140, as described above with reference to Figure 6 and Figure 7 described.

[0168] Additional interlayer dielectrics can be formed ( Fig.12F 2 (not shown) to isolate the memory elements 140 from each other, and to isolate the interconnects 242, metal layers 244, and signal lines 272, 274 from each other. Conventional BEOL processes may also be performed to fabricate other interconnects and metal layers.

[0169] According to the various non-limiting embodiments described above, memory devices 100 and memory arrays 200, 500 can be provided that employ CMOS-compatible selectors / diodes for use in smaller areas. Diodes as selectors for corresponding memory elements can be formed in the source / drain regions of transistors by implantation (e.g., in a FEOL (front-end of line) process). These CMOS-compatible diode selectors are compact and not limited by thermal budgets, and achieve advantages such as high on / off ratios, excellent durability, and the ability to withstand thermal budgets of >400°C. In addition, these diodes can be combined or arranged in a simple manner to achieve unipolar or bipolar operation of memory elements. Simple and compact CMOS-compatible diodes can be configured in a crossbar architecture to provide a high-density 1S1R (one selector and one resistor) crosspoint memory array 500 and a high-density 2S1R (double selectors and one resistor) crosspoint memory array 200 for unipolar and bipolar operation of resistive memory.

[0170] In addition, the dummy gate 130 and the additional dummy gate 230 can be formed as the gate region of the transistor and provide a compact isolation structure in the memory device 100 and the memory array 200, 500. Compared with the conventional 1T1R memory structure, a smaller cell size can be achieved by using the dummy gate 130 and the additional dummy gate 230 for isolation in the memory device 100 and the memory array 200, 500. Conventional CMOS technology can be used for the memory device 100 and the memory array 200, 500 without the need for additional masks.

[0171] The present invention may be embodied in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the foregoing embodiments are considered to be illustrative in all respects, rather than limiting the present invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description, and all changes within the meaning and scope of the equivalents of the claims are intended to be included therein.

Claims

1. A memory device, comprising: a substrate, wherein the substrate includes a well having a first conductivity type; a contact element disposed in the well, wherein the contact element comprises a first contact having the first conductivity type; a diode layer disposed in the well, wherein the diode layer has a second conductivity type opposite to the first conductivity type; a dummy gate configured to isolate the first contact from the diode layer; as well as A memory element is electrically connected to the diode layer.

2. The memory device according to claim 1, wherein: At least a portion of the well and the diode layer form a diode.

3. The memory device according to claim 1, further comprising: a channel layer having the second conductivity type, wherein the channel layer is arranged in the well; as well as A further diode layer is arranged in the channel layer, wherein the further diode layer has the first conductivity type and is electrically connected to the memory element, wherein at least a portion of the channel layer and the further diode layer form a further diode.

4. The memory device according to claim 3, further comprising: an isolation element disposed in the substrate and an isolation well located below the isolation element, wherein the isolation element is arranged between the diode layer and the further diode layer, and The isolation well has the second conductivity type.

5. The memory device according to claim 3, wherein: The contact element further comprises: a second contact disposed in the channel layer, wherein the second contact has the second conductivity type; and A third contact is disposed in the well, wherein the third contact has the first conductivity type.

6. The memory device according to claim 5, wherein: The dummy gate is configured to isolate the second contact from the further diode layer.

7. The memory device according to claim 1, wherein: The dummy gate includes a gate dielectric layer, a gate layer disposed over the gate dielectric layer, and an insulating spacer surrounding the gate dielectric layer and the gate layer.

8. The memory device according to claim 1, wherein: The contact element is electrically connected to a first signal line, and wherein the memory element is electrically connected to a second signal line.

9. The memory device according to claim 1, wherein: The memory element is a resistive memory.

10. A method of forming a memory device, the method comprising: providing a substrate, wherein the substrate includes a well having a first conductivity type; forming a contact element in the well, wherein the contact element comprises a first contact having the first conductivity type; forming a diode layer in the well, wherein the diode layer has a second conductivity type opposite to the first conductivity type; forming a dummy gate to isolate the first contact from the diode layer; as well as A memory element is electrically connected to the diode layer.

11. The method according to claim 10, further comprising: forming a channel layer in the well, wherein the channel layer has the second conductivity type; A further diode layer is formed in the channel layer and is electrically connected to the memory element, wherein the further diode layer has the first conductivity type.

12. A memory array comprising: a substrate, wherein the substrate includes a well having a first conductivity type; a plurality of columns comprising a plurality of memory cells arranged in a matrix, wherein the plurality of columns comprises a first column of memory cells and a second column of memory cells; Each memory primitive includes: a diode layer disposed in the well, wherein the diode layer has a second conductivity type opposite to the first conductivity type; and a memory element electrically connected to the diode layer; a contact element column comprising contact elements arranged in the well, wherein each contact element comprises a first contact having the first conductivity type; a dummy gate configured to isolate the column of contact elements from the diode layer in each memory cell in the first column of memory cells; and An additional dummy gate is configured to isolate the diode layer in the first column of memory cells from the diode layer in the second column of memory cells.

13. The memory array of claim 12, further comprising: A plurality of isolation elements are arranged in a column in the substrate, wherein the isolation elements are configured to isolate the diode layers in the memory cells within the same column of memory cells.

14. The memory array of claim 12, wherein: At least a portion of the well and a corresponding diode layer form a diode for each memory cell.

15. The memory array of claim 12, wherein: Each memory primitive also includes: a channel layer having the second conductivity type, wherein the channel layer is arranged in the well, A further diode layer is arranged in the channel layer, wherein the further diode layer has the first conductivity type and is electrically connected to a respective memory element, wherein at least a portion of the channel layer and the further diode layer form a further diode.

16. The memory array of claim 15, further comprising: a plurality of isolation elements arranged in columns in the substrate and corresponding isolation wells located below corresponding isolation elements, wherein the respective isolation element is arranged between the diode layer and the further diode layer in each column of memory cells, The isolation well has the second conductivity type.

17. The memory array of claim 15, wherein: The contact element array further comprises: a plurality of second contacts arranged in the channel layer, wherein the plurality of second contacts have the second conductivity type; and A plurality of third contacts are arranged in the well, wherein the plurality of third contacts have the first conductivity type.

18. The memory array according to claim 17, in, The dummy gate is configured to isolate the plurality of second contacts in the column of contact elements from the further diode layer in the first column of memory cells; Wherein the further dummy gate is configured to isolate the further diode layer in the first column of memory cells from the further diode layer in the second column of memory cells.

19. The memory array of claim 12, wherein: Each of the dummy gate and the further dummy gate includes a gate dielectric layer, a gate layer arranged over the gate dielectric layer, and an insulating spacer surrounding the gate dielectric layer and the gate layer.

20. The memory array of claim 12, wherein: Each contact element is electrically connected to a corresponding first signal line, and wherein each column of memory elements is electrically connected to a corresponding second signal line.

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