Instruction cache, instruction reading method and electronic device

Abstract

The embodiment of the present application provides a kind of instruction cache, instruction reading method and electronic equipment, wherein a kind of instruction cache, comprising: first level instruction cache, the quantity of the first level instruction cache is multiple, each first level instruction cache is one-to-one corresponding with each thread;Second level instruction cache, the second level instruction cache corresponds to each thread, and each first level instruction cache is all corresponding, the instruction cache, instruction reading method and electronic equipment provided by the embodiment of the present application can improve the efficiency of instruction reading and the utilization of instruction cache space simultaneously.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of computer, in particular to an instruction cache, an instruction reading method and an electronic device. BACKGROUND

[0002] In a typical computer structure, there are usually a processor and a multi-level memory. In the multi-level memory, a main memory stores instructions and data. The processor fetches instructions and corresponding data from the main memory, executes the instructions, and writes the result data back to the main memory. Between the processor and the main memory, there is usually one or more levels of cache memory (Cache) or cache. The cache is used to reduce the time for the processor to read instructions and data. When the processor needs to read data at a certain address in the main memory, it first checks whether the data exists in the cache. If the cache contains the data, the processor directly reads the data from the cache. Reading data from the cache is much faster than reading data from the main memory. If the cache does not contain the data, the cache reads the data from the main memory and stores it in the cache, and returns it to the processor.

[0003] In existing computer structures, the first level cache is often divided into an instruction cache and a data cache. The instruction cache is used to store instructions that the processor needs to execute, and the data cache is used to store data that the processor needs.

[0004] However, the prior art is difficult to balance the utilization of instruction cache space and the improvement of instruction reading efficiency.

[0005] Therefore, how to improve the efficiency of instruction reading and the utilization of instruction cache space at the same time has become a technical problem that those skilled in the art need to solve urgently. SUMMARY

[0006] Therefore, the embodiments of the present application provide an instruction cache, an instruction reading method and an electronic device to improve the efficiency of instruction reading and the utilization of instruction cache space at the same time.

[0007] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0008] In a first aspect, the embodiments of the present application provide an instruction cache, comprising:

[0009] A plurality of first level instruction caches, each of the first level instruction caches corresponding to one thread.

[0010] a second level instruction cache corresponding to each of the threads and corresponding to each of the first level instruction caches.

[0011] In a second aspect, an embodiment of the present application provides an instruction reading method, applied to the instruction cache as described in the first aspect, and comprising:

[0012] receiving, by the first level instruction cache, a current instruction reading request for a current instruction of a corresponding thread;

[0013] when the current instruction hits in the first level instruction cache, reading and returning the current instruction to a processor;

[0014] when the current instruction misses in the first level instruction cache, sending a current instruction reading request to a second level instruction cache.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising the instruction cache system as described in the first aspect.

[0016] The instruction cache provided by the embodiment of the present application comprises two levels of instruction caches: a first level instruction cache and a second level instruction cache, wherein the number of the first level instruction caches is multiple, and each of the first level instruction caches corresponds to a thread one by one, and the second level instruction cache is shared by all threads, corresponding to each of the threads, and corresponding to each of the first level instruction caches.

[0017] In this way, the instruction cache is divided into two levels, when reading the instructions of a thread, the corresponding first level instruction cache is determined based on the thread, and in the first level instruction cache, each thread uses an independent first level instruction cache, so that the instructions of a certain thread do not occupy too much storage space, and the instruction reading efficiency of other threads is not affected, thereby the instruction reading efficiency of each thread can be improved, and meanwhile, the number of the second level instruction cache is one, shared by all threads, so that when a certain thread in a multi-thread processor reads instructions more frequently than other threads, the cache miss of the thread can be avoided, and the second level instruction cache can be kept in use, thereby the utilization rate of the space of the instruction cache is improved. It can be seen that the instruction cache provided by the embodiment of the present application can improve the instruction reading efficiency and the utilization rate of the space of the instruction cache at the same time by dividing the instruction cache into two levels. BRIEF DESCRIPTION OF DRAWINGS

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating the application of an instruction cache in an embodiment of this application.

[0020] Figure 2 An architecture diagram of the instruction cache provided in the embodiments of this application;

[0021] Figure 3 A first-level instruction cache architecture diagram provided for embodiments of this application;

[0022] Figure 4 A second-level instruction cache architecture diagram provided for embodiments of this application;

[0023] Figure 5 Another architecture diagram of the second-level instruction cache provided in the embodiments of this application;

[0024] Figure 6 This is a schematic diagram of an optional flowchart of the instruction reading method provided in an embodiment of this application;

[0025] Figure 7 A schematic diagram of another optional flow of the instruction reading method provided in the embodiments of this application;

[0026] Figure 8 This is another optional flowchart illustrating the instruction reading method provided in the embodiments of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] Please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the application of the instruction cache provided in an embodiment of this application.

[0029] As shown in the figure, in the computer structure, between the processor 40 and the main memory 90, there is usually a first level cache 50 and a multi-level cache 80, and the first level cache 50 is often divided into two parts, an instruction cache 70 and a data cache 60, wherein the instruction cache 70 is used to store instructions required to be executed by the processor 40, and the data cache 60 is used to store data required by the processor 40.

[0030] For the instruction cache 70, if multiple threads of the processor 40 share the instruction cache 70, the instruction of a certain thread may occupy too much storage space, affecting the instruction reading efficiency of other threads; if the instruction cache is partitioned, each thread corresponds to a partition, and the partition of other threads will not be used, then when a certain thread in the multi-thread processor reads instructions more frequently than other threads, due to the existence of the partition, the thread may have more cache misses, and the utilization rate of the partition corresponding to the other threads is also low.

[0031] Therefore, the embodiment of the present application provides an instruction cache, which includes two levels of instruction caches, i.e., a first level instruction cache 10 and a second level instruction cache 20.

[0032] Please refer to Figure 2 , Figure 2 The architecture diagram of the instruction cache provided by the embodiment of the present application.

[0033] The instruction cache provided by the embodiment of the present application includes two levels of instruction caches: a first level instruction cache 10 and a second level instruction cache 20, wherein the number of the first level instruction cache 10 is multiple, and each first level instruction cache 10 corresponds to each thread (thread 0, thread 1, …, thread n) one by one, the second level instruction cache 20 is shared by all threads, corresponds to each thread, and the second level instruction cache 20 also corresponds to each first level instruction cache 10.

[0034] The second level instruction cache 20 also corresponds to each first level instruction cache 10 means that the number of the first level instruction cache 10 is multiple, and the number of the second level instruction cache 20 is one, and each first level instruction cache 10 corresponds to the second level instruction cache 20. In a specific embodiment, an arbitrator 30 can be used to connect each first level instruction cache 10 and the second level instruction cache 20.

[0035] In this way, the instruction cache is divided into two levels, when reading the instructions of a thread, the corresponding first level instruction cache 10 is determined based on the thread first, in the first level instruction cache 10, each thread uses an independent first level instruction cache 10, so that the instructions of a certain thread do not occupy too much storage space and affect the instruction reading efficiency of other threads, thereby improving the instruction reading efficiency of each thread. At the same time, the number of the second level instruction cache 20 is one, which is shared by all threads, so that when a certain thread in the multi-thread processor reads instructions more frequently than other threads, the thread can have more cache misses, and the second level instruction cache 20 can be kept in use at all times, thereby improving the utilization rate of the instruction cache space. It can be seen that the instruction cache provided by the embodiment of the present application can improve the instruction reading efficiency and the utilization rate of the instruction cache space at the same time by dividing the instruction cache into two levels.

[0036] In a specific embodiment, the first level cache 10 can be coupled inside the processor and integrated with the instruction fetch module of the processor. In this way, the first level cache 10 is physically closer to the processor, which can make the execution more efficient and faster. Of course, in other embodiments, the first level cache 10 can also be located outside the processor.

[0037] Please continue to refer to Figure 2 In another specific embodiment, the instruction cache provided by the embodiment of the present application can further include an arbitrator 30, which can be connected to each first level instruction cache 10 and the second level instruction cache 20. The instruction reading request of each first level instruction cache 10 is sent to the second level instruction cache 20 after being arbitrated by the arbitrator 30.

[0038] The arbitrator 30 is connected to each first level instruction cache 10 and the second level instruction cache 20. When multiple first level instruction caches 10 need to send instruction reading requests to the second level instruction cache 20, the arbitrator 30 needs to arbitrate to determine the order of sending.

[0039] Through the arbitration of the arbitrator 30, the instruction reading request in each first level instruction cache 10 can be more reasonably and smoothly sent to the second level instruction cache 20.

[0040] In order to further improve the efficiency of instruction reading, the embodiment of the present application provides an instruction cache, please refer to Figure 3 , Figure 3 The first level instruction cache architecture provided by the embodiment of the present application is shown in the figure.

[0041] As shown in the figure, the first-level instruction cache 10 can include a first-level storage module 100, a fetch circuit 101, an instruction prefetch circuit 102, replacement logic circuit 103, cache update circuit 104, a first-level interface circuit 105.

[0042] The first-level storage module 100 is adapted to store each instruction of the corresponding thread;

[0043] The fetch circuit 101 is connected to the first-level storage module 100 and is adapted to read the current instruction of the thread in the first-level storage module 100 according to a received current instruction read request;

[0044] The instruction prefetch circuit 102 is adapted to, when the current instruction is a non-jump instruction, obtain a next address instruction of a memory address requested by the current instruction read request, and when the next address instruction is not stored in the first-level storage module 100, issue a next address instruction read request to the second-level instruction cache 20;

[0045] The cache update circuit 104 is adapted to receive an instruction in a read request returned by the second-level instruction cache 20 and update the first-level storage module 100, wherein the instruction includes the current instruction and the next address instruction.

[0046] In one specific embodiment, the first-level storage module 100 includes a plurality of cache units, and the mapping relationship between each instruction and each cache unit is full-associative mapping.

[0047] In one specific embodiment, the cache unit can be a cache line, and the first-level storage module 100 includes a plurality of cache units, i.e., the first-level storage module 100 includes a plurality of cache lines. Specifically, each thread corresponds to a first-level instruction cache 10, and correspondingly, each thread corresponds to a first-level storage module 100, and the capacity of the first-level storage module 100 is small.

[0048] Specifically, the first-level storage module 100 can be set to include 4 cache lines, each cache line being 256 bits, and each instruction of the processor being 32 bits. Therefore, each cache line of the first-level storage module 100 can store 8 instructions of consecutive addresses, and the addresses stored by the 4 cache lines can be consecutive or not.

[0049] Since the fetch operation of the processor has strong spatial locality, i.e., when an instruction is executed, instructions adjacent to it in address are also likely to be executed, therefore, each cache line of the first-level storage module 100 stores 8 instructions of consecutive addresses, which can improve the reading efficiency of instructions.

[0050] In a specific embodiment, the execution efficiency of the processor can be further improved by increasing the bus bandwidth and reading 16 consecutive addresses of instructions at a time. The first-level storage module 100 adopts a full-associative mapping manner, i.e., the instruction data of each thread can be written to any cache line in the corresponding first-level storage module 100. The tag signal of each cache line identifies the high bits of the address and is used to retrieve the instructions in the cache line. The valid signal is used to mark whether the current cache line contains valid data. The valid signal can be a 1-bit value of 0 or 1. When the valid value is 0, the data is invalid. When the valid value is 1, the data is valid. In the initial state of the instruction cache, there is no instruction in the cache line. The valid 0 indicates that the data in the current cache line is invalid. When the cache line is updated to a state where instructions are stored, the valid value changes from 0 to 1, indicating that the data in the current cache line is valid.

[0051] The full-associative mapping can ensure that the cache space of the first-level storage module 100 is fully utilized. Although the capacity of the first-level storage module 100 is small, each thread has a corresponding first-level storage module 100, so the efficiency of instruction reading can be guaranteed.

[0052] In a specific embodiment, the instruction fetching circuit 101 is connected to the first-level storage module 100 and is adapted to read the current instruction of the thread in the first-level storage module 100 according to the received current instruction read request. Specifically, it can include: if the current instruction hits in the first-level storage module 100, returning the current instruction to the processor; if the current instruction is missing in the first-level storage module 100, sending the current instruction read request to the second-level instruction cache 20.

[0053] When the processor sends the current instruction read request, the instruction fetch circuit 101 searches the instruction at the read request address in the first level storage module 100. If the instruction exists in the first level storage module 100, the instruction fetch circuit 101 obtains the current instruction and returns the current instruction to the execution unit of the processor to execute the instruction. If the current instruction is missing in the first level storage module 100, the first interface circuit 105 sends the current instruction read request to the second level instruction cache 20. The first interface circuit 105 is a circuit in the first level instruction cache 10 and is adapted to transmit data between the first level instruction cache 10 and the second level instruction cache 20. Through the search of the current instruction in the first level storage module 100 by the instruction fetch circuit 101, it can be determined whether the current instruction is hit or missing in the first level instruction cache 10, so that the next step is performed. As described above, the first level instruction cache 10 sends the instruction read request to the second level instruction cache 20 through the arbitration of the arbiter 30. In a specific embodiment, the arbiter 30 can use a polling method, i.e., by polling each cache line of the first level storage module 100 in each first level instruction cache 10, the instruction read request is sent to the second level instruction cache 20 in turn.

[0054] It should be noted that the present application does not limit the arbitration method, and the polling arbitration method can be used. In other embodiments, the arbiter 30 can also send the instruction read request of each cache line of the first level storage module 100 in each first level instruction cache 10 through other arbitration methods.

[0055] When the second level instruction cache 20 returns the current instruction in the current instruction read request, the cache update circuit 104 obtains the current instruction and updates the current instruction to a cache line of the first level instruction cache 10. In a specific embodiment, the replacement logic circuit 103 can determine which cache line to update. The replacement logic circuit 103 is adapted to record the usage of each cache line in the first level instruction cache 10 and, when at least one cache line needs to be used, determine the cache line to be updated according to the usage of each cache line. In a specific embodiment, the replacement logic circuit can use an LRU replacement logic circuit (Least Recently Used Replacement Logic Circuit). It should be noted that the present application does not limit the specific method used by the replacement logic circuit. In other embodiments, other different replacement logic circuits can also be used.

[0056] The LRU replacement logic circuit records the least recently accessed cache line according to each access of the cache line by the instruction fetch circuit 101, and the cache update circuit 104 replaces the least recently accessed cache line when the cache line needs to be updated. Accordingly, the instruction fetch circuit 101 obtains the current instruction and returns the current instruction to the execution unit of the processor for execution of the instruction. The replacement strategy of the cache line is determined by using the replacement logic circuit 103, so that the cache line in the first-level instruction cache 10 can be more reasonably utilized.

[0057] Since the instruction fetch operation of the processor has strong spatial locality, i.e., when an instruction is executed, the instructions adjacent to the instruction in address are also likely to be executed, the first-level instruction cache 10 further provides the instruction prefetch circuit 102, which can prefetch the next address instruction adjacent to the memory address requested by the current instruction read request into the first-level storage module 100.

[0058] As described above, after the instruction fetch circuit 101 obtains the current instruction, it determines whether the current instruction is a jump instruction. If it is a jump instruction, the instruction fetch circuit 101 does not perform other operations. If it is not a jump instruction, the instruction fetch circuit 101 searches whether the next address instruction of the memory address requested by the current instruction read request exists in the first-level storage module 100 of the first-level instruction cache 10. If the next address instruction is hit in the first-level storage module 100, the instruction prefetch circuit 102 does not perform other operations. If the next address instruction is missing in the first-level storage module 100, the instruction prefetch circuit 102 sends a next address instruction read request to the second-level instruction cache 20 through the first-level interface circuit 105. When the second-level instruction cache 20 returns the next address instruction in the next address instruction read request, the cache update circuit 104 obtains the next address instruction and updates the cache line of the first-level storage module 100 according to the replacement strategy of the replacement logic circuit 103.

[0059] It can be seen that, through the cooperation of the first-level storage module 100, the instruction fetch circuit 101, the instruction prefetch circuit 102, the replacement logic circuit 103, the cache update circuit 104, and the first-level interface circuit 105, the process of the instruction read request of the processor in the first-level instruction cache 10 can be completed. The next address instruction is prefetched into the first-level storage module 100 of the first-level instruction cache 10 through the instruction prefetch circuit 102, which can further improve the efficiency of instruction reading.

[0060] To further improve the efficiency of instruction reading, the embodiment of the present application further provides an instruction cache, which is described below. Figure 4 , Figure 4The second level instruction cache architecture provided by the embodiment of the present application is shown in the figure. The second level instruction cache 20 can include a cache search circuit 200, a second level storage module 201, a missing cache circuit 202, a pending first-in-first-out memory 203, a cache replacement circuit 204, and a second level interface circuit 205.

[0061] The second level storage module 201 is adapted to store instructions of all threads.

[0062] The cache search circuit 200 is connected to the second level storage module 201 and is adapted to read instructions in the second level storage module 201 according to the instruction read request sent by the first level instruction cache, wherein the instructions include a current instruction and a next address instruction, and the instruction read request includes a current instruction read request and a next address instruction read request.

[0063] The missing cache circuit 202 is adapted to send the instruction read request and store the instruction read request in the pending first-in-first-out memory 203 when the instruction is missing in the second level storage module 201 and the instruction address of the instruction read request is different from the instruction address of each instruction read request stored in the pending first-in-first-out memory 203.

[0064] The pending first-in-first-out memory 203 is adapted to store each instruction read request sent by the second level instruction cache 20 and each unsent instruction read request with the same instruction address as each instruction read request sent by the second level instruction cache 20.

[0065] The capacity of the second level storage module 201 is large and is shared by all threads. The instruction data is mapped to the corresponding cache line of the second level storage module 201 using the set associative mapping method in the prior art. The set associative mapping method is to group the second level storage module 201 into groups of the same size, and then divide each group into blocks of the same size. Direct mapping is used between groups, and full associative mapping is used between blocks in the group.

[0066] When the second level instruction cache 20 receives the instruction read request sent by the first level instruction cache 10, the cache search circuit 200 searches the instruction in the instruction read request in the second level storage module 201, and returns the instruction to the first level instruction cache 10 when the instruction is hit in the second level storage module 201. The cache search circuit 200 searches the corresponding instruction in the second level storage module 201, and returns the instruction to the first level instruction cache 10 when the instruction is hit in the second level storage module 201. It can be seen that the instruction read request operation can be completed in the second level instruction cache 20 after the instruction is hit in the second level storage module 201. If the instruction in the read request is missing in the second level storage module 201, the cache search circuit 200 sends the instruction read request to the missing cache circuit 202.

[0067] The missing cache circuit 202 judges whether the instruction address of the instruction read request is the same as the instruction address of each instruction read request stored in the pending first-in-first-out memory 203. If the instruction address of the instruction read request is the same as at least one instruction address of each instruction read request stored in the pending first-in-first-out memory 203, the instruction read request is stored in the pending first-in-first-out memory 203, and the sending of the instruction read request is stopped. This is because in a multi-threaded processor, multiple threads can request instructions of the same address. If the instruction is missing in the second level storage module, only one read request needs to be sent to the next level cache or main memory, which can improve the efficiency of instruction reading. If they are different, the instruction read request is sent and stored in the pending first-in-first-out memory 203 corresponding to the instruction address in the instruction read request.

[0068] According to the difference of the instruction address of the instruction read request, the number of the pending first-in-first-out memory 203 is also multiple, and each different instruction address has a pending first-in-first-out memory 203 corresponding thereto. In this way, the instruction read request with the same instruction address can be stored in the pending first-in-first-out memory 203 corresponding to the instruction address.

[0069] It can be seen that the reading work of the instruction read request in the second level instruction cache 20 can be completed through the cooperation of the cache search circuit 200, the second level storage module 201, the missing cache circuit 202 and the pending first-in-first-out memory 203. At the same time, in a multi-threaded processor, multiple threads can request instructions of the same address. If the instruction is missing in the second level storage module, only one read request needs to be sent to the next level cache or main memory, so the efficiency of instruction reading can be further improved through the missing cache circuit 202 and the pending first-in-first-out memory 203.

[0070] Please continue to refer to Figure 4 , specifically, the second level instruction cache 20 can also include cache replacement circuit 204 and second level interface circuit 205, the second level interface circuit 205 is adapted to transmit data between the second level instruction cache 20 and the next level cache or main memory, when the next level cache or main memory returns the instruction in the instruction read request sent by the missing cache circuit 202, the cache replacement circuit 204 updates the instruction to the cache line of the second level storage module 201, the replacement strategy of the cache line is polling, that is, according to the mapping mode of group association, the corresponding cache line in the second level storage module 201 is updated in the corresponding group, it should be noted that the application does not limit the specific way of the replacement strategy, in other embodiments, other ways of replacement strategy different from the polling mode can also be used, and the cache replacement circuit 204 checks whether the pending first-in-first-out memory 203 stores the read request with the same address as the returned instruction read request, if yes, the instruction stored in the pending first-in-first-out memory 203 is executed, and the data read task of the instruction stored in the pending first-in-first-out memory 203 is completed.

[0071] Of course, the application also provides another instruction cache, please refer to Figure 5 , Figure 5 Another architecture diagram of the second level instruction cache provided by the application embodiment.

[0072] As shown in the figure, the second level instruction cache 20 can also include performance counter circuit 206, the performance counter circuit 206 is adapted to record the number of hits in the second level storage module 201 and the number of misses in the second level storage module 201, according to the count of the performance counter circuit 206, the second level instruction cache 20 can be optimized, for example: the size of the overall cache space of the second level storage module 201 can be adjusted, or the group association mapping mode of the second level storage module 201 can be adjusted.

[0073] In this way, according to the count of the performance counter circuit 206, the performance of the second level instruction cache 20 can be effectively evaluated, and subsequent optimization thereof is facilitated.

[0074] Please continue to refer to Figure 5In another specific embodiment, the second-level instruction cache 20 can further include an error correction code check circuit (ECC check circuit) 207 and an error handling circuit 208, the error correction code check circuit 207 being adapted to detect and / or correct storage data errors in the second-level instruction cache. To further optimize the second-level instruction cache 20, the instruction cache provided by the present application further includes the error correction code check circuit 207. In one specific embodiment, the error correction code check circuit 207 can be used to correct one-bit storage data errors in the second-level instruction cache 20 and detect two-bit storage data errors in the second-level instruction cache 20. When the error correction code check circuit 207 detects an uncorrectable error, it sends an error signal to the error handling circuit 208, which stops the instruction read request operation of the processor and sends the error signal to the host.

[0075] Thus, the error correction code check circuit 207 can ensure the correctness of the storage data in the second-level instruction cache 20.

[0076] It should be noted that in the instruction cache provided by the present application, the second-level instruction cache 20 can not include the performance counter circuit 206 and the error correction code check circuit (ECC check circuit) 207, or can include one of the performance counter circuit 206 and the error correction code check circuit (ECC check circuit) 207, or can include both the performance counter circuit 206 and the error correction code check circuit (ECC check circuit) 207.

[0077] Meanwhile, in the instruction cache provided by the present application, the number of cache lines included in the first-level instruction cache 10 and the second-level instruction cache 20, the size of the data contained in each cache line, the mapping method used by the first-level instruction cache 10 and the second-level instruction cache 20, the replacement strategy of the cache lines, and the arbitration method of the arbiter 30 are not limited, and different methods can be used in different embodiments.

[0078] Based on the instruction cache provided by the present application, the present application further provides an instruction reading method, which will be described below with reference to Figure 6 , Figure 6 An optional flowchart of the instruction reading method provided by the present application is shown in FIG. 6. The flowchart includes the following steps:

[0079] Step S601: Send a current instruction read request.

[0080] It should be understood that the current instruction read request is sent to the instruction cache by a thread in the processor.

[0081] Step S602: receiving a current instruction read request of a current instruction of a corresponding thread by the first-level instruction cache.

[0082] Since the instruction cache includes the first-level instruction cache and the second-level instruction cache, and each thread has a corresponding first-level instruction cache, the current instruction read request can be received by the first-level instruction cache corresponding to the thread in the instruction cache.

[0083] Specifically, the current instruction read request of the corresponding thread can be received by the instruction fetch circuit in the first-level instruction cache.

[0084] Step S603: determining whether the current instruction hits in the first-level instruction cache, if yes, executing step S604, if no, executing step S606.

[0085] When the first-level instruction cache receives the current instruction read request of the corresponding thread, the instruction in the current instruction read request is searched in the first-level instruction cache first, specifically, the instruction memory address in the current instruction read request can be used for searching, if the instruction exists in the first-level instruction cache, it is a first-level instruction cache hit, if the instruction does not exist in the first-level instruction cache, it is a first-level instruction cache miss, if it is a hit, it is turned to step S604, if it is a miss, it is turned to step S606.

[0086] Specifically, when the instruction fetch circuit receives the current instruction read request of the corresponding thread, the instruction in the current instruction read request can be searched in the first-level storage module in the first-level instruction cache by the instruction fetch circuit first, if the instruction exists in the first-level storage module, it is a first-level instruction cache hit, if the instruction does not exist in the first-level storage module, it is a first-level instruction cache miss, if it is a hit, it is turned to step S604, if it is a miss, it is turned to step S606.

[0087] Step S604: reading the current instruction.

[0088] If the instruction hits in the first-level instruction cache, the first-level instruction cache reads the current instruction, specifically, the instruction fetch circuit therein can read the current instruction.

[0089] Step S605: returning the current instruction.

[0090] After the first-level instruction cache reads the current instruction, the current instruction is returned to the processor.

[0091] Specifically, the fetch circuit in the first-level instruction cache can read the current instruction and return the current instruction to the processor.

[0092] Step S606: sending the current instruction read request to the second-level instruction cache.

[0093] If the current instruction requested by the current instruction read request is missing in the first-level instruction cache, the first-level instruction cache sends a request to the second-level instruction cache to obtain the current instruction from the second-level instruction cache.

[0094] Of course, the fetch circuit of the first-level instruction cache can send the current instruction read request to the second-level instruction cache through the first-level interface circuit.

[0095] It can be seen that the instruction reading method provided by the embodiment of the application utilizes the first-level instruction cache and the second-level instruction cache of the instruction cache. When reading the instructions of a thread, the request is first received by the corresponding first-level instruction cache based on the thread, and when the first-level instruction cache misses, the request is sent to the second-level instruction cache. Since each thread uses an independent first-level instruction cache in the first-level instruction cache, it can avoid that the instructions of a certain thread occupy too much storage space and affect the instruction reading efficiency of other threads, thereby improving the instruction reading efficiency of each thread. The number of second-level instruction caches is one, which is shared by all threads, which can avoid that when a certain thread in a multi-thread processor reads instructions more frequently than other threads, the thread may have more cache misses. It can ensure that the second-level instruction cache is always in use, improve the utilization rate of the space of the instruction cache, and the instruction reading efficiency and the utilization rate of the space of the instruction cache can be improved simultaneously.

[0096] Of course, after the second-level instruction cache receives the current instruction read request, it also needs to perform a hit judgment on the current instruction. For details, please refer to the following content.

[0097] Step S607: determining whether the current instruction in the current instruction read request hits, if yes, performing step S608, if no, performing step S609.

[0098] When the second-level instruction cache receives the current instruction read request sent by the first-level instruction cache, it first searches the instruction in the current instruction read request in the second-level instruction cache. If the instruction exists in the second-level instruction cache, it is a hit of the second-level instruction cache, and step S608 is performed. If the instruction does not exist in the second-level instruction cache, it is a miss of the second-level instruction cache, and step S609 is performed.

[0099] Specifically, when the cache search circuit in the second-level instruction cache receives the current instruction read request, it first searches the current instruction in the current instruction read request in the second-level storage module in the second-level instruction cache. If the current instruction exists in the second-level storage module, it is a hit of the second-level instruction cache, and step S608 is performed. If the instruction does not exist in the second-level storage module, it is a miss of the second-level instruction cache, and step S609 is performed.

[0100] Step S608: Obtain the current instruction and return it to the first-level instruction cache.

[0101] If it is a hit, the second-level instruction cache obtains the current instruction and returns it to the first-level instruction cache.

[0102] Specifically, the current instruction can be obtained by the cache search circuit of the second-level instruction cache, and returned to the first-level instruction cache.

[0103] Step S609: Send the current instruction read request.

[0104] If the instruction is a miss in the second-level instruction cache, the second-level instruction cache sends the current instruction read request to the next-level cache or the main memory.

[0105] Of course, the cache search circuit of the second-level instruction cache can send the current instruction read request to the next-level cache or the main memory through its second-level interface circuit.

[0106] Specifically, when the next-level cache exists, the current instruction read request is sent to the next-level cache, and when the next-level cache does not exist, the current instruction read request is sent to the main memory.

[0107] Step S610: Return the current instruction in the current instruction read request.

[0108] After the next-level cache or the main memory obtains the current instruction according to the current instruction read request, it returns the current instruction to the second-level instruction cache.

[0109] Step S611: obtaining the current instruction and updating the second-level instruction cache.

[0110] The second-level instruction cache receives the current instruction returned from the next-level cache or the main memory and updates it.

[0111] Specifically, the current instruction returned from the next-level cache or the main memory can be received by the cache replacement circuit in the second-level instruction cache, and then the instruction is updated into the cache line of the second-level storage module in the second-level instruction cache according to the corresponding replacement policy.

[0112] Step S612: returning the current instruction to the first-level instruction cache.

[0113] After the second-level instruction cache stores the current instruction, the second-level instruction cache further returns the current instruction to the first-level instruction cache.

[0114] Step S613: obtaining the current instruction and updating the first-level instruction cache.

[0115] After the second-level instruction cache returns the instruction to the first-level instruction cache, the cache update circuit in the first-level instruction cache obtains the instruction and updates the instruction into the cache line of the first-level storage module in the first-level instruction cache according to the corresponding replacement policy.

[0116] Step S614: returning the current instruction to the processor.

[0117] The specific content of step S614 can refer to the description of step S605, which will not be repeated here.

[0118] It can be seen that the instruction reading method based on the instruction cache provided by the embodiments of the present application can successfully read the current instruction whether the second-level instruction cache stores the current instruction or not, and can improve the efficiency of instruction reading and the utilization rate of instruction cache space at the same time.

[0119] In another specific embodiment, in order to further improve the efficiency of instruction reading, the embodiments of the present application also provide an instruction reading method, which is described below with reference to Figure 7 , Figure 7 Another optional flowchart of the instruction reading method provided by the embodiments of the present application is shown in the figure, which includes the following steps:

[0120] Step S701: sending a current instruction reading request.

[0121] Step S702: receiving the current instruction reading request of the current instruction of the corresponding thread by the first-level instruction cache.

[0122] Step S703: judging whether the current instruction hits in the first level instruction cache, if yes, executing step S704, if not, executing step S706.

[0123] Step S704: reading the current instruction.

[0124] Step S705: returning the current instruction.

[0125] Step S706: sending a current instruction read request to the second level instruction cache.

[0126] The specific content of steps S701-S706 can refer to the description of steps S601-S606. Figure 6 The description of steps S601-S606 is not repeated here.

[0127] Step S707: judging whether the current instruction is a jump instruction, if yes, executing step S704, if not, executing step S708.

[0128] It should be noted that when the current instruction is a jump instruction, executing step S704 means that if the reading of the aforementioned current instruction has not been completed, the reading of the aforementioned current instruction is continued, rather than executing the step of reading the current instruction again. It can also be understood that if the current instruction is a jump instruction, a new step will not be triggered, and when the current instruction is not a jump instruction, a new step, i.e., step S708, will be triggered.

[0129] This is because the instruction fetching operation of the processor has strong spatial locality, that is, when an instruction is executed, the instructions adjacent to it in address are also likely to be executed. In order to improve the efficiency of instruction reading, the first level instruction cache can also be provided with an instruction prefetch circuit. Through the instruction prefetch circuit, the next address instruction adjacent to the memory address requested by the current instruction read request can be prefetched into the first level storage module. In step S704, after the instruction fetching circuit in the first level instruction cache reads the current instruction, the instruction prefetch circuit will obtain the current instruction and judge whether the current instruction is a jump instruction. If it is a jump instruction, the instruction prefetch circuit will not perform any operation and continue the execution of step S704. If it is not a jump instruction, step S708 will be executed.

[0130] Step S708: judging whether the next address instruction of the memory address requested by the current instruction read request hits, if yes, executing step S704, if not, executing step S709.

[0131] The execution step S704 described herein when the next address instruction of the memory address requested by the current instruction read request is hit has the same meaning as the execution step S704 described above when the current instruction is a jump instruction, and will not be described here again.

[0132] When the instruction prefetch circuit determines that the current instruction is a non-jump instruction, it will then determine whether the next address instruction of the memory address requested by the current instruction read request is hit. If the next address instruction exists in the first-level storage module of the first-level instruction cache, it is a first-level instruction cache hit. If it is hit, the instruction prefetch circuit will not perform any operation, and then proceed to step S704. If the next address instruction does not exist in the first-level storage module of the first-level instruction cache, it is a first-level instruction cache miss. If it is a miss, it proceeds to step S709.

[0133] Step S709: Send a next address instruction read request to the second-level instruction cache.

[0134] When the instruction prefetch circuit determines that the next address instruction is missing in the first-level storage module of the first-level instruction cache, it sends a next address instruction read request to the second-level instruction cache. Specifically, the first-level interface circuit of the first-level instruction cache can send a next address instruction read request to the second-level instruction cache.

[0135] Step S710: Determine whether the instruction in the instruction read request is hit. If so, proceed to step S711. If not, proceed to step S712.

[0136] It should be noted that since the current instruction read request is sent to the second-level instruction cache when the current instruction does not hit in the first-level instruction cache, and the next address instruction read request is sent to the second-level instruction cache when the next address instruction of the memory address requested by the current instruction read request does not hit, although they are different instruction read requests, the second-level instruction cache will obtain the corresponding instruction in the same way after receiving the instruction read request. Therefore, for convenience of description, the current instruction read request or the next address instruction read request is directly represented by the instruction read request, and the current instruction or the next address instruction is directly represented by the instruction, and will not be described separately.

[0137] When the cache search circuit in the second level instruction cache receives the instruction read request sent by the first level instruction cache, it first searches the instruction in the instruction read request in the second level storage module in the second level instruction cache. If the instruction exists in the second level storage module, it is a hit of the second level instruction cache. If the instruction does not exist in the second level storage module, it is a miss of the second level instruction cache. If it is a hit, it goes to step S711. If it is a miss, it goes to step S712.

[0138] Step S711: Acquire the instruction and return it to the first level cache.

[0139] Step S712: Send the instruction read request.

[0140] Step S713: Return the instruction in the instruction read request.

[0141] Step S714: Acquire the instruction and update the second level instruction cache.

[0142] Step S715: Return the instruction to the first level instruction cache.

[0143] Step S716: Acquire the instruction and update the first level instruction cache.

[0144] The specific content of steps S711-S716 can be referred to the description of steps S608-S613, which will not be repeated here. Figure 6 The description of steps S608-S613 will not be repeated here.

[0145] It should be noted that in steps S710-S716, if the current instruction read request is received, the current instruction read request and the current instruction are processed in the foregoing steps. If the next address instruction read request is received, the next address instruction read request and the next address instruction are processed in the foregoing steps.

[0146] Step S717: Return the current instruction to the processor.

[0147] The specific content of step S717 can be referred to the description of step S614, which will not be repeated here.

[0148] It should be noted that in steps S710-S716, if the next address instruction read request and the next address instruction are processed, only the next address instruction needs to be updated in the first level instruction cache. It is not necessary to return to the processor. When the first level instruction cache receives the request sent by the processor to acquire the instruction, it returns to the processor. If the current instruction read request and the current instruction are processed, the current instruction needs to be returned to the processor.

[0149] In summary, the instruction reading method based on the instruction cache provided in the embodiments of the present application can improve the efficiency of instruction reading and the utilization rate of instruction cache space. Since the instruction fetching operation of the processor has strong spatial locality, i.e., when an instruction is executed, the instructions adjacent to it in address are also likely to be executed. It can be seen that the instruction reading method provided in the present application can, when the current instruction is determined to be a non-jump instruction, determine whether the next address instruction in the instruction reading request hits the first-level instruction cache. If the next address instruction is missing, the next address instruction reading request is sent to the second-level instruction cache, so that the next address instruction can be prefetched into the first-level storage module of the first-level instruction cache, thereby facilitating the subsequent acquisition of the next address instruction and further improving the efficiency of instruction reading.

[0150] Reference is made to Figure 8 , Figure 8 Another optional flowchart of the instruction reading method provided in the embodiments of the present application is shown in FIG. 8. The flowchart includes the following steps:

[0151] Step S801: Send a current instruction reading request.

[0152] Step S802: Receive, by the first-level instruction cache, the current instruction reading request of the current instruction of the corresponding thread.

[0153] Step S803: Determine whether the current instruction hits the first-level instruction cache. If yes, execute step S804; if no, execute step S806.

[0154] Step S804: Read the current instruction.

[0155] Step S805: Return the current instruction.

[0156] Step S806: Send the current instruction reading request to the second-level instruction cache.

[0157] Step S807: Determine whether the current instruction is a jump instruction. If yes, execute step S804; if no, execute step S808.

[0158] Step S808: Determine whether the next address instruction of the memory address requested by the current instruction reading request hits. If yes, execute step S804; if no, execute step S809.

[0159] Step S809: Send the next address instruction reading request to the second-level instruction cache.

[0160] Step S810: Determine whether the instruction in the instruction reading request hits. If yes, execute step S811; if no, execute step S812.

[0161] Step S811: Acquire the instruction and return to the first level cache.

[0162] The specific content of steps S801-S811 can refer to the description of steps S101-S111. Figure 7 The description of steps S701-S711 is not repeated here.

[0163] Step S812: Determine whether the instruction address of the instruction read request is different from the instruction addresses of each instruction read request stored in the pending FIFO memory, if yes, execute step S814, if no, execute step S813.

[0164] In a specific embodiment, since in a multi-thread processor, multiple threads can request the same address instruction, if the instruction is missing in the second level instruction cache, only one read request needs to be sent to the next level cache or the main memory, therefore, the second level instruction cache can be provided with a pending FIFO memory to store each instruction read request sent to the next level cache or the main memory, and each unsent instruction read request with the same instruction address as the instruction address of each sent instruction read request.

[0165] Therefore, if it is determined in step S810 that the instruction is missing in the second level instruction cache, the missing cache circuit in the second level instruction cache can then determine whether the address in the instruction read request is the same as the instruction addresses of each instruction read request stored in the pending FIFO memory, if yes, it is not that the instruction address of the instruction read request is different from the instruction addresses of each instruction read request stored in the pending FIFO memory, turn to step S813, if no, turn to step S814, according to the difference of the instruction address of the instruction read request, the number of the pending FIFO memory is also multiple, each different instruction address has a pending FIFO memory corresponding thereto, in this way, the instruction read request with the same instruction address can be stored in the pending FIFO memory corresponding to the instruction address.

[0166] Step S813: Store the instruction read request in the pending FIFO memory corresponding to the address in the instruction read request.

[0167] If the missing cache circuit determines in step S812 that the address in the instruction read request is the same as at least one of the instruction addresses of each sent instruction read request, stop sending the instruction read request, and store the instruction read request in the pending FIFO memory corresponding to the address in the instruction read request.

[0168] According to the different instruction address of the instruction read request, the number of pending first-in-first-out memories is also multiple, each different instruction address has a pending first-in-first-out memory corresponding thereto, so that the instruction read requests with the same instruction address can be stored in the pending first-in-first-out memory corresponding to the instruction address.

[0169] Step S814: sending the instruction read request.

[0170] If the missing cache circuit in step S812 judges that the address in the instruction read request is different from the instruction addresses requested by each of the instruction read requests sent, the instruction read request is sent to the next level cache or the main memory through the second level interface circuit in the second level instruction cache, and step S813 of storing the instruction read request into the pending first-in-first-out memory corresponding to the address in the instruction read request also needs to be performed.

[0171] Step S815: returning the instruction in the instruction read request.

[0172] Step S816: obtaining the instruction and updating the second level instruction cache.

[0173] The specific contents of steps S815-S816 can be referred to Figure 7 The description of steps S713-S714 is not repeated here.

[0174] Step S817: determining the pending first-in-first-out memory storing the instruction read request with the same instruction address as the returned instruction address, and executing the instruction read request stored in the pending first-in-first-out memory.

[0175] When the instruction read request stored in the pending first-in-first-out memory is executed, after the cache replacement circuit in the second level instruction cache obtains the instruction returned from the next level cache or the main memory and updates the instruction into the cache line of the second level storage module in the second level instruction cache according to the corresponding replacement strategy, the cache replacement circuit in the second level instruction cache will determine the pending first-in-first-out memory corresponding to the returned instruction address, and execute the instruction read request in the pending first-in-first-out memory.

[0176] Step S818: returning the instruction to the first level instruction cache.

[0177] Step S819: obtaining the instruction and updating the first level instruction cache.

[0178] The specific contents of steps S818-S819 can be referred to Figure 7 The description of steps S715-S716 is not repeated here.

[0179] It should be noted that in the step S810 to the step S819, if the current instruction read request is received, the current instruction read request and the current instruction are processed in the foregoing steps, and if the next address instruction read request is received, the next address instruction read request and the next address instruction are processed in the foregoing steps.

[0180] The step S820: obtaining the current instruction and returning to the processor.

[0181] The specific content of the step S820 can refer to the description of the step S717, and will not be described here again.

[0182] It should be noted that in the step S810 to the step S819, if the next address instruction read request and the next address instruction are processed, only the next address instruction needs to be updated to the first level instruction cache, and there is no need to return to the processor, and when the first level instruction cache receives the request of obtaining the instruction sent by the processor, the next address instruction is returned to the processor; if the current instruction read request and the current instruction are processed, the current instruction needs to be returned to the processor.

[0183] It can be seen that in the multi-thread processor, if multiple threads request the instruction of the same address, only one read request needs to be sent to the next level cache or the main memory when the instruction is missing in the second level instruction cache. The instruction reading method provided in the application stops sending the instruction read request with the same address and stores the instruction read request with the same address in the pending first-in-first-out memory corresponding to the address, and only sends the instruction read request with the different address to the next level cache or the main memory and stores the instruction read request with the different address in the pending first-in-first-out memory corresponding to the address, which can provide double guarantee for further improving the efficiency of instruction reading.

[0184] Meanwhile, it should be noted that the instruction reading method provided in the application does not limit the use of the steps S807, S808 and the related step processes for judging the jump instruction, and does not limit the use of the step S812 and the related step processes for judging whether the address in the instruction read request is the same as the instruction address of each instruction read request stored in the pending first-in-first-out memory. In one specific embodiment, neither of the two related step processes is included, in another specific embodiment, only one of the related step processes is included, and in other specific embodiments, both of the related step processes are included.

[0185] The electronic device provided in the embodiment of the application can include the instruction cache system provided in the above embodiments of the application.

[0186] Although the present application discloses the above-mentioned embodiments, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. An instruction cache, characterized in that, include: The first-level instruction cache has multiple caches, each corresponding to a specific thread. The first-level instruction cache is coupled inside the processor and integrated with the processor's instruction fetch module. The second-level instruction cache consists of one cache, which is shared by all threads and corresponds to each of the first-level instruction caches. An arbitrator is adapted to connect each of the first-level instruction caches and the second-level instruction caches. The instruction read requests of each of the first-level instruction caches are arbitrated by the arbitrator and then sent to the second-level instruction cache. If the current instruction exists in the Level 1 instruction cache, the current instruction is read and returned to the processor. If the current instruction is missing in the Level 1 instruction cache, a current instruction read request is sent to the Level 2 instruction cache. When the Level 2 instruction cache receives the current instruction read request from the Level 1 instruction cache, if the current instruction is found in the Level 2 instruction cache, the current instruction is retrieved and returned to the Level 1 instruction cache. If the current instruction is missing in the Level 2 instruction cache, and the instruction address of the instruction read request is different from the instruction addresses of all instruction read requests stored in the pending FIFO memory, the instruction read request is sent and stored in the pending FIFO memory. When the instruction is missing in the second-level storage module, and the instruction address of the instruction read request is the same as at least one instruction address of each instruction read request stored in the pending FIFO memory, the instruction read request is stored in the pending FIFO memory, and the transmission of the instruction read request is stopped.

2. The instruction cache as described in claim 1, characterized in that, The first-level instruction cache includes: The first-level storage module is suitable for storing the instructions of the corresponding thread; The instruction fetch circuit, connected to the first-level storage module, is adapted to read the current instruction of the thread from the first-level storage module according to the received current instruction read request; The instruction prefetch circuit is adapted to, when the current instruction is a non-jump instruction, obtain the next address instruction of the memory address requested by the current instruction read request, and when the next address instruction is not stored in the first-level storage module, issue the next address instruction read request to the second-level instruction cache; The cache update circuit is adapted to receive instructions from a read request returned by the second-level instruction cache and update the first-level storage module, wherein the instructions include the current instruction and the next address instruction.

3. The instruction cache as described in claim 2, characterized in that, The first-level storage module includes multiple cache units, and the mapping relationship between the instructions and each cache unit is a fully associative mapping.

4. The instruction cache as described in claim 2, characterized in that, The instruction fetching circuit is adapted to read the current instruction of the thread from the first-level storage module according to the received current instruction read request, including: When the current instruction is hit in the first-level storage module, the current instruction is returned to the processor; When the current instruction is missing in the first-level storage module, a read request for the current instruction is sent to the second-level instruction cache.

5. The instruction cache as described in claim 3, characterized in that, The cache unit is a cache line, and the first-level instruction cache further includes: The replacement logic circuit is adapted to record the usage of each of the cache lines, and when at least one of the cache lines needs to be used, to determine the appropriate cache line to be updated based on the usage of each of the cache lines.

6. The instruction cache as described in any one of claims 2-5, characterized in that, The second-level instruction cache includes: The second-level storage module is suitable for storing the instructions of all the threads. A cache search circuit, connected to the second-level storage module, is adapted to read the instruction from the second-level storage module according to the instruction read request sent by the first-level instruction cache, wherein the instruction includes the current instruction and the next address instruction, and the instruction read request includes the current instruction read request and the next address instruction read request; The pending first-in-first-out memory is adapted to store each instruction read request sent by the second-level instruction cache, as well as each unsent instruction read request that has the same instruction address as the instruction read request sent by the second-level instruction cache. The missing cache circuit is adapted to send the instruction read request and store the instruction read request in the pending FIFO memory when the instruction is missing in the second-level storage module and the instruction address of the instruction read request is different from the instruction addresses of each instruction read request stored in the pending FIFO memory.

7. The instruction cache as described in claim 6, characterized in that, The missing instruction cache circuit is further adapted to store the instruction read request into the pending FIFO memory and stop sending the instruction read request when the instruction is missing in the second-level storage module and the instruction address of the instruction read request is the same as at least one instruction address of each instruction read request stored in the pending FIFO memory.

8. The instruction cache as described in claim 6, characterized in that, The cache search circuit is adapted to read the instruction from the second-level storage module according to the instruction read request sent by the first-level instruction cache, and further includes: When the instruction is hit in the second-level storage module, the instruction is returned to the first-level instruction cache.

9. The instruction cache as described in claim 8, characterized in that, The second-level instruction cache also includes: A performance counter circuit is suitable for recording the number of hits and misses in the second-level storage module.

10. The instruction cache as described in claim 9, characterized in that, The second-level instruction cache also includes: Error correction code verification circuit, suitable for detecting and / or correcting errors in stored data in the second-level instruction cache.

11. A method for reading instructions, characterized in that, The instruction fetching method, applied to the instruction cache as described in any one of claims 1-10, includes: The first-level instruction cache receives the current instruction read request of the corresponding thread. When the current instruction is hit in the first-level instruction cache, the current instruction is read and returned to the processor; When the current instruction is missing in the first-level instruction cache, a current instruction read request is sent to the second-level instruction cache.

12. The instruction reading method as described in claim 11, characterized in that, Also includes: Read the current instruction of the current instruction read request. When the current instruction is a non-jump instruction, obtain the next address instruction of the memory address requested by the current instruction read request. If the next address instruction is missing in the first-level instruction cache, issue the next address instruction read request to the second-level instruction cache.

13. The instruction reading method as described in claim 11, characterized in that, Also includes: When the second-level instruction cache determines that the instruction is missing in the second-level storage module, and the instruction address of the instruction read request is different from the instruction addresses of all instruction read requests stored in the pending FIFO memory, the instruction read request is sent and stored in the pending FIFO memory corresponding to the address in the instruction read request. The instruction includes the current instruction or the next address instruction, and the instruction read request includes the current instruction read request or the next address instruction read request. The next address instruction is the instruction at the address following the memory address requested by the current instruction read request.

14. The instruction reading method as described in claim 13, characterized in that, Also includes: When the second-level instruction cache determines that the instruction is missing in the second-level storage module, and the instruction address of the instruction read request is the same as at least one instruction address of each instruction read request stored in the pending FIFO memory, it stops sending the instruction read request and stores the instruction read request in the pending FIFO memory corresponding to the address in the instruction read request.

15. The instruction reading method as described in claim 14, characterized in that, Also includes: When the second-level instruction cache determines that the instruction has been hit in the second-level storage module, the instruction is returned to the first-level instruction cache.

16. The instruction reading method as described in claim 11, characterized in that, Also includes: After the first-level instruction cache obtains the instruction returned by the second-level instruction cache, it updates the first-level instruction cache.

17. The instruction reading method as described in claim 14, characterized in that, Also includes: After the second-level instruction cache retrieves the instruction from the returned instruction read request, it updates the second-level instruction cache.

18. The instruction reading method as described in claim 17, characterized in that, After updating the second-level instruction cache, the method further includes: determining the pending FIFO memory that contains the instruction read request with the same address as the returned instruction, and executing the instruction read request stored in the pending FIFO memory.

19. An electronic device, characterized in that, Including the instruction cache system as described in any one of claims 1-10.

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