Data processing method and data processing apparatus

Abstract

A data processing method and a data processing device. The data processing method is applied to a parallel processor which can support a maximum of M work item sets to run in parallel, and comprises M instruction cache areas corresponding to the M work item sets respectively. The data processing method comprises: obtaining a number P of work item sets which need to run in parallel corresponding to a current computing task; configuring the M instruction cache areas according to the number P of work item sets to obtain a plurality of cache partitions, wherein, in response to the number P of work item sets being less than M, the size of each cache partition is greater than the size of one instruction cache area; and setting a jump range of a pointer of each cache partition. The data processing method re-allocates all instruction cache areas according to the number P of work item sets which need to run in parallel, improves the utilization rate of hardware resources, and reduces the waste of hardware resources.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a data processing method and a data processing apparatus. BACKGROUND

[0002] Currently, to meet the rapid development of computer network technology and related services, a large amount of data such as multimedia data (for example, media data such as voice, picture, video, etc.) needs to be transmitted and processed, and the processing of these multimedia data requires a large amount of computing resources, especially parallel computing resources. Parallel computing mainly relies on parallel processors to complete, and a parallel processor refers to a processor that can process multiple operations at the same time. At present, mainstream parallel processors include GPUs (Graphics Processing Units), GPGPUs (General-purpose computing on graphics processing units), etc. SUMMARY

[0003] At least one embodiment of the present disclosure provides a data processing method applied to a parallel processor, the parallel processor can support a maximum of M sets of work items to run in parallel, and includes M instruction cache areas corresponding to the M sets of work items respectively, the method comprising: obtaining a number P of sets of work items corresponding to a current computing task that need to run in parallel; configuring the M instruction cache areas according to the number P of sets of work items to obtain a plurality of cache partitions, wherein, in response to the number P of sets of work items being less than M, the size of each cache partition is greater than the size of the one instruction cache area; and setting a jump range of a pointer of each cache partition.

[0004] For example, in a data processing method provided by some embodiments of the present disclosure, the M instruction cache areas are configured according to the number P of sets of work items to obtain a plurality of cache partitions, and the method comprises: dividing the M instruction cache areas into N cache partitions evenly, wherein N is a positive integer and is greater than or equal to P and less than M.

[0005] For example, in a data processing method provided by some embodiments of the present disclosure, each instruction cache area includes a plurality of storage slices, and dividing the M instruction cache areas into N cache partitions evenly comprises: determining a total number of storage slices included in the M instruction cache areas; determining a total number N of cache partitions according to the total number of storage slices and the number P of sets of work items; and dividing the M instruction cache areas into N cache partitions evenly, wherein each cache partition includes n storage slices, and n is a positive integer and is a ratio of the total number of storage slices to N.

[0006] For example, in a data processing method provided by some embodiments of the present disclosure, the total number of cache partitions N is determined according to the total number of storage chips and the number P of work item sets, including: in response to the total number of storage chips being divisible by P, taking the number P of work item sets as the total number N of cache partitions; in response to the total number of storage chips being not divisible by P, selecting a selected number greater than and closest to P from a plurality of selected numbers that can divide the total number of storage chips as the total number N of cache partitions.

[0007] For example, in a data processing method provided by some embodiments of the present disclosure, the jump range of the pointer of each cache partition is set, including: determining the jump step of the pointer, and making the pointer jump in the cache partition according to the jump step, wherein the pointer includes a write pointer and a read pointer.

[0008] For example, in a data processing method provided by some embodiments of the present disclosure, each cache partition is divided into a plurality of sub-storage areas according to a preset storage length, the plurality of sub-storage areas correspond to a plurality of address numbers one by one, each cache partition includes a first end and a second end, the plurality of address numbers are sequentially increased in the direction from the first end to the second end, and the pointer jumps in the cache partition according to the jump step, including: determining a first target address number, wherein the first target address number is the sum of the address number of the sub-storage area where the pointer currently locates and the jump step; in response to the first target address number being less than or equal to the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the first target address number at the next jump, and in response to the first target address number being greater than the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to a second target address number at the next jump, wherein the second target address number is the remainder of the first target address number and the total number of the plurality of address numbers.

[0009] For example, in a data processing method provided by some embodiments of the present disclosure, the read pointer includes a first read pointer and a second read pointer, the write pointer is used to indicate the writing position of the next instruction, the first read pointer is used to indicate the position of the current instruction to be read, and the second read pointer is used to indicate the storage chip where the current instruction to be read is located, for the second read pointer and the write pointer, the cache partition is divided into a plurality of sub-storage areas according to the same preset storage length, and the second read pointer and the write pointer correspond to the same address number range.

[0010] For example, in a data processing method provided by some embodiments of the present disclosure, obtaining a number P of work item sets corresponding to a current computing task that need to be run in parallel includes: predicting a maximum number of work item sets that need to be run in parallel by the parallel processor when executing the current computing task, and taking the maximum number as the number P of work item sets.

[0011] For example, the data processing method provided by some embodiments of the present disclosure further includes: adjusting an instruction prefetch strategy according to the size of each cache partition.

[0012] For example, in a data processing method provided by some embodiments of the present disclosure, adjusting an instruction prefetch strategy according to the size of each cache partition includes: increasing the number of instructions prefetched at a time or performing instruction prefetching multiple times in succession according to the size of each cache partition.

[0013] For example, the data processing method provided by some embodiments of the present disclosure further includes: adjusting a judgment condition for the remaining storage capacity of a cache partition according to the size of each cache partition.

[0014] At least one embodiment of the present disclosure further provides a data processing apparatus applied to a parallel processor, the parallel processor being capable of supporting a maximum of M work item sets running in parallel and including M instruction cache areas corresponding to the M work item sets respectively, the data processing apparatus including: an obtaining unit configured to obtain a number P of work item sets corresponding to a current computing task that need to be run in parallel; and a configuring unit configured to configure the M instruction cache areas according to the number P of work item sets to obtain a plurality of cache partitions and set a jump range of a pointer of each cache partition, wherein, in response to the number P of work item sets being less than M, the size of each cache partition is greater than the size of the one instruction cache area.

[0015] For example, in a data processing method provided by some embodiments of the present disclosure, the obtaining unit is a register, and the register pre-stores the number P of work item sets.

[0016] For example, in a data processing method provided by some embodiments of the present disclosure, the configuring unit includes a plurality of sub-configuring units, each of the plurality of sub-configuring units corresponds to a different available number of work item sets, and each of the plurality of sub-configuring units is configured to configure the M instruction cache areas according to the corresponding available number of work item sets to obtain a plurality of cache partitions and set a jump range of a pointer of each cache partition.

[0017] For example, in a data processing method provided by some embodiments of the present disclosure, the multiplexer is configured to select one of the plurality of sub-configuring units according to the number P of work item sets. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0019] FIG. 1A is a schematic structural diagram of a GPGPU;

[0020] FIG. 1B is a schematic structural diagram of a parallel processor;

[0021] FIG. 2A is a schematic structural diagram of an instruction cache area;

[0022] FIG. 2B shows a write pointer jump schematic diagram;

[0023] FIG. 2C shows a read pointer jump schematic diagram;

[0024] FIG. 3 is a flowchart of a data processing method provided by at least one embodiment of the present disclosure;

[0025] FIG. 4 shows FIG. 3 is a schematic flowchart of step S102 in the data processing method shown;

[0026] FIG. 5A is a schematic diagram of a structure of an instruction cache area provided by at least one embodiment of the present disclosure;

[0027] FIG. 5B is a write pointer jump schematic diagram provided by at least one embodiment of the present disclosure;

[0028] FIG. 5C is a read pointer jump schematic diagram provided by at least one embodiment of the present disclosure;

[0029] FIG. 6 is a schematic diagram of a read-write flow of instruction data provided by at least one embodiment of the present disclosure;

[0030] FIG. 7 is a schematic diagram of a data processing apparatus provided by at least one embodiment of the present disclosure;

[0031] FIG. 8 is a schematic diagram of a configuration unit provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be used in conjunction with the accompanying drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort belong to the scope of protection of the present disclosure.

[0033] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote quantity limitation, but mean that there is at least one. The terms "include" or "contain" and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like only represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0034] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components can be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0035] FIG. 1A A structural schematic diagram of a general-purpose graphics processor.

[0036] In parallel computing, the tasks executed generally include a plurality of threads (work items). As shown in FIG. 1, a plurality of threads are executed in parallel in a plurality of thread groups (work groups). FIG. 1AAs shown, before these threads are executed in a general-purpose graphics processor (or parallel computing processor), they are divided into multiple workgroups in a command processor, and then the multiple workgroups are dispatched to various computing units via a workgroup dispatch unit. All threads in a workgroup must be allocated to the same computing unit for execution. Meanwhile, the workgroup is split into minimum execution workgroups (hereinafter referred to as execution groups), each of which contains a fixed number (or less than the fixed number) of threads, for example, 32 threads. Multiple workgroups can be executed in the same computing unit. In the computing unit, according to the number of arithmetic logic units and other modules in the computing unit, multiple execution groups in a workgroup can be executed simultaneously or in time-sharing manner. Multiple threads in each execution group execute the same instruction, and the reading, decoding and transmission of the instruction are completed in the scheduling module, the execution of the computing instruction is completed in the arithmetic logic unit, and the memory execution instruction is transmitted to the cache for read / write operation.

[0037] When an execution group executes a computing instruction, the required source data (from a general-purpose register) can come from a previous memory read instruction, and a wait instruction is needed to ensure that the data read by the previous memory read instruction is ready. In the same workgroup, there is also such a synchronization relationship between multiple execution groups. For example, a workgroup includes two execution groups, execution group 0 and execution group 1, and the computation of the two execution groups both needs to read data in memory region A. In order to save reading time and bandwidth, the general optimization method is that execution group 0 reads half of the data in memory region A, and execution group 1 reads the other half of the data in memory region A. However, for any execution group, all data in memory region A is needed when the execution group executes a computing instruction, so before the execution group executes the computing instruction, the memory read instructions of execution group 0 and execution group 1 need to read back the data, and a barrier instruction is needed to prevent the execution group from continuing to execute the instruction until the memory read instructions of execution group 0 and execution group 1 end, so as to obtain all data in memory region A.

[0038] FIG. 1B A schematic structural diagram of a parallel processor.

[0039] As FIG. 1BThe illustrated parallel processor can include an instruction cache, an instruction scheduler, an instruction cache, and an instruction execution unit. For example, the instruction cache can include a cache of instructions stored in an external memory, where the instruction cache is external to the instruction scheduler. The instruction scheduler can be configured to fetch instructions, decode instructions, and dispatch instructions, for example, where the instruction scheduler performs a fetch operation to obtain instruction data from the instruction cache, and where the instruction scheduler decodes and dispatches the fetched instruction data to the instruction execution unit, for example, where the instruction execution unit performs the decoded instruction. The instruction cache can be located in the instruction scheduler, for example, where the instruction cache is used to buffer a small amount of instruction data retrieved from the instruction cache by the instruction scheduler. Note that in this disclosure, instruction data refers to instructions themselves, and not instruction operands.

[0040] For example, the parallel processor can include a plurality of single instruction multiple data (SIMD) processors, for example, where a SIMD processor can be a vector processing unit (VPU), and where a SIMD processor can be configured to process a plurality of thread data in parallel.

[0041] For example, in a SIMD processor, a global execution space can be divided into a plurality of work item sets of equal size, where each work item set is configured to run in parallel, and where each work item set is configured to perform a corresponding instruction operation. For example, a SIMD processor can be configured to support a maximum of M work item sets running in parallel, and where the SIMD processor includes M instruction caches, where each instruction cache is configured to store instruction data retrieved from an instruction cache by the instruction scheduler for a work item set corresponding to the instruction cache, where M is a positive integer.

[0042] For example, the instruction scheduler can be configured to perform an independent fetch operation for each work item set, where the instruction scheduler is configured to write instruction data retrieved from the instruction cache for a work item set to an instruction cache corresponding to the work item set. For example, the instruction scheduler can be configured to retrieve instruction data in a size of 8 double words (DW) per fetch operation, where the size of instruction data retrieved per fetch operation can vary for different processors, as desired.

[0043] For example, the parallel processor can include A SIMD processors, and an instruction scheduler in the parallel processor can dispatch instructions for the A SIMD processors. As previously described, one SIMD processor can concurrently accommodate up to M sets of work items running thereon, each set of work items corresponding to a separate instruction cache, so the parallel processor needs to provide A*M instruction caches to cache instructions for A*M sets of work items, where A is a positive integer.

[0044] FIG. 2A An illustrative structure diagram of the instruction caches. As shown in FIG. 2A , the parallel processor includes 4 SIMD processors, namely single instruction multiple data processor 0, single instruction multiple data processor 1, single instruction multiple data processor 2 and single instruction multiple data processor 3, each of which can support up to 10 sets of work items running concurrently, for example, single instruction multiple data processor 0 can support up to work item set 0_0, work item set 1_0,... work item set 9_0 running concurrently, single instruction multiple data processor 1 can support up to work item set 0_1, work item set 1_1,... work item set 9_1 running concurrently, and so on.

[0045] For example, 40 sets of work items correspond to 40 instruction caches, which are composed of 40 memory banks with a bit width of 128 bits (i.e. 4 double words, each double word being 32 bits, each double word being represented by dw in FIG. 2A ). For example, the 40 memory banks are Mem0 to Mem39 in FIG. 2A . For example, each memory bank includes 4 memory slices, and a memory slice includes 4 double words of the same level of depth in the memory bank, for example, memory slice 0 in FIG. 2A is 4 double words of the same level of depth in memory Mem0, i.e. dw0 to dw3 marked by the dashed box.

[0046] The 4 levels of depth of each memory bank correspond to 4 single instruction multiple data processors, i.e. each memory bank forms part of the instruction cache corresponding to the 4 single instruction multiple data processors. For example, as shown in instruction cache 1 in FIG. 2A , the instruction cache is the instruction cache corresponding to work item set 0_0 in single instruction multiple data processor 0, and instruction cache 1 is composed of the same level of depth of memory Mem0, memory Mem1, memory Mem2 and memory Mem3, i.e. memory slice 0, memory slice 1, memory slice 2 and memory slice 3, and the same level of depth of the 4 memory banks can accommodate 16 double word instructions.

[0047] For example, each instruction cache region has a write pointer wptr, which is used to indicate the position where the next fetched instruction data is written into the instruction cache region. Once the instruction data is written, the write pointer wptr immediately jumps to the address where the next instruction data should be written.

[0048] FIG. 2B A write pointer jump schematic diagram is shown.

[0049] As FIG. 2B shown, the work item set M1_N1 processed by the single instruction multiple data processor N1 is a certain work item set processed by any one of the processors. FIG. 2A As FIG. 2B shown, taking the work item set M1_N1 processed by the single instruction multiple data processor N1 as an example, the write pointer wptr can have four values, for example, 0, 1, 2 and 3, which respectively indicate the starting positions of the four storage pieces in the instruction cache region corresponding to the work item set. For example, the length of each instruction cache region is 16 double words, and the length of the instruction data written (fetched) at a time is 8 double words, so that, FIG. 2B The value of the write pointer wptr in the instruction cache region will only jump between 0 and 2, that is, the jump range of the write pointer wptr is: 0->2->0. After the instruction data is written into the 8 double word positions (for example, the region corresponding to dw0 to dw7) after the address 0 of the instruction cache region at a time, the value of the write pointer wptr will automatically jump to 2, at which time the other half (for example, the region corresponding to dw8 to dw15) of the instruction cache region is empty to accommodate the subsequent fetched instruction data.

[0050] Since the instruction data fetched by the instruction scheduler at a time is 8 double words, which is half the size of the instruction cache region, the write enable of two consecutive memories needs to be opened when writing the instruction data into the instruction cache region, as shown in Table 1.

[0051] Table 1

[0052]

[0053] For example, Mem0_WEn, Mem1_WEn, Mem2_WEn and Mem3_WEn represent the write enables of the four storage pieces, respectively, and the number 1 represents the enable state (Enable) and the number 0 represents the disable state (Disable). The values 0, 1, 2 and 3 of the write pointer wptr respectively indicate the starting positions of the four storage pieces. For example, as FIG. 2AAs shown, 4 storage pieces are located in 4 different memories respectively, for example, when the value of the write pointer wptr is 0, the write enable of the memory Mem0 and the memory Mem1 needs to be opened simultaneously, when the value of the write pointer wptr is 1, the write enable of the memory Mem1 and the memory Mem2 needs to be opened simultaneously, when the value of the write pointer wptr is 2, the write enable of the memory Mem2 and the memory Mem3 needs to be opened simultaneously, when the value of the write pointer wptr is 3, the write enable of the memory Mem3 and the memory Mem0 needs to be opened simultaneously.

[0054] For example, each instruction cache area also has a read pointer, for example, the read pointer includes a first read pointer dw_rptr and a second read pointer rptr, the first read pointer dw_rptr is used to indicate the specific position of the current instruction data to be read, and the second read pointer rptr is used to indicate the storage piece where the current instruction data to be read is located.

[0055] FIG. 2C A read pointer jump schematic diagram is shown.

[0056] For example, as shown in FIG. 2C , taking the work item set M1_N1 processed by the single instruction multiple data processor N1 in FIG. 2A as an example, the second read pointer rptr can have 4 values, for example, can be 0, 1, 2 and 3, and the four values respectively indicate the starting position of each storage piece in the instruction cache area corresponding to the work item set. Since the second read pointer rptr indicates the storage piece where the instruction data to be read is located, the jump range of the second read pointer rptr is: 0->1->2->3->4->0.

[0057] For example, since the length of the instruction data to be read can be as small as 1 double word, for example, when the instruction data is a double word instruction, the jump step of the first read pointer dw_rptr is 1 (1 double word), when the instruction data is a four-word instruction, the jump step of the first read pointer dw_rptr is 2 (2 double words), for example, as shown in FIG. 2C , the jump range of the first read pointer dw_rptr can be 0-15, and dw_rptr=0 represents the position where dw0 is located.

[0058] For example, as shown in FIG. 2C , the jump range marked as 1 st in the figure represents the jump range when the jump step of the first read pointer dw_rptr is 1, at this time, the jump range of the first read pointer dw_rptr is: 0->1->2->...14->15->0, and the jump range marked as 2 ndThe jump range of the first read pointer dw_rptr is 0->2->4->...12->14->0 when the jump step of the first read pointer dw_rptr is 2.

[0059] It should be noted that, FIG. 2C The read pointer jump diagram shown is only illustrative, and the jump step of the first read pointer dw_rptr is not limited to fixed 1 or 2. The jump step of the first read pointer dw_rptr depends on whether the instruction to be read is a double-word instruction or a quad-word instruction, and the present disclosure does not limit this.

[0060] Since the data to be read can be one double word or two double words, when the first read pointer dw_rptr is located at the last double word of a storage slice, the read enable of two memories needs to be opened at the same time, as shown in Table 2.

[0061] Table 2

[0062]

[0063] For example, Mem0_REn, Mem1_REn, Mem2_REn and Mem3_REn represent the read enable of the four memories respectively, and the number 1 represents the enable state (Enable) and the number 0 represents the disable state (Disable). For example, as shown in Table 2, FIG. 2A As shown, the four storage slices are located in four different memories respectively, and the values 0, 1, 2, …, 14, 15 of the first read pointer dw_rptr correspond to the addresses of the double words dw in an instruction cache area respectively. For example, when the value of the first read pointer dw_rptr is 3, the first read pointer dw_rptr is located at the last double word of the first storage slice, and the read enable of the memory Mem0 and the memory Mem1 needs to be opened at the same time; when the value of the first read pointer dw_rptr is 7, the first read pointer dw_rptr is located at the last double word of the second storage slice, and the read enable of the memory Mem1 and the memory Mem2 needs to be opened at the same time; when the value of the first read pointer dw_rptr is 11, the first read pointer dw_rptr is located at the last double word of the third storage slice, and the read enable of the memory Mem2 and the memory Mem3 needs to be opened at the same time; when the value of the first read pointer dw_rptr is 15, the first read pointer dw_rptr is located at the last double word of the fourth storage slice, and the read enable of the memory Mem0 and the memory Mem3 needs to be opened at the same time.

[0064] As shown above, the instruction scheduler and the instruction cache area in the current parallel processor are respectively designed with dedicated hardware resources for the M sets of work items that the parallel processor can run at most to fetch and cache instructions, that is, the instruction cache area is fixedly divided to the corresponding set of work items, and the size of the instruction cache area corresponding to each set of work items cannot be adjusted according to the actual demand. However, sometimes the user's computing task is not so large and intensive, and it cannot be guaranteed that the M sets of work items are simultaneously run in parallel at the same time, so the instruction cache area of the set of work items that is not running will be idle all the time, and these hardware resources cannot be effectively utilized in this period of time, resulting in waste of the hardware resources of the instruction cache area corresponding to these sets of work items.

[0065] The present disclosure provides a data processing method and a data processing apparatus. The data processing method comprises: obtaining a number P of sets of work items that need to be run in parallel corresponding to a current computing task; configuring the M instruction cache areas according to the number P of sets of work items to obtain a plurality of cache partitions, wherein in response to the number P of sets of work items being less than M, the size of each cache partition is greater than the size of the one instruction cache area; and setting a jump range of a pointer of the each cache partition.

[0066] The data processing method reconfigures and divides the instruction cache area by obtaining the number of sets of work items that need to be run in parallel for the current computing task, fully utilizes the hardware resources of the instruction cache area corresponding to the set of work items that is not executed for the computing task, and reduces the waste of hardware resources.

[0067] FIG. 3 is a flowchart of a data processing method provided by at least one embodiment of the present disclosure, as shown in FIG. 3 For example, the data processing method can at least include steps S101-S103.

[0068] For example, the data processing method is applied to a parallel processor that can support M sets of work items to run in parallel at most, and comprises M instruction cache areas corresponding to the M sets of work items respectively. For related introduction of the parallel processor, please refer to the related content of FIG. 1A to FIG. 2C , which will not be described here again. For example, since only one SIMD processor is in a running state at the same time, the parallel processor here can refer to a SIMD processor.

[0069] In step S101, a number P of sets of work items that need to be run in parallel corresponding to a current computing task is obtained.

[0070] For example, the maximum number of sets of work items that need to be run in parallel by the parallel processor when executing the current computing task can be automatically predicted by an algorithm, an application, etc., and the maximum number is taken as the number of sets of work items P, i.e., the size of each instruction cache area is dynamically configured.

[0071] For example, the maximum number of sets of work items that need to be run in parallel by the parallel processor when executing the current computing task can be automatically predicted by an algorithm, an application, etc., and the maximum number is taken as the number of sets of work items P, i.e., the size of each instruction cache area is dynamically configured.

[0072] In step S102, the M instruction cache areas are configured to obtain a plurality of cache partitions according to the number of sets of work items P.

[0073] For example, in response to the number of sets of work items P being less than M, the size of each cache partition is greater than the size of one instruction cache area. That is, if M sets of work items do not need to be run in parallel at the same time, the M instruction cache areas are reconfigured in space so that the P sets of work items currently running are allocated the M instruction cache areas, and the size of the cache partition corresponding to each set of work items that needs to be run is greater than the size of the one instruction cache area that it can originally allocate.

[0074] For example, step S102 can include: allocating the M instruction cache areas evenly into N cache partitions, where N is a positive integer and is greater than or equal to P and less than M.

[0075] FIG. 4 For FIG. 3 A schematic flowchart of step S102 in the data processing method shown in FIG. 1 is shown in FIG. 2. As shown in FIG. 2, step S102 includes at least steps S1021-S1023. FIG. 4

[0076] In step S1021, the total number of storage tiles included in the M instruction cache areas is determined.

[0077] For example, each instruction cache area includes c storage tiles, and thus the M instruction cache areas include a total of c*M storage tiles. For example, as shown in FIG. 3, each instruction cache area includes 4 storage tiles, and thus the M instruction cache areas include a total of 40 storage tiles. FIG. 2A

[0078] In step S1022, the total number of cache partitions N is determined according to the total number of storage tiles and the number of sets of work items P.

[0079] ​​For example, in response to the total number of storage chips being divisible by P, the number P of work item sets is taken as the total number N of cache partitions; in response to the total number of storage chips not being divisible by P, a selected number greater than and closest to P is selected from a plurality of selected numbers that can divide the total number of storage chips as the total number N of cache partitions.

[0080] For example, when the total number of storage chips is 40 and P is 4, the total number of storage chips is divisible by P, and P is selected as the total number N of cache partitions, i.e., the total number N of cache partitions is 4, and then the 40 storage chips are evenly distributed according to the total number N of cache partitions.

[0081] For example, when the total number of storage chips is 40 and P is 6, the total number of storage chips is not divisible by P, and a selected number greater than and closest to P is selected from a plurality of selected numbers (i.e., 2, 4, 5, 8, 10, 20) that can divide 40 as the total number N of cache partitions, i.e., the total number N of cache partitions can be 8.

[0082] In the case that the total number of storage chips is not divisible by P, 100% space utilization of the M instruction cache areas is not achieved, and there is still a small amount of free space, but the size of the cache partition obtained by this distribution method is still greater than the size of the original one instruction cache area.

[0083] For example, in some embodiments, the selection range of P can be limited, i.e., P needs to be able to divide the total number of storage chips, and in this case, 100% utilization of the M instruction cache areas can be achieved, and there is no wasted free space, and the hardware resource utilization rate is significantly improved.

[0084] In step S1023, the M instruction cache areas are evenly distributed into N cache partitions.

[0085] For example, each cache partition includes n storage chips, n is a positive integer and is the ratio of the total number of storage chips to N.

[0086] For example, the total number of storage chips can be 40, and N can be 4, so the number n of storage chips included in each cache partition is 40 / N, i.e., 10.

[0087] In step S103, the jump range of the pointer of each cache partition is set.

[0088] For example, the plurality of cache partitions obtained due to the reconfiguration of the instruction cache areas in step S102, the cache partition at this time can include a plurality of instruction cache areas, and the jump range of the pointer in each cache partition needs to be adjusted accordingly.

[0089] For example, step S103 can include determining the jump step of the pointer, and making the pointer jump in the cache partition according to the jump step.

[0090] For example, the pointers include a write pointer and a read pointer, the write pointer can be the write pointer wptr as described above, and the read pointer can be the first read pointer dw_rptr and the second read pointer rptr as described above.

[0091] For example, each cache partition can be divided into a plurality of sub-storage areas according to a preset storage length, the plurality of sub-storage areas correspond to a plurality of address numbers one by one, each cache partition includes a first end and a second end, and the plurality of address numbers are sequentially increased in the direction from the first end to the second end.

[0092] For example, the preset storage length can be determined according to the jump step of the pointer. For example, for the write pointer wptr and the second read pointer rptr, the preset storage length can be the length of 1 storage slice, for example, as shown in the storage slice structure, the preset storage length can be 4 double words. For example, for the first read pointer dw_rptr, the preset storage length can be the minimum jump step of the first read pointer, for example, 1 double word. FIG. 2A

[0093] The cache partition is divided into a plurality of sub-storage areas according to a preset storage length, each sub-storage area corresponds to an address number, one end of the jump of the pointer in the cache partition is the first end, and the other end is the second end. For example, the address number of the first sub-storage area located at the first end in the cache partition is 0, and the address numbers of the sub-storage areas are sequentially 1, 2, 3… in the direction from the first end to the second end. For example, the address number can be marked at the position of the first double word of the sub-storage area.

[0094] For example, so that the pointer jumps in the cache partition according to the jump step, which can include: determining a first target address number, for example, the first target address number can be the sum of the address number of the current sub-storage area of the pointer and the jump step; in response to the first target address number being less than or equal to the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the first target address number in the next jump, and in response to the first target address number being greater than the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the second target address number in the next jump, for example, the second target address number can be the remainder of the first target address number and the total number of the plurality of address numbers.

[0095] For example, the read pointer includes the first read pointer dw_rptr and the second read pointer rptr, the write pointer wptr indicates the write position of the next instruction, the first read pointer dw_rptr is used to indicate the position of the current instruction to be read, and the second read pointer rptr is used to indicate the storage slice where the current instruction to be read is located. For the second read pointer rptr and the write pointer wptr, the cache partition is divided into a plurality of sub-storage areas according to the same preset storage length, and the second read pointer and the write pointer correspond to the same address number range.​

[0096] For example, the first read pointer dw_rptr currently points to address number n, and the jump step is determined according to the relationship between the number of double words of the jump and the preset storage length. For example, when the instruction data is a double-word instruction and the preset storage length is 1 double word, the jump step of the first read pointer dw_rptr is 1; when the instruction data is a four-word instruction and the preset storage length is 1 double word, the jump step of the first read pointer dw_rptr is 2.

[0097] After obtaining the cache partitions, the pointer jump range adjustment as described above is performed on each cache partition, so that the instruction data is sequentially read and written by the read pointer and the write pointer according to a certain rule. Through the above data processing method, the unused instruction cache area is reasonably configured for the running work item set, the size of the instruction cache area of each running work item set is increased, the hardware resources are reasonably utilized, and the storage space waste is reduced.

[0098] For example, as shown in FIG. 1, after step S103, the data processing method provided by at least one embodiment of the present disclosure can further include step S104. FIG. 3

[0099] In step S104, the number of instructions pre-fetched at a time is increased according to the size of each cache partition, or multiple instruction pre-fetching is continuously performed.

[0100] For example, in the case where the cache partition corresponding to a single work item set becomes larger, the instruction scheduler can pre-fetch more instruction data for pre-caching, for example, more instruction data can be pre-fetched at a time or multiple instruction pre-fetching can be continuously performed, so as to ensure that there is enough instruction data to meet the needs of the subsequent execution unit.

[0101] In addition, because the instruction cache is a cache, if there is no hit when the instruction scheduler fetches instructions, the instruction data will be obtained from the next level storage system, which takes a long time and is unpredictable. The processing method provided by at least one embodiment of the present disclosure can flexibly configure a larger instruction cache area for fewer work item sets, thereby reducing the time that the execution unit needs to wait for the instruction scheduler to retrieve instruction data from the instruction cache when the execution rate is faster than the instruction fetching rate, and effectively solving the problem that the instruction execution rate and the instruction scheduler instruction fetching rate do not match in some scenarios.

[0102] It should be noted that the present disclosure does not limit the specific instruction pre-fetching strategy, and any pre-fetching strategy suitable for the size of the cache partition can be used.

[0103] ​For example, the data processing method provided by at least one embodiment of the present disclosure can further include: adjusting the judgment condition of the remaining storage capacity of the cache partition according to the size of each cache partition.

[0104] Since the size of the cache partition is adjusted, the pointer jump range is also adjusted. Based on the numerical relationship between the second read pointer rptr and the write pointer wptr, the number of valid and unexecuted instruction data in the instruction cache area and the remaining storage capacity of the cache partition can be obtained, so that the instruction scheduler performs corresponding instruction fetching and other operations.

[0105] For example, when the second read pointer rptr and the write pointer wptr satisfy rptr+2==wptr or rptr==wptr, it indicates that the remaining storage capacity of the cache partition is sufficient to perform the instruction fetching operation. For example, when rptr+2==wptr, it indicates that the valid instruction data in the instruction cache area is not much, and the size of the executed instruction data exceeds or is equal to the size of the single instruction data fetched. At this time, the instruction cache area is about to be empty, and rptr==wptr indicates that the instruction cache area is empty. That is, when rptr==wptr of the second read pointer rptr and the write pointer wptr is obtained from rptr+2==wptr, it indicates that the cache partition has space to accommodate more instruction data.

[0106] Of course, the judgment condition of the remaining storage capacity can be adaptively modified according to the size of the cache partition, and the present disclosure does not limit this.

[0107] By adjusting the judgment condition of the remaining storage capacity of the cache partition, the data processing method provided by at least one embodiment of the present disclosure can correctly judge the occupation of the instruction cache area under different numbers of work item sets, so that the read and write operations of the instruction data are more efficient, and the resource utilization rate of the parallel processor is improved.

[0108] For example, the following takes the instruction cache area structure shown in FIG. 2A as an example to specifically describe the flow of the data processing method provided by at least one embodiment of the present disclosure.

[0109] As shown in FIG. 2A , the parallel processor can be any SIMD processor, for example, it can be a single instruction multiple data processor 0.

[0110] According to the data processing method provided by at least one embodiment of the present disclosure, first, in step S101, the number P of work item sets that need to be run in parallel corresponding to the current computing task is obtained.

[0111] For example, the number P of work item sets that need to be run in parallel to perform a computing task can be determined in any manner described in step S101, for example, P=4.

[0112] Afterwards, in step S102, M instruction cache areas are configured according to the number P of work item sets to obtain a plurality of cache partitions.

[0113] For example, the M instruction cache areas can be evenly allocated as N cache partitions. For example, the single instruction multiple data processor 0 includes 10 instruction cache areas, each of which includes 4 storage pieces, and the total number of storage pieces is 40. Since the total number of storage pieces 40 can be divided by 4, the number P of work item sets can be taken as the total number N of cache partitions, that is, N = 4, that is, the 10 instruction cache areas are evenly allocated as 4 cache partitions, and each cache partition contains 40 / 4 = 10 storage pieces.

[0114] Afterwards, in step S103, the jump range of the pointer of each cache partition is set. The specific setting of the jump range will be described later, and will not be described here.

[0115] It should be noted that the above steps can also be performed on the single instruction multiple data processor 1, the single instruction multiple data processor 2 and the single instruction multiple data processor 3, so that the 10 instruction cache areas in the single instruction multiple data processor 1, the single instruction multiple data processor 2 and the single instruction multiple data processor 3 are evenly allocated according to the total number N of cache partitions.

[0116] For example, the number N of cache partitions can be 2, 4, 5, 8, 10, so as to realize 100% utilization of hardware resources. When N = 10, the size of the cache partition is the same as the size of the instruction cache area, and when N = 2, 4, 5, 8, the size of the cache partition is 5 times, 2.5 times, 2 times and 1.25 times the size of the instruction cache area, respectively, which expands the space size of each running work item set for caching instructions, greatly ensuring the number of effective unexecuted instruction data in the instruction cache area.

[0117] For example, each SIMD processor can be divided by the same total number N of cache partitions, for example, the 10 cache partitions in each SIMD processor are divided according to N = 4, so as to obtain FIG. 5A The structure diagram of the cache partition is shown.

[0118] FIG. 5A The structure diagram of the instruction cache area provided by at least one embodiment of the present disclosure is shown. As shown in FIG. 5AAs shown, the instruction cache corresponding to each MIMO (Single Instruction Multiple Data) processor can be reconfigured into 4 cache partitions based on 4 work item sets. For example, the 10 instruction caches corresponding to MIMO 0 can be reconfigured into 4 cache partitions based on 4 work item sets (work item set 0_0, work item set 1_0, work item set 2_0, and work item set 3_0). The 4 MIMO processors will then correspond to a total of 4 * 4 = 16 cache partitions.

[0119] For example, cache partition 1 is the cache partition corresponding to the work item set 0_0 in the Single Instruction Multiple Data Processor 0. FIG. 5A As shown, cache partition 1 can be composed of 10 memory segments of the same level depth, namely memory segments Mem0, Mem1, ..., Mem9, that is, 10 memory segments of memory segments 0, 1, ..., 9. Each memory segment includes 4 double-word storage spaces. Therefore, cache partition 1 includes 40 double-word storage spaces from dw0 to dw39. FIG. 5A The same principle applies to other cache partitions. The internal structure of each memory chip and the corresponding memory for each memory chip... FIG. 2A The situation is the same as shown, so it will not be repeated here.

[0120] FIG. 5B This is a schematic diagram of a write pointer jump provided in at least one embodiment of the present disclosure. FIG. 5C This is a schematic diagram of the jump of the read pointer provided for at least one embodiment of the present disclosure.

[0121] The following example uses N=4, combined with FIG. 5A , FIG. 5B and FIG. 5C The specific execution process of step S103 will be explained.

[0122] like FIG. 5B As shown, with FIG. 5A Taking the cache partition 1 corresponding to the work item set 0_0 processed by the single instruction multiple data processor 0 in the example, this paper specifically explains the jump mode, jump range, and memory enable status of the write pointer wptr, the second read pointer rptr and the first read pointer dw_rptr of the cache partition 1.

[0123] For example, the jump step size of the write pointer wptr is 4 double words, so the preset storage length can be 4 double words. The cache partition 1 corresponding to work item set 0_0 has a total of 40 double words, for example, it could be like this: FIG. 5AThe dw0 to dw39 in the dashed box, so the cache partition 1 can be divided into 10 (40 / 4) sub-storage areas. The 10 sub-storage areas correspond to the 10 address numbers 0, 1, 2, …, 9, and the first end of the cache partition 1 can be the sub-storage area numbered 0, and the second end can be the sub-storage area numbered 9. The address numbers 0, 1, 2, …, 9 are sequentially increased along the direction from the first end (address number 0) to the second end (address number 9).

[0124] For example, the value of the write pointer wptr can represent the position of the next instruction data to be written in the sub-storage area of the cache partition 1. For example, the write pointer wptr can have 10 values, such as 0, 1, …, 9, and the 10 values correspond to the starting positions of each storage slice (storage slice 0 to storage slice 9) in the cache partition 1, respectively. For example, the size of the instruction data written into the cache partition 1 at a time can be fixed at 8 double words. Of course, different parallel processors can have different settings, such as 4 double words, 16 double words, etc. The present disclosure does not limit this.

[0125] For example, since the size of the instruction data written into the cache partition 1 at a time is 8 double words, and the size of each sub-storage area is 4 double words, two sub-storage areas need to be written at a time when writing instruction data. According to the change of the address number, the jump step of the write pointer wptr can be set to 2. Therefore, as shown in FIG. 2, the write pointer wptr can be cyclically jumped between the address numbers 0, 2, 4, …, 6, 8 or the address numbers 1, 3, …, 7, 9. FIG. 5B

[0126] For example, after the instruction scheduler retrieves the instruction data from the instruction cache, the instruction data is written into the cache partition at the position specified by the write pointer wptr. The value of the current write pointer wptr can be 0, for example, which corresponds to the position of the cache partition dw0 and points to the starting position of the first storage slice. After the first instruction data is retrieved and written into the position pointed to by the write pointer wptr, that is, the area corresponding to the 8 double words of dw0 to dw7, the first target address number is determined to be 2 (0+2). Since the first target address number is less than the maximum address number 9, the value of the write pointer wptr jumps from 0 to 2. After the second instruction data is retrieved and written into the sub-storage area at the address number 2, the first target address number is determined to be 4 (2+2). Since the first target address number is less than the maximum address number 9, the value of the write pointer wptr jumps from 2 to 4, and so on.

[0127] ​Continuing to write instruction data to the cache partition according to the above writing mode, and meanwhile, the value of the write pointer wptr is jumped, for example, the value of the write pointer wptr is jumped to 8, after the instruction data is written, the first target address number is 10 (8+2) at this time, since the first target address number is greater than the maximum address number 9, the write pointer wptr is jumped to the second target address number 0, the second target address number 0 is the remainder of the first target address number 10 and the total number of the address numbers 10, thus, the write pointer wptr points to the next position in the cache partition 1, for example, the start position dw0 of the first memory slice, then the above cycle is continued.

[0128] As mentioned above, when writing instruction data to the cache partition, the write enable of the two memories corresponding to the two continuous memory slices needs to be opened, the write enable change is shown in Table 3. For example, Mem0_WEn, Mem1_WEn, …, Mem9_WEn represent the write enable of the 10 memories respectively, the number 1 represents the enable state (Enable), the number 0 represents the disable state (Disable), the value of the write pointer wptr is 0, 1, 2, …, 9 respectively corresponds to the start position of the 10 memory slices (memory slice 0-memory slice 9) in the cache partition 1. FIG. 5A The start position of the 10 memory slices (memory slice 0-memory slice 9) in the cache partition 1.

[0129] Table 3

[0130]

[0131] When the write pointer wptr is 0, it points to the starting position of memory segment 0. Therefore, the write enable Mem0_WEn of the memory segment Mem0 corresponding to memory segment 0 needs to be set to 1. Simultaneously, the write enable of the memory segment Mem1, which is contiguous with Mem0, needs to be enabled, and the write enable Mem1_WEn of Mem1 needs to be set to 1. When the write pointer wptr is 1, it points to the starting position of memory segment 1. The write enable Mem1_WEn of the memory segment Mem1 corresponding to memory segment 1 needs to be set to 1. Simultaneously, the write enable of the memory segment Mem2, which is contiguous with Mem1, needs to be enabled, and the write enable Mem2_WEn of Mem2 needs to be set to 1. Furthermore, the write enable of Mem0 needs to be disabled, i.e., Mem0_Wen needs to be set to 0. When the write pointer wptr is 2, it points to... The starting position of memory chip 2 requires setting the write enable Mem2_WEn of memory chip 2 to 1, and simultaneously enabling the write enable of memory chip 3, which is contiguous with memory chip 2, by setting the write enable Mem3_WEn of memory chip 3 to 1, and disabling the write enable of memory chip 1, i.e., setting Mem1_Wen to 0. When the write pointer wptr is 3, pointing to the starting position of memory chip 3, the write enable Mem3_WEn of memory chip 3 is set to 1, and simultaneously enabling the write enable of memory chip 4, which is contiguous with memory chip 3, by setting the write enable Mem4_WEn of memory chip 4 to 1, and disabling the write enable of memory chip 2, i.e., setting Mem2_Wen to 0.

[0132] When the value of the write pointer wptr is 5 to 9, it is similar to the case when the value of the write pointer wptr is 0 to 4, which will not be elaborated here.

[0133] For example, such as FIG. 5C As shown, for the first read pointer dw_rptr, the preset storage length can be one double word. Cache partition 1 has a total of 40 double words, for example, dw0 to dw39, thus the cache partition can be divided into 40 sub-storage areas. For example, for the first read pointer dw_rptr, the 40 sub-storage areas correspond one-to-one with 40 address numbers 0, 1, 2, ..., 39. At the same time, the first end of cache partition 1 can be the sub-storage area with address number 0, and the second end of cache partition 1 can be the sub-storage area with address number 39. The address numbers 0, 1, 2, ..., 39 increase sequentially from the first end (address number 0) to the second end (address number 39).

[0134] like FIG. 5CAs shown, the first read pointer dw_rptr can actually point to the next instruction to be executed. The jump range of the first read pointer dw_rptr can be, for example, 0 to 39, which is the total number of double words that cache partition 1 can hold, 40. For example, the jump step size of the first read pointer dw_rptr can be set to 1 or 2. When the jump step size is 1, it means that the instruction data to be read is a double-word instruction; when the jump step size is 2, it means that the instruction data to be read is a quad-word instruction.

[0135] For example, the first read pointer dw_rptr can cyclically jump between 0 and 39 according to the jump step size.

[0136] For example, the first read pointer dw_rptr currently points to address 0, meaning it points to the beginning of memory segment 0. FIG. 5C In the context of dw0, if the jump step size of the first read pointer dw_rptr is 1, the first target address number can be 1 (0+1). This is because the first target address number 1 is less than the maximum value of the multiple address numbers corresponding to the first read pointer dw_rptr, which is 39. Therefore, the first read pointer dw_rptr will jump to the sub-memory area dw1 corresponding to the first target address number 1 in the next jump. Thus, the first read pointer dw_rptr jumps from address number 0 to address number 1. After the first read pointer dw_rptr jumps (e.g., ... FIG. 5C 1 at dw0 to dw1 st The first read pointer (dw_rptr) points to dw1; for example, if the jump step size of the first read pointer dw_rptr is 2, the first target address number can be 2 (0+2), so the first read pointer dw_rptr will jump to the sub-memory area dw2 corresponding to the first target address number 2 in the next jump. Therefore, the first read pointer dw_rptr jumps from address number 0 to address number 2, and after the first read pointer dw_rptr jumps (as... FIG. 5C 2 at dw0 to dw2 nd next) points to dw2.

[0137] For example, when the first read pointer dw_rptr currently points to address 38, that is, when the first read pointer dw_rptr points to sub-memory area dw38, if the jump step size of the first read pointer dw_rptr is 1, the first target address number can be 39 (38+1). Therefore, the first read pointer dw_rptr will jump to the sub-memory area dw39 corresponding to the first target address number 39 in the next jump. So, the first read pointer dw_rptr jumps from address 38 to address 39. After the first read pointer dw_rptr jumps (as... FIG. 5C 1 at dw38 to dw39 stnext) points to dw39; for example, if the jump step of the first read pointer dw rptr is 2, the first target address number can be 40 (38+2), because the first target address number 40 is greater than the maximum value 39 of the plurality of address numbers corresponding to the first read pointer dw rptr, so that the first read pointer dw rptr jumps to the second target address number corresponding sub-storage area when next time jumping, the second target address number can be the remainder of the first target address number 40 and the total number of the plurality of address numbers 40, that is, the second target address number is 0, so that the first read pointer dw rptr jumps from the address number 38 to the address number 0, and the first read pointer dw rptr jumps (for example, FIG. 5C 2 in dw38 to dw0 in nd next) points to dw0.

[0138] For example, when the first read pointer dw rptr currently points to the address number 39, that is, the first read pointer dw rptr points to the sub-storage area dw39, if the jump step of the first read pointer dw rptr is 1, the first target address number can be 40 (39+1), referring to the content as described above, the first read pointer dw rptr jumps from the address number 39 to the address number 0, and the first read pointer dw rptr jumps (for example, FIG. 5C 1 in dw39 to dw0 in st next) points to dw0; for example, if the jump step of the first read pointer dw rptr is 2, the first target address number can be 41 (39+2), and the second target address number is 1, so that the first read pointer dw rptr jumps from the address number 39 to the second address number 11, and the first read pointer dw rptr jumps (for example, FIG. 5A 2 in dw39 to dw1 in nd next) points to the storage address dw1.

[0139] It should be noted that the above embodiments are only illustrative descriptions, different instructions can correspond to different bit widths, for example, the instruction data can be 32 bits or 64 bits, etc., according to the length of the instruction data to be read each time, the jump step of the first read pointer dw rptr can be 1 or 2, of course, the jump step of the first read pointer dw rptr can also be other values, for example, when the instruction data is 128 bits, the jump step can also be 4, and the present disclosure does not limit this.

[0140] For example, for the second read pointer rptr, the preset storage length can be 4 double words, and the cache partition 1 has a total of 40 double words, so that the cache partition 1 can be divided into 40 / 4, that is, 10 sub-storage areas, for example, the 10 sub-storage areas can be FIG. 5CThe ten sub-memory areas are memory chips 0 through 9. For example, for the second read pointer rptr, these ten sub-memory areas correspond one-to-one with ten address numbers (0, 1, 2, ..., 9). At the same time, the first end of cache partition 1 can be the sub-memory area with address number 0, and the second end of cache partition 1 can be the sub-memory area with address number 9. The address numbers 0, 1, 2, ..., 9 increase sequentially along the direction from the first end (address number 0) to the second end (address number 9) of cache partition 1.

[0141] like FIG. 5C As shown, for example, the second read pointer rptr can have 10 values, such as 0, 1, 2, ..., 9, pointing to address numbers 0 to 9 respectively. For example, the second read pointer rptr jumps 4 double words at a time, and the size of each sub-memory area of ​​the second read pointer rptr is also 4 double words, therefore the jump step size of the second read pointer rptr can be 1. For example, the second read pointer rptr can cyclically jump between 0 and 9:

[0142] For example, the second read pointer rptr currently points to address 0 (e.g., the location of dw0 in cache partition 1), which is the starting position of the first sub-memory area / memory slice 0. When the instruction data to be read is located in the second sub-memory area, the second read pointer rptr jumps. At this time, the first target address number can be 1 (0+1). The second read pointer rptr jumps from address 0 to address 1. After the second read pointer rptr jumps (e.g....), FIG. 5C The next pointer (dw0 to dw4) points to dw4, which is the starting position of the second sub-memory area / memory piece 1. When the instruction data to be read is located in the third sub-memory area, the second read pointer rptr jumps. At this time, the first target address number can be 2 (1+1). The second read pointer rptr jumps from address number 1 to address number 2. After the second read pointer rptr jumps (as shown in the image), the second read pointer rptr jumps to the third sub-memory area. FIG. 5C The next pointer (dw4 to dw8) points to dw8, which is the starting position of the third sub-memory area / memory piece 2. Similarly, the second read pointer rptr jumps sequentially in the same way until it jumps to the last sub-memory area, which is the starting position of memory piece 9. Then, in the next jump (e.g., ... FIG. 5A When the loop iterates from dw36 to dw0 (next), it jumps to address 0 and points to dw0, completing one loop.

[0143] After that, the second read pointer rptr continues to execute the above loop jump, and the repeated parts will not be described again.

[0144] As mentioned earlier, when reading instruction data from the cache partition, it is necessary to enable the read enable of the two memories corresponding to two consecutive memory chips. The changes in read enable are shown in Table 4.

[0145] Table 4

[0146]

[0147]

[0148] For example, Mem0_Ren, Mem1_Ren, Mem2_Ren,..., Mem9_REn represent the read enable of the memory Mem0 to the memory Mem9 in the 10 memories respectively, and the number 1 represents the available state (Enable) and the number 0 represents the unavailable state (Disable). FIG. 5A For example, as shown in the table 4, the 10 memory chips are respectively located in the 10 different memories, and the values 0, 1, 2,..., 38, 39 of the first read pointer dw_rptr correspond to the double words dw0 to dw39 in the cache partition respectively. FIG. 6

[0149] For example, when the value of the first read pointer dw_rptr is 0-3, it points to the double words dw0 to dw3 and all belong to the memory chip 0, therefore it is needed to set the read enable Mem0_REn of the memory Mem0 corresponding to the memory chip 0 to 1, and open the read enable of the memory Mem1 continuous to the memory Mem0 when the value of the first read pointer dw_rptr is 3, and set the read enable Mem1_REn of the memory Mem1 to 1; when the value of the first read pointer dw_rptr is 4-7, it points to the double words dw4 to dw7 and all belong to the memory chip 1, therefore it is needed to set the read enable Mem1_REn of the memory Mem1 corresponding to the memory chip 1 to 1, and close the read enable of the memory Mem0, that is, set the read enable Mem0_REn of the memory Mem0 to 0, and open the read enable of the memory Mem2 continuous to the memory Mem1 when the value of the first read pointer dw_rptr is 7, and set the read enable Mem2_REn of the memory Mem2 to 1; for example, when the value of the first read pointer dw_rptr is 8-11, it points to the double words dw8 to dw11 and all belong to the memory chip 3, therefore it is needed to set the read enable Mem3_REn of the memory Mem3 corresponding to the memory chip 3 to 1, and close the read enable of the memory Mem1, that is, set the read enable Mem1_REn of the memory Mem1 to 0, and open the read enable of the memory Mem3 continuous to the memory Mem3 when the value of the first read pointer dw_rptr is 11, and set the read enable Mem3_REn of the memory Mem3 to 1.

[0150] When the value of the first read pointer dw_rptr is 12-39, it is similar to the case when the value of the first read pointer dw_rptr is 0-3, 4-7 or 8-11, which will not be repeated here. ​

[0151] Thus, in the case that the cache partition is reconfigured and divided into multiple cache partitions according to the number of work item sets, the jump range and jump step of the read pointer of the instruction data can be reconfigured, and the instruction data can be read in order by the read pointer from the instruction cache area according to a certain instruction data length, for example, the instruction data is read from the cache partition in a cycle according to a certain pointer jump step, according to the above-mentioned manner.

[0152] Similarly, when N = 2, 5, 8, the jump range of the pointer of each cache partition is adjusted according to the above-mentioned manner.

[0153] For example, when N = 2, each cache partition includes 20 storage pieces, each storage piece includes 4 double words, for the write pointer wptr and the second read pointer rptr, the preset storage length is 4 double words, the cache partition is divided into 20 sub-storage areas, and the 20 sub-storage areas correspond to address numbers 0-19 respectively. As described above, the jump step of the write pointer wptr is 2 (8 double words), and the jump step of the second read pointer rptr is 1 (4 double words). Therefore, the jump range of the write pointer wptr is 0->2->4->6->8->10->12->14->16->18->0, and the jump range of the second read pointer rptr is 0->1->2->3->4->5->6->7->8->9->10->11->12->13->14->15->16->17->18->19->0. For the first read pointer dw_rptr, the preset storage length is 1 double word, the cache partition is divided into 80 sub-storage areas, and the 80 sub-storage areas correspond to address numbers 0-79 respectively. As described above, the jump step of the first read pointer dw_rptr is 1 (1 double word) or 2 (2 double words). Therefore, the jump range of the first read pointer dw_rptr is 0-79. The jump step is selected to be 1 or 2 according to the different types of instruction data. For example, when the first read pointer dw_rptr jumps to 79, the first read pointer dw_rptr jumps to 0 when the length of the next instruction data is 1 double word.

[0154] It should be noted that in the above embodiment, the length of the storage piece, the jump step of the write pointer, the jump step of the second read pointer, and the jump step of the first read pointer are taken as examples for description, but the present disclosure is not limited thereto, and the length of the storage piece and the jump step can be changed as needed by those skilled in the art.

[0155] For example, when N=5, each cache partition includes 8 storage pieces, each storage piece includes 4 double words, for the write pointer wptr and the second read pointer rptr, the preset storage length is 4 double words, the cache partition is divided into 8 sub-storage areas, and the 8 sub-storage areas correspond to address numbers 0-7 respectively. As described above, the jump step of the write pointer wptr is 2 (8 double words), and the jump step of the second read pointer rptr is 1 (4 double words). Therefore, the jump range of the write pointer wptr is 0->2->4->6->0, and the jump range of the second read pointer rptr is 0->1->2->3->4->5->6->7->0. For the first read pointer dw_rptr, the preset storage length is 1 double word, the cache partition is divided into 32 sub-storage areas, and the 32 sub-storage areas correspond to address numbers 0-31 respectively. As described above, the jump step of the first read pointer dw_rptr is 1 (1 double word) or 2 (2 double words). Therefore, the jump range of the first read pointer dw_rptr is 0-31. The jump step is selected to be 1 or 2 according to different types of instruction data. For example, when the first read pointer dw_rptr jumps to 31, the first read pointer dw_rptr jumps to 0 when the length of the next instruction data is 1 double word.

[0156] For example, when N=8, each cache partition includes 5 storage pieces, each storage piece includes 4 double words, for the write pointer wptr and the second read pointer rptr, the preset storage length is 4 double words, the cache partition is divided into 5 sub-storage areas, and the 5 sub-storage areas correspond to address numbers 0-4 respectively. As described above, the jump step of the write pointer wptr is 2 (8 double words), and the jump step of the second read pointer rptr is 1 (4 double words). Therefore, the jump range of the write pointer wptr is 0->2->4->1->3->0, and the jump range of the second read pointer rptr is 0->1->2->3->4->0. For the first read pointer dw_rptr, the preset storage length is 1 double word, the cache partition is divided into 20 sub-storage areas, and the 20 sub-storage areas correspond to address numbers 0-19 respectively. As described above, the jump step of the first read pointer dw_rptr is 1 (1 double word) or 2 (2 double words). Therefore, the jump range of the first read pointer dw_rptr is 0-19. The jump step is selected to be 1 or 2 according to different types of instruction data. For example, when the first read pointer dw_rptr jumps to 19, the first read pointer dw_rptr jumps to 0 when the length of the next instruction data is 1 double word.

[0157] According to the data processing method provided by at least one embodiment of the present disclosure, the different number of work item sets enables the data processing method to be compatible with a plurality of different numbers of work item sets, and the instruction cache area is reconfigured according to the actual number of work item sets to obtain a plurality of cache partitions with different configurations. Meanwhile, the instruction data reading and writing mode corresponding to the different cache partition configurations is obtained, and thus the resource utilization rate of the parallel processor can be improved under different numbers of work item sets.

[0158] For example, the number of valid and unexecuted instruction data in the instruction cache area and the size of the idle space in the instruction cache area can be obtained according to the write pointer wptr, the second pointer rptr and the first read pointer dw_rptr, so as to control the instruction scheduler to perform corresponding instruction fetching and other operations. The flowchart of the whole process is shown in FIG. 6 .

[0159] FIG. 6 The schematic diagram of the reading and writing flow of instruction data provided by at least one embodiment of the present disclosure is shown in FIG. 5A and FIG. 6 . The reading and writing flow of instruction data is specifically described below.

[0160] As shown in FIG. 5A , if the cache partition is empty or will be empty, the instruction scheduler reads instruction data from the instruction cache, for example, instruction data with a length of 8 double words can be read, and the instruction scheduler writes the instruction data into the cache partition, for example, the read instruction data can be written into two continuous storage chips on the cache partition.

[0161] Then, the write pointer wptr jumps to the next write position, for example, if the write pointer wptr currently points to the address number 0, it jumps to the address number 2.

[0162] Then, the instruction scheduler performs the related operation of reading instructions, and after the reading instruction operation is performed, the first read pointer dw_rptr jumps by a corresponding length according to the size of the instruction data. For example, the first read pointer dw_rptr can be cyclically jumped by a jump step of 1 or 2 between the address number 0 and the address number A (for example, A is 39 for the cache partition shown in FIG. 5A ).

[0163] Simultaneously, it is determined whether the first read pointer dw_rptr points to the next memory slice. If the first read pointer dw_rptr points to the next memory slice, the value of the second read pointer rptr is incremented by 1, and the value of the second read pointer rptr is increased to the maximum address number B corresponding to the second read pointer rptr (for example, for a memory slice such as...). FIG. 6 The cache partition shown is B=9). The next jump will be to address 0, which is the second read pointer rptr=0.

[0164] For example, such as FIG. 5A As shown, the write pointer wptr and the second read pointer rptr can be used to determine whether the instruction buffer is empty or about to be empty. For example, for... FIG. 7 The cache partition shown is considered empty or has space to receive the next instruction data when it satisfies rptr! = wptr or rptr-1! = wptr, that is, when rptr is not equal to wptr or rptr-1 is not equal to wptr. The instruction scheduler can then perform the instruction fetch operation.

[0165] At least one embodiment of this disclosure also provides a data processing apparatus. FIG. 7 This is a schematic diagram of a data processing apparatus provided in at least one embodiment of the present disclosure.

[0166] like FIG. 8 As shown, for example, the data processing device 100 may include an acquisition unit 101 and a configuration unit 102.

[0167] For example, the acquisition unit 101 can be configured to acquire the number P of the set of work items that need to be run in parallel corresponding to the current computing task.

[0168] Configuration unit 102 can be configured to configure M instruction buffers to obtain multiple buffer partitions according to the number of work item sets P, and set the jump range of the pointer of each buffer partition. Here, in response to the number of work item sets P being less than M, the size of each buffer partition is greater than the size of an instruction buffer.

[0169] For example, the acquisition unit 101 can be a register that can pre-store the number of work item sets P. For example, the user can pre-determine the maximum number of work item sets P that need to be run for the current computing task and write the number of work item sets P into the data processing device through the register.

[0170] For example, when the acquisition unit 101 is configured to acquire the number P of work items that need to be run in parallel corresponding to the current computing task, it includes the following steps: predicting the maximum number of work items that the parallel processor needs to run in parallel when executing the current computing task, and taking the maximum number as the number of work items P.

[0171] For example, the configuration unit 102 comprises an allocating subunit and a setting subunit.

[0172] For example, the allocating subunit is configured to perform the following operation when configuring the M instruction cache areas according to the number P of work item sets: evenly allocating the M instruction cache areas into N cache partitions, where N is a positive integer and is greater than or equal to P and less than M.

[0173] For example, each instruction cache area comprises a plurality of storage pieces, and the allocating subunit performs the following operation when evenly allocating the M instruction cache areas into N cache partitions: determining a total number of storage pieces included in the M instruction cache areas; determining the total number N of cache partitions according to the total number of storage pieces and the number P of work item sets; and evenly allocating the M instruction cache areas into N cache partitions, for example, each cache partition comprises n storage pieces, where n is a positive integer and is a ratio of the total number of storage pieces to N.

[0174] For example, the allocating subunit performs the following operation when determining the total number N of cache partitions according to the total number of storage pieces and the number P of work item sets: in response to the total number of storage pieces being divisible by P, taking the number P of work item sets as the total number N of cache partitions; and in response to the total number of storage pieces being not divisible by P, selecting a selected number greater than and closest to P from a plurality of selected numbers that can divide the total number of storage pieces as the total number N of cache partitions.

[0175] For example, the setting subunit performs the following operation when setting the jump range of the pointer of each cache partition: determining a jump step of the pointer, and making the pointer cyclically jump in the cache partition according to the jump step, for example, the pointer comprises a write pointer and a read pointer.

[0176] For example, each cache partition is divided into a plurality of sub-storage areas according to a preset storage length, the plurality of sub-storage areas correspond to a plurality of address numbers one by one, each cache partition comprises a first end and a second end, and the plurality of address numbers are sequentially increased in the direction from the first end to the second end. The setting subunit performs the following operation when making the pointer cyclically jump in the cache partition according to the jump step: determining a first target address number, where the first target address number is a sum of the address number of the sub-storage area where the pointer currently locates and the jump step; in response to the first target address number being less than or equal to a maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the first target address number at the next jump, and in response to the first target address number being greater than the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to a second target address number at the next jump, where the second target address number is a remainder of the first target address number and a total number of the plurality of address numbers.

[0177] For example, the read pointers include a first read pointer dw_rptr and a second read pointer rptr, the write pointer wptr is used to indicate a write position of a next instruction, the first read pointer dw_rptr is used to indicate a position of a current instruction to be read, and the second read pointer rptr is used to indicate a storage slice where the current instruction to be read is located. For the second read pointer rptr and the write pointer wptr, the cache partition is divided into a plurality of sub-storage areas according to a same preset storage length, and the second read pointer rptr and the write pointer wptr correspond to a same address number range.

[0178] The configuration unit 102 can include a plurality of sub-configuration units, each of the plurality of sub-configuration units corresponds to a different number P of work item sets, and each of the plurality of sub-configuration units is configured to configure the M instruction cache areas according to the corresponding number P of work item sets to obtain a plurality of cache partitions, and set a jump range of a pointer of each cache partition.

[0179] FIG. 8 A schematic structural diagram of the data processing apparatus provided by at least one embodiment of the present disclosure is shown.

[0180] As shown in FIG. 2A The configuration unit 102 can be configured according to different numbers P of work item sets to obtain a plurality of configuration sub-units. For example, the K different numbers P1, P2, …, PK of work item sets can be used to configure the cache partition to obtain the K configuration sub-units 1021, 1022, …, 102K. K The instruction cache areas are configured as instruction cache area configuration 1, instruction cache area configuration 2, …, and instruction cache area configuration K, and the K instruction cache area configurations correspond to the K configuration sub-units 1021, 1022, …, and 102K, respectively. For example, each configuration sub-unit can configure a plurality of instruction cache areas according to the number P of work item sets to obtain a plurality of cache partitions corresponding thereto. For example, the number P2 of work item sets corresponding to the configuration sub-unit 1022 is 4, so that the plurality of instruction cache areas can be configured by the data processing apparatus provided by at least one embodiment of the present disclosure to obtain the instruction cache area configuration 2. For example, the instruction cache area configuration 2 can be that the plurality of instruction cache areas are divided into 4 cache partitions, and a jump range of a pointer of each cache partition is set according to a size of the cache partition. For example, the write pointer wptr can be configured to jump between the range 0-10, the first read pointer dw_rptr can be configured to jump between the range 0-39, and the second read pointer rptr can be configured to jump between the range 0-19. For example, for the instruction cache area configuration 2, the second read pointer rptr and the write pointer wptr correspond to the same address number range. FIG. 3The instruction cache area structure shown, the number of configuration sub-units can be 5, for example, the instruction cache area configuration 1 obtained by the configuration sub-unit 1021 includes the instruction cache area configuration when N = 2, that is, at this time, 10 instruction cache areas are divided into 2 cache partitions, and the pointer jump range of each cache partition is adjusted, similarly, the instruction cache area configuration 2 obtained by the configuration sub-unit 1022 includes the instruction cache area configuration when N = 4, the instruction cache area configuration 3 obtained by the configuration sub-unit 1023 includes the instruction cache area configuration when N = 5, the instruction cache area configuration 4 obtained by the configuration sub-unit 1024 includes the instruction cache area configuration when N = 8, and the instruction cache area configuration 5 obtained by the configuration sub-unit 1025 includes the instruction cache area configuration when N = 10.

[0181] For example, the data processing apparatus 100 further includes a multiplexer, for example, the multiplexer is configured to select one of the plurality of sub-configuration units according to the number P of the work item set, and perform the instruction fetching operation according to the instruction cache area configuration obtained by the selected sub-configuration unit when the hardware circuit with the data processing apparatus 100 is working.

[0182] For example, the configuration unit 102 includes code and programs stored in a memory; a processor can execute the code and programs to implement some or all of the functions of the configuration unit 102 as described above. For example, the configuration unit 102 can be a special hardware device to implement some or all of the functions of the configuration unit 102 as described above. For example, the configuration unit 102 can be one circuit board or a combination of a plurality of circuit boards for implementing the functions as described above. In the embodiments of the present application, the one circuit board or the combination of a plurality of circuit boards can include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory and executable by the processor.

[0183] It should be noted that the obtaining unit 101 is configured to implement FIG. 3 The configuration unit 102 shown in step S101 is configured to implement FIG. 3 The configuration sub-unit shown in steps S102 and S103 is configured to implement FIG. 3 The setting sub-unit shown in step S103 is configured to implement FIG. 3 The configuration sub-unit shown in step S102 is configured to implement FIG. 3 The configuration sub-unit shown in step S102 is configured to implement FIG. 3 The setting sub-unit shown in step S103 is configured to implement ​ The setting sub-unit shown in step S103 is configured to implement

[0184] The data processing apparatus 100 can achieve similar technical effects as the foregoing data processing method, which reconfigures and divides the instruction cache area by acquiring the number of work item sets that need to be run in parallel for the current computing task, fully utilizes the hardware resources of the instruction cache area corresponding to the work item set of the non-executing computing task, and reduces the waste of hardware resources.

[0185] For the present disclosure, the following points also need to be explained:

[0186] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

[0187] (2) For the sake of clarity, the thickness and size of the layers or structures in the drawings used to describe the embodiments of the present application are exaggerated. It can be understood that when an element such as a layer, film, region or substrate is referred to as being located "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0188] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0189] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing method applied to a parallel processor, the parallel processor being capable of supporting a maximum of M sets of work items running in parallel, and comprising M instruction cache regions corresponding to the M sets of work items respectively, wherein, Each of the M instruction cache areas is configured to temporarily store instruction data executed by a corresponding work item set, The method comprises: acquiring a number P of work item sets corresponding to a current computing task that need to be run in parallel; According to the number P of work item sets, the M instruction cache areas are spatially configured to obtain a plurality of cache partitions, wherein in response to the number P of work item sets being less than M, the size of each cache partition is greater than the size of one instruction cache area; Set the jump range of the pointer of each cache partition; Wherein, each instruction cache area includes a plurality of storage pieces; according to the number P of work item sets, the M instruction cache areas are spatially configured to obtain a plurality of cache partitions, comprising: Determine the total number of storage pieces included in the M instruction cache areas; According to the total number of storage pieces and the number P of work item sets, determine the total number N of cache partitions, N is a positive integer and is greater than or equal to P, less than M; The M instruction cache areas are evenly allocated as N cache partitions.

2. The data processing method of claim 1, wherein, The M instruction cache areas are evenly allocated as N cache partitions, comprising: The M instruction cache areas are evenly allocated as N cache partitions, wherein each cache partition includes n storage pieces, n is a positive integer and is the ratio of the total number of storage pieces to N.

3. The data processing method of claim 2, wherein, According to the total number of storage pieces and the number P of work item sets, determine the total number N of cache partitions, comprising: In response to the total number of storage pieces being divisible by P, the number P of work item sets is taken as the total number N of cache partitions; In response to the total number of storage pieces being unable to be divided by P, a selected number greater than and closest to P is selected from a plurality of selected numbers that can divide the total number of storage pieces as the total number N of cache partitions.

4. The data processing method according to any one of claims 1 to 3, wherein, Setting the jump range of the pointer of each cache partition, comprising: Determine the jump step of the pointer, and make the pointer jump in the cache partition according to the jump step, wherein the pointer includes a write pointer and a read pointer.

5. The data processing method of claim 4, wherein, Each cache partition is divided into a plurality of sub-storage areas according to a preset storage length, and the plurality of sub-storage areas correspond to a plurality of address numbers one by one, Each cache partition includes a first end and a second end, and the plurality of address numbers are sequentially increased in the direction from the first end to the second end, The pointer jumps in the cache partition according to the jump step, comprising: Determine a first target address number, wherein the first target address number is the sum of the address number of the sub-storage area where the pointer is currently located and the jump step; In response to the first target address number being less than or equal to the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the first target address number at the next jump, In response to the first target address number being greater than the maximum value in the plurality of address numbers, the pointer jumps to the sub-storage area corresponding to the second target address number at the next jump, wherein the second target address number is the remainder of the first target address number and the total number of the plurality of address numbers.

6. The data processing method of claim 4, wherein, The read pointer includes a first read pointer and a second read pointer, The write pointer is used to indicate the write position of the next instruction, The first read pointer is used to indicate the position of the instruction to be read currently, The second read pointer is used to indicate the storage slice where the instruction to be read currently is located, The cache partition is divided into a plurality of sub-storage areas with the same preset storage length for the second read pointer and the write pointer, and the second read pointer and the write pointer correspond to the same address number range.

7. The data processing method according to any one of claims 1 to 3, wherein, Obtaining a number P of work item sets required to be run in parallel corresponding to a current computing task, comprising: Predicting a maximum number of work item sets required to be run in parallel when the parallel processor executes the current computing task, and taking the maximum number as the number P of work item sets.

8. The data processing method according to any one of claims 1-3, further comprising: Adjusting the instruction prefetch strategy according to the size of each cache partition.

9. The data processing method of claim 8, wherein, Adjusting the instruction prefetch strategy according to the size of each cache partition, comprising: Increasing the number of instructions prefetched at a time or performing instruction prefetching continuously multiple times according to the size of each cache partition.

10. The data processing method according to any one of claims 1-3, further comprising: Adjusting the judgment condition of the remaining storage capacity of the cache partition according to the size of each cache partition.

11. A data processing apparatus applied to a parallel processor, the parallel processor being capable of supporting maximum M sets of work items running in parallel, and comprising M instruction cache regions corresponding to the M sets of work items respectively, wherein, Each of the M instruction cache areas is used to temporarily store instruction data executed by a corresponding work item set, The data processing apparatus comprises: An obtaining unit configured to obtain a number P of work item sets required to be run in parallel corresponding to a current computing task; A configuration unit configured to perform spatial configuration on the M instruction cache areas according to the number P of work item sets to obtain a plurality of cache partitions, and set the jump range of the pointer of each cache partition, wherein, in response to the number P of work item sets being less than M, the size of each cache partition is greater than the size of one instruction cache area; Each of the M instruction cache areas comprises a plurality of storage slices; The configuration unit is further configured to determine the total number of storage slices included in the M instruction cache areas, and determine the total number N of cache partitions according to the total number of storage slices and the number P of work item sets, N is a positive integer and is greater than or equal to P and less than M; the M instruction cache areas are evenly allocated as N cache partitions.

12. The data processing apparatus of claim 11, wherein, The obtaining unit is a register, and the register pre-stores the number P of work item sets.

13. The data processing apparatus according to claim 11 or 12, wherein, The configuration unit comprises a plurality of sub-configuration units, each of the plurality of sub-configuration units corresponds to a different number of work item sets, and each of the plurality of sub-configuration units is configured to perform configuration on the M instruction cache areas according to the corresponding number of work item sets to obtain a plurality of cache partitions, and set the jump range of the pointer of each cache partition.

14. The data processing apparatus of claim 13, further comprising a multiplexer, wherein, The multiplexer is configured to select one of the plurality of sub-configuration units according to the number P of work item sets.

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