Method of data reading of a memory and reading circuit

Abstract

The application provides a method and a reading circuit for data reading of a memory. The method controls the data reading process of a current reading cycle by using the reading result of at least one previous reading cycle, so as to improve the accuracy of data reading. The application can improve the accuracy of data reading by adjusting the relevant parameters of the current reading cycle by using the reading result of at least one previous reading cycle.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a data reading method and reading circuit of a memory. BACKGROUND

[0002] At present, the amount of data stored in a chip is increasing, and the speed requirement of data reading is also increasing. Under high-speed reading, the error rate of data increases, limiting the accuracy of data reading. The speed and accuracy of data reading in the memory are increasingly becoming a bottleneck that limits the working speed and overall performance of the chip.

[0003] In the current data readout circuit, the data in the storage unit is read out through differential bit lines. The data readout mainly includes three steps: first, a precharge module charges the bit line; second, the storage unit is connected to the bit line and controls the bit line to discharge, and after discharging, there is a voltage difference between the two bit lines; finally, an amplifier module detects and amplifies the voltage difference between the two bit lines, realizing the readout of the data in the storage unit (for details, refer to the related description of Figure 1 Due to the large number of storage units connected to the bit line and the long length of the bit line, when reading data at a high frequency, the voltage drop on the bit line is limited, and it cannot reach the working range of the amplifier, thereby increasing the error rate of reading data, and further unable to accurately read data. Therefore, the speed and accuracy of data reading in the memory are increasingly becoming a bottleneck that limits the working speed and overall performance of the chip.

[0004] The existing methods for improving the data reading speed of the storage unit in the memory, and thereby improving the accuracy of reading data under high-speed reading, mainly include the following two methods: (1) starting from the structure of the storage unit, increasing the reading current, and increasing the voltage difference of a group of bit lines in the same reading time; (2) starting from the structure of the bit line, by reasonable grouping and splitting, reducing the number of storage units connected to a bit line, or shortening the length of the bit line, thereby reducing the size of the parasitic capacitance and resistance of the bit line, and increasing the voltage difference of a group of bit lines during reading. However, the above two methods have the following problems: (1) both optimize the spatial structure of the storage unit circuit itself or the bit line, which needs to be designed according to specific requirements, and the method is relatively complex, and the universality is relatively poor; (2) while improving the limit frequency of data reading, the power consumption and noise of the circuit during low-frequency data reading are not reduced, and there are still problems of high power consumption and high noise, thereby affecting the overall performance of the chip. SUMMARY

[0005] In view of the problems existing in the prior art described above, the purpose of the present application is to provide a data reading method and reading circuit of a memory.

[0006] In a first aspect, the present application provides a method for data reading of a memory. The method comprises: controlling a data reading process of a current reading cycle by a reading result of at least one previous reading cycle, so as to improve accuracy of data reading.

[0007] Optionally, the controlling of the data reading process of the current reading cycle by the reading result of the at least one previous reading cycle comprises: controlling the data reading process of the current reading cycle by a reading address of the at least one previous reading cycle and a reading address of the current reading cycle.

[0008] Optionally, the controlling of the data reading process of the current reading cycle by the reading result of the at least one previous reading cycle comprises: controlling a charging and discharging process of a bit line in the current reading cycle by the reading result of the at least one previous reading cycle, so as to control the data reading process.

[0009] Optionally, the controlling of the data reading process of the current reading cycle by the reading result of the at least one previous reading cycle comprises: controlling a charging of the bit line by an up pull branch based on the reading result of the at least one previous reading cycle, so as to adjust a charging speed of the bit line in the current reading cycle.

[0010] Optionally, the method further comprises: controlling a common charging of the bit line by a charging tube based on a preset control voltage.

[0011] Optionally, the controlling of the data reading process of the current reading cycle by the reading result of the at least one previous reading cycle comprises: controlling a discharging of the bit line by a down pull branch based on the reading result of the at least one previous reading cycle, so as to adjust a discharging speed of the bit line in the current cycle.

[0012] Optionally, the method further comprises: clamping the bit line by a clamping circuit, so as to limit a lowest voltage of the bit line.

[0013] Optionally, the controlling of the data reading process of the current reading cycle by the reading result of the at least one previous reading cycle comprises: controlling an amplifier module by the reading result of the at least one previous reading cycle, so as to control the data reading process of the current reading cycle.

[0014] Optionally, the controlling of the amplifier module comprises: adopting a feedback control module, connecting to an input node of the amplifier module through a capacitor, so as to control a voltage of the input node of the amplifier module, and further control the data reading process.

[0015] In a second aspect, the present application provides a reading circuit of a memory. The reading circuit comprises a pre-charge module, a memory cell and an amplifier module; in the pre-charge module or the amplifier module, a reading result of at least one previous reading cycle is used to control a data reading process of a current reading cycle, so as to improve the accuracy of data reading.

[0016] Optionally, in the pre-charge module, a reading result of at least one previous reading cycle is used to control a charging and discharging process of a bit line, so as to control the data reading process of the current cycle.

[0017] Optionally, the bit line is connected to a pull-up branch controlled by a reading result of at least one previous reading cycle, and is used to charge the bit line, so as to adjust a charging speed of the bit line in the current cycle.

[0018] Optionally, the bit line is further connected to a charging tube controlled by a preset control voltage, and is used to charge the bit line together.

[0019] Optionally, the bit line is connected to a pull-down branch controlled by a reading result of at least one previous reading cycle, and is used to discharge the bit line, so as to adjust a discharging speed of the bit line in the current cycle.

[0020] Optionally, the bit line is connected to a clamping circuit, and is used to clamp the bit line, so as to limit a minimum voltage of the bit line.

[0021] Optionally, the clamping circuit comprises a first NMOS tube and a second NMOS tube; a source of the first NMOS tube is connected to a first bit line in the bit line; a source of the second NMOS tube is connected to a second bit line in the bit line; a gate of the first NMOS tube and a gate of the second NMOS tube are connected to a clamping control voltage; a drain of the first NMOS tube and a drain of the second NMOS tube are connected to a third potential; when a voltage of the first bit line is lower than a difference between the clamping control voltage and a threshold voltage of the first NMOS tube, the first NMOS tube is turned on to pull up the voltage of the first bit line to the difference between the clamping control voltage and the threshold voltage of the first NMOS tube; when a voltage of the second bit line is lower than a difference between the clamping control voltage and a threshold voltage of the second NMOS tube, the second NMOS tube is turned on to pull up the voltage of the second bit line to the difference between the clamping control voltage and the threshold voltage of the second NMOS tube.

[0022] Optionally, the amplifier module is connected to a feedback control module controlled by a reading result of at least one previous reading cycle, and is used to control the data reading process of the current cycle.

[0023] Optionally, the feedback control module controlled by the read result is connected to the input node of the amplifier module through a capacitor to control the voltage of the input node of the amplifier module.

[0024] In a third aspect, the present application provides another read circuit of a memory. The read circuit comprises a pre-charge module, a bit line, a plurality of memory cells, an amplifier module and a feedback control module; the feedback control module is adapted to control the data read process of a current read cycle based on the read result of at least one previous read cycle to improve the accuracy of data read.

[0025] Optionally, the read result further comprises a read address.

[0026] Optionally, the feedback control module is further adapted to control the charging and discharging process of the bit line based on the read result of at least one previous read cycle to control the data read process of a current read cycle.

[0027] Optionally, the feedback control module is further adapted to control the speed and / or time of charging and discharging the bit line in a current read cycle based on the read result of at least one previous read cycle.

[0028] Optionally, the feedback control module comprises at least two PMOS transistors; the source of each PMOS transistor is connected to a power supply in the pre-charge module; the drain of each PMOS transistor is connected to the bit line; the pre-charge module charges the bit line through the at least two PMOS transistors; and the feedback control module is further adapted to control the speed of charging the bit line through the at least two PMOS transistors based on the read result of at least one previous read cycle.

[0029] Optionally, the feedback control module comprises at least two NMOS transistors; the drain of each NMOS transistor is connected to the bit line; the source of each NMOS transistor is commonly connected to a first potential; and the feedback control module is further adapted to control the speed of discharging the bit line through the at least two NMOS transistors based on the read result of at least one previous read cycle.

[0030] Optionally, the feedback control module comprises at least two CMOS inverters; the source of the PMOS transistor in each CMOS inverter is connected to a power supply in the pre-charge module; the drain of the PMOS transistor and the NMOS transistor in each CMOS inverter is connected to the bit line; the source of the NMOS transistor in each CMOS inverter is commonly connected to a second potential; and the feedback control module is further adapted to control the speed of charging and discharging the bit line through the at least two CMOS inverters based on the read result of at least one previous read cycle.

[0031] Optionally, the feedback control module comprises a clamping circuit, and the clamping circuit is adapted to clamp the bit line to limit the minimum voltage of the bit line.

[0032] Optionally, the amplifier module is connected with the feedback control module, and the feedback control module is further adapted to control the relevant parameters of the amplifier module based on the reading result of the at least one previous reading cycle to control the data reading process of the current reading cycle.

[0033] Optionally, the feedback control module is connected to the input node of the amplifier module through a capacitor, and the feedback control module is further adapted to control the voltage of the input node of the amplifier module based on the reading result of the at least one previous reading cycle to control the data reading process of the current reading cycle.

[0034] As described above, compared with the prior art, the method and the reading circuit for data reading of the memory of the present application have the following beneficial effects:

[0035] (1) When reading data from the memory cells in the memory, the data reading process of the current reading cycle can be controlled through the reading result of the at least one previous reading cycle and the relevant data, so that the voltage difference on the bit line cannot reach the working range of the amplifier at a high data reading frequency, thereby improving the accuracy of data reading.

[0036] (2) The present application can form a new pre-charge module or an amplifier module by adding different components on the basis of the pre-charge module and the amplifier module. The present application can also form a separate feedback control module by adding different components. The feedback control module can control the charging and discharging process of the bit line through the reading result of the at least one previous reading cycle and the relevant data. The present application does not need to improve the memory cells in the memory, and the method is simple, easy to implement and has strong operability.

[0037] (3) The present application proposes to add a clamping circuit on the basis of the pre-charge module, which can avoid discharging the bit line to a too low potential and prevent the bit line from interfering with the signal of the memory cell during the reading data process, thereby reducing the power consumption and noise during data reading at low frequency and improving the overall performance of the chip.

[0038] Some of the additional features of the present application can be described in the following description. Some of the additional features of the present application are apparent to those skilled in the art from inspection of the following description and corresponding drawings or from practice of the application or from practice of the embodiments. The features of the present application can be realized and attained by practice or use of the methods, instrumentalities and combinations of the various aspects of the specific embodiments described in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0039] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as read in conjunction with the accompanying drawings.

[0040] Figure 1 An exemplary schematic diagram of a read circuit for a memory cell of the prior art;

[0041] Figure 2 An exemplary circuit diagram of a pre-charge module in Figure 1

[0042] Figure 3 An exemplary circuit diagram of a memory cell in Figure 1

[0043] Figure 4 An exemplary circuit diagram of an amplifier module in Figure 1

[0044] Figure 5 A circuit diagram of a feedback control module of a read circuit for a memory according to an exemplary embodiment of the present application;

[0045] Figure 6 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0046] Figure 7 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0047] Figure 8 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0048] Figure 9 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0049] Figure 10 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0050] Figure 11 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0051] Figure 12 A circuit diagram of a feedback control module of a read circuit for a memory according to another exemplary embodiment of the present application;

[0052] Figure 13 ​​​A circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention;

[0053] Figure 14 According to Figure 1 Timing diagram of the read circuit reading data from the memory cell;

[0054] Figure 15 This is a schematic diagram of a memory read circuit according to an exemplary embodiment of the present invention;

[0055] Figure 16 This is a timing diagram of a read circuit reading data from a memory cell according to an exemplary embodiment of the present invention;

[0056] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0057] To address the problems in the prior art, this invention provides a method and circuit for reading data from a memory. By adding a feedback control module, the data reading process of the current reading cycle is controlled based on the reading results of at least one previous reading cycle, thereby improving the accuracy of data reading at high speeds, increasing the data reading speed, and enhancing the data reading capability. The method is simple, easy to implement, and highly operable. In addition, it can reduce power consumption and noise during low-frequency data reading, thereby improving the overall performance of the chip.

[0058] In the following detailed description of embodiments, reference will be made to the accompanying drawings, which form part of this invention. The accompanying drawings illustrate specific embodiments by way of example that enable the implementation of the invention. The exemplary embodiments are not intended to be exhaustive of all embodiments according to the invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the invention is defined by the appended claims.

[0059] Figure 1 This is a schematic diagram of a readout circuit in a memory, which includes a precharge module 110, multiple memory cells 120-1, 120-2, ..., 120-n, and an amplifier module 130.

[0060] Figure 2 for Figure 1 An exemplary circuit diagram of the pre-charge module 110 in the example.

[0061] Figure 3 for Figure 1 An exemplary circuit diagram of a storage cell 120-1.

[0062] Figure 4 An exemplary circuit diagram of the amplifier module 130 in FIG. 1 is shown in FIG. 2. Figure 1

[0063] For example, in the case of static random access memory (SRAM), the circuits of the three parts are shown in FIGS. 3, 4 and 5, respectively. Figures 2-4 For example, in the case of the storage unit 120-1, in the data reading process, first enable the pre-charge module 110 to charge the bit line BL / BLB to a high voltage; then set the word line WL signal to high to read out the data in the storage unit 120-1, so that the voltage of the bit line BL / BLB has a certain voltage difference; finally, the voltage difference is transmitted to the amplifier module 130, and the data Q / QB can be read out after the voltage difference is amplified.

[0064] The data reading process is as follows: as shown in FIG. 6, in the data writing process, the peripheral circuit (not shown) sets the bit line BL and BLB signals to opposite values, such as 1 and 0, respectively, and then sets the WL signal to 1, so that the values of BL / BLB can be stored at the BIT and BITB points; in the data reading process, first set the gate control voltage PRCHB (also referred to as a preset control voltage) signal of the charging tube P3, P4 in FIG. 1 to 0, and then set the PRCHB signal to 1 after the P2 / P3 / P4 tube pulls the bit line BL / BLB signal to a high voltage, and then set the word line WL signal to 1. Assuming that the voltages at the BIT / BITB points are 1 and 0, respectively, at this time, the charge on BLB will flow out from the channels of N3 and N0, and at this time, because the voltage at the BITB point is 0, N1 is in the off state, and the voltage of the bit line BL does not change. Therefore, during the period when the word line WL is set to 1, there will be a certain voltage difference between BL and BLB. Among them, P0 / P1 / P2 / P3 / P4 are PMOS tubes, and N0 / N1 / N2 / N3 are NMOS tubes. Figure 3 Figure 2

[0065] As shown in FIG. 7, in the data writing process, the peripheral circuit (not shown) sets the bit line BL and BLB signals to opposite values, such as 1 and 0, respectively, and then sets the WL signal to 1, so that the values of BL / BLB can be stored at the BIT and BITB points; in the data reading process, first set the gate control voltage PRCHB (also referred to as a preset control voltage) signal of the charging tube P3, P4 in FIG. 1 to 0, and then set the PRCHB signal to 1 after the P2 / P3 / P4 tube pulls the bit line BL / BLB signal to a high voltage, and then set the word line WL signal to 1. Assuming that the voltages at the BIT / BITB points are 1 and 0, respectively, at this time, the charge on BLB will flow out from the channels of N3 and N0, and at this time, because the voltage at the BITB point is 0, N1 is in the off state, and the voltage of the bit line BL does not change. Therefore, during the period when the word line WL is set to 1, there will be a certain voltage difference between BL and BLB. Among them, P0 / P1 / P2 / P3 / P4 are PMOS tubes, and N0 / N1 / N2 / N3 are NMOS tubes. Figure 4 ​​​As shown, BLSWB is the gate control voltage signal of M1 transistor, the voltage of bit line BL / BLB is transmitted to the input signal DL / DLB of amplifier module 130 via M1 transistor; SACHB is the gate control voltage signal of M3 transistor, the power supply charges the input signal DL / DLB of amplifier module 130 via M3 transistor; SAEN is the enable signal of amplifier module 130. When BLSWB is 0 and SACHB is 1, the voltage of BL / BLB is transmitted to DL / DLB via M1 / M2 transistor; after the voltage of bit line is transmitted to DL / DLB, SAEN is set to 1 to enable amplifier module 130, and the voltage difference of DL / DLB is amplified by amplifier module, and the voltage of DL / DLB is pulled to logic 1 and 0 respectively, and subsequent processing can be performed to complete the data readout process; after the readout process is completed, SACHB is set to 1 and SAEN is set to 0, and the power supply charges the potential of DL / DLB point to the power supply voltage VDD via M3 / M4. Wherein, M1 / M2 / M3 / M4 transistors are PMOS transistors.

[0066] The present application provides a data read circuit of a memory. The data read circuit can control the data read process of a current read cycle based on the read result of at least one previous read cycle, so as to improve the accuracy of data read. The at least one previous read cycle can be referred to as at least one historical read cycle. The at least one previous read cycle can be the previous read cycle of the current read cycle, or can be multiple read cycles before the current read cycle. For example, the process of reading the current memory cell is the current read cycle, and the process of reading the previous memory cell is the previous read cycle.

[0067] In some embodiments, the data read circuit can include a pre-charge module, a bit line, a plurality of memory cells, an amplifier module, a feedback control module, etc. The feedback control module can control the data read process of a current read cycle based on the read result of at least one previous read cycle, so as to improve the accuracy of data read. The read circuit can be used in a memory array, a memory array including a plurality of memory cells, a memory array including a plurality of memory cells and a plurality of bit lines, etc. Figure 1The feedback control module is added on the basis of the pre-charge module. Specifically, the memory can include a pre-charge module, a word line, a bit line, a plurality of storage units, an amplifier module, a feedback control module, and the like. The pre-charge module is connected to the bit line. The pre-charge module can pre-charge the bit line according to a pre-charge signal. The storage units can store various types of data. The amplifier module is connected to the bit line and can read the data stored in the selected storage unit. The memory can refer to a device having a storage function. The memory can include a static random access memory (SRAM), a dynamic random access memory (DRAM), a non-volatile memory, a ferroelectric memory (FRAM), a phase change memory (PRAM), a magnetic memory (MRAM), a resistive random access memory (RRAM), and the like. The feedback control module can control the data reading process of the current reading cycle based on the reading result of at least one previous reading cycle. In some embodiments, the reading result includes the reading address of the storage unit. In some embodiments, the feedback control module can control the speed and / or time of the pre-charge module charging and discharging the bit line in the current reading cycle based on the reading result of at least one previous reading cycle. The reading cycle of reading the storage unit can include a pre-charge process of the bit line, a discharge process, a process of reading the data stored in the storage unit, and the like, which are not limited herein.

[0068] In some embodiments, the data reading circuit can include a pre-charge module, a bit line, a plurality of storage units, an amplifier module, and the like. The pre-charge module and / or the amplifier module can control the data reading process of the current reading cycle through the reading result of at least one previous reading cycle to improve the accuracy of data reading. In some embodiments, a feedback control module can be added on the basis of the pre-charge module to form a new pre-charge module, for example, as shown in Figures 5 to 11 In some embodiments, a feedback control module can be added on the basis of the amplifier module to form a new amplifier module, for example, as shown in Figure 12 and 13 .

[0069] Specifically, the present application exemplarily provides a variety of circuit diagrams of feedback control modules, which can be specifically referred to the description of Figures 5 to 16 . It should be noted that the feedback control module in Figures 5 to 13 may exist independently, or can be combined with the pre-charge module to form a new pre-charge module, or can be combined with the amplifier module to form a new amplifier module.

[0070] Figure 5 A circuit diagram of a feedback control module of a reading circuit of a memory according to an exemplary embodiment of the present application.

[0071] Figure 5 A circuit diagram of a feedback control module of a reading circuit of a memory according to an exemplary embodiment of the present application. Figure 1The feedback control module 210 is added on the basis of the reading circuit, and the feedback control module 210 is connected with the pre-charge module 110. The feedback control module 210 can also be called a pull-up branch.

[0072] As shown in Figure 5 The feedback control module 210 includes at least two PMOS tubes (P4, P5) (only two are shown). The source of each PMOS tube is connected with the power supply in the pre-charge module 110. The drain of each PMOS tube is connected with the bit line BL / BLB. The pre-charge module 110 can charge the bit line BL / BLB through the at least two PMOS tubes. The feedback control module 210 can control the speed of charging the bit line BL / BLB through the at least two PMOS tubes based on the reading result of the previous at least one reading cycle. The at least two PMOS tubes are controlled by the reading result of the previous at least one reading cycle. For example, as shown in Figure 1The read circuit shown, after the end of the current read cycle (the reading of the data of the previous memory cell has been completed), when the next memory cell is about to be read, the pre-charge module 110 needs to charge the potential of the bit line BL / BLB. In high-speed reading, due to the short charging time and slow charging speed, the bit line that is discharged to a lower voltage in the previous read cycle can not reach a high enough voltage. During the current read cycle, after a period of time of discharging, the voltage of one of the bit line BL or the bit line BLB decreases, and the voltage difference between the bit line BL and the bit line BLB can be too small. Due to the too small voltage difference between the bit line BL and the bit line BLB, the data read by the amplifier module 130 can be incorrect. In this embodiment, based on the result Q / QB read in the previous read cycle, the charging speed of the bit line BL / BLB can be adjusted by whether the PMOS tube is turned on or not through the two PMOS tubes of the feedback control module 210. For example, when Q or QB is a low potential, that is, the PMOS tube is turned on, the charging speed of the bit line can be increased. Therefore, by increasing the PMOS tube, the charging speed of the bit line that is discharged to a lower voltage in the previous read cycle can be increased, and the feedback control process can continue until the discharging process, so that one of the bit line BL or the bit line BLB can reach a higher voltage after the pre-charge ends, and after a period of time of discharging, the voltage difference between the bit line BL and the bit line BLB input to the amplifier module can be increased. Therefore, when reading the data in the current read memory cell, due to the adjustment of the voltage difference between the bit line BL / BLB by the feedback control module 210, the data stored in the memory cell can be correctly read in the current read cycle. In some embodiments, the feedback control module 210 can also control the read process of the current read cycle based on the read address and the read result of the memory cell. For example, the read process of the current read cycle can be controlled based on the read address and the read result of one or more memory cells in at least one previous read cycle. In some embodiments, different feedback control modules 210 can be designed by increasing the number of PMOS tubes, which is not limited here.

[0073] Figure 6 Circuit diagram of the feedback control module of the read circuit of the memory according to another exemplary embodiment of the present application.

[0074] Figure 6 Based on the read circuit of Figure 1 The feedback control module 220 is added to the read circuit, and the feedback control module 220 is connected with the bit line BL / BLB. The feedback control module 220 can also be called a pull-down branch.

[0075] As Figure 6As shown, the feedback control module 220 includes at least two NMOS transistors (N4, N5) (only two are shown). The drain of each NMOS transistor is connected to the bit line BL / BLB. The source of each NMOS transistor is connected to a first potential (e.g., Figure 6 (VSS in the example). For example, the sources of each NMOS transistor can be grounded together. The feedback control module 220 can control the discharge speed of the two NMOS transistors on the bit line BL / BLB based on the read result of at least one previous read cycle. The at least two NMOS transistors are controlled by the read result of at least one previous read cycle. For example, as... Figure 1 In the read circuit shown, after the current read cycle ends (after reading the data of the previous memory cell is complete) and the next memory cell is about to be read, the pre-charge module 110 needs to charge the bit lines BL / BLB. During the current read cycle, after a period of discharge, the voltage of one of the bit lines BL or BLB drops. Due to the slow discharge rate, one of the bit lines may not reach a sufficiently low potential, resulting in an excessively small voltage difference between BL and BLB. Because the voltage difference between BL and BLB is too small, the data read by the amplifier module 130 may be erroneous. In this embodiment, the feedback control module 220 uses two NMOS transistors to adjust the discharge rate of the bit lines BL / BLB based on the result Q / QB read in the previous read cycle. For example, when Q or QB is at a high potential, i.e., the NMOS transistor is on, the discharge rate of the bit lines can be increased. Therefore, by adding NMOS transistors, the discharge rate of the bit line with a higher voltage after discharge in the previous read cycle can be increased in the current read cycle. This allows one of the bit lines, BL or BLB, to reach a lower voltage after discharge, thereby increasing the potential difference between BL and BLB. This effectively pulls the voltage of the bit line, which was originally at a low potential, further increasing the voltage difference between BL and BLB, ensuring that the amplifier module 130 can correctly read the data. Therefore, when reading data from the current memory cell, the feedback control module 220 adjusts the potential difference between bit lines BL and BLB, ensuring that the data stored in the memory cell can be correctly read in the current read cycle. In some embodiments, the feedback control module 220 can control the read process of the current read cycle based on the read address of the memory cell and the read result. For example, it can control the read process of the current read cycle based on the read address and read result of one or more memory cells in at least one previous read cycle. In some embodiments, different feedback control modules 220 can be designed by increasing the number of NMOS transistors; no limitation is imposed here.

[0076] Figure 7This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0077] Figure 7 In order to be in Figure 1 Based on the reading circuit, a feedback control module 230 was added.

[0078] like Figure 7 As shown, the feedback control module 230 includes two CMOS inverters. The source of the PMOS transistor in each CMOS inverter is connected to the power supply in the precharge module 110. The drains of the PMOS and NMOS transistors in each CMOS inverter are connected to the bit line. The source of the NMOS transistor in each CMOS inverter is connected to a second potential (e.g., ...). Figure 7 (VSS in the example). For example, the sources of each NMOS transistor can be grounded together. The feedback control module 230 can control the charging and discharging speed of the two CMOS inverters on the bit line based on the read result of at least one previous read cycle. In this embodiment, the two CMOS inverters of the feedback control module 220 can adjust the charging and / or discharging speed of the two CMOS inverters on the bit line BL / BLB based on the result Q / QB read in the previous read cycle, so that the bit line BL and the bit line BLB can reach a larger voltage difference before the input amplifier module 130, thereby enabling the data stored in the memory cell to be read correctly in the current read cycle. In some embodiments, the feedback control module 210 can control the read process of the current read cycle based on the read address of the memory cell and the read result. For example, the read process of the current read cycle can be controlled based on the read address and read result of one or more memory cells in at least one previous read cycle. In some embodiments, different feedback control modules 230 can be designed by increasing the number of CMOS inverters, which is not limited here.

[0079] Figure 8 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0080] Figure 8 In order to be in Figure 1 Based on the reading circuit, a feedback control module 240 was added.

[0081] like Figure 8As shown, the feedback control module 240 includes a clamping circuit. This clamping circuit clamps the bit line BL / BLB to limit the minimum voltage of the bit line. The clamping circuit includes a first NMOS transistor (N6) and a second NMOS transistor (N7). The source of the first NMOS transistor is connected to the bit line; the source of the second NMOS transistor is connected to the bit line; the gates of the first and second NMOS transistors are connected together; the drains of the first and second NMOS transistors are connected together to a third potential (e.g., ...). Figure 8 VLCAMP in the equation can be the power supply voltage. When the voltage of bit line BL is lower than the clamping control voltage VCEN and the threshold voltage VTH of the first NMOS transistor (i.e., VCEN-VTH), the first NMOS transistor will conduct, pulling the voltage of bit line BL up to VCEN-VTH. When the voltage of bit line BLB is lower than the clamping control voltage VCEN and the threshold voltage VTH of the second NMOS transistor (i.e., VCEN-VTH), the second NMOS transistor will conduct, pulling the voltage of bit line BL up to VCEN-VTH. Therefore, the feedback control module 240 can use the clamping circuit to turn on the first NMOS transistor (N6) and the second NMOS transistor (N7) to pull up the voltage of bit lines BL / BLB. In some embodiments, different feedback control modules 230 can be designed by designing different clamping circuits, which is not limited here.

[0082] Figure 9 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0083] Figure 9 In order to be in Figure 5 Based on the feedback control module 210, the following has been added Figure 8 The clamping circuit in the middle forms a feedback control module 310. The feedback control module 310 can adjust the charging speed of the bit lines BL / BLB by controlling the conduction of the PMOS transistor, and can also control the minimum voltage of the bit lines BL / BLB through the clamping circuit. Figure 5 Adding a clamping circuit to the existing circuitry can adjust the charging speed of the bit lines BL / BLB and also limit the minimum voltage of the bit lines.

[0084] Figure 10 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the invention.

[0085] Figure 10 In order to be in Figure 6 Based on the feedback control module 220, the following has been added Figure 8The clamping circuit in the middle forms a feedback control module 320. The feedback control module 320 can adjust the discharge speed of the bit lines BL / BLB by controlling the conduction of the NMOS transistor, and can also control the minimum voltage of the bit lines BL / BLB through the clamping circuit. Figure 6 Adding a clamping circuit to the existing circuitry can adjust the discharge speed of the bit lines BL / BLB and also limit the minimum voltage of the bit lines.

[0086] Figure 11 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0087] Figure 11 In order to be in Figure 7 Based on the feedback control module 230, the following has been added Figure 8 The clamping circuit in the middle forms a feedback control module 330. The feedback control module 310 can adjust the charging and / or discharging speed of the bit lines BL / BLB via a CMOS inverter, and can also control the minimum voltage of the bit lines BL / BLB via the clamping circuit. Figure 7 Adding a clamping circuit to the existing circuitry can adjust the charging and discharging speed of the bit lines BL / BLB, and also limit the minimum voltage of the bit lines.

[0088] Figure 12 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0089] like Figure 12 As shown, amplifier module 130 is connected to feedback control module 340. Feedback control module 340 can control relevant parameters of amplifier module 130 based on the reading results of at least one previous reading cycle, thereby controlling the data reading process in the current reading cycle. For example, when the voltage difference between the bit lines BL and BLB input to amplifier module 130 is too low, feedback control module 340 can adjust some parameters of amplifier module 130 to increase the voltage difference between the bit lines BL and BLB, thereby ensuring that amplifier module 130 can correctly read the data from the memory cell.

[0090] Figure 13 This is a circuit diagram of a feedback control module for a memory read circuit according to another exemplary embodiment of the present invention.

[0091] like Figure 13As shown, the feedback control module 350 is connected to the input nodes of the amplifier module 130 via capacitors (C1, C2). Based on the reading results of at least one previous read cycle, the feedback control module 350 controls the voltage of the input nodes (DL, DLB) of the amplifier module 130 to control the data reading process of the current read cycle. When the voltage difference between the bit lines BL and BLB is too low, the feedback control module 350 can adjust the voltage of the input nodes (DL, DLB) of the amplifier module 130 to increase the voltage difference, thereby ensuring that the amplifier module 130 can correctly read the data from the memory cell.

[0092] Figure 14 According to Figure 1 The timing diagram for the read circuit to read data from the memory cell.

[0093] like Figure 14 As shown, the read cycle includes charging and discharging phases. During the discharging phase, the amplifier module is enabled, and the data stored in the memory cell can be read. When the word line WL(0) is enabled and the amplifier is enabled, the data in the memory cell controlled by the word line WL(0) can be read (phases t13~t14). After the previous read cycle ends, the pre-charging module needs to pre-charge the bit line BL (phases t14~t15) to make BLB reach a high potential. Due to the slow charging speed, the potential of the bit line BLB does not reach a sufficiently high potential. When reading the data of the next memory cell, during the amplifier module enabling phase (phases t16~t17), the voltage difference between the bit line BL and BLB is ΔV1. Due to the small voltage difference, a misread occurs. As shown in the dashed box in the figure, Q / QB should have flipped, but it did not, resulting in a misread.

[0094] Figure 15 This is a schematic diagram of a memory read circuit according to an exemplary embodiment of the present invention.

[0095] Figure 16 This is a timing diagram of a read circuit reading data from a memory cell according to an exemplary embodiment of the present invention.

[0096] To describe the read circuit and method of the memory of the present invention, Figure 15An exemplary memory reading circuit is provided. The reading circuit includes a pre-charge module 410, a plurality of memory cells 420-1, 420-2, …, 420-n, an amplifier module 430, a feedback control module 440, etc. The feedback control module 440 can control the reading process of the current memory cell to be read based on the reading result of at least one previous reading cycle. For example, when the reading result Q(1) / QB(1) of the previous memory cell 420-1 is read out, the feedback control module 440 can control the charging and discharging process of the bit line BL / BLB based on Q(1) / QB(1), so that when the next memory cell 420-2 is read, the voltage difference of the bit line BL / BLB can be large enough, so that the amplifier module 440 can correctly read out the reading result Q(2) / QB(2) of the memory cell 420-2. Figure 16 An exemplary timing diagram of the reading circuit based on Figure 15 is provided. As shown in Figure 16 , after the reading of the previous memory cell 420-1 is completed, the pre-charge module 410 needs to charge the bit line (t24~t25 stage), compared with t14~t15 stage in Figure 14 , since the feedback control module 440 is added, the charging speed of the bit line can be increased, i.e. in the same time, the bit line BLB can reach a higher potential; when the next memory cell 420-2 is read (t26~t27 stage), the voltage difference of the bit line BL / BLB is ΔV2 (larger than ΔV1 in Figure 14 ), the reading result Q / QB is flipped, and the data of the memory cell 420-2 is correctly read out.

[0097] The present application provides a method for reading data of a memory. The method adds a feedback control module to a conventional reading circuit, and controls the data reading process of the current reading cycle based on the reading result of at least one previous reading cycle, so as to improve the accuracy of data reading and avoid misreading. The feedback control module can control the charging and discharging of the bit line, the node voltage input to the amplifier module, the related parameters of the amplifier module, etc. The specific description of the feedback control module can be referred to Figures 5 to 16 .

[0098] It should be noted that the above is only an exemplary schematic diagram of the reading circuit and the reading process, and different reading circuits can be realized by connecting and combining the above different circuits. It can be understood that those skilled in the art can arbitrarily combine the modules or connect the subsystems to other modules without departing from the principle of the system after understanding the principle of the system.

[0099] It will be obvious to a person skilled in the art that the application is not limited to the details of the foregoing exemplary embodiments and can be implemented in other concrete forms without departing from the spirit or general characteristics of the application. Accordingly, the embodiments should be considered in all respects as illustrative and not restrictive. Moreover, it must be stressed that the word "comprising" does not exclude other elements and steps and the word "a" or "an" does not exclude a plurality. A single processor or other unit can fulfil the functions of several units recited in the device claims. The terms first, second and the like do not denote any ordinal number, but are used to distinguish different steps of the method.

Claims

1. A method of data read of a memory, characterized in that, The application comprises the following steps: The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The previous at least one reading cycle can be the previous reading cycle of the current reading cycle or multiple reading cycles before the current reading cycle.

2. The method of data read of a memory according to claim 1, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

3. The method of data read of a memory according to claim 1, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

4. The method of data read of a memory according to claim 3, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

5. The method of data read of a memory according to claim 4, characterized in that, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

6. The method of data read of a memory according to claim 3, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

7. The method of data read of a memory according to claim 3, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

8. The method of data read of a memory according to claim 1, wherein, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

9. The method of data reading of a memory according to claim 8, characterized in that, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

10. A memory read circuit, characterized in that, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading.

11. The read circuit for a memory as claimed in claim 10, characterized in that, The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data in the storage unit to improve the accuracy of data reading. The reading result of the previous at least one reading cycle is applied to the bit line of the current reading cycle to control the data reading process of the current reading cycle, increase the voltage difference between the bit line and the input of the amplifier module to reach the working range of the amplifier module, and ensure that the amplifier module correctly reads the data 12. The read circuit for a memory as claimed in claim 11, characterized in that, The bit line is connected to a pull-up branch controlled by the reading result of at least one previous reading cycle, and is used to charge the bit line to adjust the charging speed of the bit line in the current reading cycle.

13. The read circuit for a memory as claimed in claim 12, characterized in that, The bit line is also connected to a charging tube controlled by a preset control voltage, and is used to charge the bit line.

14. The read circuit for a memory as claimed in claim 11, characterized in that, The bit line is connected to a pull-down branch controlled by the reading result of at least one previous reading cycle, and is used to discharge the bit line to adjust the discharging speed of the bit line in the current cycle.

15. The read circuit for a memory as claimed in claim 11, characterized in that, The bit line is connected to a clamping circuit, which is used to clamp the bit line to limit the minimum voltage of the bit line.

16. The read circuit for a memory as claimed in claim 15, characterized in that, The clamping circuit includes a first NMOS tube and a second NMOS tube. The source of the first NMOS tube is connected to a first bit line in the bit line. The source of the second NMOS tube is connected to a second bit line in the bit line. The gates of the first NMOS tube and the second NMOS tube are commonly connected to a clamping control voltage. The drains of the first NMOS tube and the second NMOS tube are commonly connected to a third potential. When the voltage of the first bit line is lower than the difference between the clamping control voltage and the threshold voltage of the first NMOS tube, the first NMOS tube is turned on to pull up the voltage of the first bit line to the difference between the clamping control voltage and the threshold voltage of the first NMOS tube. When the voltage of the second bit line is lower than the difference between the clamping control voltage and the threshold voltage of the second NMOS tube, the second NMOS tube is turned on to pull up the voltage of the second bit line to the difference between the clamping control voltage and the threshold voltage of the second NMOS tube.

17. The read circuit for a memory as claimed in claim 10, wherein, The amplifier module is connected to a feedback control module controlled by the reading result of at least one previous reading cycle, and is used to control the data reading process of the current cycle.

18. The read circuit for a memory as claimed in claim 17, characterized in that, The feedback control module controlled by the reading result is connected to the input node of the amplifier module through a capacitor to control the voltage of the input node of the amplifier module.

19. A memory read circuit, comprising: It comprises: a precharge module, a bit line, a plurality of storage units, an amplifier module and a feedback control module. The feedback control module is adapted to apply the inverse signal of the reading result of at least one previous reading cycle to the bit line of the current reading cycle, control the data reading process of the current reading cycle, increase the voltage difference between the bit line input to the amplifier module to reach the working range of the amplifier module, and thus ensure that the amplifier module correctly reads out the data in the storage unit, so as to improve the accuracy of data reading. The at least one previous reading cycle can be the previous reading cycle of the current reading cycle, or a plurality of reading cycles before the current reading cycle.

20. The read circuit for a memory as claimed in claim 19, characterized in that, The reading result also includes a reading address.

21. The read circuit for a memory as claimed in claim 19, wherein, The feedback control module is also adapted to control the charging and discharging process of the bit line based on the reading result of at least one previous reading cycle to control the data reading process of the current reading cycle.

22. The read circuit for a memory as claimed in claim 19, wherein, The feedback control module is also adapted to control the speed and / or time of charging and discharging the bit line in the current reading cycle based on the reading result of at least one previous reading cycle.

23. The memory reading circuit of claim 19, wherein, The feedback control module includes at least two PMOS tubes. The source of each PMOS transistor is connected to a power supply in the pre-charge module; The drain of each PMOS transistor is connected to the bit line; The pre-charge module charges the bit line through the at least two PMOS transistors; The feedback control module is further adapted to control the speed of charging the bit line through the at least two PMOS transistors based on the read result of at least one previous read cycle.

24. The read circuit for a memory as claimed in claim 19, wherein, The feedback control module comprises at least two NMOS transistors; The drain of each NMOS transistor is connected to the bit line; The source of each NMOS transistor is commonly connected to a first potential; The feedback control module is further adapted to control the speed of discharging the bit line through the at least two NMOS transistors based on the read result of at least one previous read cycle.

25. The read circuit for a memory as defined in claim 19, wherein, The feedback control module comprises at least two CMOS inverters; The source of the PMOS transistor in each CMOS inverter is connected to a power supply in the pre-charge module; The drain of the PMOS transistor and the NMOS transistor in each CMOS inverter is connected to the bit line; The source of the NMOS transistor in each CMOS inverter is commonly connected to a second potential; The feedback control module is further adapted to control the speed of charging and discharging the bit line through the at least two CMOS inverters based on the read result of at least one previous read cycle.

26. The read circuit for a memory according to any one of claims 22 to 25, wherein, The feedback control module comprises a clamp circuit; The clamp circuit is adapted to clamp the bit line to limit the lowest voltage of the bit line.

27. The read circuit for a memory as defined in claim 19, wherein, The amplifier module is connected to the feedback control module; The feedback control module is further adapted to control the relevant parameters of the amplifier module based on the read result of at least one previous read cycle to control the data read process of the current read cycle.

28. The read circuit for a memory as claimed in claim 27, characterized in that, The feedback control module is connected to the input node of the amplifier module through a capacitor; The feedback control module is further adapted to control the voltage of the input node of the amplifier module based on the read result of at least one previous read cycle to control the data read process of the current read cycle.

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