Method for reading a memory and voltage compensation device

Abstract

This invention provides a method for reading a memory. The memory includes multiple word lines and multiple multi-bit storage cells connected to the word lines. The multi-bit storage cells are used to read the stored values ​​of the multi-bit storage cells through multiple preset read voltages. The reading method includes: defining at least one read offset for each of the multiple preset read voltages; selecting at least one preset read voltage as a sampling voltage; reading the multi-bit storage cells on adjacent word lines of the multi-bit storage cell to be read; setting an offset flag representing the magnitude of the read offset based on the sampled read value of the sampling voltage; and then combining the multiple preset read voltages with the read offset corresponding to the offset flag for each preset read voltage to read the multi-bit storage cell to be read, thereby compensating the preset read voltage of the multi-bit storage cell to be read.

Description

[0001] This application is a divisional application of Chinese patent application filed on October 20, 2020, with application number 202011121625.5 and entitled "Method for reading memory and voltage compensation device". Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a method for reading a memory and a voltage compensation device. Background Technology

[0003] In 3D NAND Flash, TLC (Telematics Cell, i.e., each cell can store 3 bits of data) products typically use one-time programming, meaning the state of the cell during the read process differs from that during the program verification process. During program verification, WLn+1 (i.e., the (n+1)th word line) is not programmed, but in most cases, WLn+1 is programmed during the read process.

[0004] However, in existing NAND flash memory technology, when writing to WLn+1, the threshold voltage of the memory cell on WLn (i.e. the nth word line) will shift, which will lead to errors in reading data. Summary of the Invention

[0005] This invention provides a memory reading method and a voltage compensation device, which effectively solves the problem of threshold voltage shift of the multi-bit memory cell to be read when writing adjacent word lines of the multi-bit memory cell to be read.

[0006] To address the aforementioned problems, this invention provides a method for reading a memory, wherein the memory includes multiple word lines and multiple multi-bit storage cells connected to the multiple word lines, and the multi-bit storage cells are used to read the stored values ​​of the multi-bit storage cells through multiple preset read voltages. The reading method includes:

[0007] Define the steps, and define at least one read offset for each of the multi-stage preset read voltages;

[0008] The offset setting step involves selecting at least one of the preset read voltages from the multiple preset read voltages as the sampling voltage, reading multiple memory cells on adjacent word lines of the multiple memory cells to be read, and setting an offset flag representing the magnitude of the read offset based on the sampled read value of the sampling voltage.

[0009] The reading step involves combining the multi-level preset reading voltages with the reading offsets corresponding to the offset flags for each preset reading voltage level, and then reading the multi-bit storage units to be read.

[0010] More preferably, each of the multi-bit storage cells is programmed to be one of multiple threshold voltages. When there are N sampling voltages, the multi-bit storage cell falls into one of N+1 sampling read value partitions obtained due to the different threshold voltages at each level. Each sampling read value partition corresponds to an offset flag. The offset setting step specifically includes:

[0011] The sampling read value acquisition step involves acquiring the read values ​​of multiple memory cells on adjacent word lines of the multiple memory cells to be read using N sampling voltages.

[0012] The sampling read value partitioning step involves classifying the multi-bit storage units on adjacent word lines of the multi-bit storage unit to be read into one of the N+1 sampling read value partitions based on the read value.

[0013] The offset flag acquisition step involves obtaining the corresponding offset flag based on the sampled read value partition to which the partition is classified.

[0014] More preferably, each preset reading voltage has N+1 reading offsets, and the reading step specifically includes:

[0015] The determination step, corresponding to the offset flag, is to determine the current read offset of the preset read voltage for that stage;

[0016] The execution step involves reading the voltage of the multi-bit memory cell to be read as the sum of the preset read voltage for that stage and the current read offset.

[0017] More preferably, the offset flag is represented by log2(N+1) bits.

[0018] More preferably, the read offset includes either a voltage offset value or a voltage bias time.

[0019] More preferably, the adjacent word line is the word line following the word line of the multi-bit storage unit to be read.

[0020] On the other hand, the present invention also provides a voltage compensation device applied to a memory, the memory including multiple word lines and multiple multi-bit storage cells connected to the multiple word lines, the multi-bit storage cells being used to read the stored value of the multi-bit storage cells through multiple preset read voltages, the voltage compensation device comprising:

[0021] A definition module is used to define at least one read offset for each of the multi-stage preset read voltages;

[0022] The offset setting module is used to select at least one of the preset read voltages among the multi-level preset read voltages as the sampling voltage, read the multi-bit memory cells on the adjacent word lines of the multi-bit memory cells to be read, and set an offset flag representing the magnitude of the read offset according to the sampled read value of the sampling voltage.

[0023] The reading module is used to read the multi-bit storage unit to be read by combining the multi-level preset reading voltage with the reading offset amount corresponding to the offset flag of each preset reading voltage.

[0024] More preferably, each of the multi-bit storage cells is programmed to be one of multiple threshold voltages. When there are N sampling voltages, the multi-bit storage cell falls into one of N+1 sampling read value partitions obtained due to the different threshold voltages at each level. Each sampling read value partition corresponds to an offset flag. The offset setting module specifically includes:

[0025] The sampling read value acquisition unit is used to acquire the read values ​​of multiple memory cells on adjacent word lines of the multiple memory cells to be read using N sampling voltages;

[0026] A read value partitioning unit is used to classify the multi-bit storage cells on adjacent word lines of the multi-bit storage cell to be read into one of the N+1 sampled read value partitions according to the read value;

[0027] The offset flag acquisition unit is used to acquire the corresponding offset flag according to the sampled read value partition to which it is classified.

[0028] More preferably, each preset reading voltage has N+1 reading offsets, and the reading module specifically includes:

[0029] A determining unit is used to determine the current read offset of the preset read voltage corresponding to the offset flag;

[0030] An execution unit is used to read the voltage of the multi-bit memory cell to be read as the sum of the preset read voltage of that stage and the current read offset.

[0031] More preferably, the offset flag is stored in the program block latch of the memory.

[0032] More preferably, when the number of sampled voltages is N, the program block latch has log2(N+1) data bits for storing the offset flag.

[0033] More preferably, the voltage compensation device is suitable for lower page read operations, middle page read operations, and higher page read operations of the memory.

[0034] The beneficial effects of this invention are as follows: This invention provides a method for reading a memory. The memory includes multiple word lines and multiple multi-bit storage cells connected to the multiple word lines. The multi-bit storage cells are used to read the stored values ​​of the multi-bit storage cells through multiple preset read voltages. The reading method includes: defining at least one read offset for each of the multiple preset read voltages; selecting at least one preset read voltage as a sampling voltage; reading the multi-bit storage cells on adjacent word lines of the multi-bit storage cell to be read; setting an offset flag representing the magnitude of the read offset based on the sampled read value of the sampling voltage; and then combining the multiple preset read voltages with the read offset corresponding to the offset flag for each preset read voltage to read the multi-bit storage cell to be read. This allows the preset read voltage of the multi-bit storage cell to be read to be compensated, effectively solving the problem of threshold voltage shift of the multi-bit storage cell to be read when writing to adjacent word lines of the multi-bit storage cell to be read. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic flowchart of a memory reading method provided by an embodiment of the present invention.

[0037] Figure 2 This is a further flowchart illustrating the memory reading method provided by an embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram of the structure of a voltage compensation device provided in an embodiment of the present invention.

[0039] Figure 4 This is another structural schematic diagram of a voltage compensation device provided according to an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] The present invention addresses the problem in existing memory technologies where, when writing adjacent word lines of a multi-bit memory cell to be read, the threshold voltage of that multi-bit memory cell is shifted. The embodiments of the present invention are used to solve this problem.

[0042] Please see Figure 1 , Figure 1 This is a schematic flowchart of a memory reading method provided by an embodiment of the present invention. The memory includes multiple word lines and multiple multi-bit storage cells connected to the multiple word lines. The multi-bit storage cells are used to read the stored values ​​of the multi-bit storage cells through multiple preset read voltages. The specific flow of the reading method is as follows:

[0043] Define step S101. Define at least one read offset for each of the multi-level preset read voltages;

[0044] Offset setting step S102: Select at least one preset read voltage from the multi-level preset read voltage as the sampling voltage, read the multi-bit memory cells on the adjacent word lines of the multi-bit memory cells to be read, and set an offset flag representing the magnitude of the read offset according to the sampled read value of the sampling voltage.

[0045] Reading step S103. Combine the multi-level preset reading voltage with the reading offset of the offset flag corresponding to each level preset reading voltage to read the multi-bit memory cell to be read.

[0046] It should be noted that each multi-level storage cell can store multiple bits of data, specifically including but not limited to MLC (Multi-Level Cell), TLC (Trinary-Level Cell), and QLC (Quad-Level Cell). In this embodiment, TLC, i.e., a three-bit storage cell, will be used for explanation. A three-bit storage cell can be programmed to one of eight threshold voltages. The three-bit storage cell has a corresponding storage state at each threshold voltage; therefore, it can store eight data points. By applying a preset read voltage to the three-bit storage cell, its storage state can be determined, and then the stored value can be read.

[0047] Furthermore, each multi-bit storage cell has multiple preset read voltages to read the stored values ​​under different storage states. In the definition step S101, a read offset is set for each preset read voltage, and at least one read offset is set so that the preset read voltage can be compensated when the multi-bit storage cell is read later, thereby solving the problem of threshold voltage shift of the multi-bit storage cell.

[0048] Please see Figure 2 , Figure 2 This is a further flowchart illustrating a memory reading method provided by an embodiment of the present invention. Each of the multi-bit storage cells is programmed with one of multiple threshold voltages. When there are N sampling voltages, the multi-bit storage cell falls into one of N+1 sampling read value partitions obtained due to the different threshold voltages. Each sampling read value partition corresponds to an offset flag, such as... Figure 2 As shown, the offset setting step S102 specifically includes:

[0049] Sampling and reading value acquisition step S1021. Acquire the reading values ​​of multiple memory cells on adjacent word lines of the multiple memory cells to be read using N sampling voltages;

[0050] Sampling read value partitioning step S1022. Based on the read value, classify the multi-bit storage cells on the adjacent word lines of the multi-bit storage cells to be read into one of the N+1 sampling read value partitions;

[0051] Offset flag acquisition step S1023: Based on the sampled read value partition to which it is classified, obtain the corresponding offset flag.

[0052] It should be noted that when there is one sampled voltage, there are two corresponding sampled read partitions, each with an offset flag. Since the offset flag is represented by log2(N+1) bits, only one bit is needed to represent it. The offset flag is stored in the program block latch of the memory and has values ​​of 0 and 1. When there are three sampled voltages, there are four corresponding sampled read partitions. In this case, two bits are needed to represent the offset flag, which has values ​​of 00, 01, 10, and 11.

[0053] Furthermore, taking one sampling voltage as an example, such as sampling voltage R4, the sampling read value of the memory cells with threshold voltages E, P1, P2, and P3 will be 0, and the sampling read value of the memory cells with threshold voltages P4, P5, P6, and P7 will be 1. Taking three sampling voltages as an example, such as sampling voltages R1, R4, and R7, the sampling read value of the memory cell with threshold voltage E will be 00, the sampling read value of the memory cell with threshold voltages P1, P2, and P3 will be 01, the sampling read value of the memory cell with threshold voltages P4, P5, and P7 will be 10, and the sampling read value of the memory cell with threshold voltage P7 will be 10.

[0054] Please continue reading. Figure 2 The reading step S103 specifically includes:

[0055] Step S1031: Determine the current reading offset of the preset reading voltage corresponding to the offset flag;

[0056] Execute step S1032. Read the voltage of the multi-bit memory cell to be read, which is the sum of the preset read voltage of this level and the current read offset.

[0057] It should be noted that when there are N sampled voltages, each preset read voltage has N+1 read offsets, with one of the read offsets being 0. For example, when there is one sampled voltage, two read offsets are set, with one read offset being 0; when there are three sampled voltages, four read offsets are set, with one read offset being 0. For instance, for the first preset read voltage, there are three offsets: Offset1_R1, Offset2_R1, and Offset3_R1; for the second preset read voltage, there are three offsets: Offset1_R2, Offset2_R2, and Offset3_R2, and so on, up to the seventh preset read voltage, which has three offsets: Offset1_R7, Offset2_R7, and Offset3_R7. Furthermore, the read offset includes either the voltage offset value or the voltage bias time.

[0058] Specifically, the adjacent word line is the word line following the word line containing the memory cell to be read. Furthermore, this memory read method can improve ESUM to 120mV.

[0059] In one possible implementation, the multi-bit memory cell is a TLC, and the fourth preset read voltage out of eight preset read voltages is selected as the sampling voltage. This corresponds to two sampling read value partitions: the first partition is from level 0 to level 3, and the second partition is from level 4 to level 7. Each preset read voltage has two read offsets, one of which is 0. In this embodiment, the adjacent word line is WLn+1, and the current word line is WLn. When WLn+1 is in the first sampling read value partition, the read offset of WLn is 0. When WLn+1 is in the second sampling read value partition, the read offset of WLn is as shown in the table below:

[0060]

[0061]

[0062] Unlike existing technologies, this invention provides a method for reading a memory. The memory includes multiple word lines and multiple multi-bit storage cells connected to each word line. The multi-bit storage cells are used to read the stored values ​​of the multi-bit storage cells through multiple preset read voltages. The reading method includes: defining at least one read offset for each of the multiple preset read voltages; selecting at least one preset read voltage as a sampling voltage; reading the multi-bit storage cells on adjacent word lines of the multi-bit storage cell to be read; setting an offset flag representing the magnitude of the read offset based on the sampled read value of the sampling voltage; and then combining the multiple preset read voltages with the read offset corresponding to the offset flag for each preset read voltage to read the multi-bit storage cell to be read. This compensates for the preset read voltage of the multi-bit storage cell to be read, effectively solving the problem of threshold voltage shift of the multi-bit storage cell to be read when writing to adjacent word lines of the multi-bit storage cell to be read.

[0063] Please see Figure 3 , Figure 3 This is a schematic diagram of a voltage compensation device provided according to an embodiment of the present invention. The voltage compensation device is applied to a memory, which includes multiple word lines and multiple multi-bit storage cells connected to the word lines. The multi-bit storage cells are used to read their stored values ​​using multiple preset read voltages. The voltage compensation device provided in this embodiment may include: a definition module 10, an offset setting module 20, and a read module 30, wherein:

[0064] (1) Define module 10

[0065] Define module 10 to perform definition step S101, that is, to define at least one read offset for each of the multi-level preset read voltages.

[0066] (2) Offset setting module 20

[0067] The offset setting module 20 is used to perform the offset setting step S102, that is, to select at least one of the preset reading voltages in the multi-level preset reading voltage as the sampling voltage, to read the multi-bit storage cells on the adjacent word lines of the multi-bit storage cells to be read, and to set an offset flag representing the magnitude of the reading offset according to the sampling reading value of the sampling voltage.

[0068] It should be noted that each multi-level storage cell can store multiple bits of data, specifically including but not limited to MLC (Multi-Level Cell), TLC (Trinary-Level Cell), and QLC (Quad-Level Cell). In this embodiment, TLC, i.e., a three-bit storage cell, will be used for explanation. A three-bit storage cell can be programmed to one of eight threshold voltages. The three-bit storage cell has a corresponding storage state at each threshold voltage; therefore, it can store eight bits of data. By applying a preset read voltage to the three-bit storage cell, its storage state can be determined, and then the stored value can be read.

[0069] Furthermore, each multi-bit storage cell has multiple preset read voltages to read the stored values ​​under different storage states. In the definition step S101, a read offset is set for each preset read voltage, and at least one read offset is set so that the preset read voltage can be compensated when the multi-bit storage cell is read later, thereby solving the problem of threshold voltage shift of the multi-bit storage cell.

[0070] Further, please refer to Figure 4 , Figure 4 This is another structural schematic diagram of a voltage compensation device provided according to an embodiment of the present invention. Each of the multi-bit storage cells is programmed to be one of multiple threshold voltages. When there are N sampling voltages, the multi-bit storage cell falls into one of N+1 sampling read value partitions obtained due to the different threshold voltages. Each sampling read value partition corresponds to an offset flag. The offset setting module 20 may specifically include:

[0071] The sampling read value acquisition unit 21 is used to acquire the read values ​​of multiple memory cells on adjacent word lines of the multiple memory cells to be read using N sampling voltages.

[0072] The read value partitioning unit 22 is used to classify the multi-bit storage cells on the adjacent word lines of the multi-bit storage cells to be read into one of the N+1 sampled read value partitions according to the read value;

[0073] The offset flag acquisition unit 23 is used to acquire the corresponding offset flag according to the sampled reading partition that has been classified.

[0074] It should be noted that when there is one sampled voltage, there are two corresponding sampled read partitions, each with an offset flag. Since the offset flag is represented by log2(N+1) bits, only one bit is needed to represent it. The offset flag is stored in the program block latch of the memory and has values ​​of 0 and 1. When there are three sampled voltages, there are four corresponding sampled read partitions. In this case, two bits are needed to represent the offset flag, which has values ​​of 00, 01, 10, and 11.

[0075] (3) Reading module 30

[0076] The reading module 30 is used to execute the reading step S103, that is, to read the multi-bit storage cell to be read by combining the multi-level preset reading voltage with the reading offset amount corresponding to the offset flag of each preset reading voltage.

[0077] For details, please continue reading Figure 4 The reading module 30 may specifically include:

[0078] The determination unit 31 is used to determine the current reading offset of the preset reading voltage corresponding to the offset flag;

[0079] The execution unit 32 is used to read the voltage of the multi-bit memory cell to be read as the sum of the preset read voltage and the current read offset.

[0080] It should be noted that when there are N sampled voltages, each preset read voltage has N+1 read offsets, and one of the read offsets is 0. For example, when there is one sampled voltage, two read offsets will be set, with one read offset being 0; when there are three sampled voltages, four read offsets will be set, with one read offset being 0. Furthermore, the read offset includes either the voltage offset value or the voltage bias time.

[0081] Specifically, the offset flag is stored in the program block latch of the memory. Furthermore, when there are N sampled voltages, the program block latch has log2(N+1) data bits for storing the offset flag.

[0082] Furthermore, the voltage compensation device is suitable for lower page read operations, intermediate page read operations, and higher page read operations of the memory.

[0083] Specifically, this voltage compensation device can improve ESUM to 120mV.

[0084] Unlike existing technologies, this invention provides a voltage compensation device applied to a memory. The memory includes multiple word lines and multiple multi-bit storage cells connected to the word lines. The multi-bit storage cells are used to read stored values ​​through multiple preset read voltages. The voltage compensation device includes: a definition module 10 for defining at least one read offset for each of the multiple preset read voltages; an offset setting module 20 for selecting at least one preset read voltage as a sampling voltage to read the multi-bit storage cells on adjacent word lines of the multi-bit storage cell to be read, and setting an offset flag representing the magnitude of the read offset based on the sampled read value of the sampling voltage; and a read module 30 for combining the multiple preset read voltages with the read offsets corresponding to the offset flags of each preset read voltage to read the multi-bit storage cell to be read. This compensates the preset read voltage of the multi-bit storage cell to be read, effectively solving the problem of threshold voltage shift of the multi-bit storage cell to be read when writing to adjacent word lines of the multi-bit storage cell to be read.

[0085] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0086] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for reading a memory, the memory comprising multiple word lines and multiple multi-bit storage cells connected to the multiple word lines, wherein the multi-bit storage cells are used to read stored values ​​by means of multiple preset read voltages, characterized in that, The reading method includes: The offset determination step involves using sampling voltages to read multiple memory cells on adjacent word lines of the multi-bit memory cell to be read, and determining an offset flag representing the magnitude of the read offset based on the sampled reading value of the sampling voltages; wherein, the sampling voltage is at least one of the multiple preset read voltages; there are N sampling voltages, and each preset read voltage corresponds to N+1 read offsets, where N is a positive integer greater than or equal to 1; the read offsets corresponding to each preset read voltage of the multi-bit memory cell to be read are at least partially different. The reading step involves using the multi-stage preset reading voltage and the reading offset of each preset reading voltage corresponding to the offset flag to read the multi-bit storage unit to be read.

2. The reading method according to claim 1, characterized in that, The read offset decreases as the preset read voltage order increases.

3. The reading method according to claim 1, characterized in that, Each of the multi-bit storage cells is programmed to one of multiple threshold voltages; the multi-bit storage cell falls into one of N+1 sampled read partitions resulting from the different threshold voltages, each sampled read partition corresponding to an offset flag.

4. The reading method according to claim 3, characterized in that, The offset determination step specifically includes: The sampling and reading step involves using N sampling voltages to obtain the reading values ​​of multiple memory cells on adjacent word lines of the multiple memory cells to be read. The sampling read value partitioning step involves classifying the multi-bit storage units on adjacent word lines of the multi-bit storage unit to be read into one of the N+1 sampling read value partitions based on the read value. The offset flag acquisition step involves determining the corresponding offset flag based on the sampled read value partition to which the partition is classified.

5. The reading method according to claim 4, characterized in that, The reading steps specifically include: The determination step involves determining the current read offset of the corresponding preset read voltage based on the offset flag. The execution step involves using the sum of the corresponding preset read voltage and the current read offset to read the multi-bit storage unit to be read.

6. The reading method according to claim 1, characterized in that, The method further includes: Define the steps, and define N+1 reading offsets corresponding to each preset reading voltage.

7. The reading method according to claim 1, characterized in that, The offset flag is represented by log2(N+1) bits.

8. The reading method according to claim 1, characterized in that, The read offset includes either the voltage offset value or the voltage bias time.

9. The reading method according to claim 1, characterized in that, The adjacent word line is the word line following the word line of the multi-bit storage unit to be read.

10. The reading method according to claim 1, characterized in that, The storage unit includes a three-bit storage unit, and the memory includes low pages, middle pages, and high pages; The reading method is applicable to the reading operation of the lower page, the reading operation of the middle page, and the reading operation of the higher page.

11. A memory, comprising a memory cell array and peripheral circuitry coupled to the memory cell array; wherein, The memory cell array includes multiple word lines and multiple multi-bit memory cells connected to the multiple word lines; the peripheral circuit is configured to read the stored value of the multi-bit memory cells through multiple preset read voltages, characterized in that the peripheral circuit is configured as follows: The sampling voltage is used to read multiple memory cells on adjacent word lines of the multi-bit memory cell to be read, and an offset flag representing the size of the read offset is determined according to the sampled read value of the sampling voltage; the multi-level preset read voltage and the read offset corresponding to the offset flag of each level of the preset read voltage are used to read the multi-bit memory cell to be read; wherein, the sampling voltage is at least one of the multi-level preset read voltages; there are N sampling voltages, and there are N+1 read offsets corresponding to each level of the preset read voltage, where N is a positive integer greater than or equal to 1; the read offsets corresponding to each level of the preset read voltage of the multi-bit memory cell to be read are at least partially different.

12. The memory according to claim 11, characterized in that, The read offset decreases as the preset read voltage order increases.

13. The memory according to claim 11, characterized in that, Each of the multi-bit storage cells is programmed to one of multiple threshold voltages; the multi-bit storage cell falls into one of N+1 sampled read partitions resulting from the different threshold voltages, each sampled read partition corresponding to an offset flag.

14. The memory according to claim 13, characterized in that, The peripheral circuit is configured as follows: The reading values ​​of the multi-bit memory cells on the adjacent word lines of the multi-bit memory cell to be read are obtained by using N sampling voltages respectively; according to the reading values, the multi-bit memory cells on the adjacent word lines of the multi-bit memory cell to be read are classified into one of the N+1 sampling reading value partitions; according to the sampling reading value partition to which they are classified, the corresponding offset flag is determined.

15. The memory according to claim 14, characterized in that, The peripheral circuit is configured as follows: Based on the offset flag, the current read offset of the corresponding preset read voltage is determined; the multi-bit memory cell to be read is read using the sum of the corresponding preset read voltage and the current read offset.

16. The memory according to claim 11, characterized in that, The offset flag is stored in the program block latch of the memory.

17. The memory according to claim 16, characterized in that, The program block latch has log2(N+1) data bits for storing the offset flag.

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