3D NAND memory device and method of manufacturing the same

Abstract

The application provides a 3D NAND memory device and a manufacturing method thereof. A plurality of storage areas are separated by a pseudo storage area. A stack layer is etched to form a plurality of gate line isolation gaps in the pseudo storage area. An insulating layer is filled in the gate line isolation gaps. A connection hole is obtained by etching the insulating layer to penetrate the insulating layer to a substrate. A metal is filled in the connection hole to form a contact plug in the gate line isolation gap. Finally, an electrical connection is formed from one side surface of the 3D NAND memory device to the opposite side surface through a plurality of contact plugs. As can be seen, the application forms sufficient contact plugs in the 3D NAND memory device by forming the contact plugs in the gate line isolation gaps, and avoids reducing the area of the storage area in the memory device, thereby improving the performance of the memory device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices and manufacturing thereof, in particular to a 3D NAND memory device and a manufacturing method thereof. BACKGROUND

[0002] NAND memory device is a non-volatile storage product with low power consumption, light weight and good performance, which has been widely used in electronic products. The planar structure of NAND device has reached the limit of actual expansion. In order to further improve the storage capacity and reduce the storage cost per bit, 3D NAND memory device is proposed.

[0003] However, the current 3D NAND memory device has the problem of insufficient storage performance, which cannot meet the demand of high-performance storage. SUMMARY

[0004] The present application provides a 3D NAND memory device and a manufacturing method thereof, which can form sufficient contact plugs in the 3D NAND memory device to improve the performance of the memory device.

[0005] The present application provides a manufacturing method of a 3D NAND memory device, comprising:

[0006] providing a substrate, wherein a stack layer of alternating layers of a sacrificial layer and a dielectric layer is formed on the substrate;

[0007] etching the stack layer to form a plurality of gate line isolation gaps in the stack layer, the gate line isolation gaps penetrating through the stack layer to the substrate, the plurality of gate line isolation gaps being formed in a pseudo storage area, the pseudo storage area dividing the stack layer into a plurality of storage areas;

[0008] filling an insulating layer into the gate line isolation gaps;

[0009] etching the insulating layer to form a connection hole, the connection hole penetrating through the insulating layer to the substrate;

[0010] performing metal filling of the connection hole.

[0011] Optionally, the gate line isolation gap comprises a first isolation gap and a second isolation gap, and the first isolation gap is close to the storage area.

[0012] Further comprising:

[0013] performing etching from the substrate to form a contact hole penetrating through the substrate, and the contact hole exposes the metal filled in the connection hole of the second isolation gap;

[0014] performing metal filling of the contact hole.

[0015] Optionally, the etching the insulating layer comprises:

[0016] only etching the insulating layer in the second isolation gap;

[0017] further comprising:

[0018] etching from the substrate to form an isolation via through the substrate; the isolation via is close to the storage region and exposes the insulating layer of the first isolation gap;

[0019] filling the isolation via with insulating material to form a deep trench isolation layer.

[0020] Optionally, before filling the contact hole with metal, further comprising:

[0021] depositing insulating material;

[0022] removing the insulating material at the bottom of the contact hole, while retaining the insulating material at the sidewall of the contact hole;

[0023] wet cleaning the contact hole.

[0024] Optionally, a channel hole is formed in the stack layer of the storage region, the channel hole penetrates the stack layer to the substrate, and a storage functional layer and a channel layer are sequentially formed in the channel hole;

[0025] before filling the gate line isolation gap with insulating layer, further comprising:

[0026] using the gate line isolation gap to remove the sacrificial layer to form an opening;

[0027] forming a gate layer in the opening.

[0028] Optionally, after filling the connection hole with metal, further comprising:

[0029] forming a bonding layer on the stack layer, the bonding layer comprising a metal bonding layer;

[0030] the metal bonding layer is electrically connected with the metal in the connection hole.

[0031] Optionally, the insulating layer is a silicon oxide layer, and the filled metal in the connection hole is tungsten.

[0032] Embodiments of the present application also provide a 3D NAND memory device, comprising:

[0033] a substrate, the substrate having a stack layer of alternating sacrificial layers and dielectric layers formed thereon;

[0034] The stack layer has a plurality of gate line isolation gaps, the gate line isolation gaps penetrating the stack layer to the substrate; the plurality of gate line isolation gaps are formed in a dummy storage area, the dummy storage area dividing the stack layer into a plurality of storage areas;

[0035] The gate line isolation gap has an insulating layer and a connection hole formed therein; the connection hole penetrates the insulating layer to the substrate;

[0036] The connection hole is filled with metal.

[0037] Optionally, further comprising:

[0038] A contact hole penetrating the substrate to expose the metal in the connection hole and an isolation via penetrating the substrate;

[0039] The contact hole is filled with metal, and the isolation via has a deep trench isolation layer formed therein.

[0040] Optionally, further comprising:

[0041] A bonding layer is formed on the stack layer, the bonding layer comprising a metal bonding layer;

[0042] The metal bonding layer is electrically connected to the metal in the connection hole.

[0043] The embodiments of the present application provide a 3D NAND memory device and a manufacturing method thereof. A plurality of storage areas are separated by a dummy storage area. A stack layer is etched to form a plurality of gate line isolation gaps in the dummy storage area. An insulating layer is filled in the gate line isolation gaps, and the insulating layer is etched to form a connection hole penetrating the insulating layer to the substrate. Metal is filled in the connection hole to form a contact plug in the gate line isolation gap. Finally, a plurality of contact plugs are formed to electrically connect from one side surface of the 3D NAND memory device to the opposite side surface. As can be seen, the contact plug is formed in the gate line isolation gap, enough contact plugs can be formed in the 3D NAND memory device, and the area of the storage area in the memory device is not reduced, and the performance of the memory device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Figure 1 A structure schematic diagram of a 3D NAND memory device is shown;

[0046] Figure 2 A flow chart of a manufacturing method of a 3D NAND memory device is shown in the embodiments of the present application;

[0047] Figures 3-7 A structural schematic diagram of a 3D NAND memory device is shown in the embodiments of the present application;

[0048] Figure 8 A top view structural diagram of a 3D NAND memory device is shown in the embodiments of the present application;

[0049] Figures 9-13 A structural schematic diagram of another 3D NAND memory device is shown in the embodiments of the present application. DETAILED DESCRIPTION

[0050] In order to make the above objectives, characteristics and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] In the following description, a lot of specific details are set forth in order to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0052] Secondly, the present application is described in detail in combination with the schematic diagram, in the detailed description of the embodiments of the present application, for the convenience of description, the cross-sectional view of the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacturing.

[0053] Reference Figure 1 As shown, the plurality of storage areas 10 of the 3D NAND memory device are only isolated and distinguished by the gate line isolation structure 21 and the small area pseudo storage area 20, which can improve the proportion of the storage area in the 3D NAND memory device and increase the storage performance. However, the 3D NAND memory device with such structure has no sufficient contact plug formed by the spare area, which further causes that the electrical signal cannot be transmitted from one side surface of the 3D NAND memory device to the opposite side surface, and finally leads to the performance degradation of the memory device.

[0054] Based on this, embodiments of this application provide a 3D NAND memory device and its manufacturing method. Multiple memory regions are separated by pseudo-memory regions. A stacked layer is etched to form multiple gate line isolation gaps in the pseudo-memory regions. An insulating layer is filled into the gate line isolation gaps, and the insulating layer is etched to obtain connection holes penetrating the insulating layer to the substrate. Metal is filled into the connection holes to form contact plugs within the gate line isolation gaps. Finally, multiple contact plugs form an electrical connection from one surface of the 3D NAND memory device to the opposite surface. Therefore, this application, by forming contact plugs in the gate line isolation gaps, can form sufficient contact plugs in the 3D NAND memory device and can avoid reducing the area occupied by the memory regions, thereby improving the performance of the memory device.

[0055] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0056] refer to Figure 2 The image shows a method for manufacturing a 3D NAND memory device according to an embodiment of this application. This method may include:

[0057] S201, a substrate 100 is provided, on which a stacked layer 110 of alternating sacrificial layers 111 and dielectric layers 112 is formed, reference. Figure 3 As shown.

[0058] In the embodiments of this application, the substrate 100 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may also include substrates of other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as a Si / SiGe substrate, or other epitaxial structures, such as SGOI (Silicon On Germanium). In this embodiment, the substrate 100 is a silicon substrate.

[0059] In embodiments of this application, a stacked layer 110 may be formed on the substrate 100, as shown in the reference. Figure 3 As shown. Stacked layer 110 is used to form a string of memory cells perpendicular to the substrate direction. The string of memory cells has a storage function. The number of stacked layers 110 is determined by the number of memory cell layers in the formed 3D NAND memory device. The more stacked layers 110 there are, the more memory cells are contained in the formed string of memory cells, and the higher the integration of the device.

[0060] The stack layer 110 can include a sacrificial layer 111 and a medium layer 112. The sacrificial layer 111 occupies a position for a subsequent gate layer. The medium layer 112 separates the sacrificial layer 111. After the sacrificial layer 111 is replaced by the gate layer, the medium layer 112 separates the gate layer to avoid contact. The medium layer 112 can be a silicon oxide layer, and the sacrificial layer 111 can be a silicon nitride layer.

[0061] The stack layer 110 can be formed by a single deck, for example, by alternately stacking the sacrificial layer 111 and the medium layer 112. The stack layer 110 can also be formed by a dual-deck, for example, by sequentially stacking. The stack layer 110 can also be formed by a multiple deck, for example, by forming a sub-deck by alternately stacking part of the sacrificial layer 111 and the medium layer 112. In specific embodiments, the sacrificial layer 111 and the medium layer 112 can be sequentially and alternately deposited by chemical vapor deposition, atomic layer deposition, or other suitable deposition methods to form the stack layer 110.

[0062] S202, etching the stack layer 110 to form a plurality of gate line isolation gaps 121 / 122 in the stack layer 110, the gate line isolation gaps 121 / 122 penetrating the stack layer 110 to the substrate 100, the plurality of gate line isolation gaps 121 / 122 being formed in a dummy storage area 1000, the dummy storage area 1000 dividing the stack layer into a plurality of storage areas 2000, as shown in Figure 4 .

[0063] In embodiments of the present application, after the stack layer 110 is formed on the substrate 100, the stack layer 110 can be etched to form a plurality of gate line isolation gaps 121 / 122. The area where the plurality of gate line isolation gaps 121 / 122 are located constitutes a gate line isolation structure 121 / 122. The gate line isolation structure 121 / 122 divides the stack layer 110 into a plurality of storage areas 2000, and the stack layer 110 of the storage area is used to form a storage cell.

[0064] In embodiments of the present application, the etching of the stack layer 110 can be performed by an etching technique, for example, by using reactive ion etching. The etching is performed until the surface of the substrate 100 is etched, thereby forming the gate line isolation gaps 121 / 122 penetrating the stack layer 110 to the substrate 100, as shown in Figure 4 .

[0065] S203, filling the gate line isolation gaps 121 / 122 with an insulating layer, as shown in Figure 5 .

[0066] In the embodiments of the present application, after the plurality of gate line isolation gaps 121 / 122 are formed by etching the stack layer 110, in order to be able to isolate through the gate line isolation gaps 121 / 122, an insulating material can be deposited in the gate line isolation gaps 121 / 122 to form an insulating layer 130 in the gate line isolation gaps 121 / 122, as shown in FIG. 1C. The insulating layer 130 can be a single layer structure, for example, can be silicon nitride, silicon oxide, silicon oxynitride, etc., or can be a multi-layer structure, for example, a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. The deposition method of the insulating layer 130 can be chemical vapor deposition (CVD). In the embodiments of the present application, the insulating layer 130 is a silicon oxide layer. Figure 5

[0067] In the embodiments of the present application, the gate line isolation gaps 121 / 122 can include a first isolation gap 121 and a second isolation gap 122. The first isolation gap 121 is close to the storage region 2000, and after the insulating layer 130 is filled in the first isolation gap, the insulating layer is used to isolate the storage cells formed subsequently in different storage regions. The second isolation gap 122 is away from the storage region 2000, and is used to form a connection hole subsequently in the second isolation gap 122 to increase the number of contact plugs in the 3D NAND memory device, thereby improving the performance of the device.

[0068] In actual applications, the second isolation gap 122 will form a contact plug subsequently, so when the second isolation gap 122 and the first isolation gap 121 are formed by etching the stack layer 110, the size of the second isolation gap 122 can be greater than the size of the first isolation gap 121.

[0069] S204, etching the insulating layer 130 to form a connection hole 140, the connection hole 140 penetrating through the insulating layer 130 to the substrate 100, as shown in FIG. 1D. Figure 6

[0070] In the embodiments of the present application, after the insulating layer 130 is deposited in the plurality of gate line isolation gaps 121 / 122, the insulating layer in the gate line isolation gaps 121 / 122 can be etched to form a connection hole 140 in the gate line isolation gaps 121 / 122, the connection hole 140 penetrating through the insulating layer 130 to the substrate 100, the connection hole 140 being used to form a contact plug subsequently, and providing sufficient channels for electrical connection between the first surface and the second surface of the memory device, the first surface and the second surface being two opposite surfaces of the memory device.

[0071] Optionally, only the insulating layer 130 in the second isolation gap 122 can be anisotropically etched to expose the substrate 100, thereby forming a connection hole 140 penetrating through the insulating layer 130 in the second isolation gap 122, as shown in FIG. 1D.​​Figure 6 as shown.

[0072] S205, metal filling of the connection hole 140 is performed, referring to Figure 7 as shown.

[0073] In the embodiment of the present application, after the insulating layer 130 in the etched gate line isolation gap 121 / 122 is etched to obtain the connection hole 140, the filling of the connection hole 140 can be continued, referring to Figure 7 as shown. Since the connection hole 140 is used to form a contact plug to realize the electrical connection between the first surface and the second surface of the memory device, the filling layer 150 in the connection hole 140 is a conductive material, such as copper, tungsten or other metal materials. In the embodiment, the material of the filling layer 150 is tungsten.

[0074] Referring to Figure 8 as shown, a top view structural diagram of a 3D NAND memory device provided by the embodiment of the present application, Figure 7 as shown, the structural schematic diagram of the 3D NAND memory device is obtained by cutting from the AA direction in Figure 8 .

[0075] As can be seen from Figure 8 , the first isolation gap 121 isolates the pseudo storage area 1000 and the storage area 2000, and a plurality of second isolation gaps 122 are arranged in the pseudo storage area, one or more connection holes 140 are formed in each second isolation gap 122, and the plurality of connection holes 140 are filled with metal to form a contact plug. The shape of the connection hole is not specifically limited in the embodiment of the present application, and can be set by itself according to the actual situation. When a plurality of connection holes 140 are formed in each second isolation gap 122, the number of connection holes 140 and the distance between the connection holes 140 can be set by itself according to the actual situation. The connection holes 140 in different second isolation gaps 122 can constitute an array arrangement.

[0076] Therefore, the method provided by the embodiments of the present application can form sufficient contact plugs in the memory device of the 3D NAND memory device by forming a plurality of contact plugs in the gate line isolation structure, and the contact plugs are not formed in a separate area, so that the area of the memory region in the memory device wafer is not reduced, that is, the method of the embodiments of the present application can increase the number of contact plugs and does not reduce the area of the memory region in the memory device wafer, thereby improving the performance of the memory device.

[0077] In addition, in the process of forming the connection hole, only the insulating layer filled in the gate line isolation gap needs to be etched, and the stack layer does not need to be etched, thereby reducing the process difficulty.

[0078] In the embodiments of the present application, after the connection hole 140 is formed in the gate line isolation gap 121 / 122 of the stack layer 110 and the connection hole 140 is filled with metal, a bonding layer can be formed on the stack layer 110, and the material of the bonding layer can be a dielectric material. The metal bonding layer is formed in the bonding layer and is electrically connected with the metal in the connection hole 140, which is used for electrical connection when bonding with other wafers or devices in the subsequent process.

[0079] In the embodiments of the present application, after the connection hole 140 is formed in the second isolation gap 122 and the metal is filled in the connection hole 140, the substrate 100 can also be etched to obtain a contact hole 160 penetrating through the substrate 100, and the metal in the contact hole 160 is filled to form electrical connection between the metal in the connection hole 140 and the metal in the contact hole 160.

[0080] Specifically, the substrate 100 has opposite first and second surfaces. The stack layer 110 is formed on the first surface of the substrate 100, and the connection hole 140 is formed subsequently. The contact hole 160 penetrating through the substrate 100 is formed by etching from the second surface of the substrate 100, and the contact hole 160 exposes the metal filled in the connection hole 140 of the second isolation gap 122, as shown in FIG. 8. Figure 9

[0081] After the contact hole 160 is formed, deposition of the insulating material 170 can also be performed, so that the insulating material 170 covers the bottom and sidewall of the contact hole 160, as shown in FIG. 9. Figure 10 ​The insulating material 170 can form a single layer structure, such as silicon nitride, silicon oxide, silicon oxynitride, etc., or a multi-layer structure, such as a stack of silicon nitride, silicon oxide, silicon oxynitride, etc. In the present embodiment, the insulating material can be silicon oxide. The insulating material can be deposited by chemical vapor deposition (CVD). The insulating material 170 is used to insulate and isolate the metal filling material formed in the contact hole 160 from the substrate 100 later, thereby improving the reliability and performance of the device.

[0082] In the present embodiment, after the insulating material is deposited, an etching process can be used to remove the insulating material at the bottom of the contact hole 160 to expose the metal filling material in the connection hole 140 of the second isolation gap 122, while retaining the insulating material 170 on the sidewall of the contact hole 160, as shown in FIG. 2B. Figure 11 Specifically, a dry etching process can be used to remove the insulating material at the bottom of the contact hole 160. The dry etching process can use chlorine gas or a fluorine-containing gas, which can be carbon tetrafluoride (CF4).

[0083] After the insulating material at the bottom of the contact hole 160 is removed by the etching process, a wet cleaning process can also be used to clean the contact hole 160 to remove residues left after etching. After wet cleaning, the contact hole 160 is filled with metal to form a contact 180 for subsequent electrical leads, as shown in FIG. 2C. Figure 12 The contact hole 160 is filled with a conductive material, such as a metal material such as copper, tungsten, etc. In the present embodiment, the conductive material filled is tungsten.

[0084] In the present embodiment, the first isolation gap 121 is adjacent to the storage region 2000, and after the insulating layer 130 is filled in the first isolation gap, the insulating layer is used to isolate the storage cells formed in different storage regions later. That is, no connection hole 140 is formed in the first isolation gap 121. In order to isolate the substrate 100 of different storage regions, an isolation through hole 190 can be etched from the substrate 100 to penetrate the substrate 100, the isolation through hole 190 being adjacent to the storage region 2000 and exposing the insulating layer 130 of the first isolation gap 121, as shown in FIG. 2D. Figure 9

[0085] The isolation through hole 190 can be etched simultaneously with the contact hole 160, or can be etched at different times, and the present embodiment does not specifically limit the order in which the isolation through hole 190 and the contact hole 160 are etched.

[0086] ​In the embodiments of the present application, after the isolation via hole 190 penetrating the substrate 100 is etched, an insulating material can be deposited and filled in the isolation via hole 190 to form a deep trench isolation layer 200, which is used to isolate different storage regions of the substrate 100, as shown in Figure 10

[0087] In actual applications, the isolation via hole 190 can be etched at the same time as the contact hole 160, and then the insulating material can be deposited and filled in the isolation via hole 190 and the contact hole 160 at the same time, saving the process flow and reducing the process cost.

[0088] As shown in Figure 13 The plurality of storage regions 2000 are isolated by the gate line isolation structure 121 / 122, and the channel hole 210 is formed in the stack layer 110 of the plurality of storage regions 2000, the channel hole 210 penetrates the 110 stack layer to the substrate 100, and the storage functional layer 211 and the channel layer 212 are sequentially formed in the channel hole 210.

[0089] Specifically, after the stack layer 110 is formed on the substrate 100, the stack layer 110 can be etched to form the channel hole 210, which is used to form a storage cell string subsequently.

[0090] The method of forming the channel hole 210 can be: forming a hard mask layer on the surface of the stack layer 110, which can be, for example, a silicon oxide layer or a silicon nitride layer; then spin-coating a photoresist layer on the surface of the hard mask layer, forming a patterned photoresist layer through exposure, development and other steps, and the pattern of the photoresist layer can be determined by a mask plate used to form the channel hole in the 3D NAND memory manufacturing process; transferring the pattern to the hard mask layer; then etching the stack layer 110 with the hard mask layer as a shield to form the channel hole 210 penetrating the stack layer 110, which can penetrate into the substrate 100. After the channel hole 210 is formed, the hard mask layer and the photoresist layer can be removed. In specific implementation, the channel hole 210 can penetrate the stack layer 110 into the substrate 100.

[0091] Then, the storage functional layer 211 and the channel layer 212 are sequentially formed in the channel hole 210. The storage functional layer 211 can include a blocking layer, a charge storage layer and a tunneling layer which are sequentially stacked. In specific embodiments, the blocking layer, the charge storage layer and the tunneling layer can be an ONO stack, and the channel layer 212 can be a polysilicon layer.

[0092] ​In the embodiments of the present application, the storage functional layer 211 can be formed by sequentially stacking the blocking layer, the charge storage layer and the tunneling layer in the channel hole 210, and then forming the channel layer 212 on the sidewall of the storage functional layer 211. The filling layer of insulating material can be formed between the channel layers 212, and the filling layer can be a silicon oxide layer. In specific embodiments, a conductive layer can be formed above the storage cell string, and the conductive layer is used to form the upper select gate device of the storage cell string, and the conductive layer will also form an interconnection structure to further form a bit line. Then, a dielectric layer can be formed above the stack layer 110, and the dielectric layer is used to protect the formed storage functional layer and the conductive layer. The dielectric layer can be, for example, silicon oxide, silicon nitride, etc. In specific embodiments, the dielectric layer material can be deposited above the stack layer 110, and then a planarization process is performed to form a dielectric layer with uniform thickness above the stack layer. For example, chemical mechanical polishing can be used to planarize the dielectric layer.

[0093] In the embodiments of the present application, the channel hole 210 can be formed before the gate line isolation gap 121 / 122 is formed, and the storage functional layer and the channel layer can be formed in the channel hole 210.

[0094] In the embodiments of the present application, before the insulating layer 130 is filled into the gate line isolation gap 121 / 122, the sacrificial layer 111 in the stack layer 110 can be removed by etching through the gate line isolation gap 121 / 122 to form an opening, so that the gate layer can be formed in the opening later. Specifically, the gate layer is formed in the opening by the gate line isolation gap 121 / 122, and the material of the gate layer is a metal material.

[0095] The manufacturing method of the embodiments of the present application is described in detail above. In addition, the embodiments of the present application also provide a 3D NAND memory device formed by the above method. As shown in FIG. 11, the memory device includes: Figure 13

[0096] a substrate, wherein a stack layer formed by alternately stacking a sacrificial layer and a dielectric layer is formed on the substrate;

[0097] a plurality of gate line isolation gaps in the stack layer, wherein the gate line isolation gaps penetrate the stack layer to the substrate; the plurality of gate line isolation gaps are formed in a dummy storage area, and the dummy storage area divides the stack layer into a plurality of storage areas;

[0098] an insulating layer and a connection hole are formed in the gate line isolation gap; the connection hole penetrates the insulating layer to the substrate;

[0099] the connection hole is filled with a metal.

[0100] Optionally, the memory device further includes:

[0101] ​contact holes filled with metal and isolation vias through the substrate;

[0102] the contact holes are filled with metal and the isolation vias are formed with deep trench isolation layers.

[0103] Optionally, further comprising:

[0104] a bonding layer is formed on the stack, the bonding layer comprising a metal bonding layer;

[0105] the metal bonding layer is electrically connected with the metal in the connection holes.

[0106] The above merely provides the preferred embodiment of the present application, and the present application is not intended to be limited to the above. Any person skilled in the art, without departing from the scope of the present application, can make many possible changes and modifications to the above disclosed methods and technical contents, or modify equivalent embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the scope of the present application, shall still fall within the scope of protection of the present application.

Claims

1. A method for manufacturing a 3D NAND memory device, characterized in that, include: A substrate is provided on which a stack of sacrificial layers and dielectric layers are formed alternately; The stacked layer is etched to form a plurality of gate line isolation gaps in the stacked layer, the gate line isolation gaps extending through the stacked layer to the substrate, the plurality of gate line isolation gaps being formed in a pseudo memory region, the pseudo memory region dividing the stacked layer into a plurality of memory regions; the gate line isolation gaps include a first isolation gap and a second isolation gap, the first isolation gap being adjacent to the memory region. Fill the gaps in the grid lines with an insulating layer; Only the insulating layer in the second isolation gap is etched to form a connection hole, the connection hole penetrating the insulating layer to the substrate; The connection hole is then filled with metal.

2. The manufacturing method according to claim 1, characterized in that, Also includes: Etching is performed from the substrate to form contact holes that penetrate the substrate; The contact hole exposes the metal filling the connection hole of the second isolation gap; The contact hole is then filled with metal.

3. The manufacturing method according to claim 2, characterized in that, Also includes: Etching is performed from the substrate to form an isolation via through the substrate; The isolation via is located near the storage area and exposes the insulating layer of the first isolation gap; The insulating material is filled into the isolation vias to form a deep trench isolation layer.

4. The manufacturing method according to claim 2, characterized in that, Before performing the metal filling of the contact hole, the following steps are also included: Deposited insulating materials; Remove the insulating material at the bottom of the contact hole, while retaining the insulating material on the sidewalls of the contact hole; The contact holes are wet-cleaned.

5. The manufacturing method according to claim 1, characterized in that, A channel hole is formed in the stacked layer of the storage region, the channel hole penetrates the stacked layer to the substrate, and a storage functional layer and a channel layer are formed sequentially in the channel hole; Before filling the insulating layer into the grid line isolation gap, the method further includes: The sacrificial layer is removed by using the grid lines to isolate the gaps, thus forming an opening; A gate layer is formed in the opening.

6. The method according to claim 1, characterized in that, After filling the connection hole with metal, the process further includes: A bonding layer is formed on the stacked layers, the bonding layer comprising a metal bonding layer; The metal bonding layer is electrically connected to the metal inside the connection hole.

7. The method according to claim 1, characterized in that, The insulating layer is a silicon oxide layer, and the metal filling the connection hole is tungsten.

8. A 3D NAND storage device, characterized in that, include: A substrate on which a stack of sacrificial layers and dielectric layers are alternately stacked; The stacked layer has a plurality of gate line isolation gaps, which penetrate the stacked layer to the substrate; The plurality of gate isolation gaps are formed in the pseudo memory region, which divides the stacked layer into a plurality of memory regions; the gate isolation gaps include a first isolation gap and a second isolation gap, wherein the first isolation gap is close to the memory region; An insulating layer and a connection hole are formed in the second isolation gap; the connection hole penetrates the insulating layer to the substrate.

9. The device according to claim 8, characterized in that, Also includes: Contact holes extending through the substrate to expose the metal within the connection hole and isolation vias extending through the substrate; The contact hole is filled with metal, and a deep trench isolation layer is formed in the isolation through hole.

10. The device according to claim 8, characterized in that, Also includes: A bonding layer is formed on the stacked layer, and the bonding layer includes a metal bonding layer; The metal bonding layer is electrically connected to the metal inside the connection hole.

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