Semiconductor device and method of manufacturing the same

Abstract

This invention relates to a semiconductor device and a method for fabricating the same, comprising: forming a substrate, the substrate including a substrate, a first insulating layer covering a first isolation region of the substrate, and a second insulating layer with a flat surface covering the first insulating layer and a second isolation region; etching the second insulating layer to form a first shallow trench and a second shallow trench, the first shallow trench being located on the first isolation region and exposing a portion of the surface of the first insulating layer, and the second shallow trench being located on the second isolation region; selectively etching the first insulating layer and the substrate relative to the second insulating layer to form a first transition trench including the first shallow trench, and etching the second insulating layer to form a second transition trench including the second shallow trench; etching the substrate to form a first isolation trench and a second isolation trench of different depths; and forming a shallow trench isolation structure in the first isolation trench and the second isolation trench, thereby simplifying the process flow, reducing the number of photomasks used in the process, and lowering production costs.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a semiconductor device and its fabrication method. [Background Technology]

[0002] In semiconductor integrated circuit (IC) devices, shallow trench isolation (STI) structures are generally used as isolation regions to enable the various discrete circuit elements contained in the IC device to operate independently.

[0003] In the prior art, IC devices generally include multiple CMOS (Complementary Metal-Oxide Semiconductor) devices with different turn-on voltages. In order to meet the different requirements of CMOS devices with different turn-on voltages in terms of voltage withstand and leakage current, there will inevitably be differences in the physical structure of different CMOS devices.

[0004] However, in order to meet the differences in physical structure of different CMOS devices, the traditional process approach is to fabricate CMOS devices with different physical structures separately, which results in complex process flow and high production costs, thus weakening product competitiveness. [Summary of the Invention]

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method to solve the problems of overly complex process flow and high production cost in the prior art for forming CMOS devices with different physical structures, thereby improving product competitiveness.

[0006] To address the aforementioned problems, the present invention provides a method for fabricating a semiconductor device. The method includes: forming a substrate, the substrate comprising a base, a first insulating layer, and a second insulating layer; the base comprising a first isolation region and a second isolation region; the first insulating layer covering the first isolation region; and the second insulating layer having a flat surface and covering both the first insulating layer and the second isolation region; etching the second insulating layer to form a first shallow trench and a second shallow trench, the first shallow trench being located on the first isolation region and exposing a portion of the surface of the first insulating layer, and the second shallow trench being located on the second isolation region; selectively etching the first insulating layer and the substrate relative to the second insulating layer along the bottom of the first shallow trench to form a first transition trench including the first shallow trench, and etching the second insulating layer along the bottom of the second shallow trench to form a second transition trench including the second shallow trench, the first transition trench and the second transition trench exposing the substrate, and the depth of the first transition trench being greater than the depth of the second transition trench; etching the substrate along the bottom of the first transition trench and the bottom of the second transition trench to form a first isolation trench including the first transition trench and a second isolation trench including the second transition trench of different depths; forming a first shallow trench isolation structure in the first isolation trench and forming a second shallow trench isolation structure in the second isolation trench.

[0007] The process of forming a substrate specifically includes: providing a substrate; forming a transition insulating layer covering a first isolation region and a second isolation region of the substrate; forming a first opening in the transition insulating layer, the first opening exposing at least a portion of the surface of the substrate in the first isolation region; forming a first insulating layer in the first opening; and forming a cover insulating layer on the transition insulating layer and the first insulating layer to obtain a second insulating layer including the transition insulating layer and the cover insulating layer.

[0008] Specifically, along the bottom of the first shallow groove, the first insulating layer and the substrate are selectively etched relative to the second insulating layer to form a first transition groove including the first shallow groove, and along the bottom of the second shallow groove, the second insulating layer is etched to form a second transition groove including the second shallow groove. This includes: along the bottom of the first shallow groove, the first insulating layer is selectively etched relative to the second insulating layer to form an upper transition groove, which exposes the substrate; along the bottom of the upper transition groove, the substrate is selectively etched relative to the second insulating layer to form a lower transition groove, thus obtaining a first transition groove including the first shallow groove, the upper transition groove, and the lower transition groove. Furthermore, during the selective etching of the substrate relative to the second insulating layer, the second insulating layer exposed at the bottom surface of the second shallow groove is simultaneously etched to form a second transition groove including the second shallow groove.

[0009] Specifically, along the bottom of the first shallow groove, the first insulating layer and the substrate are selectively etched relative to the second insulating layer to form a first transition groove including the first shallow groove, and along the bottom of the second shallow groove, the second insulating layer is etched to form a second transition groove including the second shallow groove. This includes: along the bottom of the first shallow groove, the first insulating layer is selectively etched relative to the second insulating layer to form an upper transition groove, which exposes the substrate; along the bottom of the upper transition groove, the substrate is selectively etched relative to the second insulating layer to form a lower transition groove, thus obtaining a first transition groove including the first shallow groove, the upper transition groove, and the lower transition groove; along the bottom of the second shallow groove, the second insulating layer is selectively etched relative to the substrate to form a second transition groove including the second shallow groove.

[0010] Specifically, etching the second insulating layer to form the first shallow groove and the second shallow groove includes: forming a mask layer on the second insulating layer; etching the mask layer to form a second opening to obtain a mask layer with the second opening; and etching the second insulating layer through the mask layer with the second opening to form the first shallow groove and the second shallow groove.

[0011] The substrate further includes a first well region and a second well region, with a first isolation region located around the first well region and a second isolation region located around the second well region.

[0012] The first well region includes a first source region, a first channel region, and a first drain region connected in sequence. The substrate also includes a third insulating layer, which covers the first channel region. A second insulating layer covers the third insulating layer, and the third insulating layer and the first insulating layer are formed through the same process steps.

[0013] The process includes, after forming a first shallow trench isolation structure in the first isolation groove and a second shallow trench isolation structure in the second isolation groove, removing the second insulating layer.

[0014] The second well region includes a second source region, a second channel region, and a second drain region connected in sequence. After removing the second insulating layer, it also includes: forming a fourth insulating layer on the second channel region, the thickness of the fourth insulating layer being less than the thickness of the third insulating layer.

[0015] The process includes, after forming a fourth insulating layer on the second channel region, forming a first gate layer on the third insulating layer and forming a second gate layer on the fourth insulating layer.

[0016] To address the aforementioned problems, the present invention also provides a semiconductor device comprising: a substrate including a first isolation region and a second isolation region; a first insulating layer covering the first isolation region; a first shallow trench isolation structure and a second shallow trench isolation structure, wherein the first shallow trench isolation structure penetrates the first insulating layer in the first isolation region, with one end extending into the substrate and the other end extending above the first insulating layer, and the second shallow trench isolation structure is located on the second isolation region, with one end extending into the substrate and the other end extending above the first insulating layer, wherein the extension depth of the first shallow trench isolation structure in the substrate is greater than the extension depth of the second shallow trench isolation structure in the substrate.

[0017] The semiconductor device further includes: a second insulating layer with a flat surface covering the first insulating layer and the second isolation region; a second shallow trench isolation structure having one end away from the substrate penetrating the second insulating layer and located within the second insulating layer; and a first shallow trench isolation structure having one end away from the substrate penetrating the second insulating layer and located within the second insulating layer.

[0018] The substrate further includes a first well region and a second well region, with a first isolation region located around the first well region and a second isolation region located around the second well region.

[0019] The first well region includes a first source region, a first channel region, and a first drain region connected in sequence. The semiconductor device also includes a third insulating layer, which covers the first channel region. A second insulating layer covers the third insulating layer, and the third insulating layer and the first insulating layer are formed through the same process steps.

[0020] The second well region includes a second source region, a second channel region, and a second drain region connected in sequence. The semiconductor device also includes a fourth insulating layer, which covers the second channel region and has a thickness less than that of the third insulating layer.

[0021] The semiconductor device also includes a first gate layer located on the third insulating layer.

[0022] The beneficial effects of this invention are as follows: Unlike existing technologies, the semiconductor device and its fabrication method provided by this invention involve forming a substrate, including a base, a first insulating layer, and a second insulating layer. The base includes a first isolation region and a second isolation region. The first insulating layer covers the first isolation region. The second insulating layer has a flat surface and covers both the first insulating layer and the second isolation region. Then, the second insulating layer is etched to form a first shallow groove and a second shallow groove. The first shallow groove is located on the first isolation region and exposes a portion of the surface of the first insulating layer. The second shallow groove is located on the second isolation region. Next, along the bottom of the first shallow groove, the first insulating layer and the substrate are selectively etched relative to the second insulating layer to form a first transition groove including the first shallow groove. Then, along the bottom of the second shallow groove, the second insulating layer is etched to form a second transition groove including the second shallow groove. The first and second transition trenches expose the substrate, with the depth of the first transition trench being greater than the depth of the second transition trench. Then, along the bottom of the first and second transition trenches, the substrate is etched to form a first isolation trench including the first transition trench and a second isolation trench including the second transition trench, with different depths. A first shallow trench isolation structure is then formed in the first isolation trench, and a second shallow trench isolation structure is formed in the second isolation trench. This avoids the problems of overly complex processes and high production costs associated with fabricating semiconductor devices with different physical structures (e.g., shallow trench isolation structures of different depths) separately in the prior art. It also reduces the number of masks used in the manufacturing process of shallow trench isolation structures of different depths, which is beneficial for optimizing the process, reducing production costs, and improving product competitiveness. [Attached Image Description]

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0025] Figures 2a-2n This is a structural schematic diagram corresponding to the manufacturing process of the semiconductor device provided in the embodiments of the present invention.

Detailed Implementation Methods

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the invention. Similarly, the following embodiments are only some, not all, embodiments of the present invention, and all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Furthermore, the directional terms used in this invention, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.

[0028] This invention can be presented in various forms, some of which will be described below.

[0029] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The specific process of the method for fabricating the semiconductor device can be as follows:

[0030] Step S11: Form a substrate, the substrate including a base, a first insulating layer and a second insulating layer, the base including a first isolation region and a second isolation region, the first insulating layer covering the first isolation region, and the second insulating layer having a flat surface and covering the first insulating layer and the second isolation region.

[0031] The cross-sectional structure diagram after step S11 is shown below. Figure 2a As shown.

[0032] The substrate 211 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The first insulating layer 212 and the second insulating layer 213 can be made of insulating materials such as silicon oxynitride, silicon nitride, or silicon oxide, and the first insulating layer 212 and the substrate 211 have etching selectivity relative to the second insulating layer 213.

[0033] In one specific embodiment, the first insulating layer 212 can have a high etching selectivity relative to the second insulating layer 213, so that in subsequent process steps, when selectively etching the first insulating layer 212 relative to the second insulating layer 213, the second insulating layer 213 will not be consumed by the etchant, or the second insulating layer 213 consumed by the etchant can be ignored.

[0034] In one specific embodiment, the substrate 211 can have a high etching selectivity relative to the second insulating layer 213, so that in subsequent process steps, when selectively etching the substrate 211 relative to the second insulating layer 213, a certain amount of the second insulating layer 213 can be simultaneously consumed by the etchant (that is, the second insulating layer 213 can be simultaneously consumed by the etchant, and the amount of the second insulating layer 213 consumed by the etchant cannot be ignored). Furthermore, the reaction rate between the second insulating layer 213 and the etchant is less than the reaction rate between the substrate 211 and the etchant.

[0035] In one specific embodiment, the material of the first insulating layer 212 may include silicon oxide, and the material of the second insulating layer 213 may include silicon nitride.

[0036] In one embodiment, such as Figure 2b As shown, the second insulating layer 213 may include a transition insulating layer 2131 and a cover insulating layer 2132 sequentially formed on the substrate 211. Accordingly, in order to form the substrate 21, step S11 may specifically include:

[0037] Step S111: Provide substrate 211.

[0038] Specifically, the first isolation region 211A and the second isolation region 211B in the substrate 211 are used to isolate different regions in the substrate 211.

[0039] In one specific embodiment, please refer to Figure 2c , Figure 2c This is a top view of the substrate 211 provided in an embodiment of the present invention, as shown in the figure. Figure 2c As shown, the substrate 211 may further include a first well region 211C and a second well region 211D. The first isolation region 211A may be located around the first well region 211C to isolate the first well region 211C from other regions (e.g., other well regions) located around it, thereby facilitating independent control of the transistor formed based on the first well region 211C. The second isolation region 211B may be located around the second well region 211D to isolate the second well region 211D from other regions (e.g., other well regions) located around it, thereby facilitating independent control of the transistor formed based on the second well region 211D.

[0040] In one possible embodiment, there may be multiple first well regions 211C, which may be spaced apart and adjacent first well regions 211C may be separated by the first isolation region 211A to ensure electrical isolation between different transistor devices in the semiconductor device.

[0041] In another possible embodiment, when there are multiple second well regions 211D, the multiple second well regions 211D can be arranged at intervals, and two adjacent second well regions 211D can be separated by the second isolation region 211B to ensure electrical isolation between different transistor devices in the semiconductor device.

[0042] Accordingly, adjacent first well region 211C and second well region 211D can be separated by the second isolation region 211B and / or the first isolation region 211A. In some embodiments, the second isolation region 211B and the first isolation region 211A can also be connected as one unit.

[0043] Furthermore, in specific implementation, the above step S111 may specifically include: doping ions on the upper surface of the substrate 211 (that is, the surface facing the first insulating layer 212 and the second insulating layer 213 in subsequent processes) to form a first well region 211C and a second well region 211D that are spaced apart.

[0044] The first well region 211C and the second well region 211D can be either P-type or N-type well regions. Specifically, the P-type well region can be formed by heavy P-type doping, and the N-type well region can be formed by heavy N-type doping. Taking a silicon substrate as an example, the N-type well region can be formed by doping the silicon substrate with a Group 5 element, such as nitrogen, phosphorus, or arsenic, and the P-type well region can be formed by doping the silicon substrate with a Group 3 element, such as boron or aluminum.

[0045] Step S112: Form a transition insulating layer 2131 covering the first isolation region 211A and the second isolation region 211B of the substrate 211.

[0046] Specifically, the transition insulating layer 2131 can be formed on the substrate 211 by methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition.

[0047] Step S113: A first opening 2131A is formed on the transition insulating layer 2131, the first opening 2131A exposing at least a portion of the surface of the substrate 211 in the first isolation region 211A.

[0048] Step S114: Form a first insulating layer 212 in the first opening 2131A.

[0049] The first opening 2131A is used to define the formation location of the first insulating layer 212. In a specific implementation, step S114 may specifically include: depositing insulating material in the first opening 2131A on the substrate 211; and removing the insulating material located outside the first opening 2131A by chemical mechanical polishing to obtain the first insulating layer 212.

[0050] It is understood that removing the insulating material overflowing from the first opening 2131A by chemical mechanical polishing can give the first insulating layer 212 a flat upper surface, so as to improve the stability of the structure formed on the first insulating layer 212 in subsequent steps.

[0051] Step S115: A covering insulating layer 2132 is formed on the transition insulating layer 2131 and the first insulating layer 212 to obtain a second insulating layer 213 including the transition insulating layer 2131 and the covering insulating layer 2132.

[0052] Specifically, the aforementioned transition insulating layer 2131 and cover insulating layer 2132 may have the same material, for example, both may be silicon nitride layers.

[0053] In some alternative embodiments, steps S112, S113, S114, and S115 described above can be replaced with:

[0054] Step S116: Form a first insulating layer 212 covering the first isolation zone 211A.

[0055] Step S117: Form a second insulating layer 213 with a flat surface that covers the first insulating layer 212 and the second isolation region 211B.

[0056] Specifically, the surface of the second insulating layer 213 facing away from the substrate 211 can be a flat surface. Therefore, the thickness of the second insulating layer 213 covering the surface of the first insulating layer 212 facing away from the substrate 211 will be less than the thickness of the second insulating layer 213 covering the second isolation region 211B.

[0057] In a specific embodiment completed by steps S111 to S115, the thickness of the second insulating layer 213 covering the surface of the first insulating layer 212 away from the substrate 211 can be the same as the thickness of the first insulating layer 212, so as to control the depth of the two etching processes and reduce the difficulty of the process.

[0058] It is understandable that, compared to the specific embodiment completed in steps S116 to S117 which requires etching to form the first insulating layer 212, the specific embodiment completed in steps S111 to S115 only requires etching to form the first opening 2131A, and the first insulating layer 212 can be obtained by filling. This is beneficial to reduce the damage of the etchant to the substrate 211 during the formation of the first insulating layer 212 and the second insulating layer 213, and improves the film quality of the first insulating layer 212 and the second insulating layer 213.

[0059] Step S12: Etch the second insulating layer to form a first shallow groove and a second shallow groove. The first shallow groove is located on the first isolation area and exposes part of the surface of the first insulating layer. The second shallow groove is located on the second isolation area.

[0060] The cross-sectional structure diagram after step S12 is shown below. Figure 2d As shown.

[0061] The first shallow groove 22A and the second shallow groove 22B are formed by the same etching process, and the depth of the first shallow groove 22A and the depth of the second shallow groove 22B can be the same.

[0062] Specifically, an anisotropic etching process (e.g., dry etching) can be used to etch the second insulating layer 213 from top to bottom on the first isolation region 211A and the second isolation region 211B to form the first shallow groove 22A and the second shallow groove 22B. Furthermore, by controlling the etching depth to be equal to or greater than the thickness T1 of the second insulating layer 213 covering the first insulating layer 212, and less than the thickness T2 of the second insulating layer 213 covering the second isolation region 211B, it can be ensured that at least a portion of the surface of the first insulating layer 212 can be exposed through the first shallow groove 22A, and that the second shallow groove 22B does not penetrate the second insulating layer 213.

[0063] In one specific embodiment, the cross-sectional structural diagram after step S12 is completed can be as follows: Figure 2e As shown, step S12 above can specifically include:

[0064] Step S121: Form a mask layer 23 on the second insulating layer 213.

[0065] Step S122: Form a second opening 23A on the mask layer 23 to obtain a mask layer 23 having a second opening 23A.

[0066] Specifically, the mask layer 23 can be a photoresist layer. Accordingly, the second opening 23A can be formed on the mask layer 23 by exposure and development. In an alternative embodiment, the mask layer 23 can be a hard mask layer, wherein the material of the hard mask layer can include amorphous carbon (AC). Accordingly, the second opening 23A can be formed on the mask layer 23 by etching.

[0067] Step S123: Etch the second insulating layer 213 through the mask layer 23 having the second opening 23A to form the first shallow groove 22A and the second shallow groove 22B.

[0068] The number and shape of the second openings 23A can correspond to the number and shape of the first shallow grooves 22A and the second shallow grooves 22B. That is, there are at least two second openings 23A, and the shape of each second opening 23A can be the same as the shape of its corresponding first shallow groove 22A or second shallow groove 22B.

[0069] Step S13: Along the bottom of the first shallow groove, selectively etch the first insulating layer and the substrate relative to the second insulating layer to form a first transition groove including the first shallow groove, and along the bottom of the second shallow groove, etch the second insulating layer to form a second transition groove including the second shallow groove. The first transition groove and the second transition groove expose the substrate, and the depth of the first transition groove is greater than the depth of the second transition groove.

[0070] In one embodiment, step S13 may specifically include:

[0071] Step S131: Selectively etch the first insulating layer relative to the second insulating layer along the bottom of the first shallow groove to form an upper transition groove, which exposes the substrate.

[0072] The cross-sectional structural diagram after step S131 can be as follows: Figure 2f As shown.

[0073] In this embodiment, the first insulating layer 212 has etching selectivity relative to the second insulating layer 213. Specifically, an anisotropic etching process (e.g., dry etching process) can be used to etch the first insulating layer 212 exposed through the bottom surface of the first shallow groove 22A according to the etching selectivity, so as to form the upper transition groove 241.

[0074] In one specific embodiment, the first insulating layer 212 can have a high etch selectivity relative to the second insulating layer 213. Therefore, during the etching process to form the upper transition groove 241, because the first insulating layer 212 has a high etch selectivity relative to the second insulating layer 213, the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B will not react with the etchant and be consumed, or the reaction rate of the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B with the etchant is much smaller than the reaction rate of the first insulating layer 212 exposed through the bottom surface of the first shallow groove 22A with the etchant, ensuring that the second insulating layer 213 consumed by the etchant during the etching process to form the upper transition groove 241 is negligible.

[0075] In some embodiments, during the etching process of forming the upper transition groove 241, the etching depth can be controlled to be equal to or greater than the thickness T3 of the first insulating layer 212, so as to ensure that at least a portion of the surface of the substrate 211 in the first isolation region 211A can be exposed via the upper transition groove 241.

[0076] Step S132: Along the bottom of the upper transition groove, selectively etch the substrate relative to the second insulating layer to form a lower transition groove, so as to obtain a first transition groove including a first shallow groove, an upper transition groove and a lower transition groove. When selectively etching the substrate relative to the second insulating layer, the second insulating layer exposed at the bottom surface of the second shallow groove is simultaneously etched to form a second transition groove including the second shallow groove.

[0077] The cross-sectional structure diagram after step S132 can be as follows: Figure 2g As shown.

[0078] In this embodiment, the substrate 211 exhibits etching selectivity relative to the second insulating layer 213. Specifically, an anisotropic etching process (e.g., dry etching) can be employed to selectively etch the substrate 211 exposed through the bottom surface of the upper transition groove 241 to form the lower transition groove 242, thereby obtaining a first transition groove 25A composed of the interconnected first shallow groove 22A, the upper transition groove 241, and the lower transition groove 242. The reaction rate between the second insulating layer 213 and the etchant is less than the reaction rate between the substrate 211 and the etchant.

[0079] In one specific embodiment, the substrate 211 can have a higher etching selectivity relative to the second insulating layer 213. That is, during the etching process to form the lower transition groove 242, the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B will also react with the etchant and be consumed. The amount of the second insulating layer 213 consumed by the etchant cannot be ignored.

[0080] Furthermore, in specific implementation, the etching selectivity ratio of the substrate 211 relative to the second insulating layer 213 can be set by selecting a suitable etchant, so that the etching selectivity ratio is such that when the substrate 211 is etched to a predetermined depth, the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B can be completely consumed by the etchant to form an intermediate transition groove 26, thereby obtaining a second transition groove 25B composed of the interconnected second shallow groove 22B and intermediate transition groove 26.

[0081] In an alternative embodiment, step S132 can be replaced by steps S133 and S134, and steps S133 and S134 can be specifically as follows:

[0082] Step S133: Selectively etch the substrate along the bottom of the upper transition groove relative to the second insulating layer to form a lower transition groove, so as to obtain a first transition groove including a first shallow groove, an upper transition groove and a lower transition groove.

[0083] The cross-sectional structure diagram after step S133 can be as follows: Figure 2h As shown.

[0084] In this embodiment, the substrate 211 can have a high etching selectivity relative to the second insulating layer 213. Specifically, an anisotropic etching process (e.g., dry etching process) can be used to selectively etch the substrate 211 exposed through the bottom surface of the upper transition groove 241 to form the lower transition groove 242, thereby obtaining a first transition groove 25A composed of the interconnected first shallow groove 22A, upper transition groove 241, and lower transition groove 242.

[0085] Furthermore, it is understood that during the etching process to form the lower transition groove 242, since the substrate 211 has a high etching selectivity relative to the second insulating layer 213, the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B will not react with the etchant and be consumed, or the reaction rate of the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B with the etchant is much smaller than the reaction rate of the substrate 211 exposed through the bottom surface of the upper transition groove 241 with the etchant, so as to ensure that the second insulating layer 213 consumed by the etchant during the etching process to form the lower transition groove 242 can be ignored.

[0086] Step S134: Selectively etch the second insulating layer relative to the substrate along the bottom of the second shallow groove to form a second transition groove including the second shallow groove.

[0087] The cross-sectional structure diagram after step S134 can be as follows: Figure 2g As shown.

[0088] In this embodiment, the second insulating layer 213 can have a high etching selectivity relative to the substrate 211. Specifically, an anisotropic etching process (e.g., dry etching process) can be used to selectively etch the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B to form an intermediate transition groove 26, thereby obtaining a second transition groove 25B composed of the interconnected second shallow groove 22B and the intermediate transition groove 26.

[0089] Furthermore, it is understood that during the etching process to form the intermediate transition groove 26, since the second insulating layer 213 has a high etching selectivity relative to the substrate 211, the substrate 211 exposed through the bottom surface of the first transition groove 25A will not react with the etchant and be consumed, or the reaction rate of the substrate 211 exposed through the bottom surface of the first transition groove 25A with the etchant is much smaller than the reaction rate of the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B with the etchant, so as to ensure that the substrate 211 consumed by the etchant during the etching process to form the intermediate transition groove 26 can be ignored.

[0090] In some alternative embodiments, in specific embodiments completed by steps S131, S133, and S134, steps S131 and S132 can be replaced with:

[0091] Step S135: Along the bottom of the first shallow groove, selectively etch the first insulating layer and the substrate relative to the second insulating layer through a single etching process to form a first transition groove including the first shallow groove.

[0092] Specifically, the first insulating layer 212 and the substrate 211 can simultaneously have a high etching selectivity relative to the second insulating layer 213. Furthermore, an anisotropic etching process (e.g., a dry etching process) can be used to selectively etch the first insulating layer 212 and the substrate 211 exposed through the bottom surface of the first shallow groove 22A in the same etching step to form the upper transition groove 241 and the lower transition groove 242.

[0093] Furthermore, it is understood that during the etching process of forming the upper transition groove 241 and the lower transition groove 242 in the same etching step, since the first insulating layer 212 and the substrate 211 have a high etching selectivity relative to the second insulating layer 213, the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B will not react with the etchant and be consumed, or the reaction rate of the second insulating layer 213 exposed through the bottom surface of the second shallow groove 22B with the etchant is much smaller than the reaction rate of the first insulating layer 212 and the substrate 211 exposed through the bottom surface of the first shallow groove 22A with the etchant, so as to ensure that the second insulating layer 213 consumed by the etchant can be ignored during the etching process of forming the upper transition groove 241 and the lower transition groove 242 in the same etching step.

[0094] Step S14: Etch the substrate along the bottom of the first transition groove and the bottom of the second transition groove to form a first isolation groove including the first transition groove and a second isolation groove including the second transition groove with different depths.

[0095] The cross-sectional structure diagram after step S14 is shown below. Figure 2i As shown.

[0096] Specifically, an anisotropic etching process (e.g., dry etching) can be used to etch the substrate 211 exposed through the bottom surface of the first transition groove 25A to form the first substrate groove 27A, and to etch the substrate 211 exposed through the bottom surface of the second transition groove 25B to form the second substrate groove 27B. Thus, a first isolation groove 28A composed of the interconnected first transition groove 25A and the first substrate groove 27A, and a second isolation groove 28B composed of the interconnected second transition groove 25B and the second substrate groove 27B are obtained.

[0097] The first substrate groove 27A and the second substrate groove 27B are formed by the same etching process, and the depths of the first substrate groove 27A and the second substrate groove 27B can be the same. Therefore, the difference between the total depth of the first isolation groove 28A in the longitudinal direction Z perpendicular to the substrate 211 and the total depth of the second isolation groove 28B in the longitudinal direction Z perpendicular to the substrate 211 is the difference between the depth of the first transition groove 25A in the longitudinal direction Z perpendicular to the substrate 211 and the depth of the second transition groove 25B in the longitudinal direction Z perpendicular to the substrate 211 (that is, the depth D1 of the lower transition groove 242 included in the first transition groove 25A).

[0098] Furthermore, in specific implementation, during the etching process to form the first substrate groove 27A and the second substrate groove 27B, the etching depth can be controlled to ensure that the first isolation groove 28A and the second isolation groove 28B formed do not penetrate the substrate 211.

[0099] It is understandable that during the etching process to form the first isolation groove 28A and the second isolation groove 28B, the mask layer 23 with the second opening 23A can react with the etchant and be consumed at the same time. Furthermore, the thickness of the patterned hard mask layer 23 should be large enough to ensure that it still has a certain thickness when the etching is completed.

[0100] In some embodiments, after etching to form the first isolation groove 28A and the second isolation groove 28B, that is, after step S14, the process may further include removing the remaining mask layer 23 with the second opening 23A on the second insulating layer 213.

[0101] Step S15: A first shallow trench isolation structure is formed in the first isolation groove, and a second shallow trench isolation structure is formed in the second isolation groove.

[0102] The cross-sectional structure diagram after step S15 is shown below. Figure 2j As shown.

[0103] Specifically, an isolation material (such as silicon oxide or other insulating material) can be deposited on the substrate 211 in the first isolation groove 28A and the second isolation groove 28B. Then, the isolation material located outside the first isolation groove 28A and the second isolation groove 28B can be removed by chemical mechanical polishing to obtain the first shallow trench isolation structure 29A located in the first isolation groove 28A and the second shallow trench isolation structure 29B located in the second isolation groove 28B.

[0104] In this configuration, the ends of the first shallow trench isolation structure 29A and the second shallow trench isolation structure 29B near the second insulating layer 213 are aligned longitudinally in the Z direction. Furthermore, the extension depth D2 of the end of the first shallow trench isolation structure 29A near the substrate 211 is greater than the extension depth D3 of the end of the second shallow trench isolation structure 29B near the substrate 211. That is, the length of the first shallow trench isolation structure 29A in the Z direction is greater than the length of the second shallow trench isolation structure 29B in the Z direction.

[0105] It should be noted that the inventors have discovered that, compared to the method of using two mask processes to fabricate two shallow trench isolation structures with different extension depths, this embodiment utilizes the characteristic that the film layer structure on different isolation regions in semiconductor devices is different. By using one mask process and multiple selective etching processes, two shallow trench isolation structures with different extension depths can be fabricated. This reduces the number of masks used in the manufacturing process of shallow trench isolation structures with different extension depths, which is beneficial for optimizing the process, reducing production costs, and thus improving product competitiveness.

[0106] In one specific embodiment, such as Figure 2c As shown, the substrate 211 may include a first well region 211C, which may include a first source region 211C-1, a first channel region 211C-2, and a first drain region 211C-3 connected in sequence. Furthermore, as... Figure 2k As shown, the substrate 21 may further include a third insulating layer 214, which covers the first channel region 211C-2 of the first well region 211C, and the second insulating layer 213 may cover the third insulating layer 214.

[0107] Specifically, the third insulating layer 214 and the first insulating layer 212 can be formed through the same process steps. Furthermore, the third insulating layer 214 can be used to provide the gate insulating layer for the transistor subsequently formed based on the first well region 211C. That is, the first insulating layer 212 can be formed in the existing process steps for forming the gate insulating layer, thereby saving process steps.

[0108] In some specific embodiments, after step S15 described above, the following may also be included:

[0109] S16: Remove the second insulation layer.

[0110] The cross-sectional structure diagram after step S16 is shown below. Figure 2l As shown.

[0111] Specifically, a wet etching process can be used to remove the second insulating layer 213 to expose the first insulating layer 212 and the substrate 211.

[0112] In some specific embodiments, such as Figure 2c As shown, the second well region 211D may further include a second source region 211D-1, a second channel region 211D-2, and a second drain region 211D-3 connected in sequence, and after step S16, it may further include:

[0113] Step S17: Form a fourth insulating layer 30 on the second channel region 211D-2 (e.g. Figure 2m As shown, the thickness T4 of the fourth insulating layer 30 is less than the thickness T5 of the third insulating layer 214. The third insulating layer 214 can be used to provide the gate insulating layer for the transistor subsequently formed based on the second well region 211D.

[0114] In this embodiment, the semiconductor device may contain a plurality of transistors, and the plurality of transistors may be classified into at least one transistor type (e.g., high voltage transistor type, low voltage transistor type, and ultra-low voltage transistor type) according to their operating voltage (i.e., gate turn-on voltage). The gate turn-on voltage of the high voltage transistor type is higher than that of the low voltage transistor type, and the gate turn-on voltage of the low voltage transistor type is higher than that of the ultra-low voltage transistor type.

[0115] Specifically, the first well region 211C can be used to form a transistor of one type (e.g., a high-voltage transistor), and the second well region 211D can be used to form a transistor of another type (e.g., a low-voltage transistor).

[0116] It is understandable that for transistors with higher operating voltages (i.e., gate turn-on voltages), a thicker gate insulating layer is more beneficial for improving the transistor's electrical characteristics, such as saturation current and leakage current, thereby enhancing the transistor's performance. Furthermore, in the above embodiments, for transistors with high operating voltages, a greater depth of the shallow trench isolation structure in the substrate used to isolate the used well region from other well regions is more beneficial for improving the transistor's performance.

[0117] In some embodiments, after step S17 described above, the following may also be included:

[0118] Step S18: Form a first gate layer on the third insulating layer and form a second gate layer on the fourth insulating layer.

[0119] The cross-sectional structure diagram after step S18 is shown below. Figure 2n As shown.

[0120] Specifically, the first gate layer 31A can be used to provide the gate for a transistor subsequently formed based on the first well region 211C. The second gate layer 31B can be used to provide the gate for a transistor subsequently formed based on the second well region 211D. The materials of the first gate layer 31A and the second gate layer 31B may include polysilicon.

[0121] The semiconductor device fabrication method in this embodiment involves forming a substrate, which includes a base, a first insulating layer, and a second insulating layer. The base includes a first isolation region and a second isolation region. The first insulating layer covers the first isolation region, and the second insulating layer has a flat surface and covers both the first insulating layer and the second isolation region. Then, the second insulating layer is etched to form a first shallow trench and a second shallow trench. The first shallow trench is located on the first isolation region and exposes a portion of the surface of the first insulating layer. The second shallow trench is located on the second isolation region. Next, along the bottom of the first shallow trench, the first insulating layer and the substrate are selectively etched relative to the second insulating layer to form a first transition trench including the first shallow trench. Then, along the bottom of the second shallow trench, the second insulating layer is selectively etched relative to the substrate to form a second... The substrate is etched along the bottom of the first and second transition grooves to form a first isolation groove and a second isolation groove with different depths, including the first transition groove and the second transition groove. Then, a first shallow trench isolation structure is formed in the first isolation groove and a second shallow trench isolation structure is formed in the second isolation groove. This avoids the problems of overly complex process flow and high production cost caused by separately fabricating semiconductor devices with different physical structures (e.g., shallow trench isolation structures of different depths) in the prior art. It also reduces the number of masks used in the manufacturing process of shallow trench isolation structures of different depths, which is beneficial for optimizing the process, reducing production costs, and improving product competitiveness.

[0122] Semiconductor devices manufactured according to the above-described method embodiments of the present invention, such as... Figure 2lAs shown, the semiconductor device includes a substrate 211, a first insulating layer 212, a first shallow trench isolation structure 29A, and a second shallow trench isolation structure 29B. The substrate 211 includes a first isolation region 211A and a second isolation region 211B. The first insulating layer 212 covers the first isolation region 211A. The first shallow trench isolation structure 29A penetrates the first insulating layer 212 in the first isolation region 211A, with one end extending into the substrate 211 and the other end extending above the first insulating layer 212. The second shallow trench isolation structure 29B is located on the second isolation region 211B, with one end extending into the substrate 211 and the other end extending above the first insulating layer 212. Furthermore, the depth of the first shallow trench isolation structure 29A within the substrate 211 is greater than the depth of the second shallow trench isolation structure 29B within the substrate 211.

[0123] In one specific embodiment, such as Figure 2k As shown, the semiconductor device may further include a second insulating layer 213 with a flat surface covering the first insulating layer 212 and the second isolation region 211B. Furthermore, the end of the second shallow trench isolation structure 29B away from the substrate 211 penetrates the second insulating layer 213 and is located within the second insulating layer 213. The end of the first shallow trench isolation structure 29A away from the substrate 211 penetrates the second insulating layer 213 and is located within the second insulating layer 213.

[0124] In one embodiment, such as Figure 2c As shown, the substrate 211 may further include a first well region 211C and a second well region 211D. The first isolation region 211A is located around the first well region 211C, and the second isolation region 211B is located around the second well region 211D.

[0125] Specifically, the first well region 211C may include a first source region 211C-1, a first channel region 211C-2, and a first drain region 211C-3 connected in sequence. Furthermore, as... Figure 2l As shown, the semiconductor device may further include a third insulating layer 214. The third insulating layer 214 covers the first channel region 211C-2, the second insulating layer 213 covers the third insulating layer 214, and the third insulating layer 214 and the first insulating layer 212 can be formed by the same process steps.

[0126] In some specific embodiments, such as Figure 2c As shown, the second well region 211D may include a second source region 211D-1, a second channel region 211D-2, and a second drain region 211D-3 connected in sequence. Furthermore, as... Figure 2mAs shown, the semiconductor device may further include a fourth insulating layer 30. The fourth insulating layer 30 covers the second channel region 211D-2, and the thickness T4 of the fourth insulating layer 30 is less than the thickness T5 of the third insulating layer 214.

[0127] In one specific embodiment, such as Figure 2n As shown, the semiconductor device may further include a first gate layer 31A located on the third insulating layer 214 and a second gate layer 31B located on the fourth insulating layer 30.

[0128] It should be noted that the various structures of the semiconductor devices in this embodiment can be referred to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0129] The semiconductor device provided in this embodiment can avoid the problems of overly complex process flow and high production cost caused by fabricating semiconductor devices with different physical structures (e.g., shallow trench isolation structures of different depths) separately in the prior art. It can also reduce the number of photomasks used in the manufacturing process of shallow trench isolation structures of different depths, which is conducive to optimizing the process, reducing production costs, and improving product competitiveness.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is formed, the substrate including a substrate, a first insulating layer and a second insulating layer, the substrate including a first isolation region and a second isolation region, the first insulating layer covering the first isolation region, and the second insulating layer having a flat surface and covering the first insulating layer and the second isolation region; The second insulating layer is etched to form a first shallow groove and a second shallow groove. The first shallow groove is located on the first isolation area and exposes a portion of the surface of the first insulating layer. The second shallow groove is located on the second isolation area. Along the bottom of the first shallow groove, the first insulating layer and the substrate are selectively etched relative to the second insulating layer to form a first transition groove including the first shallow groove, and along the bottom of the second shallow groove, the second insulating layer is etched to form a second transition groove including the second shallow groove. The first transition groove and the second transition groove expose the substrate, and the depth of the first transition groove is greater than the depth of the second transition groove. The substrate is etched along the bottom of the first transition groove and the bottom of the second transition groove to form a first isolation groove including the first transition groove and a second isolation groove including the second transition groove with different depths; A first shallow trench isolation structure is formed in the first isolation groove, and a second shallow trench isolation structure is formed in the second isolation groove.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of the substrate specifically includes: Provide substrate; A transition insulating layer is formed covering the first and second isolation regions of the substrate; A first opening is formed on the transition insulating layer, the first opening exposing at least a portion of the surface of the substrate in the first isolation region; A first insulating layer is formed in the first opening; A covering insulating layer is formed on the transition insulating layer and the first insulating layer to obtain a second insulating layer comprising the transition insulating layer and the covering insulating layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process involves selectively etching the first insulating layer and the substrate along the bottom of the first shallow groove, relative to the second insulating layer, to form a first transition groove including the first shallow groove, and etching the second insulating layer along the bottom of the second shallow groove to form a second transition groove including the second shallow groove. Specifically, this includes: Along the bottom of the first shallow groove, the first insulating layer is selectively etched relative to the second insulating layer to form an upper transition groove, the upper transition groove exposing the substrate; Along the bottom of the upper transition groove, the substrate is selectively etched relative to the second insulating layer to form a lower transition groove, thereby obtaining a first transition groove including the first shallow groove, the upper transition groove, and the lower transition groove. When selectively etching the substrate relative to the second insulating layer, the second insulating layer exposed at the bottom surface of the second shallow groove is simultaneously etched to form a second transition groove including the second shallow groove.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process involves selectively etching the first insulating layer and the substrate along the bottom of the first shallow groove, relative to the second insulating layer, to form a first transition groove including the first shallow groove, and etching the second insulating layer along the bottom of the second shallow groove to form a second transition groove including the second shallow groove. Specifically, this includes: Along the bottom of the first shallow groove, the first insulating layer is selectively etched relative to the second insulating layer to form an upper transition groove, the upper transition groove exposing the substrate; Along the bottom of the upper transition groove, the substrate is selectively etched relative to the second insulating layer to form a lower transition groove, thereby obtaining a first transition groove including the first shallow groove, the upper transition groove, and the lower transition groove; Along the bottom of the second shallow groove, the second insulating layer is selectively etched relative to the substrate to form a second transition groove including the second shallow groove.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching of the second insulating layer to form a first shallow groove and a second shallow groove specifically includes: A mask layer is formed on the second insulating layer; The mask layer is etched to form a second opening, thereby obtaining a mask layer having the second opening; The second insulating layer is etched through a mask layer having the second opening to form a first shallow groove and a second shallow groove.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate further includes a first well region and a second well region, wherein the first isolation region is located around the first well region and the second isolation region is located around the second well region.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The first well region includes a first source region, a first channel region, and a first drain region connected in sequence. The substrate also includes a third insulating layer, which covers the first channel region. A second insulating layer covers the third insulating layer, and the third insulating layer and the first insulating layer are formed through the same process steps.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, After forming a first shallow trench isolation structure in the first isolation groove and a second shallow trench isolation structure in the second isolation groove, the method further includes: Remove the second insulating layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The second well region includes a second source region, a second channel region, and a second drain region connected in sequence, and after the second insulating layer is removed, it further includes: A fourth insulating layer is formed on the second channel region, the thickness of the fourth insulating layer being less than the thickness of the third insulating layer.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, After forming the fourth insulating layer on the second channel region, the process further includes: A first gate layer is formed on the third insulating layer, and a second gate layer is formed on the fourth insulating layer.

11. A semiconductor device, characterized in that, include: The substrate includes a first isolation region and a second isolation region, a first well region and a second well region; the first isolation region is located around the first well region, and the second isolation region is located around the second well region. The first insulating layer covers only the first isolation area; A first shallow trench isolation structure and a second shallow trench isolation structure, wherein the first shallow trench isolation structure penetrates the first insulating layer in the first isolation region, with one end extending into the substrate and the other end extending above the first insulating layer; the second shallow trench isolation structure is located in the second isolation region, with one end extending into the substrate and the other end extending above the first insulating layer; wherein the extension depth of the first shallow trench isolation structure in the substrate is greater than the extension depth of the second shallow trench isolation structure in the substrate. A second insulating layer with a flat surface covering the first insulating layer and the second isolation region, wherein one end of the second shallow trench isolation structure away from the substrate penetrates the second insulating layer and is located in the second insulating layer, and one end of the first shallow trench isolation structure away from the substrate penetrates the second insulating layer and is located in the second insulating layer; The first well region includes a first source region, a first channel region, and a first drain region connected in sequence, and the semiconductor device further includes: A third insulating layer covers the first channel region, and a second insulating layer covers the third insulating layer.

12. The semiconductor device according to claim 11, characterized in that, The third insulating layer is formed using the same process steps as the first insulating layer.

13. The semiconductor device according to claim 11, characterized in that, The second well region includes a second source region, a second channel region, and a second drain region connected in sequence. The semiconductor device further includes: A fourth insulating layer, the fourth insulating layer covering the second channel region, and the thickness of the fourth insulating layer being less than the thickness of the third insulating layer.

14. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: The first gate layer is located on the third insulating layer.

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