System architecture, structure and manufacturing method of hybrid random access memory

Abstract

The present invention discloses a system architecture, structure and manufacturing method of a hybrid random access memory, wherein the hybrid random access memory for a single-chip system includes: a semiconductor substrate having a magnetoresistive random access memory region and a variable resistance random access memory region, a first dielectric layer located on the semiconductor substrate, a plurality of variable resistance random access memory cells located in the first dielectric layer of the variable resistance random access memory region, a second dielectric layer located on the first dielectric layer, and a plurality of magnetoresistive random access memory cells located in the second dielectric layer of the magnetoresistive random access memory region.

Description

Technical Field

[0001] The present invention relates to a hybrid random access memory system architecture, and more particularly, to a hybrid random access memory system architecture having both a magnetoresistive random access memory and a variable resistance random access memory on a single-chip system (SOC). Background Art

[0002] After years of research and development, several emerging memory types are now emerging in the electronics industry, including 3D XPoint, magnetoresistive random access memory (MRAM), phase-change memory (PCM), resistive random access memory (ReRAM), and ferroelectric random access memory (FeRAM). Some of these emerging memories are even expected to replace dynamic random access memory (DRAM), NOR flash memory, NAND flash memory, and static random access memory (SRAM) commonly used in today's electronic products. They are beginning to be used in standalone chips and embedded in application-specific integrated circuits (ASICs), microcontrollers (MCUs), and even processors, making them more competitive than existing memory technologies.

[0003] For today's microcontroller architectures and artificial intelligence applications, the memory used must meet the requirements of both high performance and non-volatility. Therefore, emerging memories with these characteristics are promising candidates. However, current use of emerging memories is limited to system-level applications, and it is not yet feasible to integrate multiple hybrid emerging memories into a single system-on-chip (SOC). Therefore, researchers in related fields still need to further develop and research current hybrid random access memory architectures. Summary of the Invention

[0004] Given that current memory system architectures and related manufacturing processes are unable to integrate hybrid memory into a single-chip system (SOC), the present invention proposes a hybrid random access memory system architecture, structure, and manufacturing method that integrates magnetoresistive random access memory (MRRAM) and variable resistance random access memory (VRAM) into a single-chip system. This hybrid random access memory system architecture is suitable for high-performance microcontrollers and artificial intelligence applications, and can simultaneously meet the requirements of high-speed and low-speed access, as well as digital and analog circuits.

[0005] One aspect of the present invention is to provide a system architecture for a hybrid random access memory on a single-chip system, comprising an arithmetic unit, a hybrid register coupled to the arithmetic unit, a plurality of magnetoresistive random access memory (MRAM) blocks, each of which includes a plurality of magnetoresistive random access memory (MRAM) cells coupled to a magnetoresistive random access memory (MRAM) controller, which in turn is coupled to the hybrid register; and a plurality of variable resistance random access memory (VRAM) blocks, each of which includes a plurality of variable resistance random access memory (VRAM) cells coupled to a VRAM controller, which in turn is coupled to the hybrid register. The VRAM cells and the magnetoresistive random access memory (MRAM) cells are located on the same semiconductor substrate.

[0006] Another aspect of the present invention is to provide a hybrid random access memory for a single-chip system, comprising a semiconductor substrate having a magnetoresistive random access memory region and a variable resistance random access memory region, a first dielectric layer located on the semiconductor substrate, a plurality of variable resistance random access memory cells located in the first dielectric layer of the variable resistance random access memory region, a second dielectric layer located above the first dielectric layer, and a plurality of magnetoresistive random access memory cells located in the second dielectric layer of the magnetoresistive random access memory region.

[0007] Another aspect of the present invention is to provide a method for fabricating a hybrid random access memory for a single-chip system, the method comprising: providing a semiconductor substrate having a magnetoresistive random access memory region and a variable resistance random access memory region; forming a plurality of variable resistance random access memory cells on the variable resistance random access memory region of the semiconductor substrate; forming a first dielectric layer on the semiconductor substrate such that the variable resistance random access memory cells are located in the first dielectric layer; forming a plurality of magnetoresistive random access memory cells above the magnetoresistive random access memory region of the first dielectric layer; and forming a second dielectric layer on the first dielectric layer such that the magnetoresistive random access memory cells are located in the second dielectric layer.

[0008] These and other objects of the present invention will become more readily apparent after reading the following detailed description of the preferred embodiment which is illustrated in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This specification includes accompanying drawings, which constitute a part of this specification and provide a further understanding of embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate the principles thereof. In these drawings:

[0010] Figure 1 A system architecture diagram of a hybrid random access memory according to an embodiment of the present invention;

[0011] Figure 2 A basic system architecture diagram of a hybrid random access memory according to an embodiment of the present invention; and

[0012] Figures 3 to 14 FIG. 4 is a cross-sectional view of the fabrication process of two different memories, MRAM and ReRAM, on a single wafer according to an embodiment of the present invention.

[0013] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0014] Description of main component symbols

[0015] 100 System Architecture

[0016] 102 Data Backup Unit

[0017] 104 MRAM disk array controller

[0018] 106 Data Backup Unit

[0019] 108 ReRAM disk array controller

[0020] 110 Arithmetic Unit

[0021] 111 High-Speed Data Controller

[0022] 112 Medium-Speed Data Controller

[0023] 113 Low-speed data controller

[0024] 114 chips

[0025] 115 Fibre Channel

[0026] 116 processors

[0027] 117 Cache

[0028] 120 mixed registers

[0029] 121 High-speed data register

[0030] 122 medium-speed data register

[0031] 123 Low-speed data register

[0032] 130 MRAM blocks

[0033] 131 MRAM cells

[0034] 132 Hot spare disk

[0035] 133 Disk array failure component

[0036] 134 Data Backup Unit

[0037] 135 MRAM controller

[0038] 140 ReRAM blocks

[0039] 141 ReRAM cells

[0040] 142 Hot spare disk

[0041] 143 Disk array failure component

[0042] 144 ReRAM controller

[0043] 200 interlayer dielectric layer

[0044] 201 First Area

[0045] 202 Second Area

[0046] 204 dielectric cover

[0047] 205 Opening

[0048] 206 Tantalum Oxide Layer

[0049] 208 lower electrode

[0050] 209 Tantalum Pentoxide Layer

[0051] 210 Iridium Layer

[0052] 212 Ruthenium layer

[0053] 214 Titanium Nitride Layer

[0054] 216 Upper electrode

[0055] 218 Covering

[0056] 220 Next door

[0057] 224 Intermetallic Dielectric Layer

[0058] 226 dielectric cover

[0059] 228 Intermetallic Dielectric Layer

[0060] 230 Dielectric Covering

[0061] 232 dielectric layer

[0062] 234 guide hole parts

[0063] 236 lower electrode layer

[0064] 238 Magnetic Tunnel Junction Stack

[0065] 240 upper electrode layer

[0066] 242 upper electrode

[0067] 244 Magnetic Tunnel Junction Stack

[0068] 246 lower electrode

[0069] 248 Intermetallic Dielectric Layer

[0070] 250 Dielectric Covering

[0071] 252 Overlay

[0072] CT contact structure

[0073] MRAM Magnetoresistive Random Access Memory Cell

[0074] M1 first metal layer

[0075] M2 second metal layer

[0076] M3 third metal layer

[0077] ReRAM Resistive Random Access Memory Cell

[0078] V1, V2 guide hole parts DETAILED DESCRIPTION

[0079] The following will now describe in detail exemplary embodiments of the present invention, which will illustrate the described features with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. The reader will understand that the description herein is provided by way of example only and is not intended to limit the present invention. The various embodiments of the present invention and the various features of the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the present invention will be understood by those skilled in the art without departing from the spirit and scope of the present invention and are intended to be included within the scope of the present invention.

[0080] Readers should be able to easily understand that the meanings of “on,” “above,” and “over” in this case should be interpreted broadly, so that “on” not only means “directly on” something, but also includes the meaning of being “on” something with intervening features or layers, and “on” or “over” not only means “on” or “above” something, but also includes the meaning of being “on” or “above” something with no intervening features or layers (i.e., directly on something).

[0081] In addition, spatially relative terms such as "under," "beneath," "lower," "over," "upper," and the like may be used herein for descriptive convenience to describe the relationship of one element or feature to another or more elements or features, as shown in the accompanying drawings.

[0082] A reader can generally understand a term, at least in part, from usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," "the," or "said" can also be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0083] Readers can further understand that when words such as "include" and / or "contain" are used in this specification, they specify the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0084] As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0085] As used herein, the term "layer" refers to a portion of a material that includes an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer that may include one or more layers, and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0086] Furthermore, as used herein, RAID refers to a fault-tolerant disk array. Generally, RAID technology is a method of storing the same data in different locations on multiple hard drives or storage devices. By storing data on different hard drives or storage devices, input / output operations can be overlapped in a balanced manner, improving system performance. Because multiple hard drives or storage devices increase the mean time between failures (MTBF), storing data in a fault-tolerant manner can also improve fault tolerance.

[0087] The present invention proposes a hybrid random access memory system architecture comprising two distinct types of memory: magnetoresistive random access memory (MRAM) and resistive random access memory (ReRAM). More specifically, the MRAM and ReRAM are fabricated using the same process on the same wafer or substrate, offering the advantages of integrated manufacturing processes and suitability for single-chip system designs.

[0088] Now please refer to Figure 1 , which schematically illustrates a system architecture diagram of a hybrid random access memory according to an embodiment of the present invention. The reader should be aware that this architecture implements data storage including two different memories, MRAM and ReRAM. Generally speaking, magnetoresistive random access memory (MRAM) is a non-volatile memory in which data is not stored in the form of charge or current, but is stored through magnetic storage elements. Resistive random access memory (ReRAM) is also a non-volatile memory. Its operating principle is to use the resistance value of transition metal oxide to change with the applied bias voltage, so as to distinguish the value stored inside the element.

[0089] As shown, the system architecture 100 can be implemented in a microcontroller (MCU) or a system-on-a-chip (SOC), and includes a hybrid register 120 coupled to an arithmetic unit 110. A data backup unit 102, an MRAM disk array controller / decoder 104, and a ReRAM disk array controller / decoder 108 are coupled to the hybrid register 120. A data backup unit 106 and an MRAM block 130 are coupled to the MRAM disk array controller 104. The MRAM disk array controller 104 and the ReRAM disk array controller 108 can manage data access to the MRAM block 130 and the ReRAM block 140 in the physical and logical arrays, respectively.

[0090] As shown, each MRAM block 130 includes multiple MRAM cells 131, a hot spare drive 132 coupled to the MRAM cells 131, an MRAM controller 135 coupled to the MRAM cells 131, a RAID failover component 133 coupled to the MRAM controller 135, and a data backup unit 134 coupled to the MRAM controller 135. Each MRAM cell 131 is the smallest unit of memory storage, and the MRAM controller 135 controls the connections and operations of the various functional blocks within the MRAM block 130.

[0091] Furthermore, a ReRAM block 140 is coupled to the ReRAM disk array controller 108. ReRAM block 140 includes multiple ReRAM cells 141, a hot spare disk 142 coupled to the ReRAM cells 141, a ReRAM controller 144 coupled to the ReRAM cells 141, and a disk array failure unit 143 coupled to the ReRAM controller 144 and the hot spare disk 142. Each ReRAM cell 141 is the smallest unit of memory storage, and the ReRAM controller 144 controls the connection and operation of each functional block in the ReRAM block 140.

[0092] In an embodiment of the present invention, the hybrid register 120 includes a high-speed data register 121, a medium-speed data register 122, and a low-speed data register 123. The data backup unit 102 is coupled to the hybrid register 120. The hybrid register 120 can be used to temporarily store instructions, data, and addresses, accelerating the execution of computer programs by quickly accessing data. In particular, to accommodate various memory architectures, three different registers (high-speed, medium-speed, and low-speed) 121, 122, and 123 are used to temporarily store data from memories with different read / write speeds. For example, these three speeds correspond to the cache 117, MRAM block 130, and ReRAM block 140 on the computing unit 110, respectively.

[0093] The arithmetic unit 110 generally includes a chip 114, such as a system and peripheral integrated circuit chip. A high-speed data controller 111, a medium-speed data controller 112, and a low-speed data controller 113 are coupled to the chip 114, and can respectively receive data of different speeds from the hybrid register 120 or transmit corresponding data thereto. A fiber channel 115 is coupled to the chip 114, which can provide high-speed network interconnection. A processor 116, which can be an instruction and data processor, is coupled to the chip 114, and a cache 117, such as a static random access memory (SRAM), is coupled to the processor 116.

[0094] Please refer to Figure 2 . In practical applications, the MRAM block 130 in this embodiment can be used to replace the traditional DRAM as the data temporary storage area of the system, which has the advantages of higher read / write speed, non-volatility, and large capacity density. The ReRAM block 140 can be used to replace the traditional flash memory (Flash) or solid-state drive (SSD) with slower read / write speed as a data storage area. The MRAM block 130 and the ReRAM block 140 can be coupled to each other and are jointly coupled to the cache 117 at the operation unit end, such as SRAM, through the aforementioned hybrid register 120. The operation unit 110 can perform operations on the data stored or temporarily stored in the three different memories.

[0095] After describing the system architecture of the hybrid random access memory of the present invention, the following will refer to Figures 3 to 14 This article will explain the manufacturing process of two different memories, MRAM and ReRAM, on the same substrate or wafer. Please note that since the locations and features of the general semiconductor front-end manufacturing process (FEOL) are not the focus of this invention, in order to avoid blurring the focus, Figures 3 to 14 In the cross-sectional views and embodiments, illustrations and descriptions of the front-end manufacturing process including the gate, source / drain, active (active) region and / or doped region will be omitted. The entire memory manufacturing process will be described starting from the interlayer dielectric layer and contact structure of the middle-end manufacturing process (MEOL).

[0096] Please refer to Figure 3 First, a substrate, such as a silicon substrate, is provided, on which an interlayer dielectric layer (ILD) 200 is formed. In an embodiment of the present invention, the substrate is divided into a first region 201 and a second region 202. The first region 201 is intended for forming an MRAM memory device, and the second region 202 is intended for forming a ReRAM memory device. The substrate may also be divided into other regions of different nature, such as a logic region and a peripheral region, but these are not shown in the figure.

[0097] In an embodiment of the present invention, the interlayer dielectric layer 200 may be a single-layer structure or a multi-layer structure. Its material may be tetraethoxysilane (TEOS), which can be formed by chemical vapor deposition (CVD). A contact structure CT is formed in the interlayer dielectric layer 200, which is electrically connected to the gate, source / drain, and active region formed in the previous stage manufacturing process below (not shown). The material of the contact structure CT may be copper, aluminum, or tungsten, and a barrier layer (not shown) may be formed at the interface between the contact structure CT and the interlayer dielectric layer 200. A thin dielectric cap layer 204 is formed on the entire surface of the interlayer dielectric layer 200, covering the contact structure CT. The dielectric cap layer 204 serves as a diffusion barrier and an etch stop, and its material may be silicon carbonitride (SiCN). In this embodiment, an opening 205 is formed in the dielectric cap layer 204 above the second region 202 by a photolithography process, exposing a portion of the contact structure CT below. The dielectric cover layer 204 above the first region 202 will not be opened in this step.

[0098] Please refer to Figure 4 After the opening 205 is formed, the bottom electrode 208 of the ReRAM cell is formed in the opening 205 and electrically connected to the contact structure CT below. The bottom electrode 208 can be made of tantalum nitride (TaN). A conformal bottom electrode material layer is formed on the surface of the dielectric cap layer 204 through a CVD process. A chemical mechanical planarization (CMP) process is then performed using the dielectric cap layer 204 as a stop layer to remove the portion located on the dielectric cap layer 204. This allows the bottom electrode 208 to be flush with the top surface of the dielectric cap layer 204.

[0099] Please refer to Figure 5 After the bottom electrode 208 is formed, tantalum oxide (TiO X ) layer 206, a tantalum pentoxide (Ta2O5) layer 209, an iridium (Ir) layer 210, a ruthenium (Ru) layer 212, and a titanium nitride (TiN) layer 214. The tantalum oxide layer 206, the tantalum pentoxide layer 209, and the iridium layer 210 collectively serve as the variable resistor portion of the ReRAM cell and can be formed using a CVD process or a physical vapor deposition (PVD) process. The ruthenium layer 212 and the titanium nitride layer 214 collectively serve as the top electrode portion of the ReRAM cell and can be formed using a PVD process. The ruthenium layer 212 also serves as an etch stop layer in the fabrication process of this embodiment.

[0100] Please refer to Figure 6After forming the material layer structure of tantalum oxide layer 206, tantalum pentoxide layer 209, iridium layer 210, ruthenium layer 212, and titanium nitride layer 214, a photolithography process is then performed using the ruthenium layer 212 as an etch stop layer to pattern the titanium nitride layer 214 to form the pattern of the top electrode 216 of the ReRAM cell. In this step, except for the top electrode 216 formed on the second region 202, the remaining titanium nitride layer 214 on the first region 201 and the second region 202 is removed.

[0101] Please refer to Figure 7 After the top electrode 216 is formed, a reactive ion etching process is performed using the top electrode 216 as a hard mask and the dielectric cap layer 204 as an etch stop layer to remove the tantalum oxide layer 206, tantalum pentoxide layer 209, iridium layer 210, and ruthenium layer 212 from other layers except those below the top electrode 216. This forms a ReRAM cell having a bottom electrode 208, a variable resistance layer (including the tantalum oxide layer 206 and the tantalum pentoxide layer 209), and a top electrode 216. A conformal, protective cap layer 218 is then formed over the entire substrate surface. The cap layer 218 may be made of silicon nitride (SiN), which may be formed by a CVD process.

[0102] Please refer to Figure 8 After the capping layer 218 is formed, an anisotropic etching process is performed to remove the capping layer 218 on the surface of the ReRAM cell and the dielectric capping layer 204, leaving only the capping layer 218 on the sidewalls of the material layer of the ReRAM cell, thereby forming the spacer 220 structure of the ReRAM cell.

[0103] Please refer to Figure 9 After the spacers 220 are formed, an intermetallic dielectric layer 224 is formed around the ReRAM cell. The intermetallic dielectric layer 224 can be made of an ultra-low dielectric material (ULK), such as silicon oxycarbide (SiOC). This can be formed by depositing a layer of ultra-low dielectric material on the entire substrate surface through a CVD process, and then performing a CMP process using the top electrode 216 of the ReRAM cell as a stop layer to remove the portion above the top electrode 216. In this way, the top surface of the intermetallic dielectric layer 224 will be flush with the top surface of the top electrode 216 of the ReRAM cell.

[0104] Re-reference Figure 9. After the intermetal dielectric layer 224 is formed, a metal interconnect structure such as a first metal layer M1 can be formed in the intermetal dielectric layer 224, which is electrically connected to the contact structure CT below. The material of the first metal layer M1 can be a metal material such as copper (Cu), cobalt (Co) or ruthenium (Ru), which can be formed using a single inlay process. It should be noted that in an embodiment of the present invention, unlike the ReRAM unit being formed only in the second area 202 of the substrate, the first metal layer M1 can be formed on both the first area 201 and the second area 202 of the substrate. Finally, another thin dielectric cap layer 226 is formed on the entire surface of the substrate to cover the ReRAM unit and the first metal layer M1. The material of the dielectric cap layer 226 also uses SiCN with diffusion barrier and etching stop.

[0105] Please refer to Figure 10 . After the dielectric cap layer 226 is formed, another intermetallic dielectric layer 228 is formed on the dielectric cap layer 226, and an interconnect structure is formed in the intermetallic dielectric layer 228, including a via V1 and a second metal layer M2. Among them, the via V1 will electrically connect to the first metal layer M1 below or the upper electrode 216 of the ReRAM unit. The material of the intermetallic dielectric layer 228 can be an ultra-low dielectric material (ULK), which can be formed by a CVD process plus a CMP process. The via V1 and the second metal layer M2 can be formed using a dual-damascene process, which includes etching the intermetallic dielectric layer 228 with the dielectric cap layer 226 as a stop layer to form a hole and groove pattern of the via V1 and the second metal layer M2, and then filling the hole with a metal material such as copper or cobalt. Finally, another dielectric cap layer 230 made of SiCN is formed on the entire substrate surface to cover the second metal layer M2 and the intermetallic dielectric layer 228.

[0106] After the ReRAM cell (including the interconnect structures such as the via V1 and the second metal layer M2 electrically connected thereto) is fabricated, the MRAM cell can then be fabricated in the layer above the ReRAM cell. In the embodiment of the present invention, the fabrication of the MRAM cell is described using the next layer below the intermetallic dielectric layer 228 (which includes the via V2 and the third metal layer M3) as an example. However, it should be noted that the MRAM cell in the embodiment of the present invention can also be fabricated in other different intermetallic dielectric layers above the substrate, and the MRAM cell will only be formed in the first region 201 outside the second region 202, and will not overlap with the ReRAM cell in the second region 202.

[0107] Re-reference Figure 10First, a dielectric layer 232 is formed above the dielectric cap layer 230. The dielectric layer 232 may be made of TEOS, which may be formed by chemical vapor deposition (CVD). Next, vias 234 are formed in the dielectric layer 232 in the first region 201. The vias 234 may be made of, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), and the like. The vias 234 will electrically connect to the underlying interconnect structure, such as the second metal layer M2.

[0108] Please refer to Figure 11 . After the via member 234 is formed, a lower electrode layer 236, a magnetic tunneling junction stack 238, and an upper electrode layer 240 are sequentially formed on the dielectric layer 232. The lower electrode layer 236, the magnetic tunneling junction stack 238, and the upper electrode layer 240 can be formed in-situ in the same cavity using a PVD manufacturing process. In the embodiment of the present invention, the material of the lower electrode layer 236 preferably includes a conductive material, such as tantalum nitride (TaN), but is not limited thereto. According to other embodiments of the present invention, the lower electrode layer 236 may include tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), aluminum (Al) or a combination thereof. The magnetic tunneling junction stack 238 is a multi-layer structure, which may include a seed layer, a pinned layer, a reference layer, a tunneling barrier layer, a free layer, and a metal spacer.

[0109] In general terms, the fixed layer can be composed of antiferromagnetic (AFM) materials, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or limit the direction of the magnetic moment of the adjacent layer. The tunnel barrier layer can be composed of an insulating material containing an oxide, such as aluminum oxide (AlOx) or magnesium oxide (MgO), but it is not limited to this. The free layer can be composed of ferromagnetic materials, such as iron, cobalt, nickel or their alloys such as cobalt iron boron (CoFeB), but it is not limited to this. Among them, the magnetization direction of the free layer will be "freely" changed by the external magnetic field. Since the structure of the magnetic tunnel junction stack 238 is not the focus of the present invention, the figure summarizes the above-mentioned multilayer structures as the magnetic tunnel junction stack 238. The material of the upper electrode layer 240 is preferably titanium nitride (TiN)

[0110] Please refer to Figure 12 After forming the lower electrode layer 236, the magnetic tunneling junction stack 238, and the upper electrode layer 240, a photolithography process is then performed to pattern the upper electrode layer 240 to form the pattern of the upper electrode 242 of the MRAM cell. In this step, except for the upper electrode 242 formed on the first region 201, the remaining upper electrode layer 240 on the first region 201 and the second region 202 is removed.

[0111] Please refer to Figure 13 . After the upper electrode 242 is formed, a reactive ion etching process is performed using the upper electrode 242 as a hard mask to remove the magnetic tunneling junction stack 238 and the lower electrode layer 236 except for the area below the upper electrode 242, thereby forming individual MRAM cells having a lower electrode 246, a magnetic tunneling junction stack 244 and an upper electrode 242. Due to the characteristics of the ion beam etching process, the upper surface of the remaining dielectric layer 232 after etching will be slightly lower than the top surface of the guide hole 234 and present an arc or curved surface. Thereafter, a conformal, protective covering layer 252 is formed on the entire surface of the substrate. The material of the covering layer 252 may be silicon nitride, but other dielectric materials may be selected according to the requirements of the manufacturing process, such as silicon oxide, silicon oxynitride or silicon carbide nitride, which may be formed by a CVD manufacturing process.

[0112] Please refer to Figure 14 . After the cover layer 252 is formed, a photolithography process is then performed to remove the cover layer 252 and the dielectric layer 232 outside the MRAM area, leaving only the cover layer 218 on the sidewalls of the material layer of the MRAM cell, thereby forming the spacer 220 structure of the MRAM cell. After the MRAM cell is completed, an intermetallic dielectric layer 248 and interconnect structures such as the vias V2 and the third metal layer M3 located therein are formed around the MRAM cell, and a thin dielectric cover layer 250 is formed on the entire surface to cover the MRAM cell and the third metal layer M3. The materials and manufacturing processes of the above components are the same as those in the aforementioned embodiment and will not be elaborated here.

[0113] It should be noted that in other embodiments, the aforementioned MRAM cell can be formed in other layers above the substrate, not limited to the vias V2 and the third metal layer M3 shown in the figure. Furthermore, after the MRAM cell is completed, subsequent back-end-of-line (BEOL) processes are performed to fabricate other components above it, such as the upper interconnect structure, top metal layer, and contact pads. Since these fabrication processes and components are not the focus of this application, they will be omitted from the description and illustrations.

[0114] In summary, the hybrid RAM system architecture proposed in this invention integrates two different types of RAM: ReRAM and MRAM, meeting both high-speed and low-speed access requirements, as well as digital and analog circuit requirements. Furthermore, these two different RAMs, ReRAM and MRAM, are fabricated in the same process flow on the same substrate or wafer, making this system architecture suitable for today's high-performance microcontrollers, single-chip systems, and artificial intelligence applications.

[0115] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A system architecture for a hybrid random access memory on a single chip system, characterized in that: Include: Arithmetic unit; a hybrid register coupled to the arithmetic unit; a plurality of MRAM blocks, each of the MRAM blocks comprising a plurality of MRAM cells, the MRAM cells being coupled to a MRAM controller, and the MRAM controller being coupled to the hybrid register; as well as a plurality of variable resistance random access memory blocks, each of the variable resistance random access memory blocks including a plurality of variable resistance random access memory cells, the variable resistance random access memory cells being coupled to a variable resistance random access memory controller, and the variable resistance random access memory controller being coupled to the hybrid register; The plurality of variable resistance random access memory units and the plurality of magnetoresistive random access memory units are located on a same semiconductor substrate. 2 . The hybrid random access memory system architecture for a single chip system according to claim 1 , wherein the magnetoresistive random access memory blocks are coupled to the variable resistance random access memory blocks.

3. The system architecture for hybrid random access memory on a single chip system according to claim 1 , wherein each of the magnetoresistive random access memory blocks further comprises: A hot spare disk coupled to the magnetoresistive random access memory units; a data backup unit coupled to the magnetoresistive random access memory controller; and The disk array failure component is coupled to the magnetoresistive random access memory controller.

4. The hybrid random access memory system architecture for a single chip system according to claim 1 , wherein each of the variable resistance random access memory blocks further comprises: A hot spare disk coupled to the variable resistance random access memory units; and The disk array failure component is coupled to the variable resistance random access memory controller. 5 . The system architecture for hybrid random access memory on a single chip system according to claim 1 , wherein the hybrid register comprises a high-speed data register and a low-speed data register.

6. The system architecture for hybrid random access memory on a single chip system according to claim 1 , wherein the arithmetic unit comprises: chip; a high-speed data operation controller coupled to the chip; a low-speed data operation controller coupled to the chip; a processor coupled to the chip; as well as A cache is coupled to the processor.

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