Memory system and method of manufacturing the same

Abstract

An embodiment of the present application discloses a memory system and a manufacturing method thereof. The memory system includes: at least one memory device and a memory controller coupled to the memory device; wherein, the memory device and the memory controller are disposed on the same die; the memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system; the memory controller includes a second phase change memory, and the second phase change memory is configured to cache the transmitted data when the memory controller performs data transmission with a host or the memory device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a memory system and a manufacturing method thereof. Background Art

[0002] With the rapid development of data storage technology, more and more data memory systems appear in electronic devices used by people, such as: solid state drives (SSDs, Solid State Drives), etc. SSDs have been widely used in military, vehicle-mounted, industrial, medical, and aviation fields due to their fast read and write speeds, anti-vibration, low power consumption, no noise, low heat, and light weight.

[0003] However, the memory systems in related technologies still need to further improve the bandwidth. Summary of the Invention

[0004] To solve the problems in related technologies, embodiments of this application propose a memory system and a manufacturing method thereof.

[0005] Embodiments of this application provide a memory system, including: at least one memory device and a memory controller coupled to the memory device; wherein,

[0006] The memory device and the memory controller are disposed on the same die;

[0007] The memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system;

[0008] The memory controller includes a second phase change memory, and the second phase change memory is configured to cache the data being transmitted when the memory controller performs data transmission with a host or the memory device.

[0009] In the above solution, the speed at which the second phase change memory performs read operations and write operations is greater than the speed at which the first phase change memory performs read operations and write operations.

[0010] In the above solution, the phase change material used in the first phase change memory includes an alloy based on chalcogenide; the phase change material used in the second phase change memory includes a superlattice material.

[0011] In the above solution, the first phase change memory includes a first phase change memory array and a first peripheral circuit that are electrically connected to each other; the second phase change memory includes a second phase change memory array and a second peripheral circuit that are electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit that are electrically connected to both the first phase change memory and the second phase change memory;

[0012] The first peripheral circuit, the second peripheral circuit, and the third peripheral circuit are arranged in parallel on the same substrate;

[0013] The first phase change memory array is disposed on the first peripheral circuit; the capacitors are disposed on the second peripheral circuit and the third peripheral circuit, and the second phase change memory array is disposed on the capacitors.

[0014] In the above solution, the first phase change memory array has four stacked memory cell layers; the second phase change memory array has one memory cell layer.

[0015] In the above solution, the capacitor is used to provide power; the capacitor includes multiple metal layers and insulating layers located between the multiple metal layers.

[0016] In the above solution, the third peripheral circuit includes an interface and an overall control unit; wherein,

[0017] The interface is used to connect to the host;

[0018] The overall control unit is at least used to control data transmission between the first phase change memory and the second phase change memory.

[0019] In the above solution, the communication protocol between the interface and the host includes the Peripheral Component Interconnect Express (PCIe) 5.0 version of the High-Speed Serial Computer Extension Bus Standard.

[0020] In the above solution, the memory device further includes a first metal interconnect layer; the memory controller further includes a second metal interconnect layer; wherein, data transmission between the memory device and the memory controller is achieved through electrical connection of the first metal interconnect layer and the second metal interconnect layer.

[0021] An embodiment of the present application further provides a solid-state drive, including: the memory system provided by the embodiment of the present application.

[0022] An embodiment of the present application further provides a method for manufacturing a memory system, including:

[0023] Forming at least one memory device and a memory controller coupled to the memory device on the same die; wherein,

[0024] The memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system;

[0025] The memory controller includes a second phase change memory, which is configured to cache the transmitted data when the memory controller performs data transmission with a host or the memory device.

[0026] In the above solution, the first phase change memory includes a first phase change memory array and a first peripheral circuit that are electrically connected to each other; the second phase change memory includes a second phase change memory array and a second peripheral circuit that are electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit that are both electrically connected to the first phase change memory and the second phase change memory;

[0027] Forming at least one memory device and a memory controller coupled to the memory device on the same die includes:

[0028] The first peripheral circuit, the second peripheral circuit, and the third peripheral circuit are formed side by side on the same substrate;

[0029] The first phase change memory array is formed on the first peripheral circuit;

[0030] The capacitor is formed on the second peripheral circuit and the third peripheral circuit;

[0031] The second phase change memory array is formed on the capacitor.

[0032] In the above solution, the method further includes:

[0033] A first metal interconnect layer is formed in the memory device, and a second metal interconnect layer is formed in the memory controller; wherein, data transmission between the memory device and the memory controller is achieved through the electrical connection between the first metal interconnect layer and the second metal interconnect layer.

[0034] Embodiments of the present application provide a memory system and a manufacturing method thereof. The memory system includes: at least one memory device and a memory controller coupled to the memory device; wherein, the memory device and the memory controller are disposed on the same die; the memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system; the memory controller includes a second phase change memory, and the second phase change memory is configured to cache the data being transmitted when the memory controller performs data transmission with a host or the memory device. In the embodiments of the present application, on the one hand, by disposing the memory device and the memory controller on the same die, the area utilization rate of the memory system is improved, which is beneficial to the miniaturization requirement of the memory system; on the other hand, by using the first phase change memory to store data and the second phase change memory to cache data, since the phase change memory has a relatively fast speed of performing read and write operations, the bandwidth of the formed memory system is improved. Description of the Drawings

[0035] Figure 1 FIG. is a schematic structural diagram of a solid-state drive in the related art;

[0036] Figure 2 FIG. is a schematic structural diagram of a main controller of a solid-state drive in the related art;

[0037] Figure 3 FIG. is a schematic diagram of a data transmission path of a solid-state drive in the related art;

[0038] Figure 4a FIG. is a schematic structural diagram of the memory system provided by the embodiments of the present application Figure 1 ;

[0039] Figure 4b FIG. is a schematic structural diagram of the memory system provided by the embodiments of the present application Figure 2 ;

[0040] Figure 4c FIG. is a schematic structural diagram of the memory system provided by the embodiments of the present application Figure 3 ;

[0041] Figure 5 FIG. is a schematic layout diagram of the memory device and the memory controller of the memory system provided by the embodiments of the present application;

[0042] Figures 6a - 6d FIG. is an architecture diagram of the first phase change memory having four stacked memory cell layers provided by the embodiments of the present application;

[0043] Figure 7a FIG. is a partial three-dimensional schematic diagram of the memory device of the memory system provided by the embodiments of the present application;

[0044] Figure 7b A partial schematic diagram of the memory device of the memory system provided by the embodiment of the present application;

[0045] Figure 7c A partial schematic of the memory controller of the memory system provided by the embodiment of the present application Figure 1 ;

[0046] Figure 7d A partial schematic of the memory controller of the memory system provided by the embodiment of the present application Figure 2 . Detailed implementation manners

[0047] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0048] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some well-known technical features are not described in order to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0049] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0050] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that there must be a first element, component, region, layer or portion in the present application.

[0051] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0053] In order to understand the features and technical content of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of the present application.

[0054] In practical applications, there are various types of memory systems, such as SSDs, USB flash drives, etc. The embodiments of this application are applicable to all memory systems with memory devices and memory controllers. The embodiments of this application will only take SSDs as an example for illustrative purposes.

[0055] As Figure 1 shown, the SSDs in the related art mainly include SSD cache chips, main controllers, storage chips, and capacitors. In the related art, dynamic random access memory (DRAM) is mainly used as the SSD cache chip, and multiple NAND flash memories are used as the storage chips. Among them, DRAM can be used to store the mapping table of logical addresses and physical addresses; the main controller is the bridge between the host (which can be expressed in English as Host) and the NAND flash memory, responsible for scheduling and executing host commands and converting them into read / write commands for the NAND flash memory; the NAND flash memory is used as the storage medium of the SSD to store data.

[0056] Figure 2 shows a schematic structural diagram of the main controller of the SSD in the related art. As Figure 2 shown, the main controller of the SSD includes a first interface, a second interface, a third interface, a double data rate (DDR) control unit, and a peripheral circuit. Among them, the first interface is the interface for connecting the host and the SSD main controller. During data transmission, the first interface existing between the host and the SSD main controller enables the host and the SSD main controller to interact data and instructions. That is to say, the first interface between the host and the SSD main controller provides a data transmission channel for the host and the SSD main controller. The interface protocols of the first interface in the related art include PCIe, SAS, and SATA. The second interface is the interface existing between the DRAM and the SSD main controller, used to transmit control information and data to the DRAM or obtain data from the DRAM. The third interface is the interface existing between the main controller and the NAND flash memory, used to interact data and instructions between the SSD main controller and the NAND flash memory. The double data rate control unit is used for timing control and scheduling. The peripheral circuit of the main controller in the SSD can perform corresponding control on the DRAM.

[0057] Figure 3 is a schematic diagram of the data transmission path of the SSD in the related art. From Figure 3 it can be seen that the data instructions sent by the host can be transmitted to the SSD main controller through the Peripheral Component Interconnect Express (PCIe) interface. There are multiple channels between the main controller and the NAND flash memory. The SSD main controller operates multiple NAND flash memories in parallel through multiple channels.

[0058] In the related art, the underlying bandwidth is determined by the memory read time, write time, channel transfer time, and the number of channel parallelisms. With the rapid development of data storage technology, it is necessary to further increase the bandwidth to meet the read and write speeds of the fifth-generation double data rate (DDR5).

[0059] For this reason, the following technical solutions of the embodiments of the present application are proposed.

[0060] The embodiments of the present application provide a memory system, as Figure 4a and Figure 4b shown, including: at least one memory device and a memory controller coupled to the memory device; wherein,

[0061] the memory device and the memory controller are disposed on the same die;

[0062] the memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system;

[0063] the memory controller includes a second phase change memory, and the second phase change memory is configured to cache the data being transmitted when the memory controller performs data transmission with a host or the memory device.

[0064] Here, the die refers to the chip used to manufacture the integrated circuit. That is to say, the memory device and the memory controller are integrated on one chip.

[0065] Here, the first phase change memory is mainly used to store data, and the second phase change memory is mainly used to cache data.

[0066] It can be understood that, as an emerging non-volatile storage device, the phase change memory has great advantages over the flash memory in many aspects such as read and write speeds, read and write times, data retention time, cell area, and multi-value implementation. In the embodiments of the present application, on the one hand, by disposing the memory device and the memory controller on the same die, the area utilization rate of the memory system is improved, which is beneficial to the miniaturization requirements of the memory system; on the other hand, the first phase change memory is used to replace the NAND flash memory in the related art as the memory device of the SSD, and the second phase change memory is used to replace the DRAM in the related art as the cache part of the SSD, and the bandwidth of the SSD is increased by improving the read data speed and the write data speed.

[0067] In practical applications, the memory device and the memory controller are disposed side by side on the same substrate.

[0068] Here, the constituent material of the substrate may include semiconductor materials, such as silicon, germanium, or gallium arsenide, etc.

[0069] Here, the co - setting of the memory device and the memory controller on the same substrate can be understood as that the memory device and the memory controller are formed on the same surface of the same chip, or can be formed on different surfaces of the same chip. It can be understood that in the related art, the memory device and the memory controller are set on different substrates, forming three parts: a storage chip, a control chip, and a cache chip, and these three parts need to be connected through corresponding external pipelines to achieve data transmission. However, in the embodiments of the present application, the memory device and the memory controller are directly integrated on the same substrate, that is, the memory device and the memory controller are formed on the same chip. In this way, corresponding connections can be formed inside the same chip, without the need to additionally form pipelines outside the chip, thereby greatly improving the area utilization rate, being beneficial to the miniaturization requirements of the memory system, and the memory device and the memory controller transmit data through the corresponding internal connections formed, saving the time for outputting data in the external pipeline, and greatly improving the data transmission speed.

[0070] In some embodiments, such as Figure 4b and Figure 4c shown, the first phase - change memory includes a first phase - change memory array and a first peripheral circuit that are electrically connected to each other; the second phase - change memory includes a second phase - change memory array and a second peripheral circuit that are electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit that are both electrically connected to the first phase - change memory and the second phase - change memory;

[0071] The first peripheral circuit, the second peripheral circuit, and the third peripheral circuit are co - set on the same substrate;

[0072] Such as Figure 5 shown, the first phase - change memory array is provided on the first peripheral circuit; the capacitor is provided on the second peripheral circuit and the third peripheral circuit, and the second phase - change memory array is provided on the capacitor.

[0073] It should be noted that Figure 4b shows a more detailed structural schematic diagram of the memory system provided by the embodiments of the present application based on Figure 4a . The arrangement of each part of the memory system shown in Figure 4c , Figure 4b and Figure 4a does not represent the actual arrangement order of each part in the memory system, and is only used to indicate that the memory system provided by the embodiments of the present application includes such as Figure 4b and such as Figure 4aThe several parts shown. Figure 5 It is a partial schematic diagram observed along the Y direction of the first phase change memory and the second phase change memory.

[0074] Here, the first peripheral circuit mainly plays a role in controlling the first phase change memory array of the first phase change memory; the second peripheral circuit mainly plays a role in controlling the second phase change memory array of the second phase change memory; the third peripheral circuit mainly can play a role in controlling the connection between the first phase change memory and the second phase change memory. The capacitor mainly can play a role in supplying power to the first phase change memory and the second phase change memory.

[0075] In practical applications, both the first phase change memory and the second phase change memory include a phase change memory array and a peripheral circuit (which can be simply referred to as CMOS); among them, the phase change memory array can be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the phase change memory array and the peripheral circuit can be formed in different regions on the same plane; or the phase change memory array and the peripheral circuit can form a stacked structure, that is, they are formed on different planes. For example, the phase change memory array can be formed above the peripheral circuit to reduce the chip size. The embodiments of the present application exemplarily show a stacked structure formed by the phase change memory array and the peripheral circuit. In practical applications, the peripheral circuit can include any suitable digital, analog, and / or mixed signal circuits for facilitating various operations such as read operation, write operation, and erase operation of the PCM. For example, the peripheral circuit can include control logic, data buffers, decoders (decoders can also be referred to as encoders), drivers, and read / write circuits, etc. When the control logic receives read / write operation commands and address data, under the action of the control logic, the decoder can apply the corresponding voltage generated from the driver to the corresponding bit lines and word lines based on the decoded address to implement data read / write, and perform data interaction with the outside through the data buffer.

[0076] It can be understood that the first phase change memory is mainly used for storing data, with a higher requirement for the data storage capacity and a secondary requirement for the speed of data read operation and write operation; the second phase change memory is mainly used for caching data, with a higher requirement for the speed of data read operation and write operation and a secondary requirement for the data storage capacity. That is to say, in practical applications, the corresponding storage capacity and storage material can be selected according to the requirements of the memory system. In the embodiments of the present application, the first phase change memory array preferably has four stacked memory cell layers, while the second phase change memory array preferably has one memory cell layer.

[0077] In some embodiments, the first phase change memory array has four stacked memory cell layers; the second phase change memory array has one memory cell layer.

[0078] In practical applications, the first phase change memory array may have a single layer of memory cell layer, a two-layer stacked memory cell layer, a four-layer stacked memory cell layer, etc.; the second phase change memory array is not limited to having only a single layer of memory cell layer either. The second phase change memory array can also have a single layer of memory cell layer, a two-layer stacked memory cell layer, a four-layer stacked memory cell layer, etc. In practical applications, the number of layers of the memory cell layers of the first phase change memory array and the second phase change memory array can be selected according to requirements. In the embodiments of the present application, the first phase change memory array preferably has a four-layer stacked memory cell layer, while the second phase change memory array preferably has a single layer of memory cell layer.

[0079] In some embodiments, the capacitor is used to provide power; the capacitor includes multiple metal layers and insulating layers located between the multiple metal layers.

[0080] In practical applications, the material of the insulating layer between the metal layers in the capacitor may include silicon oxide, but is not limited thereto.

[0081] Here, the capacitor can provide power supply for dozens of milliseconds after the SSD loses power, helping the SSD save the cache data and key management data to the first phase change memory.

[0082] In practical applications, in Figure 5 There is also an interconnection layer in the area indicated by the ellipsis. Through the interconnection layer, the second peripheral circuit is electrically connected to the second phase change memory array.

[0083] It should be noted that Figure 5 Exemplarily, the capacitor is shown to be disposed between the second phase change memory array and the second peripheral circuit to maximize the space utilization rate. In practical applications, the capacitor can also be disposed on either side of the second phase change memory array along the Y direction, or on either side of the second peripheral circuit along the Y direction.

[0084] In practical applications, the first phase change memory array and the second phase change memory array can be made flush by adjusting the thickness of the capacitor, so as to form other structures on the first phase change memory array and the second phase change memory array.

[0085] In practical applications, the structures of the first phase change memory and the second phase change memory are similar. The structure of the first phase change memory will be described in detail below in conjunction with Figures 6a - 6d The structure of the first phase change memory will be described in detail.

[0086] Figures 6a - 6d The architecture diagram of the first phase change memory with a four-layer stacked memory cell layer in the embodiments of the present application is shown. Figure 6a It is a partial horizontal schematic view of the first phase change memory array of the first phase change memory observed along the Y direction; Figure 6bThe local horizontal schematic diagram of the first phase change memory array of the first phase change memory as observed along the X direction; Figure 6c The local horizontal schematic diagram of the first phase change memory array of the first phase change memory as observed along the Z direction; Figure 6d The local horizontal schematic diagram of the area for setting the functional devices of the first peripheral circuit in the first peripheral circuit of the first phase change memory as observed along the Z direction.

[0087] It can be understood that with the first phase change memory array placed in the front, the Z direction can be understood as the top-down direction (the direction of looking from the top bit line to the bottom bit line), the Y direction can be understood as the left-view direction (the direction in which the bit line extends), and the X direction can be understood as the front-view direction (the direction in which the word line extends).

[0088] Combined with Figures 6a - 6c , the first phase change memory with four storage cell layers includes: a first phase change memory array and a first peripheral circuit; wherein, the first phase change memory array includes: multiple parallel first bit lines 61, multiple parallel first word lines 63, multiple parallel second bit lines 65, multiple parallel second word lines 67, multiple parallel third bit lines 69, and multiple first storage cells 62 located between the multiple first bit lines 61 and the multiple first word lines 63 ( Figures 6a - 6c not shown in Figures 6a - 6c ), multiple second storage cells 64 located between the multiple first word lines 63 and the multiple second bit lines 65 ( Figures 6a - 6c not shown in Figures 6a - 6c ), multiple third storage cells 66 located between the multiple second bit lines 65 and the multiple second word lines 67 (

[0089] not shown in Figure 6a ), and multiple fourth storage cells 68 located between the multiple second word lines 67 and the multiple third bit lines 69 ( Figure 6b not shown in

[0090] ). That is to say, the first phase change memory includes three layers of bit lines, two layers of word lines, and four layers of storage cell layers.

[0089] Among them, there is an offset between the second bit line 65 and the corresponding first bit line 61 (a first bit line located below the second bit line). In practical applications, the offset here can refer to the Figure 6a offset shown along the Y direction with a half-bit line length. The third bit line 69 and the corresponding first bit line 61 (a first bit line located below the third bit line) overlap in the projection on the first plane, where the first plane includes any plane perpendicular to the Z axis. There is an offset between the second word line 67 and the corresponding first word line 63 (a first word line located below the second word line). In practical applications, the offset here can refer to the Figure 6b offset shown along the X direction with a half-word line length. The first bit line 61, the second bit line 65, and the third bit line 69 are all perpendicular to the first word line 63 and the second word line 67.

[0090] The first phase change memory with four storage cell layers further includes: a third bit line connection portion 691 that contacts the third bit line 69 and is connected to the first bit line 61, and is used to connect the third bit line 69 to related devices such as a decoder; a second word line connection portion 671 that contacts the second word line 67 and extends from between two adjacent second bit lines 65, two adjacent first word lines 63, and two adjacent first bit lines 61, and is used to connect the second word line 67 to related devices such as a decoder; a second bit line connection portion 651 that contacts the second bit line 65 and extends from between two adjacent first word lines 63 and two adjacent first bit lines 61, and is used to connect the second bit line 65 to related devices such as a decoder; a first word line connection portion 631 that contacts the first word line 63 and extends from between two adjacent first bit lines 61, and is used to connect the first word bit line 63 to related devices such as a decoder; and a first bit line connection portion 611 that contacts the first bit line 61 and is used to connect the first bit line 61 to related devices such as a decoder.

[0091] It should be noted that the first bit line 61, the corresponding second bit line 65, and the corresponding third bit line 69 may be offset-free or have a small offset in the X direction. In Figure 6c order to fully display the bit lines of each layer, an offset is provided in the X direction between the first bit line 61, the corresponding second bit line 65, and the corresponding third bit line 69; in terms of the word lines, in order to facilitate display, an offset is also provided in the Y direction between the first word line 63 and the corresponding second word line 67.

[0092] It should be noted that in Figures 6a - 6c the first phase change memory with four storage cell layers shown, each bit line connection portion and each word line connection portion penetrate vertically (in the Z direction) from the storage array portion to the peripheral circuit portion. And in order to ensure that the contact area between each bit line connection portion and each word line connection portion and the decoder in the peripheral circuit is large enough to achieve sufficient contact, there is a certain misalignment in the Y direction between the contact positions of adjacent first bit line connection portions 611 and the corresponding first bit line 61, there is a certain misalignment in the X direction between the contact positions of adjacent first word line connection portions 631 and the corresponding first word line 63, there is a certain misalignment in the Y direction between the contact positions of adjacent second bit line connection portions 651 and the corresponding second bit line 65, there is a certain misalignment in the X direction between the contact positions of adjacent second word line connection portions 671 and the corresponding second word line 67, and there is a certain misalignment in the Y direction between the contact positions of adjacent third bit line connection portions 691 and the corresponding third bit line 69.

[0093] Figure 6d shows in Figure 6c the distribution of the setting areas of the decoders corresponding to the architecture of Figure 6dThe distribution of the setting areas of the decoders corresponding to each memory cell block is shown in each dashed box. Here, the memory cell block is the smallest unit in the first phase change memory array of the first phase change memory. The first phase change memory array is based on this smallest unit and extends along the X direction and the Y direction respectively to form the first phase change memory array of the first phase change memory. The decoder includes a first bit line decoder (third bit line decoder), a first word line decoder, a second bit line decoder, and a second word line decoder; wherein, the corresponding bit line decoder is respectively connected to all the bit lines in the memory cell block through the corresponding bit line connection parts, and can selectively activate the corresponding bit lines; the corresponding word line decoder is respectively connected to all the word lines in the memory cell block through the corresponding word line connection parts, and can selectively activate the corresponding word lines.

[0094] It should be noted that in practical applications, the number of memory cell blocks of the first phase change memory with four memory cell layers is not limited to Figure 6c the 6 shown in Figure 6d ; the number of setting areas of the decoder of the first phase change memory with four memory cell layers is also not limited to

[0095] From Figure 6c it can be seen that since the first bit line connection part 611, the first word line connection part 631, the second bit line connection part 651, and the second word line connection part 671 all vertically enter the first peripheral circuit, based on this, in a memory cell block, in order to avoid the first word line connection part 631 corresponding to the first word line 63 extending into the first peripheral circuit, a Figure 6c first vertical bar area is vacated between the two middle first bit lines 61. At the same time, a second vertical bar area dedicated to placing the second word line connection part 671 is also vacated between two adjacent memory cell blocks. It can be seen that no bit lines and memory cells are provided for data storage in this first vertical bar area and the second vertical bar area. This first vertical bar corresponds to the dedicated area of the word line decoder, that is, Figure 6d the shown areas 3 and 4 in Figure 6d ; this second vertical bar corresponds to the dedicated area of the word line decoder, that is, Figure 6d the shown areas 7 and 8 in Figure 6d . At the same time, in a memory cell block, a third vertical bar area corresponding to the dedicated area for placing the third bit line decoder (first bit line decoder) is also vacated between the two middle first word lines 63. The dedicated area of this bit line decoder includes

[0096] Next, refer toFigures 7a - 7b The structure of the first phase change memory is further described. Figure 7a It is a partial three-dimensional schematic diagram of the memory device of the memory system provided by the embodiment of the present application; Figure 7b It is a partial schematic diagram of the memory device of the memory system provided by the embodiment of the present application. As Figures 7a - 7b shown, the first storage unit 62 is perpendicular to both the first bit line 61 and the first word line 63, the second storage unit 64 is perpendicular to both the first word line 63 and the second bit line 65, the third storage unit 66 is perpendicular to both the second bit line 65 and the second word line 67, and the fourth storage unit 68 is perpendicular to both the second word line 67 and the third bit line 69; each storage unit may include a stacked first electrode 601, a PCM element 602, a second electrode 603, a select element 604, and a third electrode 605. In practical applications, the vertical position relationship between the PCM element 602 and the select element 604 is not limited.

[0097] In practical applications, each storage unit layer of the first phase change memory may include multiple storage units, and each storage unit in the storage unit layer may include a stacked PCM element, a select element, and multiple electrodes. By turning on the select element, the electrode heats or quenches the PCM element to achieve the switching between the crystalline state and the amorphous state of the PCM element; data storage is achieved by the switching between the crystalline state and the amorphous state of the PCM element. In practical applications, the material of the PCM element includes a chalcogenide-based alloy (chalcogenide glass), such as GST (Ge-Sb-Te) alloy, or includes any other suitable phase change material; the material of the select element may include any suitable OTS material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc.; the material of the electrode may include a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some specific embodiments, the material of the electrode includes carbon, such as amorphous carbon.

[0098] Figure 7c It shows a partial schematic diagram of the memory controller of the memory system. From Figure 7c it can be seen that the structure of the second phase change memory array of the memory controller is similar to that of the first phase change memory array of the memory device, and both include word lines, bit lines, and storage units between the word lines and the bit lines.

[0099] It should be noted that Figure 7c only shows one design form of the capacitor, that is, the capacitor is designed to be parallel to the word line and the bit line. In practical applications, as Figure 7d shown, the capacitor can also be designed to be perpendicular to the word line and the bit line. Figure 7dOnly the number and arrangement of the capacitors are exemplarily shown herein and are not used to limit the number and arrangement manner of the capacitors in the embodiments of the present application. In the embodiments of the present application, it is preferred that the capacitors are in a form parallel to the word lines and bit lines. It can be understood that, on the one hand, it is easier to implement the process of designing the capacitors in a form parallel to the word lines and bit lines; on the other hand, when the capacitors are designed in a form parallel to the word lines and bit lines, capacitors with a larger area can be formed in the same space, so that a larger capacitance can be provided for the memory system.

[0100] In some embodiments, the second phase change memory performs read operations and write operations at a speed greater than that of the first phase change memory performing read operations and write operations.

[0101] In some embodiments, the phase change material used in the first phase change memory includes an alloy based on chalcogenide; the phase change material used in the second phase change memory includes a superlattice material.

[0102] Here, the superlattice material is a multilayer film formed by alternately growing two different components in thin layers of several nanometers to dozens of nanometers and maintaining strict periodicity. In fact, it is a specific form of layered fine composite material. The second phase change memory formed by using the superlattice material has excellent electrical transport properties, so that the second phase change memory has a faster read and write operation speed than the phase change memory formed by using conventional materials.

[0103] In some embodiments, as Figure 4b shown, the third peripheral circuit includes an interface and an overall control unit; wherein,

[0104] The interface is used to connect to the host;

[0105] The overall control unit is at least used to control the data transmission between the first phase change memory and the second phase change memory.

[0106] Here, in practical applications, the overall control unit is mainly composed of transistors, and the overall control unit may specifically include a storage data control circuit and a communication control circuit.

[0107] In some embodiments, the communication protocol between the interface and the host includes the Peripheral Component Interconnect Express 5.0 (PCIe5.0), a high-speed serial computer expansion bus standard version 5.0.

[0108] It can be understood that since the transmission rate of PCIe 5.0 can reach 32 GT / s, while the transmission rate of the previous generation of the high-speed serial computer expansion bus standard, PCIe 4.0, is 16 GT / s, and PCIe 5.0 expands from 8 lanes to 16 lanes, thus enabling a throughput and the number of read and write operations per second (IOPS, Input / Output Operations Per Second) that are twice that of PCIe 4.0, making it more suitable for the needs of large data centers and artificial intelligence. It can be understood that in the embodiments of the present application, a memory device and a memory controller are formed on the same chip, and data transmission between the memory device and the memory controller can be carried out through an interconnection structure formed inside the chip, and the interface where the memory controller is connected to the host is also integrated on the chip, which can reduce the size of the device and the time for data to be transmitted in the external channel, thus enabling the formation of a high-performance and small-sized memory system.

[0109] In some embodiments, the memory device further includes a first metal interconnection layer; the memory controller further includes a second metal interconnection layer; wherein, data transmission between the memory device and the memory controller is achieved through the electrical connection between the first metal interconnection layer and the second metal interconnection layer.

[0110] In practical applications, the metal interconnection layer can be disposed above the first phase change memory array and the second phase change memory array.

[0111] In the related art, the read data latency of NAND flash is approximately 50 - 70 us, the data latency in the main controller is approximately 15 - 20 us, the data transmission latency between interfaces is approximately 1 - 2 us, and the total data latency is approximately 80 - 100 us. In the currently relatively new technology, the read data latency of phase change memory is approximately 3 - 5 us, the data latency in the new error checking and correcting (ECC, Error Correcting Code) structure is approximately 5 us, and the data latency based on the PCIe 4.0 interface protocol is approximately 0.6 us, and the total data latency is approximately 10 us. However, the memory system provided by the embodiments of the present application forms an embedded memory device, a memory controller, and a transmission channel, and the interface protocol uses PCIe 5.0, so that the total data latency is less than 1 us.

[0112] In the embodiments of the present application, such as Figure 4bAs shown in 4c, in the first aspect, the host and the second phase change memory adopt the interface protocol of PCIe 5.0, enabling a throughput and IOPS that are twice that of PCIe 4.0; in the second aspect, a low-latency SSD based on a storage-class memory architecture and software optimization is constructed; in the third aspect, an embedded SSD main controller and memory are formed, that is, the controller and memory are integrated on the same substrate, and additional external channels (such as the first interface, the second interface, and the third interface in the related art) are removed, and the third peripheral circuit is used to replace the first interface and the peripheral circuit in the related art, thereby greatly improving the area utilization rate of the memory system; in the fourth aspect, the first phase change memory is used to replace the flash memory in the related art. Since the phase change memory has a faster read data, write data, and channel data transmission speed than NAND flash memory, the bandwidth of the memory system is improved. The second phase change memory is used to replace the dynamic random access memory in the related art, and the peripheral circuit of the second phase change memory can be formed while forming the peripheral circuit of the first phase change memory, without separately forming the peripheral circuit of the cache part, thus simplifying the process flow and saving area; in the fifth aspect, the control circuit part is simplified by removing the second interface and the DRAM control circuit in the related art.

[0113] In the embodiments of the present application, the embedded three-dimensional phase change memory is used to replace the DRAM in the related art as the mapping table. At the same time, the three-dimensional phase change memory is used to replace the NAND flash memory in the related art to store data. The three-dimensional phase change memory has a faster read data and write data speed than NAND flash memory, enabling the bandwidth of the memory system to be improved. Through the solution provided by the embodiments of the present application, the bandwidth of the memory system is improved, so that the memory system has a faster speed for storing and caching data. Moreover, the design of the memory system proposed in the embodiments of the present application is simple, and the device size is reduced at the same time.

[0114] An embodiment of the present application provides a memory system, including: at least one memory device and a memory controller coupled to the memory device; wherein, the memory device and the memory controller are disposed on the same die; the memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system; the memory controller includes a second phase change memory, and the second phase change memory is configured to cache the transmitted data when the memory controller performs data transmission with a host or the memory device. In the embodiment of the present application, on the one hand, by disposing the memory device and the memory controller on the same die, the area utilization rate of the memory system is improved, which is beneficial to the miniaturization requirement of the memory system; on the other hand, by using the first phase change memory to store data and the second phase change memory to cache data, since the phase change memory has a relatively fast speed for performing read operations and write operations, the bandwidth of the formed memory system is improved.

[0115] Based on the above memory system, an embodiment of the present application further provides a solid-state drive, including: the memory system provided by the embodiment of the present application.

[0116] It should be noted that: the solid-state drive provided in the above embodiment and the memory system embodiment described above belong to the same concept. For the specific structure, please refer to the memory system embodiment and will not be elaborated here.

[0117] Based on the above memory system, an embodiment of the present application further provides a manufacturing method of a memory system, including:

[0118] Forming at least one memory device and a memory controller coupled to the memory device on the same die; wherein,

[0119] The memory device includes a first phase change memory, and the first phase change memory is configured to store data for the memory system;

[0120] The memory controller includes a second phase change memory, and the second phase change memory is configured to cache the transmitted data when the memory controller performs data transmission with a host or the memory device.

[0121] In some embodiments, the first phase change memory includes a first phase change memory array and a first peripheral circuit that are electrically connected to each other; the second phase change memory includes a second phase change memory array and a second peripheral circuit that are electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit that are electrically connected to both the first phase change memory and the second phase change memory;

[0122] Forming at least one memory device and a memory controller coupled to the memory device on the same die, comprising:

[0123] Forming the first peripheral circuit, the second peripheral circuit, and the third peripheral circuit side by side on the same substrate;

[0124] Forming the first phase change memory array on the first peripheral circuit;

[0125] Forming the capacitor on the second peripheral circuit and the third peripheral circuit;

[0126] Forming the second phase change memory array on the capacitor.

[0127] In some embodiments, the method further comprises:

[0128] Forming a first metal interconnect layer in the memory device and a second metal interconnect layer in the memory controller; wherein, data transmission between the memory device and the memory controller is achieved through electrical connection of the first metal interconnect layer and the second metal interconnect layer.

[0129] The methods for forming the first phase change memory array, the second phase change memory array, the first peripheral circuit, the second peripheral circuit, the third peripheral circuit, and the capacitor are relatively mature in the related art and will not be elaborated here.

[0130] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the sequence numbers of the above processes do not mean the order of execution is prior or posterior, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The sequence numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0131] The methods disclosed in several method embodiments provided by the present application can be arbitrarily combined without conflict to obtain new method embodiments.

[0132] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory system, characterized in that, Comprising: At least one memory device and a memory controller coupled to the memory device; wherein, The memory device and the memory controller are disposed on the same die; The memory device includes a first phase change memory configured to store data for the memory system; The memory controller includes a second phase change memory configured to cache data being transferred when the memory controller transfers data with a host or the memory device; The first phase change memory includes a first phase change memory array and a first peripheral circuit electrically connected to each other; the second phase change memory includes a second phase change memory array and a second peripheral circuit electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit electrically connected to both the first phase change memory and the second phase change memory; The first peripheral circuit, the second peripheral circuit, and the third peripheral circuit are disposed side by side on the same substrate; The first phase change memory array is disposed on the first peripheral circuit; the capacitor is disposed on the second peripheral circuit and the third peripheral circuit, and the second phase change memory array is disposed on the capacitor; 2. The memory system according to claim 1, wherein The second phase change memory performs read operations and write operations at a speed greater than the speed at which the first phase change memory performs read operations and write operations; 3. The memory system according to claim 2, wherein The phase change material used in the first phase change memory includes a chalcogenide-based alloy; the phase change material used in the second phase change memory includes a superlattice material; 4. The memory system according to claim 1, wherein The first phase change memory array has four stacked memory cell layers; the second phase change memory array has one memory cell layer; 5. The memory system according to claim 1, wherein The capacitor is used to provide power; the capacitor includes multiple metal layers and insulating layers located between the multiple metal layers; 6. The memory system according to claim 1, wherein The third peripheral circuit includes an interface and an overall control unit; wherein, The interface is used to connect to a host; The overall control unit is at least used to control data transfer between the first phase change memory and the second phase change memory; 7. The memory system according to claim 6, wherein The communication protocol between the interface and the host includes the Peripheral Component Interconnect Express 5.0 (PCIe 5.0) of the High-Speed Serial Computer Extension Bus Standard; 8. The memory system according to claim 1, wherein The memory device further includes a first metal interconnect layer; the memory controller further includes a second metal interconnect layer; wherein, data transfer between the memory device and the memory controller is achieved through electrical connection of the first metal interconnect layer and the second metal interconnect layer; 9. A solid-state drive, characterized in that, Comprising: The memory system according to any one of claims 1 to 8; 10. A manufacturing method of a memory system, characterized in that, Comprising: Forming at least one memory device and a memory controller coupled to the memory device on the same die; wherein, The memory device includes a first phase change memory configured to store data for the memory system; The memory controller includes a second phase change memory configured to cache data being transferred when the memory controller transfers data with a host or the memory device; The first phase change memory includes a first phase change memory array and a first peripheral circuit electrically connected to each other; the second phase change memory includes a second phase change memory array and a second peripheral circuit electrically connected to each other; the memory controller further includes a capacitor and a third peripheral circuit both electrically connected to the first phase change memory and the second phase change memory; Forming at least one memory device and a memory controller coupled to the memory device on the same die, includes: Forming the first peripheral circuit, the second peripheral circuit, and the third peripheral circuit side by side on the same substrate; Forming the first phase change memory array on the first peripheral circuit; Forming the capacitor on the second peripheral circuit and the third peripheral circuit; Forming the second phase change memory array on the capacitor.

11. The method according to claim 10, characterized in that, The method further includes: Forming a first metal interconnect layer in the memory device and a second metal interconnect layer in the memory controller; wherein, data transmission between the memory device and the memory controller is achieved through electrical connection of the first metal interconnect layer and the second metal interconnect layer.

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