Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor and a capacitor connected with the driving transistor, and the display panel further comprises: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer comprising: a first conductive part for forming a gate electrode of the driving transistor; a second conductive part for forming a first electrode of the capacitor, the second conductive part being distributed around at least part of the side of the first conductive part in the orthographic projection of the substrate and separated from the first conductive part in the orthographic projection of the substrate; and a second conductive layer located on the side of the first conductive layer away from the substrate, the second conductive layer comprising: a third conductive part for forming a second electrode of the capacitor, the third conductive part at least partially overlapping with the second conductive part in the orthographic projection of the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related art, pixel drive circuits typically include a storage capacitor and a drive transistor. The storage capacitor is connected to the gate of the drive transistor and is used to store data signals to drive the drive transistor to output a drive current during the light-emitting phase. In related art, the storage capacitor and the drive transistor share a common conductive structure, which limits the storage capacitor's structure.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0005] According to one aspect of the present disclosure, a display panel is provided, which includes a pixel driving circuit, the pixel driving circuit including a driving transistor and a capacitor, the first electrode of the capacitor being electrically connected to the gate of the driving transistor, and the display panel further including: a base substrate; a first conductive layer located on one side of the base substrate, the first conductive layer including: a first conductive portion, the first conductive portion being used to form the gate of the driving transistor; a second conductive portion, the second conductive portion being used to form the first electrode of the capacitor, the orthographic projection of the second conductive portion on the base substrate being distributed around at least part of the side of the orthographic projection of the first conductive portion on the base substrate and being separated from the orthographic projection of the first conductive portion on the base substrate; a second conductive layer located on a side of the first conductive layer facing away from the base substrate, the second conductive layer including: a third conductive portion, the third conductive portion being used to form the second electrode of the capacitor, the orthographic projection of the third conductive portion on the base substrate at least partially overlapping with the orthographic projection of the second conductive portion on the base substrate.

[0006] In an exemplary embodiment of the present disclosure, the display panel also includes: a third conductive layer, located on the side of the second conductive layer away from the base substrate, the third conductive layer includes: a first connecting portion, the first connecting portion is electrically connected to the second conductive portion through a first via hole, and is electrically connected to the first conductive portion through a second via hole.

[0007] In an exemplary embodiment of the present disclosure, an opening is provided on the third conductive portion, the orthographic projection of the opening on the base substrate is located on the orthographic projection of the second conductive portion on the base substrate, and the orthographic projection of the first via on the base substrate is located within the orthographic projection of the opening on the base substrate.

[0008] In an exemplary embodiment of the present disclosure, the orthographic projection of the second conductive portion on the base substrate is distributed around the side of the orthographic projection of the first conductive portion on the base substrate; the third conductive portion includes: a first sub-conductive portion, the orthographic projection of the first sub-conductive portion on the base substrate overlaps with the orthographic projection of the second conductive portion on the base substrate; a second sub-conductive portion, the orthographic projection of the second sub-conductive portion on the base substrate overlaps with the orthographic projection of the second conductive portion on the base substrate, and the opening is formed between the second sub-conductive portion and the first sub-conductive portion.

[0009] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the first sub-conductive portion in any pixel driving circuit is connected to the second sub-conductive portion in the pixel driving circuit adjacent to the pixel driving circuit in the first direction.

[0010] In an exemplary embodiment of the present disclosure, the orthographic projection of the second conductive portion on the base substrate is a closed ring, and the orthographic projection of the first conductive portion on the base substrate is located within the orthographic projection of the second conductive portion on the base substrate; the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the opening of the third conductive portion on the base substrate form a closed ring, and the orthographic projection of the first conductive portion on the base substrate is located within the closed ring formed by the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the opening of the third conductive portion on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, which are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the pixel driving circuit also includes a second transistor, the first electrode of the second transistor is connected to the first electrode of the driving transistor, the second electrode is connected to the gate of the driving transistor, and the gate is connected to the gate driving signal line; the first conductive layer also includes: the gate driving signal line, the positive projection on the substrate extends along the first direction, and the second conductive portion is at least partially located between the gate driving signal line and the first conductive portion.

[0012] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a second transistor, the first electrode of the second transistor is connected to the first electrode of the driving transistor, and the second electrode is connected to the gate of the driving transistor; the display panel also includes: an active layer, located between the base substrate and the first conductive layer, the active layer includes a second active portion, the second active portion includes a first sub-active portion, a second sub-active portion and a third sub-active portion, the first sub-active portion and the second sub-active portion are used to form a channel region of the second transistor, and the third sub-active portion is connected between the first sub-active portion and the second sub-active portion; the second conductive layer also includes a fourth conductive portion, the fourth conductive portion is connected to a stable voltage source, the fourth conductive portion includes a third sub-conductive portion, and the orthographic projection of the third sub-conductive portion on the base substrate at least partially overlaps with the third sub-active portion.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor being connected to the gate of the driving transistor, and a second electrode being connected to the first initial signal line; the display panel further includes: an active layer, located between the base substrate and the first conductive layer, the active layer including a first active portion and an eighth active portion, the first active portion including a fourth sub-active portion and a fifth sub-active portion, the fourth sub-active portion and the fifth sub-active portion being used to form a channel region of the first transistor, the eighth active portion being connected between the second sub-active portion and the fifth sub-active portion, and the eighth active portion being connected to the first connecting portion through a via; the second conductive layer further includes a fourth conductive portion, the fourth conductive portion being connected to a stable voltage source, the fourth conductive portion including a fourth sub-conductive portion, the orthographic projection of the fourth sub-conductive portion on the base substrate at least partially overlapping with the orthographic projection of the eighth active portion on the base substrate.

[0014] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the pixel driving circuit also includes a fourth transistor, a first electrode of the fourth transistor is connected to a data signal line, and a second electrode is connected to the second electrode of the driving transistor; the fourth conductive portion also includes: a fifth sub-conductive portion, connected to the fourth sub-conductive portion, and the orthographic projection of the fifth sub-conductive portion on the substrate extends along the second direction, and in the same pixel driving circuit, the orthographic projection of the fifth sub-conductive portion on the substrate is located between the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the data signal line on the substrate.

[0015] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor and a fifth transistor, wherein the first electrode of the fourth transistor is connected to the data signal line, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the gate driving signal line; the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first power line, and the gate is connected to the enable signal line; the display panel further includes: an active layer, located between the base substrate and the first conductive layer, the active layer including a fourth active portion and a fifth active portion, the fourth active portion is used to form a channel region of the fourth transistor, and the fifth active portion is used to form a channel region of the fifth transistor; the first conductive layer also includes : The gate drive signal line, whose orthographic projection on the substrate extends along the first direction, partially covers the orthographic projection of the fourth active portion on the substrate, and a partial structure of the gate drive signal line forms the gate of the fourth transistor; the enable signal line, whose orthographic projection on the substrate extends along the first direction and partially covers the orthographic projection of the fifth active portion on the substrate, and a partial structure of the enable signal line forms the gate of the fifth transistor; the orthographic projection of the second conductive portion on the substrate is located between the orthographic projection of the gate drive signal line on the substrate and the orthographic projection of the enable signal line on the substrate.

[0016] In an exemplary embodiment of the present disclosure, the third conductive layer also includes: a data signal line, the orthographic projection of the base substrate extending along the second direction; a first power line, the orthographic projection of the first power line on the base substrate extending along the second direction, the first power line being connected to the third conductive portion through a via; the orthographic projection of the first power line on the base substrate being located between the orthographic projection of the first connection portion on the base substrate and the orthographic projection of the data signal line on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, which are arrayed in a first direction and a second direction, and the first direction and the second direction intersect; the pixel driving circuit further includes a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first electrode of the fourth transistor is connected to a data signal line, and a second electrode is connected to the second electrode of the driving transistor; a first electrode of the fifth transistor is connected to the second electrode of the driving transistor, and a second electrode is connected to a first power line; a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode is connected to a light-emitting unit; the display panel further includes: an active layer, including a fourth active portion, a fifth active portion, and a sixth active portion, wherein the fourth active portion is used to form a channel region of the fourth transistor, and the fifth active portion is used to form a channel region of the fourth transistor. The channel region of the fifth transistor is formed, and the sixth active portion is used to form the channel region of the sixth transistor; the first conductive layer also includes: an enable signal line, the orthographic projection on the base substrate extends along the first direction and partially covers the orthographic projection of the fifth active portion on the base substrate, and partially covers the orthographic projection of the sixth active portion on the base substrate, and a partial structure of the enable signal line is used to form the gate of the fifth transistor, and a partial structure is used to form the gate of the sixth transistor; a gate drive signal line, the orthographic projection on the base substrate extends along the first direction and partially covers the orthographic projection of the fourth active portion on the base substrate, and a partial structure of the gate drive signal line is used to form the gate of the fourth transistor; the first conductive portion is located between the gate drive signal line and the enable signal line.

[0018] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor being connected to the second electrode of the sixth transistor, and a second electrode being connected to a second initial signal line; the active layer further includes: a seventh active portion for forming a channel region of the seventh transistor; the first conductive layer further includes: a reset signal line, an orthographic projection of the substrate extending along the first direction, the orthographic projection of the reset signal line on the substrate being located on a side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the first conductive portion on the substrate; the second conductive layer further includes: a second initial signal line, an orthographic projection of the substrate extending along the first direction, the orthographic projection of the second initial signal line on the substrate being located between the orthographic projection of the reset signal line on the substrate and the orthographic projection of the enable signal line on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the pixel driving circuit also includes a first transistor, a first electrode of the first transistor is connected to the gate of the driving transistor, and a second electrode is connected to the first initial signal line; the active layer also includes a first active portion, the first active portion includes a fourth sub-active portion, a fifth sub-active portion and a sixth sub-active portion, the fourth sub-active portion and the fifth sub-active portion are used to form a channel region of the first transistor, and the sixth sub-active portion is connected between the fourth sub-active portion and the fifth sub-active portion; the display panel also includes: the first initial signal line, the orthographic projection of the first initial signal line on the substrate extends along the first direction, and the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion on the substrate.

[0020] In an exemplary embodiment of the present disclosure, the first direction is the row direction, and the second direction is the column direction; wherein, the orthographic projection of the reset signal line in the previous row on the substrate covers the orthographic projection of the fourth sub-active portion and the orthographic projection of the fifth sub-active portion in the current row on the substrate, a partial structure of the reset signal line in the previous row is used to form the gate of the first transistor in the current row, and the orthographic projection of the reset signal line in the previous row on the substrate is located on the side of the orthographic projection of the gate drive signal line in the current row on the substrate away from the orthographic projection of the first conductive portion in the current row on the substrate; the orthographic projection of the second initial signal line in the current row on the substrate is located on the side of the orthographic projection of the gate drive signal line in the current row on the substrate away from the orthographic projection of the reset signal line in the previous row on the substrate.

[0021] According to another aspect of the present disclosure, a display device is provided, comprising the display panel described in any embodiment of the present disclosure.

[0022] The display panel provided by the present disclosure has a first conductive portion located in the first conductive layer forming the gate of the driving transistor, and a second conductive portion forming the first electrode of the capacitor. The first conductive portion and the second conductive portion are arranged separately, so that the first electrode of the capacitor does not share the gate of the driving transistor. As a result, the capacitor size can be flexibly adjusted according to the size of the display panel, thereby improving the flexibility of capacitor layout. By increasing the capacitor size, the stability of the capacitor operation can be increased, which is beneficial for maintaining the stability of the driving transistor during the light-emitting phase. Alternatively, by reducing the size of the capacitor, the space occupied by the pixel driving circuit can be increased, thereby improving the resolution of the display panel.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0025] Figure 1 1 is a schematic diagram of a circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure;

[0026] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0027] Figure 3 A structural diagram of a display panel according to an embodiment of the present disclosure;

[0028] Figure 4 for Figure 3 The structural layout of the second conductive layer;

[0029] Figure 5 for Figure 3 The structural layout of the first conductive layer and the second conductive layer;

[0030] Figure 6 for Figure 3 The structural layout of the active layer;

[0031] Figure 7 for Figure 3 The structural layout of the first conductive layer;

[0032] Figure 8 for Figure 3 The structural layout of the third conductive layer;

[0033] Figure 9 for Figure 3 A structural layout of the active layer and the first conductive layer;

[0034] Figure 10 for Figure 3 A structural layout of an active layer, a first conductive layer, and a second conductive layer;

[0035] Figure 11 for Figure 3 Cross-sectional view along AA direction;

[0036] Figure 12 is a structural diagram of a first conductive layer according to another embodiment of the present disclosure;

[0037] Figure 13 is a structural layout of a first conductive layer according to another embodiment of the present disclosure;

[0038] Figure 14 is a structural diagram of a second conductive layer according to another embodiment of the present disclosure;

[0039] Figure 15 is a structural diagram of a second conductive layer according to another embodiment of the present disclosure;

[0040] Figure 16 is a structural diagram of a display panel according to another embodiment of the present disclosure;

[0041] Figure 17 for Figure 13 The structural layout of the first conductive layer;

[0042] Figure 18 for Figure 13 A structural layout of the active layer and the first conductive layer;

[0043] Figure 19 for Figure 13 The structural layout of the second conductive layer;

[0044] Figure 20 for Figure 13 The structure layout of the active layer, the first conductive layer and the second conductive layer. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0047] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0048] Figure 1 The figure is a circuit diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first transistor T1 has a first electrode connected to node N, a second electrode connected to the first initial signal terminal Vinit1, and a gate connected to the reset signal terminal Re1. The second transistor T2 has a first electrode connected to the first electrode of the driving transistor T3, a second electrode connected to node N, and a gate connected to the gate drive signal terminal Gate. The gate of the driving transistor T3 is connected to node N. The fourth transistor T4 has a first electrode connected to the data signal terminal Da, a second electrode connected to the second electrode of the driving transistor T3, and a gate connected to the gate drive signal terminal Gate. The fifth transistor T5 has a first electrode connected to the second electrode of the driving transistor T3, a second electrode connected to the first power supply terminal VDD, and a gate connected to the enable signal terminal EM. The sixth transistor T6 has a first electrode connected to the first electrode of the driving transistor T3, and a gate connected to the enable signal terminal EM. The seventh transistor T7 has a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the second initial signal terminal Vinit2, and a gate connected to the reset signal terminal Re2. A capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting element OLED to drive the light-emitting element OLED to emit light. The light-emitting element OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. The transistors T1 - T7 may all be P-type transistors.

[0049] It should be noted that the transistors used in each embodiment of the present disclosure can be thin film transistors, field effect transistors, or other devices with the same characteristics. In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0050] Figure 2 for Figure 1A timing diagram of each node in a driving method of a pixel driving circuit. Wherein, Gate represents the timing of the gate driving signal terminal Gate, Re1 represents the timing of the reset signal terminal Re1, Re2 represents the timing of the reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the reset signal terminal Re2 and the gate driving signal terminal Gate output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time, the data signal terminal Da outputs a driving signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal, Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t3: The enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the output current formula of the driving transistor I = (μWCox / 2L)(Vgs-Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0051] This exemplary embodiment provides a display panel, which includes a pixel driving circuit distributed in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect, and the pixel driving circuit includes a driving transistor T3 and a capacitor C, wherein a first electrode of the capacitor C is electrically connected to a gate of the driving transistor T3, and a second electrode of the capacitor C is electrically connected to a first power line. The pixel driving circuit can be as follows Figure 1 shown. Figure 3 is a structural diagram of a display panel according to one embodiment of the present disclosure, Figure 4 for Figure 3 The structural layout of the second conductive layer, Figure 5 for Figure 3 The structural layout of the first conductive layer and the second conductive layer, such as Figure 3-Figure 5As shown, each display panel may include: a base substrate, a first conductive layer 20, and a second conductive layer 30, wherein the first conductive layer 20 is located on one side of the base substrate, and the first conductive layer 20 may include a first conductive portion 21 and a second conductive portion 22, wherein the first conductive portion 21 is used to form the gate of the driving transistor T3; the second conductive portion 22 is used to form the first electrode of the capacitor C, and the orthographic projection of the second conductive portion 22 on the base substrate is distributed around at least part of the side of the orthographic projection of the first conductive portion 21 on the base substrate and is separated from the orthographic projection of the first conductive portion 21 on the base substrate; the second conductive layer 30 is located on the side of the first conductive layer 20 away from the base substrate, and the second conductive layer 30 may include a third conductive portion 23, which is used to form the second electrode of the capacitor C, and the orthographic projection of the third conductive portion 23 on the base substrate at least partially overlaps with the orthographic projection of the second conductive portion 22 on the base substrate.

[0052] In the display panel provided by the present disclosure, the first conductive portion 21 located in the first conductive layer 20 forms the gate of the driving transistor T3, and the second conductive portion 22 forms the first electrode of the capacitor C. The first conductive portion 21 and the second conductive portion 22 are provided separately, so that the first electrode of the capacitor C does not share the gate of the driving transistor T3. As a result, the size of the capacitor C can be flexibly adjusted according to the size of the display panel, improving the flexibility of the layout of the capacitor C. By increasing the size of the capacitor C, the stability of the capacitor C can be increased, which is conducive to maintaining the stability of the driving transistor T3 during the light-emitting phase. Alternatively, by reducing the size of the capacitor C, the space occupied by the pixel driving circuit can be increased, thereby improving the resolution of the display panel.

[0053] like Figure 3 、 Figure 5 As shown, in this exemplary embodiment, the first direction X may be a row direction, and the second direction Y may be a column direction. In this exemplary embodiment, the display panel may further include an active layer 10 and a third conductive layer 40, wherein the base substrate, the active layer 10, the first conductive layer 20, the second conductive layer 30, and the third conductive layer 40 are stacked in sequence, and an insulating layer may be provided between the above functional layers. Figure 6-10 As shown, Figure 6 for Figure 3 The structural layout of the active layer, Figure 7 for Figure 3 The structural layout of the first conductive layer, Figure 8 for Figure 3 The structural layout of the third conductive layer, Figure 9 for Figure 3 The structural layout of the active layer and the first conductive layer, Figure 10 for Figure 3 The structure layout of the active layer, the first conductive layer and the second conductive layer.

[0054] like Figure 6 、 Figure 9As shown, the active layer 10 may include a first active portion 11, a second active portion 12, a fourth active portion 14, a fifth active portion 15, a sixth active portion 16, a seventh active portion 17, and a ninth active portion 19, wherein the first active portion 11 may include a fourth sub-active portion 111, a fifth sub-active portion 112, and a sixth sub-active portion 113, the fourth sub-active portion 111 being used to form a first channel region of the first transistor T1, the fifth sub-active portion 112 being used to form a second channel region of the first transistor T1, and the sixth sub-active portion 113 being connected between the fourth sub-active portion 111 and the fifth sub-active portion 112. The second active portion 12 may include a first sub-active portion 121, a second sub-active portion 122, and a third sub-active portion 123. The first sub-active portion 121 is used to form the first channel region of the second transistor T2, the second sub-active portion 122 is used to form the second channel region of the second transistor T2, and the third sub-active portion 123 is connected between the first sub-active portion 121 and the second sub-active portion 122. The fourth active portion 14 is used to form the channel region of the fourth transistor T4, the fifth active portion 15 is used to form the channel region of the fifth transistor T5, and the sixth active portion 16 is used to form the channel region of the sixth transistor T6. The sixth active portion 16 may be connected to the light-emitting unit OLED through the via H4. The seventh active portion 17 is used to form the channel region of the seventh transistor T7. The ninth active portion 19 is used to form the channel region of the driving transistor T3. The active layer 10 may further include an eighth active portion 18, which may extend along the second direction Y and connect between the first active portion 11 and the second active portion 12. Specifically, the eighth active portion 18 may connect between the second sub-active portion 122 and the fifth sub-active portion 112. The active layer 10 may be formed of a polycrystalline silicon semiconductor material. Accordingly, the transistors in the display panel of the present disclosure may be P-type low-temperature polycrystalline silicon thin film transistors.

[0055] like Figure 7 、 Figure 9 、 Figure 10 As shown, in this exemplary embodiment, the first conductive layer 20 includes, in addition to the first conductive portion 21 and the second conductive portion 22, a gate drive signal line Gate, an enable signal line EM, and a reset signal line RE, wherein the orthographic projection of the gate drive signal line Gate on the base substrate can extend along the first direction X, and the orthographic projection of the gate drive signal line Gate on the base substrate partially covers the first sub-active portion 121, partially covers the second sub-active portion 122, and partially covers the fourth active portion 14, so that part of the structure of the gate drive signal line Gate forms the gate of the second transistor T2, and part of the structure forms the gate of the fourth transistor T4. At the same time, the gate drive signal line Gate can be used to provide Figure 1The orthographic projection of the enable signal line EM on the substrate can extend along the first direction X and partially cover the orthographic projection of the fifth active portion 15 on the substrate and partially cover the orthographic projection of the sixth active portion 16 on the substrate. Part of the structure of the enable signal line EM forms the gate of the fifth transistor T5 and part of the structure forms the gate of the sixth transistor T6. At the same time, the enable signal line EM can provide Figure 1 The enable signal end in the substrate. The orthographic projection of the reset signal line RE on the substrate can extend along the first direction X and partially cover the fourth active portion 14, and a partial structure of the reset signal line RE forms the gate of the first transistor T1. The gate drive signal line Gate, the enable signal line EM, and the reset signal line RE in the pixel driving circuit of the same row are arranged in sequence along the second direction Y in the first conductive layer 20. Specifically, the orthographic projection of the gate drive signal line Gate on the substrate and the orthographic projection of the enable signal line EM on the substrate are located on both sides of the orthographic projection of the first conductive portion 21 on the substrate, and the orthographic projection of the reset signal line RE on the substrate is located on the side where the orthographic projection of the enable signal line EM on the substrate is away from the orthographic projection of the first conductive portion 21 on the substrate. At the same time, the reset signal line RE can be used to provide the pixel driving circuit of this row. Figure 1 The reset signal terminal Re1 in the upper row is provided to the pixel driving circuit Figure 1 The second reset signal terminal Re2 in the pixel driving circuit. In this exemplary embodiment, the reset signal lines RE in different rows of pixel driving circuits can be reused. The orthographic projection of the reset signal line RE of the previous row on the substrate covers the orthographic projection of the fourth sub-active portion 111 and the orthographic projection of the fifth sub-active portion 112 of this row on the substrate. Part of the structure of the reset signal line RE of the previous row forms the gate of the first transistor T1 of this row, and the orthographic projection of the reset signal line RE of the previous row on the substrate is located on the side of the orthographic projection of the gate drive signal line Gate of this row on the substrate away from the orthographic projection of the first conductive portion 21 of this row on the substrate; the orthographic projection of the second initial signal line of this row on the substrate is located on the side of the orthographic projection of the gate drive signal line Gate of this row on the substrate away from the orthographic projection of the reset signal line RE of the previous row on the substrate. By multiplexing the reset signal lines RE, the number of signal lines can be reduced and the structure of the display panel can be simplified. In this exemplary embodiment, the display panel can use the first conductive layer 20 as a mask to perform conductor processing on the active layer 10, that is, the active layer 10 covered by the first conductive layer 20 forms the channel region of the transistor, and the area not covered by the first conductive layer 20 forms a conductor structure.

[0056] It should be understood that when the orthographic projection of a structure on the substrate described in this exemplary embodiment extends in a certain direction, it can be understood that the orthographic projection of the structure on the substrate extends entirely in that direction, that is, the orthographic projection of the structure on the substrate can extend in a straight line or in a curved direction. Furthermore, when the orthographic projection of a structure A on the substrate described in this exemplary embodiment overlaps the orthographic projection of another structure B on the substrate, it can be understood that the outline of the projection of B on the substrate plane is completely within the outline of the projection of A on the same plane.

[0057] like Figure 4 As shown, in this exemplary embodiment, the second conductive layer 30 includes a third conductive portion 23. An opening 25 can be provided in the third conductive portion 23 to expose a portion of the second conductive portion 22 for connection to the first conductive portion 21. Exemplarily, the third conductive portion 23 can be provided with an opening 25, the orthographic projection of the opening 25 on the substrate being located on the orthographic projection of the second conductive portion 22 on the substrate, and the orthographic projection of the first via connecting the first connecting portion and the second conductive portion on the substrate being located within the orthographic projection of the opening 25 on the substrate. This allows for electrical connection between the first conductive portion 21 and the second conductive portion 22. It should be understood that in other exemplary embodiments of the present disclosure, the electrical connection between the first conductive portion 21 and the second conductive portion 22 can be achieved through other methods. The orthographic projection of the third conductive portion 23 on the substrate at least partially overlaps with the orthographic projection of the second conductive portion 22 on the substrate, which can be understood as the orthographic projection of the third conductive portion 23 on the substrate covering the orthographic projection of the second conductive portion 22 on the substrate that is not directly opposite the opening 25. In this exemplary embodiment, in addition to the third conductive portion 23, the second conductive layer 30 may also include a first initial signal line Vinit1, a second initial signal line Vinit2, and a fourth conductive portion 24, wherein the orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate may both extend along a first direction X. In this exemplary embodiment, the first direction X may be a row direction, and the second direction Y may be a column direction. The orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the current row on the substrate may be located between the orthographic projection of the reset signal line RE in the pixel driving circuit of the next row on the substrate and the orthographic projection of the enable signal line EM in the pixel driving circuit of the current row on the substrate, and the orthographic projection of the first initial signal line Vinit1 in the pixel driving circuit of the current row on the substrate may be located between the orthographic projection of the reset signal line RE in the pixel driving circuit of the current row on the substrate and the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the previous row on the substrate. The second initial signal line Vinit2 can be connected to the seventh active portion 17 through the via H5, so that the second electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2. Figure 10As shown, the orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the sixth sub-active portion 113 on the substrate can both extend along the first direction X, and the orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the sixth sub-active portion 113 on the substrate at least partially overlap (for example, the width of the first initial signal line Vinit1 in the second direction can be set to be greater than the width of the sixth sub-active portion 113 in the second direction), so that the first initial signal line Vinit1 can stabilize the voltage of the sixth sub-active portion 113, reduce the leakage current of the sixth sub-active portion 113 to the first transistor T1, and reduce the voltage fluctuation of the pixel driving circuit driving the transistor T3 during the light-emitting stage. Figure 4As shown, the fourth conductive portion 24 is connected to a stable voltage source. The fourth conductive portion 24 may include a third sub-conductive portion 241. The orthographic projection of the third sub-conductive portion 241 on the substrate may extend along the second direction Y. The orthographic projection of the third sub-conductive portion 241 on the substrate at least partially overlaps with the orthographic projection of the third sub-active portion 123 on the substrate (for example, the width of the third sub-conductive portion 241 in the first direction may be set to be greater than the width of the third sub-active portion 123 in the first direction). The third sub-active portion 123 is a conductive structure, which is connected to form the second transistor T 2, and the orthographic projection of the third sub-active portion 123 on the substrate covers the orthographic projection of the third sub-active portion 123 on the substrate. Because the fourth conductive portion 24 is connected to a stable voltage source, the fourth conductive portion 24 can stabilize the third sub-active portion 123, thereby reducing the leakage of the second transistor T2 and preventing the influence of the pixel data voltage change of the adjacent column on the pixel, thereby reducing the voltage fluctuation of the pixel driving circuit driving the transistor T3 during the light-emitting stage, thereby improving the picture quality. The fourth conductive portion 24 may further include a fourth sub-conductive portion 242, the orthographic projection of the fourth sub-conductive portion 242 on the substrate at least partially overlapping with the orthographic projection of the eighth active portion 18 on the substrate (for example, the width of the fourth sub-conductive portion 242 in the first direction may be set to be greater than the width of the eighth active portion 18 in the first direction), so that the fourth sub-conductive portion 242 can form a voltage stabilizing effect on the eighth active portion 18, thereby eliminating or reducing the noise influence of the data signal line Vdata or other signal lines on the eighth active portion 18. Because the eighth active portion 18 is connected to the first electrode of the first transistor T1 and the gate of the driving transistor T3, the voltage stabilization of the eighth active portion 18 can reduce the voltage fluctuation of the driving transistor T3 of the pixel driving circuit during the light-emitting stage. In addition, the fourth conductive portion 24 may further include a fifth sub-conductive portion 243, which is connected to the fourth sub-conductive portion 242 to connect to a stable voltage source. The orthographic projection of the fifth sub-conductive portion 243 on the substrate may extend along the second direction Y. The orthographic projection of the fifth sub-conductive portion 243 on the substrate is located between the orthographic projection of the eighth active portion 18 on the substrate and the orthographic projection of the data signal line Vdata on the substrate, thereby shielding the alternating voltage of the data signal line Vdata from interfering with the eighth active portion 18, thereby improving the voltage stabilizing effect of the fourth conductive portion 24 on the eighth active portion 18. In this exemplary embodiment, combined with Figure 3 、 Figure 4 、 Figure 8 and Figure 10, the fourth conductive portion 24 can be connected to the first power line Vdd through the via H7 at the location of the fourth sub-conductive portion 242, so as to provide a stable voltage source for the fourth conductive portion 24 through the first power line Vdd. Of course, in other exemplary embodiments of the present disclosure, a stable voltage source can also be provided by other means. In addition, it should be understood that there is a conductive connection portion between the third sub-conductive portion 241 and the fourth sub-conductive portion 242.

[0058] like Figure 8 As shown, in this exemplary embodiment, the third conductive layer 40 may include a first connecting portion 41, and the first connecting portion 41 is electrically connected to the second conductive portion 22 through the first via H1, and is electrically connected to the first conductive portion 21 through the second via H2. The orthographic projection of the first connecting portion 41 on the base substrate may extend along the second direction Y, and the orthographic projection of the first connecting portion 41 on the base substrate intersects with the orthographic projection of the opening 25 on the base substrate to connect to the second conductive portion 22 through the first via H1. In addition, in this exemplary embodiment, the third conductive layer 40 may include a first power line Vdd and a data signal line Vdata. The orthographic projection of the first power line Vdd on the base substrate and the orthographic projection of the data signal line Vdata on the base substrate may both extend along the second direction Y. The first power line Vdd may be used to provide Figure 1 The first power supply terminal shown, the data signal line Vdata can be used to provide Figure 1 The data signal end in the middle. The first power line Vdd can be connected to the third conductive part 23 through the via H6 to achieve electrical connection of the second electrode of the capacitor C to the first power line Vdd. The orthographic projection of the data signal line Vdata on the substrate can be located on the side of the orthographic projection of the first power line Vdd on the substrate away from the orthographic projection of the first conductive part 21 on the substrate. In this exemplary embodiment, the first connecting part 41 can be connected to the eighth active part 18 through the via H3, so that the first electrode of the first transistor T1 and the second electrode of the second transistor T2 are connected to the gate of the driving transistor T3. The first power line Vdd can be connected to the fourth conductive part 24 through the via H7 to provide a stable voltage source for the fourth conductive part 24. The first power line Vdd is connected to the third conductive part 23 through the via H6 to achieve electrical connection of the second plate of the capacitor C with the first power line Vdd. The first power line Vdd is connected to the fifth active part 15 through the via H10 to achieve connection of the fifth transistor T5 with the first power line Vdd. The data signal line Vdata may be connected to the fourth active portion 14 through the via H8 , so that the first electrode of the fourth transistor T4 is connected to the data signal line Vdata.

[0059] Figure 11 for Figure 3In the cross-sectional view along the AA direction, the display panel may further include a buffer layer 2, a first insulating layer 3, a second insulating layer 4, and a first dielectric layer 5, wherein the base substrate 1, the buffer layer 2, the active layer, the first insulating layer 3, the first conductive layer 20, the second insulating layer 4, the second conductive layer 30, the first dielectric layer 5, and the third conductive layer 40 are stacked in sequence. The first conductive layer 20, the second conductive layer 30, and the third conductive layer 40 can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer 3, the second insulating layer 4, and the first dielectric layer 5 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The base substrate 1 may include a glass substrate, a barrier layer, a polyimide layer, etc. which are stacked in sequence, and the barrier layer may be made of an inorganic material.

[0060] The following further describes the structure of the second conductive portion 22 and the third conductive portion 23 forming the capacitor C in the present disclosure in conjunction with the accompanying drawings. The second conductive portion 22 is located in the first conductive layer 20, and the third conductive portion 23 is located in the second conductive layer 30. The second conductive portion 22 and the third conductive portion 23 are arranged opposite to each other to form a parallel plate capacitor structure. Figure 3-10As shown, in an exemplary embodiment of the present disclosure, the orthographic projection of the second conductive portion 22 on the substrate is distributed around the side of the orthographic projection of the first conductive portion 21 on the substrate; the third conductive portion 23 may include a first sub-conductive portion 231 and a second sub-conductive portion 232, wherein the orthographic projection of the first sub-conductive portion 231 on the substrate overlaps with the orthographic projection of the second conductive portion 22 on the substrate, and the orthographic projection of the second sub-conductive portion 232 on the substrate overlaps with the orthographic projection of the second conductive portion 22 on the substrate, and the opening 25 is formed between the second sub-conductive portion 232 and the first sub-conductive portion 231. The orthographic projection of the third conductive portion 23 on the substrate may cover the orthographic projection of the portion of the second conductive portion 22 on the substrate that is not directly opposite the opening 25. The second conductive portion 22 may be a continuous structure, and the third conductive portion 23 includes two sub-conductive portions. The opening 25 formed between the two sub-conductive portions is used to expose a portion of the second conductive portion 22 for electrical connection to the first conductive portion 21 via the first connecting portion 41. The second conductive portion 22 is arranged adjacent to the first conductive portion 21 and distributed around part of the side of the first conductive portion 21. The two sub-conductive portions of the third conductive portion 23 are arranged opposite to the second conductive portion 22 to form a parallel plate capacitor. This structure can save the space occupied by the capacitor plate, which is beneficial to the miniaturization of the display panel, thereby facilitating the improvement of the resolution of the display panel. It should be understood that if the display panel size allows and meets the PPI design requirements, the area of ​​the second conductive portion 22 can be increased as much as possible, and the area of ​​the third conductive portion 23 can be increased accordingly to increase the capacitance of the capacitor C. In this exemplary embodiment, Figure 7 As shown, the first conductive portion 21 is located between the gate drive signal line Gate and the enable signal line EM, and the second conductive portion 22 is distributed around the first conductive portion 21 and is located between the gate drive signal line Gate and the enable signal line EM. Further, the second conductive portion 22 is at least partially located between the gate drive signal line Gate and the first conductive portion 21. Figure 5 、 Figure 7 、 Figure 9 As shown, the second conductive portion 22 can be distributed around one side and the other two adjacent sides of the first conductive portion 21. It should be understood that the second conductive portion 22 can be distributed around some sides of the first conductive portion 21 from different directions, such as Figure 12 As shown, they are distributed around part of the side of the first conductive portion 21, or as shown Figure 13 As shown, the first conductive portion 21 is only distributed on one side of one side, and the position of the third conductive portion 23 is adjusted accordingly, which all fall within the scope of protection of the present disclosure. Figure 3 、 Figure 4As shown, in this exemplary embodiment, there is an opening 25 between the two sub-conductive parts of the third conductive part 23, the first sub-conductive part 231 and the second sub-conductive part 232 are separated by the opening 25, and the second via connecting the first conductive part 21 and the first connecting part is located in the opening 25. At this time, the opening 25 not only serves to expose part of the structure of the second conductive part 22, but also serves to electrically isolate the first sub-conductive part 231 from the second sub-conductive part 232. Figure 14 is a structural layout diagram of the second conductive layer according to another embodiment of the present disclosure. In some embodiments of the present disclosure, the opening 25 can be as follows Figure 14 As shown, the opening 25 does not separate the first sub-conductive part 231 and the second sub-conductive part 232. The opening 25 only serves to expose part of the structure of the second conductive part 22, so that the second conductive part 22 can be connected to the first connecting part 41 through the first via hole, and then connected to the first conductive part 21. It should be understood that under this structure, the second via hole is insulated from the first sub-conductive part 231 and the second sub-conductive part 232.

[0061] In some embodiments of the present disclosure, Figure 4 As shown, the first sub-conductive portion 231 and the second sub-conductive portion 232 are electrically isolated by the opening 25, and by connecting the first sub-conductive portion 231 in any pixel driving circuit with the second sub-conductive portion 232 in the pixel driving circuit adjacent to the pixel driving circuit in the first direction X, the two sub-conductive portions constituting the second plate of the capacitor in the same pixel driving circuit have the same potential. For example, Figure 15 is a structural diagram of the second conductive layer according to another embodiment of the present disclosure, such as Figure 15 As shown, the first sub-conductive portion 231 of the first pixel driving circuit P1 is connected to the second sub-conductive portion 232 of the pixel driving circuit P0 adjacent to it on the left side in the row direction, and the second sub-conductive portion 232 of the first pixel driving circuit P1 is connected to the first sub-conductive portion of the pixel driving circuit P2 adjacent to it in the row direction. The same arrangement is performed on the third sub-conductive portion in each pixel driving circuit in turn, so that the third conductive portion 23 forms a mesh structure, thereby improving the voltage stability of the third conductive portion 23, reducing the influence of other signals (such as the voltage signal of the data signal line Vdata) on the voltage of the capacitor C, and improving the stability of the voltage of the capacitor C. In this exemplary embodiment, a via hole connected to the first power line Vdd can be provided at the position of the second sub-conductive portion 232 in each pixel driving circuit corresponding to the first power line Vdd, so that the two sub-conductive portions of the third conductive portion 23 in any pixel driving circuit are electrically connected to the first power line Vdd.

[0062] like Figure 4As shown, in an exemplary embodiment of the present disclosure, two sub-conductive portions of the third conductive portion 23 may each be provided with an extension portion for connecting sub-conductive portions in the third conductive portion adjacent in the row direction. Exemplarily, in the same pixel driving circuit, a first extension portion 233 is provided on the side of the first sub-conductive portion 231 away from the second sub-conductive portion 232 along the first direction X, and a second extension portion 234 is provided on the side of the second sub-conductive portion 232 away from the first sub-conductive portion 231. The first extension portion 233 and the second extension portion 234 can extend along the first direction X, so that the second sub-conductive portion 232 of this column is electrically connected to the first extension portion 233 of the first sub-conductive portion 231 in the pixel driving circuit adjacent to the row direction through the second extension portion 234, and the first sub-conductive portion 231 of this column is electrically connected to the second extension portion 234 of the second sub-conductive portion 232 in the pixel driving circuit adjacent to the row direction through the first extension portion 233, thereby realizing the electrical connection between the first sub-conductive portion 231 of any pixel driving circuit and the second sub-conductive portion 232 in the pixel driving circuit adjacent to it in the row direction, so that the third conductive portion 23 forms a mesh structure. Of course, in other exemplary embodiments of the present disclosure, the first sub-conductive portion 231 of the pixel driving circuit of this column can be connected to the second sub-conductive portion 232 of the pixel driving circuit adjacent to the row direction through other structures, such as through via connections through other conductive layers, etc., which all fall within the scope of protection of the present disclosure.

[0063] Figure 16 is a structural diagram of a display panel according to another embodiment of the present disclosure, Figure 17 for Figure 16 The structural layout of the first conductive layer, Figure 18 for Figure 16 The structural layout of the active layer and the first conductive layer, Figure 19 for Figure 16 The structural layout of the second conductive layer, Figure 20 for Figure 16 The structure layout of the active layer, the first conductive layer and the second conductive layer, wherein: Figure 16 The display panel shown has Figure 3 All the features of the active layer and the third conductive layer in the display panel are not described here in detail. Figures 16-20As shown, the orthographic projection of the second conductive part 22 on the substrate is a closed ring, and the orthographic projection of the first conductive part 21 on the substrate is located within the orthographic projection of the second conductive part 22 on the substrate; the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the opening 25 on the third conductive part 23 on the substrate form a closed ring, and the orthographic projection of the first conductive part 21 on the substrate is located within the closed ring formed by the orthographic projection of the third conductive part 23 on the substrate and the orthographic projection of the opening 25 on the third conductive part 23 on the substrate. Among them, the second conductive part 22 is a closed ring and surrounds the first conductive part 21. The second conductive part 22 is located between the gate drive signal line Gate and the enable signal line EM. The third conductive part 23 is arranged opposite to the second conductive part 22. Compared with Figure 3 The display panel structure shown in FIG. 1 increases the plate area of ​​the capacitor C provided by this exemplary embodiment. This structure is beneficial for increasing the capacitance of the capacitor C, thereby improving the voltage stability of the capacitor C during the light-emitting stage. Figure 19 As shown, in this exemplary embodiment, an opening 25 is also provided on the third conductive portion 23 to expose a portion of the structure of the second conductive layer 30. Figure 16 、 Figure 20 As shown, the second via connecting the first connecting portion and the first conductive portion 21 is located within the opening 25 to achieve electrical connection between the first conductive portion 21 and the second conductive portion 22. It will be understood that in this exemplary embodiment, the opening 25 may or may not block the third conductive portion 23. In addition, a via may be provided at a position on the third conductive portion 23 corresponding to the first power line Vdd and connected to the first power line Vdd to achieve electrical connection between the second plate of the capacitor C and the first power line Vdd.

[0064] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the generality of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A display panel, characterized in that: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a capacitor, a first electrode of the capacitor is electrically connected to a gate of the driving transistor, and the display panel further includes: substrate; A first conductive layer is located on one side of the base substrate, and the first conductive layer includes: a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; a second conductive portion, the second conductive portion being used to form a first electrode of the capacitor, the second conductive portion being distributed around at least a portion of a side edge of the orthographic projection of the first conductive portion on the base substrate and being separated from the orthographic projection of the first conductive portion on the base substrate; The second conductive layer is located on a side of the first conductive layer facing away from the base substrate, and the second conductive layer includes: a third conductive portion, the third conductive portion being used to form a second electrode of the capacitor, the orthographic projection of the third conductive portion on the base substrate at least partially overlapping the orthographic projection of the second conductive portion on the base substrate; the second conductive portion being arranged parallel to the third conductive portion; The display panel further includes: A third conductive layer is located on a side of the second conductive layer facing away from the substrate, and the third conductive layer includes: a first connecting portion, the first connecting portion being electrically connected to the second conductive portion through a first via hole and being electrically connected to the first conductive portion through a second via hole; An opening is provided on the third conductive portion, wherein the orthographic projection of the opening on the base substrate is located on the orthographic projection of the second conductive portion on the base substrate, and the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the opening on the base substrate; The orthographic projection of the second conductive portion on the base substrate is a closed ring, and the orthographic projection of the first conductive portion on the base substrate is located within the orthographic projection of the second conductive portion on the base substrate; The orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the opening on the third conductive portion on the base substrate form a closed ring, and the orthographic projection of the first conductive portion on the base substrate is located within the closed ring formed by the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of the opening on the third conductive portion on the base substrate.

2. The display panel according to claim 1, wherein: The display panel includes a plurality of pixel driving circuits, which are arrayed in a first direction and a second direction, wherein the first direction and the second direction intersect; The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the first electrode of the driving transistor, a second electrode is connected to the gate of the driving transistor, and the gate is connected to a gate driving signal line; The first conductive layer further comprises: The orthographic projection of the gate driving signal line on the base substrate extends along a first direction, and the second conductive portion is at least partially located between the gate driving signal line and the first conductive portion.

3. The display panel according to claim 1, wherein: The pixel driving circuit further includes a second transistor, wherein a first electrode of the second transistor is connected to the first electrode of the driving transistor, and a second electrode is connected to the gate of the driving transistor; The display panel further includes: an active layer located between the base substrate and the first conductive layer, the active layer including a second active portion, the second active portion including a first sub-active portion, a second sub-active portion, and a third sub-active portion, the first sub-active portion and the second sub-active portion being used to form a channel region of the second transistor, and the third sub-active portion being connected between the first sub-active portion and the second sub-active portion; The second conductive layer further includes a fourth conductive portion connected to a stable voltage source. The fourth conductive portion includes a third sub-conductive portion. The orthographic projection of the third sub-conductive portion on the base substrate at least partially overlaps with the third sub-active portion.

4. The display panel according to claim 3, wherein: The pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to the gate of the driving transistor, and a second electrode of the first transistor is connected to the first initial signal line; The display panel further includes: an active layer located between the base substrate and the first conductive layer, the active layer including a first active portion and an eighth active portion, the first active portion including a fourth sub-active portion and a fifth sub-active portion, the fourth sub-active portion and the fifth sub-active portion being used to form a channel region of the first transistor, the eighth active portion being connected between the second sub-active portion and the fifth sub-active portion, and the eighth active portion being connected to the first connecting portion through a via; The second conductive layer also includes a fourth conductive portion, the fourth conductive portion is connected to a stable voltage source, the fourth conductive portion includes a fourth sub-conductive portion, and the orthographic projection of the fourth sub-conductive portion on the base substrate at least partially overlaps with the orthographic projection of the eighth active portion on the base substrate.

5. The display panel according to claim 4, wherein: The display panel includes a plurality of pixel driving circuits, which are arrayed in a first direction and a second direction, wherein the first direction and the second direction intersect; The pixel driving circuit further includes a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data signal line, and a second electrode of the fourth transistor is connected to the second electrode of the driving transistor; The fourth conductive portion further includes: A fifth sub-conductive portion is connected to the fourth sub-conductive portion, and the orthographic projection of the fifth sub-conductive portion on the base substrate extends along the second direction. In the same pixel driving circuit, the orthographic projection of the fifth sub-conductive portion on the base substrate is located between the orthographic projection of the eighth active portion on the base substrate and the orthographic projection of the data signal line on the base substrate.

6. The display panel according to claim 1, wherein: The pixel driving circuit further includes a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is connected to the data signal line, a second electrode is connected to the second electrode of the driving transistor, and a gate is connected to the gate driving signal line; a first electrode of the fifth transistor is connected to the second electrode of the driving transistor, a second electrode is connected to the first power line, and a gate is connected to the enable signal line; The display panel further includes: an active layer located between the base substrate and the first conductive layer, the active layer comprising a fourth active portion and a fifth active portion, the fourth active portion being used to form a channel region of the fourth transistor, and the fifth active portion being used to form a channel region of the fifth transistor; The first conductive layer further comprises: The orthographic projection of the gate drive signal line on the base substrate extends along a first direction, the orthographic projection of the gate drive signal line on the base substrate partially covers the orthographic projection of the fourth active portion on the base substrate, and a portion of the gate drive signal line forms the gate of the fourth transistor; The enable signal line extends along the first direction when projected onto the base substrate, and partially covers the fifth active portion when projected onto the base substrate, and a portion of the structure of the enable signal line forms the gate of the fifth transistor; The orthographic projection of the second conductive portion on the base substrate is located between the orthographic projection of the gate driving signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

7. The display panel according to claim 2 or 5, characterized in that: The third conductive layer further includes: A data signal line, an orthographic projection of the base substrate extending along the second direction; a first power line, wherein an orthographic projection of the first power line on the base substrate extends along the second direction, and the first power line is connected to the third conductive portion through a via hole; The orthographic projection of the first power line on the base substrate is located between the orthographic projection of the first connection portion on the base substrate and the orthographic projection of the data signal line on the base substrate.

8. The display panel according to claim 1, wherein: The display panel includes a plurality of pixel driving circuits, which are arrayed in a first direction and a second direction, wherein the first direction and the second direction intersect; The pixel driving circuit further includes a fourth transistor, a fifth transistor, and a sixth transistor, wherein a first electrode of the fourth transistor is connected to the data signal line, and a second electrode is connected to the second electrode of the driving transistor; a first electrode of the fifth transistor is connected to the second electrode of the driving transistor, and a second electrode is connected to the first power line; A first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode is connected to the light emitting unit; The display panel further includes: an active layer, comprising a fourth active portion, a fifth active portion, and a sixth active portion, the fourth active portion being used to form a channel region of the fourth transistor, the fifth active portion being used to form a channel region of the fifth transistor, and the sixth active portion being used to form a channel region of the sixth transistor; The first conductive layer further comprises: an enable signal line, the orthographic projection of which on the base substrate extends along the first direction and partially covers the orthographic projection of the fifth active portion on the base substrate and partially covers the orthographic projection of the sixth active portion on the base substrate, wherein a portion of the structure of the enable signal line is used to form the gate of the fifth transistor, and a portion of the structure of the enable signal line is used to form the gate of the sixth transistor; a gate drive signal line, an orthographic projection of which on the base substrate extends along the first direction and partially covers the orthographic projection of the fourth active portion on the base substrate, wherein a portion of the gate drive signal line is used to form a gate of the fourth transistor; The first conductive portion is located between the gate driving signal line and the enable signal line.

9. The display panel according to claim 8, wherein: The pixel driving circuit further includes a seventh transistor, wherein a first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and a second electrode of the seventh transistor is connected to the second initial signal line; The active layer further includes: a seventh active portion, configured to form a channel region of the seventh transistor; The first conductive layer further includes: a reset signal line, the orthographic projection of which on the base substrate extends along the first direction, the orthographic projection of which on the base substrate is located on a side of the orthographic projection of which the enable signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate; The second conductive layer also includes: a second initial signal line, the orthographic projection of which on the base substrate extends along the first direction, and the orthographic projection of which on the base substrate is located between the orthographic projection of the reset signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

10. The display panel according to claim 9, wherein: The pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to the gate of the driving transistor, and a second electrode of the first transistor is connected to the first initial signal line; The active layer further includes a first active portion, the first active portion including a fourth sub-active portion, a fifth sub-active portion, and a sixth sub-active portion, the fourth sub-active portion and the fifth sub-active portion being used to form a channel region of the first transistor, and the sixth sub-active portion being connected between the fourth sub-active portion and the fifth sub-active portion; The display panel further includes: The orthographic projection of the first initial signal line on the base substrate extends along the first direction, and the orthographic projection of the first initial signal line on the base substrate at least partially overlaps with the orthographic projection of the sixth sub-active portion on the base substrate.

11. The display panel according to claim 10, wherein: The first direction is the row direction, and the second direction is the column direction; wherein, The orthographic projection of the reset signal line in the previous row on the substrate covers the orthographic projection of the fourth sub-active portion and the orthographic projection of the fifth sub-active portion in the current row on the substrate, a portion of the structure of the reset signal line in the previous row is used to form the gate of the first transistor in the current row, and the orthographic projection of the reset signal line in the previous row on the substrate is located on a side of the orthographic projection of the gate drive signal line in the current row on the substrate away from the orthographic projection of the first conductive portion in the current row on the substrate; The orthographic projection of the second initial signal line in this row on the base substrate is located on a side of the orthographic projection of the gate drive signal line in this row on the base substrate away from the orthographic projection of the reset signal line in the previous row on the base substrate.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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