Device for power conversion and method for converting a first voltage into a second voltage

Abstract

The present invention provides an apparatus for power conversion and a method for converting a first voltage to a second voltage. The apparatus includes a precharge circuit, a switch, and a gate driver circuit. The switch includes an active semiconductor switching element and is configured to transition between a first state and a second state. The first state and the second state result in corresponding first and second electrical interconnections between a capacitor and at least one of a first terminal and a second terminal. The first terminal is coupled to a first external circuit at a first voltage, and the second terminal is coupled to a second voltage. Each gate driver circuit includes a control input, a power connection, and a drive output. Each switch is coupled to and controlled by the drive output of one of the gate driver circuits. The gate driver circuit includes a first gate driver circuit, and the first gate driver circuit receives power from at least one of the capacitors through its power connection.

Description

[0001] This application is a divisional application of a patent application (first-generation divisional application) filed on August 13, 2019, with application number 201910745987.2 and invention title "Device for Power Conversion and Method for Converting a First Voltage to a Second Voltage". The above-mentioned patent application (first-generation divisional application) is a divisional application of an invention patent application filed on March 11, 2014, with application number "201480028501.9" and invention title "High-Efficiency Gate Driver for a Switched Capacitor Converter" (which is an application after the PCT application with international application number PCT / US2014 / 023025 enters the Chinese national phase).

[0002] Cross-Reference to Related Applications

[0003] This application claims the benefit of the priority date of U.S. Application No. 13 / 837,796, filed on March 15, 2013, the content of which is hereby incorporated by reference in its entirety. Technical Field

[0004] The present invention relates to switched capacitor converters, and more particularly to high-efficiency gate drivers for such converters. Background Art

[0005] A switching mode power converter is a particular type of power converter that produces an output voltage by switching energy storage elements (i.e., inductors and capacitors) to different electrical configurations using a switching network. A switched capacitor converter is a class of switching mode power converters that primarily utilizes capacitors to transfer energy. In such converters, the number of capacitors and switches increases as the conversion gain increases.

[0006] As used herein, if a switched capacitor power converter produces an output voltage greater than the input voltage, then the conversion gain represents a voltage gain, or if a switched capacitor power converter produces an output voltage less than the input voltage, then the conversion gain represents a current gain.

[0007] FIG. 1 and FIG. 2 illustrate two examples of switched capacitor power converters that receive an input voltage VI from a voltage source 16 and provide an output voltage VO to a load 18. These two examples are also referred to as cascade multipliers. Note that in FIG. 2, a plurality of switch devices in the circuit of FIG. 1 are replaced by a series of multiple devices, thereby reducing the maximum voltage across the individual devices in the circuit.

[0008] During normal operation, charge packets are pumped along the link of diode-connected NMOS transistors M0 - M5 while the pump capacitors C1 - C3 are being continuously charged and discharged. As shown in FIGS. 1 and 2, the phase voltages VP1, VP2 are 180 degrees out of phase. Each of the NMOS transistors M0 - M5 is diode-connected, thus only allowing boost operation (i.e., VO greater than VI). Additionally, the efficiency is severely affected because the voltage across each of the transistors M0 - M5 is significantly reduced during normal operation. Therefore, it is desirable to operate the NMOS transistors M0 - M5 in their ohmic region, but due to the difficulty and / or complexity of driving the transistors M0 - M5, typically a combination of both PMOS transistors and high-voltage transistors is used.

[0009] If the transistors in a switched-capacitor power converter are integrated on a single substrate, it is desirable to use as few different types of devices as possible. For a given semiconductor process, the cost is related to the number of mask layers. As the number of different types of devices in a semiconductor process increases, the number of mask layers also increases, and thus the cost increases.

[0010] Furthermore, it is well known that electrons have a higher mobility than holes in silicon. As a result, an NMOS device with a given on-resistance has a smaller gate capacitance than a PMOS device with the same on-resistance. It is also true that an NMOS device with a given gate capacitance has a smaller on-resistance than a PMOS device with the same gate capacitance. In a power converter, therefore, it is desirable to replace as many PMOS devices as possible in the main power path with NMOS devices and replace as many high-voltage devices as possible with low-voltage devices. SUMMARY OF THE INVENTION

[0011] According to a first aspect of the present invention, there is provided a device for power conversion, the device comprising a pre-charge circuit, a switch and a gate driver circuit, wherein the switch comprises an active semiconductor switching element, wherein the switch is configured to transition between a first state and a second state, the first state and the second state resulting in respective first and second electrical interconnections between a capacitor and at least one of a first terminal and a second terminal, wherein the first terminal is configured to be coupled to a first external circuit at a first voltage, wherein the second terminal is configured to be coupled to a second voltage, the magnitude of the second voltage being less than the magnitude of the first voltage, wherein the pre-charge circuit is coupled to at least one of the capacitors, wherein each gate driver circuit comprises a control input, a power connection and a drive output, wherein each switch is coupled to and controlled by the drive output of one of the gate driver circuits, wherein the gate driver circuit comprises a first gate driver circuit, and wherein the first gate driver circuit receives power from at least one of the capacitors via its power connection.

[0012] According to a second aspect of the present invention, there is provided a method for converting a first voltage to a second voltage, the method comprising: connecting a first terminal of a switched capacitor power converter to a first external circuit; connecting a second terminal of the switched capacitor power converter to a second external circuit; pre-charging a capacitor within the switched capacitor power converter; providing a first control signal to a control input of a gate driver circuit of the power converter; providing a second control signal to the control input of the gate driver circuit, wherein the switched capacitor power converter includes a switched capacitor network in which capacitors are selectively interconnected by active semiconductor switches; connecting the second terminal of the switched capacitor power converter to the second external circuit; causing the capacitors in the switched capacitor network to provide power to the gate driver circuit through a power connection of the gate driver circuit; and causing there to be a voltage across the power connection of the gate driver circuit, wherein the voltage across the power connection of the gate driver circuit that exists is less than the greater of the first voltage and the second voltage, wherein pre-charging the capacitor within the switched capacitor power converter includes: pre-charging the capacitor before starting normal operation of the switched capacitor power converter, wherein the first control signal causes a first drive signal at a corresponding drive output of the gate driver circuit, wherein the first drive signal causes the active semiconductor switches to perform a first switch activation mode, wherein the second control signal causes a second drive signal at the corresponding drive output of the gate driver circuit, wherein the second drive signal causes the active semiconductor switches to perform a second switch activation mode, and wherein, in the first switch activation mode, a first series of active semiconductor switches connects a first capacitor and a second capacitor in the switched capacitor network of the power converter to allow conduction current to flow between high voltage terminals of the first capacitor and the second capacitor.

[0013] According to a third aspect of the present invention, there is provided an apparatus, the apparatus comprising a circuit and a controller for operating the circuit, wherein the circuit is a dual-phase series-parallel switched capacitor circuit configured to be connected between a source and a load, wherein the circuit comprises a first charge transfer path and a second charge transfer path, a gate driver along the first charge transfer path, a first capacitor bank and a second capacitor bank, and a first transistor bank and a second transistor bank, wherein the first capacitor bank and the first transistor bank define a first phase, wherein the second capacitor bank and the second transistor bank define a second phase, wherein the capacitor bank supplies power to the gate driver, wherein the capacitor bank comprises capacitors connected in series on one of the first charge transfer path and the second charge transfer path, wherein the controller causes the circuit to transition between a first state and a second state at a specific frequency, wherein, in the first state, the first capacitor bank is in parallel with the load, and the second capacitor bank is in series between the source and the load, and wherein, in the second state, the second capacitor bank is in parallel with the load, and the first capacitor bank is in series between the source and the load, such that the gate driver obtains power from the capacitors in both phases.

[0014] According to a fourth aspect of the present invention, there is provided a method, comprising: connecting a dual-phase switched capacitor circuit between a source and a load, and causing the circuit to transfer charge from the source to the load, wherein causing the circuit to transfer charge comprises: during a first stage, causing charge to transfer from the source to the load along a first charge transfer path; and during a second stage, causing charge to transfer from the source to the load along a second charge transfer path, wherein causing charge to transfer from the source to the load along the first charge transfer path comprises: applying a voltage to the gate of a first transistor that controls the flow of charge between a first capacitor and a second capacitor, the first capacitor and the second capacitor storing charge when the charge passes through the first charge transfer path, and wherein applying the voltage to the gate comprises connecting the gate to a third capacitor, wherein the third capacitor is a capacitor that stores charge passing through the second charge transfer path.

[0015] According to a fifth aspect of the present invention, there is provided an apparatus including a circuit and a controller for operating the circuit, wherein the circuit is a bi-phase series-parallel switched capacitor circuit configured to be connected between a source and a load, wherein the circuit includes a gate driver, a first capacitor bank and a second capacitor bank, and a first transistor bank and a second transistor bank, wherein the capacitors from the first capacitor bank and the transistors from the first transistor bank define a first phase, wherein the capacitors from the second capacitor bank and the transistors from the second transistor bank define a second phase, wherein the capacitor bank powers the gate driver, wherein the capacitor bank is from one of the first capacitor bank and the second capacitor bank, wherein the controller causes the circuit to transition between a first state and a second state at a specific frequency, wherein, in the first state, the capacitors from the first capacitor bank are in parallel with the load, and the capacitors from the second capacitor bank are in series between the source and the load, and wherein, in the second state, the capacitors from the second capacitor bank are in parallel with the load, and the capacitors from the first capacitor bank are in series between the source and the load, and wherein the gate driver obtains power from the capacitors in the capacitor bank of the two phases.

[0016] According to a sixth aspect of the present invention, there is provided an apparatus including a first plurality of switches, a second plurality of switches, a controller for controlling the first plurality of switches and the second plurality of switches, a gate driver for driving the switches in the first plurality of switches, and a first terminal and a second terminal configured to be coupled to a corresponding first external circuit and a second external circuit at corresponding first and second voltages, respectively, wherein, during operation, the controller causes the first plurality of switches to transition between consecutive states, each state being characterized by a switch activation pattern defining which switches will be open and which switches will be closed during the state, the transition causing the second voltage to be maintained at a value that is a multiple of the first voltage, the controller causes the second plurality of switches to transition between consecutive states, each state being characterized by a switch activation pattern defining which switches will be open and which switches will be closed during the state, the transition causing a capacitor to be coupled or decoupled from the second voltage, and the gate driver obtaining charge from the capacitor to generate a voltage enabling the driving of the switches in the first plurality of switches.

[0017] According to a seventh aspect of the present invention, there is provided an apparatus comprising a first switch group, a controller for controlling switches in the first switch group, a gate drive circuit for driving the gates of the switches, a first terminal and a second terminal, and a node for coupling the gate drive circuit to a power supply, the first and second terminals being configured to be coupled to a first external circuit and a second external circuit at respective first and second voltages, wherein the power supply includes a capacitor that is part of a switched capacitor network coupled to the switches, wherein during operation, the controller causes the switches in the first switch group to transition between successive states, each state being characterized by a switch activation pattern that defines which switches are to be open and which switches are to be closed during that state, the transition causing the second voltage to be maintained at a value that is a multiple of the first voltage, and wherein the node couples the gate drive circuit to the capacitor.

[0018] According to an eighth aspect of the present invention, there is provided an apparatus comprising: a first switch group; a controller for controlling switches in the first switch group; a gate drive circuit for driving the switches; a first terminal and a second terminal configured to be coupled to a first terminal and a second terminal of a switched capacitor network that transforms a first voltage into a second voltage to provide power to a load, wherein during operation, the controller causes the switches in the first switch group to transition between successive states, each state being characterized by a switch activation pattern that defines which switches are to be open and which switches are to be closed during that state, the transition causing the second voltage to be maintained at a value that is a multiple of the first voltage and causing charge to be transferred from the first terminal to the load, the apparatus further comprising means for diverting charge that is transferred from the switched capacitor network to the load so as to reduce the efficiency of power transfer to the load.

[0019] In one aspect, in general, a switched-capacitor power converter has: a first terminal for coupling to a first external circuit at a substantially high voltage (e.g., 20V); and a second terminal for coupling to a second external circuit at a substantially low voltage (e.g., 5V) that is lower in magnitude than the high voltage. A first plurality of active semiconductor switching elements are configured to electrically interconnect capacitors to each other and / or to the first or second terminal in a continuous state. The switching elements are configured to interconnect at least some of the capacitors to each other through a series of a plurality of switching elements. The plurality of switching elements are coupled to and for controlling by a drive output of one of the switching drive circuits. Each drive circuit has a control input, a power connection, and a drive output that is coupled to and for controlling one or more of the switching elements. At least some of the switching drive circuits are configured to be powered from one or more of the capacitors via the power connection of the drive circuit such that the voltage across the power connection of the drive circuit is substantially less than the high voltage.

[0020] In another aspect, in general, a switched-capacitor power converter has: a first terminal for coupling to a first external circuit at a substantially high voltage; and a second terminal for coupling to a second external circuit at a substantially low voltage that is lower in magnitude than the high voltage. A plurality of active semiconductor switching elements are configured to electrically interconnect capacitors to each other and to the first or second terminal in a continuous state. The switching elements and capacitors are configured to form multiple separate charge transfer paths between the first and second terminals. A plurality of switching drive circuits are coupled to and for controlling by a drive output of one of the switching drive circuits, each drive circuit having a control input, a power connection, and a drive output that is coupled to and for controlling one or more of the switching elements. At least some of the switching drive circuits are configured to be powered from one or more of the capacitors via the power connection of the drive circuit such that the voltage across the power connection of the drive circuit is substantially less than the high voltage. At least some of the switching drive circuits that control the switching elements in one of the separate charge transfer paths are powered from the capacitors of one or more other charge transfer paths.

[0021] Each aspect may include one or more of the following features.

[0022] The switched-capacitor power converter further includes a plurality of capacitors that are coupled to the first plurality of switching elements and controllably coupled through the semiconductor switches, or includes a plurality of terminals that are coupled to the first plurality of switching elements for connection to the capacitors.

[0023] The converter is configured to provide a time-varying voltage relative to the low voltage to at least some of the drive circuits.

[0024] Each switching element has a maximum rated voltage that is lower than the high voltage.

[0025] Each of a series of switching elements includes N elements, where N > 1, and where the maximum rated voltage of the switching element is not greater than 2 / N times the low voltage.

[0026] The voltage across the power connection of the drive circuit is configured to be driven from a capacitor at less than or substantially equal to twice the low voltage.

[0027] Each switching element in a series of a plurality of switching elements is driven by a corresponding drive circuit, each of the drive circuits being configured to be powered from a different one of the plurality of capacitors having different voltages in operation via the power connection of the drive circuit.

[0028] The switching element and the capacitor are configured to form multiple separate charge transfer paths between a first terminal and a second terminal, and where at least some of the switching drive circuits of the switching elements that control one of the separate charge transfer paths are powered from the capacitors of one or more other charge transfer paths.

[0029] The switched-capacitor power converter further includes a phase-shift generator that includes a second plurality of switching elements. The phase-shift generator is configured to provide a time-varying voltage level to one terminal of each of the plurality of capacitors, and is configured to generate the voltage level for at least one of the capacitors in one charge transfer path using the voltage from the capacitors in other charge transfer paths.

[0030] Advantages of one or more aspects can include the following.

[0031] By reducing the losses in the gate drive signals that repeatedly charge and discharge the gates of the transistors in the switched-capacitor power converter, the overall efficiency of the converter is improved.

[0032] By limiting the gate-source voltage, low-voltage transistors can be used.

[0033] By driving different transistors in a cascade series with different voltages, the cascade configuration can be driven efficiently.

[0034] In the case of a converter that utilizes external (e.g., discrete) capacitors, using these same capacitors to power the internal gate driver circuit eliminates the need to provide additional intermediate power terminals to the device.

[0035] Integrated circuits are typically limited by the number of pins they are allowed to have. Each pin occupies a certain amount of area on the silicon die, and if the pin count is large, the area occupied by the pins can be greater than the area occupied by the active devices on the silicon die. Each capacitor will require at least one pin, and in some cases, two pins. Powering the gate driver using the available voltage on the capacitors used in the charge transfer path is preferable to providing these voltages through additional pins on the device, as the total pin count does not have to be increased.

[0036] Other features and advantages of the present invention will be apparent from the following description and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG. 1 is a schematic diagram of a single-phase boost cascade multiplier;

[0038] FIG. 2 is a schematic diagram of a single-phase boost cascade multiplier with a cascade switcher;

[0039] Figure 3 is a schematic diagram of a single-phase cascade multiplier with a cascade switcher and a corresponding gate driver and precharge circuit;

[0040] Figure 4 and Figure 5 are respectively annotated schematic diagrams of the Figure 3 circuit in two operating phases;

[0041] Figure 6 is a schematic diagram of a ramp gate driver;

[0042] Figure 7 is a schematic diagram of a cascade gate driver;

[0043] Figure 8 is a schematic diagram of a two-phase cascade multiplier with a cascade switcher and a corresponding gate driver;

[0044] Figure 9 is an annotated schematic diagram of the Figure 8 circuit in one of two operating phases;

[0045] Figure 10 is a schematic diagram of a two-phase cascade multiplier and a corresponding gate driver;

[0046] Figure 11 and Figure 12 are schematic diagrams of two optional phase shift generators for use in conjunction with the Figure 10 circuit; and

[0047] Figure 13 is a schematic diagram of a two-phase series-parallel switched capacitor converter and a corresponding gate driver. DETAILED DESCRIPTION

[0048] 1. Overview

[0049] The following describes various methods used in the context of active control of a switched-capacitor power converter. These methods address one or more of the following objectives:

[0050] · Improve the efficiency of the converter by reducing the charge deposited and discharged from the gates of the control transistors

[0051] · Allow the use of low-voltage transistors for switching.

[0052] In general, the methods for achieving these objectives are: by designing and powering the circuitry that drives the switching transistors during operation, to efficiently limit the gate-source voltage. A variety of specific methods (some of which are described below) use control circuitry for the switching transistors, which are coupled to capacitors in a charge transfer path, and are themselves powered by capacitors in the same path, and / or, in the case of a multiphase converter, by capacitors in additional parallel paths.

[0053] 2. Single-phase Cascade Multiplier

[0054] Referring Figure 3 , the single-phase cascade multiplier circuit 30 utilizes transistors M0-M5, which are coupled to first, second, and third pumping capacitors C1-C3 on a charge transfer path between a high-voltage terminal (i.e., VO) and a low-voltage terminal (i.e., VI). In the Figure 3 illustrated embodiment, the pumping capacitors C1-C3 are coupled by a cascade transistor switch (e.g., M1 and M2 in series), but it should be understood that a single transistor may also be used while still achieving at least some of the advantages of the illustrated configuration.

[0055] Each transistor is driven by a corresponding gate driver circuit. As described in more detail below, at least some of the gate drive circuits are powered from the pumping capacitors C1-C3 in the charge transfer path between the high-voltage and low-voltage terminals. The voltage across each of the pumping capacitors C1-C3 is a fraction of that high voltage, thereby allowing for the efficient generation of gate drive signals that maintain the desired limitation of the gate-source voltage of the transistors.

[0056] The driver group 32 provides gate signals to activate or deactivate each transistor in the cascade multiplier circuit 30. The driver group 32 includes four low-voltage gate driver circuits 34, two high-voltage gate driver circuits 35, and four voltage followers 36A - 36D. Each gate driver circuit receives a drive signal with a label starting with "A" or "B". The drive signals A0, B0, B1, A1, A2, B2 control transistors M0, M1, M2, M3, M4, M5 respectively. In addition, the voltage followers 36A - 36D receive corresponding bias voltages V1 - V4 respectively. The control circuit (not shown in Figure 3 is shown) generates the drive signals A0 - B2 and the bias voltages V1 - V4.

[0057] The low-voltage gate driver circuits 34 are coupled to transistors M0, M2, M4, M5, while the high-voltage gate driver circuits 35 are coupled to transistors M1, M3. The high-voltage gate driver circuits 35 support twice the supply voltage of the low-voltage gate driver circuits 34. Each of the voltage followers 36A - 36D receives the voltage from one of the pump capacitors C1 - C3 and provides a constant voltage equal to or lower in value to their corresponding gate driver circuits (i.e., 34 or 35). When the received voltage is equal to the provided voltage, the corresponding voltage follower (e.g., 36A) behaves similarly to a switch. To achieve this behavior, the bias voltages V1 - V3 are at least the threshold voltage higher than the corresponding source voltage, while the bias voltage V4 is at least the threshold voltage lower than the corresponding source voltage. In addition, the voltage followers 36A - 36D are subject to the same voltage stress as the transistors M0 - M5 in the cascade multiplier circuit 30.

[0058] Similarly, an example of a precharge circuit 38 is illustrated in Figure 3 which is used to initialize the voltages on the pump capacitors C1 - C3 before the clocked operation of the cascade multiplier circuit 30. By precharging the pump capacitors C1 - C3, the drain-source voltages across the transistors M0 - M5 within the cascade multiplier circuit 30 can be maintained within the required limits during startup, and in addition, the precharged pump capacitors C1 - C3 can immediately supply the required power to the gate driver circuits at the start of the clocked operation of the cascade multiplier circuit 30. The precharge circuit 38 can be disabled during the clocked operation

[0059] To facilitate the use of low-voltage transistors throughout the power converter, the precharge circuit 38 uses a combination of low-voltage transistors and bias resistors. A resistive voltage divider sets the precharge voltage for each of the pump capacitors C1 - C3 during startup, where the source voltage of each transistor within the precharge circuit 38 is at least the threshold voltage lower than its corresponding gate voltage. As a result, none of the transistors within the precharge circuit 38 or the cascaded multiplier circuit 30 are exposed to voltage stress that can damage the device during startup or clocked operation.

[0060] Referring to Figures 4 to 5 which shows two operating states, the operation of the cascaded multiplier circuit 30 and the resulting voltage levels supplied to the gate drive circuit can be understood. The cascaded multiplier circuit 30 transfers energy from the source 16 to the load 18 by cycling between a first state and a second state at a specific frequency. All transistors coupled to the "A" signal are simultaneously activated and deactivated; the same is true for all transistors coupled to the "B" signal. To ensure a clean transition between the first state and the second state, the "A" signal and the "B" signal are non-overlapping. Additionally, the first-phase voltage and the second-phase voltage VP1, VP2 are synchronized with the "A" signal and the "B" signal.

[0061] Assuming the input voltage VI is five volts, the cascaded multiplier circuit 30 produces an output voltage VO of twenty volts. The maximum voltage across any transistor is five volts. Additionally, the low-voltage gate drive circuit 34 supports five volts, while the high-voltage gate drive circuit 35 must support ten volts.

[0062] Figure 4 Figure shows the first state, where the first-phase voltage VP1 is five volts and the second-phase voltage VP2 is zero volts. The gate drive circuits receiving the "B" signal activate their corresponding transistors, and the gate drive circuits receiving the "A" signal deactivate their corresponding transistors. As a result, gate voltages of fifteen volts activate transistors M1, M2, M5 respectively, while gate voltages of five volts, ten volts, and fifteen volts deactivate transistors M0, M3, M4 respectively.

[0063] Conversely, Figure 5 Figure shows the second state, where the first-phase voltage VP1 is zero volts and the second-phase voltage VP2 is five volts. The gate drive circuits receiving the "A" signal activate their corresponding transistors, and the gate drive circuits receiving the "B" signal deactivate their corresponding transistors. As a result, gate voltages of five volts, ten volts, and twenty volts deactivate transistors M1, M2, M5 respectively, while gate voltages of ten volts, twenty volts, and twenty volts activate transistors M0, M3, M4 respectively.

[0064] Unfortunately, the voltage followers 36A - 36D associated with transistors M0, M1, M2, M5 consume power. Each voltage follower drops five volts across its drain and source terminals, while its corresponding gate driver sinks or sources current. In the case of transistors M1, M2, M5, this occurs during the first state, and for transistor M0, this occurs during the second state.

[0065] In the cascaded multiplier circuit 30, charge is transferred from the source 16 to the load 18 at a rate determined by the load 18. Since this is a single - phase design, there is only one charge - transfer path that a single unit of charge can follow. For example, at the start of the first clock cycle, the unit charge leaves the source 16 and flows into the first pump capacitor C1. After a state transition, the unit charge moves to the second pump capacitor C2. When the second clock cycle starts, the unit charge then moves from the second pump capacitor C2 to the third pump capacitor C3, and after another state transition, the unit charge finally reaches the load 18. It takes two complete clock cycles (i.e., four consecutive states) for the initial charge to reach the load 18 from the source 16.

[0066] Normally, as the conversion gain of the cascaded multiplier increases, the number of pump capacitors also increases. As a result, it takes longer for a unit charge to reach the load 18 from the source 16 because the unit charge needs to travel back and forth between more pump capacitors. The number of clock cycles in the charge - transfer path is M - 2, where M is equal to the conversion gain. In this example, M is equal to four; thus, the number of clock cycles is two.

[0067] Figures 6 to 7 Two alternative designs of the gate - drive circuit are illustrated. Both of these alternative designs can be used for the high - voltage gate - driver circuit 35 and the low - voltage gate - driver circuit 34. However, as will be clear in the following description, the gate driver in Figure 6 is more suitable for the low - voltage gate driver 34, while the gate driver in Figure 7 is more suitable for the high - voltage gate driver 35.

[0068] As Figure 6 shown, the tapered gate driver is characterized by an input terminal IN, an output terminal OUT, and power terminals VDD, VSS. The input terminal IN is coupled to the output terminal OUT through a first inverter, a second inverter, a third inverter, and a fourth inverter (in that order). These four inverters include high - side PMOS transistors MP1 - MP4 and low - side NMOS transistors MN1 - MN4. Due to the difference in electron and hole mobilities, each of the PMOS transistors MP1 - MP4 is typically designed to be larger than their corresponding NMOS transistors MN1 - MN4.

[0069] Starting from the input terminal IN, each subsequent inverter is k times larger than the previous one. For example, if k equals 5 and the width of the first inverter is one micron, then the widths of the second, third, and fourth inverters are five microns, twenty-five microns, and one hundred and twenty-five microns, respectively. By varying the inverters, a small logic gate coupled to the input terminal IN can drive a high-power transistor coupled to the output terminal OUT.

[0070] The maximum supply voltage of the varying gate driver is equal to or less than the breakdown voltage of the transistor. Therefore, the varying gate driver is a good choice for the low-voltage gate driver circuit 34 in the cascaded multiplier circuit 30. Unfortunately, due to Figures 3 to 5 the higher voltage requirements of the high-voltage gate driver circuit 35 in

[0071] An alternative method to increase the supply voltage without the need for higher-voltage transistors is to use a cascaded gate driver. As Figure 7 shown, the cascaded gate driver includes an input terminal IN, an output terminal OUT, and power terminals VDD, VSS. The cascaded gate driver is characterized by an output stage that includes a first high-side transistor and a second high-side transistor MP5, MP6, and a first low-side transistor and a second low-side transistor MN5, MN6. The output stage requires additional support circuitry, such as, level shifters, two gate drivers, delay blocks, and voltage regulators, all of which can be designed using transistors having the same breakdown voltage as the transistors in the output stage.

[0072] During normal operation of the cascaded gate driver, the high-side transistors MP5, MP6 are activated when the low-side transistors MN5, MN6 are deactivated, and vice versa. Therefore, the cascaded gate driver can support twice the supply voltage because the differential voltage across the power terminals VDD, VSS is always supported by two deactivated transistors. In general, a larger number of transistors can be cascaded to further increase the supply voltage. For example, if the output stage includes three high-side transistors and three low-side transistors, then the maximum supply voltage will be three times, and so on. Unfortunately, as the number of cascaded transistors increases, the complexity of the support circuitry also increases.

[0073] 3. Biphase Cascade Multiplier

[0074] In general, a single-phase cascaded multiplier can be converted into a multi-phase cascaded multiplier characterized by multiple charge transfer paths that are time-shifted. As Figure 8As shown, the bipolar cascaded multiplier circuit 40 can be formed by placing two copies of the single-phase cascaded multiplier circuit 30 in parallel. Each copy is referred to as a phase (to avoid confusion with states), and thus, the cascaded multiplier circuit 30 is characterized by a first phase and a second phase. The first phase includes capacitors C1A - C3A, transistors M0A - M5A, and phase voltages VP1, VP2, while the second phase includes capacitors C1B - C3B, transistors M0B - M5B, and phase voltages VP3, VP4. Each of the transistors M0A - M5A has a corresponding gate driver circuit 34 that receives drive signals with labels starting with "A" or "B". The first phase includes drive signals A0a - B2a, while the second phase includes drive signals A0b - B2b.

[0075] The control signals of the first phase and the second phase are shifted by one hundred and eighty degrees. This can be achieved by swapping the "A" and "B" signals in one of the two phases and then inverting the corresponding phase voltages. For example, in normal operation, when phase voltages VP2, VP4 are low, phase voltages VP1, VP3 are high, and vice versa. Additionally, the voltage followers in the first phase receive bias voltages V1a - V4a, while the voltage followers in the second phase receive bias voltages V1b - V4b. As in the single-phase embodiment above, the control circuit (not shown Figure 8 in the figure) can generate drive signals A0a - B2b and bias voltages V1a - V4b.

[0076] In addition, by swapping the positions of the source 16 and the load 18, a buck power converter can be converted into a boost converter, and vice versa. Thus, the cascaded multiplier circuit 40 is a buck power converter, rather than Figure 3 the boost power converter in the figure.

[0077] The bipolar structure has several advantages compared to the single-phase structure. The most obvious advantage is that there is always a charge transfer path between the source 1 and the load 18, regardless of the operating state (the first or the second). A less obvious advantage is that one phase can extract energy from the other phase to the power circuitry, and vice versa. Additionally, this technique allows the cascaded multiplier circuit 40 to use only low-voltage gate driver circuits 34.

[0078] Since the bipolar converter is essentially two single-phase converters operating in parallel, the cascaded multiplier circuit 40 operates as described with reference to Figures 3 - 5 the figure. Assuming the input voltage VI is twenty volts, referring to the figure that shows one operating state, the resulting voltage levels for powering the gate drive circuits can be understood. Another operating state is not shown because it is simply the mirror image of the state shown in Figure 9 the figure. Figure 9 the figure.

[0079] In the cascaded multiplier circuit 40, transistors M0A - M3B derive power from opposite phases, while transistors M4A - M5B derive power from the input voltage VI. Powering the gate driver from parallel charge transfer paths (i.e., opposite phases) results in one less voltage follower per phase, and this voltage follower does not consume power. This is because transistors M0A, M2A, M5A, M0B, M2B, M5B are deactivated while the corresponding voltage followers across them are being turned down. Due to the more efficient voltage followers and the lack of a high - voltage gate driver circuit 35, in a two - phase design, the energy required to drive the gates is less than in a single - phase design.

[0080] As in Figure 3 the single - phase structure of, the initial charge entering the cascaded multiplier circuit 40 takes two full clock cycles to reach the load 18. However, in the two - phase structure, there are two charge transfer paths between the source 16 and the load 18, rather than just one as in the single - phase structure. Additionally, these two separate charge transfer paths are time - shifted relative to each other.

[0081] For example, a first unit of charge from the source 16 enters the first charge transfer path at the input of the cascaded multiplier circuit 40. During each state transition, the first unit of charge jumps between the positive terminals of capacitors C3B, C2B, C1B (in that order), and thus is transferred to the load 18 after four state transitions. Similarly, in the second charge transfer path, a second unit of charge leaves the source 16 and then proceeds to jump between the positive terminals of capacitors C3B, C2B, C1B during each state transition. After the fourth state transition, the second unit of charge is transferred to the load 18. By shifting the first and second charge transfer paths 180 degrees out of phase with each other, there is always a charge path between the source 16 and the load 18.

[0082] It should be realized that the above two - phase cascaded multiplier circuit 40 is one of many different embodiments. Figure 10 An optional two - phase cascaded multiplier circuit 50 is illustrated, which is formed by removing the cascaded switches M2A, M4A, M2B, M4B in the cascaded multiplier circuit 40, thus reducing control complexity and potentially increasing robustness. Unfortunately, because of the absence of these cascaded switches, all internal switches M1A, M3A, M1B, M3B need to support twice the output voltage VO and its corresponding gate driver 35.

[0083] Additionally, the pump capacitors C3A, C3B in the cascaded multiplier circuit 50 are pumped in series with their corresponding pump capacitors C1A, C1B, as compared to being pumped in parallel, as in the cascaded multiplier circuit 40. This series arrangement reduces the voltage across the pump capacitors C3A, C3B. For example, if the output voltage VO is five volts, then, compared to the fifteen volts in Figure 8 the voltage across the pump capacitors C3A, C3B in Figure 10 is ten volts. Due to the similarity between the cascaded multiplier circuits 40, 50, the cascaded multiplier circuit 50 operates as described in conjunction with Figure 10

[0084] 4. Phase Generation

[0085] In addition to the efficient generation of the gate drive signal, the capacitor voltage can also be used to efficiently drive the phase signal of the drive capacitor. Two examples of the phase shift generator 110 are shown in Figures 11 to 12 and are suitable for use with the dual-phase cascaded multiplier circuit 50 shown in Figure 10

[0086] Figure 11 The phase shift generator 110 is illustrated as receiving the output voltage VO and generating a first phase voltage, a second phase voltage, a third phase voltage, and a fourth phase voltage VP1-VP4. The first phase voltage and the second phase voltage VP1, VP2 correspond to the first phase of the cascaded multiplier circuit 50, while the third phase voltage and the fourth phase voltage VP3, VP4 correspond to the second phase of the cascaded multiplier circuit 50.

[0087] The phase shift generator 110 features four transistor pairs, where each transistor pair generates one of the phase voltages VP1-VP4. The first pair of transistors MH1, ML1 generates the first phase voltage VP1; the second pair of transistors MH2, ML2 generates the second phase voltage VP2; the third pair of transistors MH3, ML3 generates the third phase voltage VP3; and the fourth pair of transistors MH4, ML4 generates the fourth phase voltage VP4. In each transistor pair, the high-side transistor (e.g., MH1) is a PMOS device, while the low-side transistor (e.g., ML1) is an NMOS device.

[0088] Separate gate driver circuits control each transistor in the phase shift generator 110, thereby allowing three-state operation of each transistor pair. The output voltage VO powers each gate driver circuit. The gate driver circuits can be implemented using a variety of circuit topologies, such as those shown in Figure 6 ​​The illustrated scalable gate driver. Each gate driver circuit receives a drive signal with a label starting with “A” or “B”. The drive signals AL1, BL1, AL2, and BL2 control the low-side transistors ML1, ML2, ML3, and ML4, respectively, while the drive signals BH1, AH1, BH2, and AH2 control the high-side transistors MH1, MH2, MH3, and MH4, respectively.

[0089] In normal operation, the phase shift generator 110 cycles between a first state and a second state at a specific frequency. During the first state, the gate driver circuits receiving “B” signals activate their corresponding transistors, and the gate driver circuits receiving “A” signals deactivate their corresponding transistors. As a result, the first-phase voltage and the third-phase voltage VP1, VP3 are equal to the output voltage VO, while the second-phase voltage and the fourth-phase voltage VP2, VP4 are equal to zero volts.

[0090] Conversely, during the second state, the gate driver circuits receiving “B” signals deactivate their corresponding transistors, and the gate driver circuits receiving “A” signals activate their corresponding transistors. As a result, the first-phase voltage and the third-phase voltage VP1, VP3 are equal to zero volts, while the second-phase voltage and the fourth-phase voltage VP2, VP4 are equal to the output voltage VO.

[0091] Figure 12 An optional phase shift generator 110 is illustrated that receives the output voltage VO and generates the first-phase voltage, the second-phase voltage, the third-phase voltage, and the fourth-phase voltage VP1-VP4. In a two-phase design, the first-phase voltage and the third-phase voltage VP1, VP3 are in phase; and the second-phase voltage and the fourth-phase voltage VP2, VP4 are out of phase. As a result, as Figure 12 shown, the first-phase voltage and the third-phase voltage VP1, VP3 can be commonly shorted, and the second-phase voltage and the fourth-phase voltage VP2, VP4 can be commonly shorted.

[0092] Additionally, the high-side transistors MH1, MH2 can utilize NMOS transistors instead of the PMOS transistors as in Figure 11 . The higher electron mobility in NMOS transistors allows for the use of smaller high-side transistors MH1, MH2, thereby reducing the energy required for activation. Since NMOS transistors require a gate voltage higher than their source voltage to activate, the high-side transistors MH1, MH2 derive this boosted voltage from the pump capacitors within the cascade multiplier being driven by the phase shift generator 110.

[0093] For example, if the phase shift generator 110 is coupled to the cascaded multiplier circuit 50, then the gate driver of the high-side transistor MH1 is coupled to the positive terminal of the pump capacitor C1A from phase 1. Conversely, the gate driver of the high-side transistor MH2 is coupled to the positive terminal of the pump capacitor C1B from phase 2. Thus, each gate driver and its corresponding high-side transistor are powered by the pump capacitors from separate parallel charge transfer paths.

[0094] Because Figures 11 - 12 of the similarity of the phase shift generator 110 in Figure 12 , the operation of the phase shift generator 110 in Figure 11 operates as described in conjunction with

[0095] 5. Alternative Forms

[0096] Multiple alternative forms of the switched-capacitor power converter design under discussion utilize the approaches embodied in these designs. For example, the converter illustrated in Figure 13 is a two-phase series-parallel switched-capacitor circuit 60 that includes certain gate drivers powered by capacitors in the same charge transfer path or parallel charge transfer paths.

[0097] The switched-capacitor circuit 60 includes a pair of phases. The first phase includes capacitors C1C - C3C, odd transistors M1C - M7C, and even transistors M2C - M12C. Similarly, the second phase includes capacitors C1D - C3D, odd transistors M1D - M7D, and even transistors M2D - M12D. All transistors coupled to signals with an "A" prefix via their respective gate drivers are simultaneously activated and deactivated; all transistors coupled to signals with a "B" prefix via their respective gate drivers are also simultaneously activated and deactivated.

[0098] The switched-capacitor circuit 60 generates an output voltage VO that is four times lower than the input voltage VI by cycling between a first state and a second state at a specific frequency. During the first state, the odd transistors M1C - M7C of the first phase and the even transistors M2D - M12D of the second phase are activated, while the even transistors M2C - M12C of the first phase and the odd transistors M1D - M7D of the second phase are deactivated. This switch activation pattern places the second-phase capacitors C1D - C3D in parallel with the load 18 and arranges the first-phase capacitors C1C - C3C in series between the source 16 and the load 18.

[0099] Conversely, during the second state, the first-phase odd transistors M1C - M7C and the second-phase even transistors M2D - M12D are deactivated, while the first-phase even transistors M2C - M12C and the second-phase odd transistors M1D - M7D are activated. This switch activation pattern places the first-phase capacitors C1C - C3C in parallel with the load 18 and arranges the second-phase capacitors C1D - C3D in series between the source 16 and the load 18.

[0100] Unlike either the biphasic cascaded multiplier circuit 40 or 50, within a single phase of the switched capacitor circuit 60, the gate drivers derive their power from capacitors in both phases. For example, the gate drivers for the corresponding transistors M1C, M3C, M5C are powered by the capacitors C1C, C2C, C3C respectively, while the gate drivers for the corresponding transistors M4C, M8C, M12C are powered by the capacitor C1D.

[0101] Furthermore, the voltage stress across the transistors in a series - parallel switched capacitor power converter can be extremely high compared to a cascaded multiplier. Assuming the input voltage VI equals twenty volts, the maximum voltage across the transistors M12C, M12D is fifteen volts. In this embodiment, the gate - source voltage is always five volts, and the gate drivers for the top PMOS transistors require two series voltage followers biased by the used voltages V1c - V2d.

[0102] Although described in the context of single - phase and biphasic converters, it should be understood that other polyphase converter configurations can be used. For example, a four - phase cascaded multiplier can be constructed by placing two copies of the cascaded multiplier circuit 40 in parallel and shifting their respective clocks by ninety degrees. Adding an even number of phases is straightforward since the pairing of each subsequent phase can be operated in isolation.

[0103] However, if the switched capacitor power converter includes an odd number of phases, it is a bit more difficult to power the gate drivers from capacitors in different parallel charge transfer paths. In such a case, each gate driver draws power from capacitors in multiple parallel charge transfer paths as compared to a single parallel charge transfer path in the case of an even number of phases.

[0104] Typically, switched capacitor converters are characterized by a large number of switches and capacitors. Necessarily, at least some of the switches are floating, meaning that the switch terminals are not attached to a constant potential. It should be realized that a switched capacitor converter with at least one floating switch can benefit from deriving power from the same charge transfer path or parallel charge transfer paths. Examples of such switched capacitor converters include cascaded multipliers, series - parallel, parallel - series, Fibonacci, and voltage multiplier topologies.

[0105] 6. Embodiments

[0106] The switched-capacitor power converter and associated gate driver illustrated herein may all be integrated on one or more semiconductor substrates. If all of the transistors are integrated on a single substrate and any of the transistors are floating, then the transistors must be isolated from the substrate. For example, in a CMOS process, NMOS transistors are typically formed in a p-type substrate. These devices may only float when the body of the NMOS transistor is isolated from the substrate. If this is not the case, then an alternative possibility would be to use multiple semiconductor substrates.

[0107] The capacitors in a switched-capacitor power converter may be integrated, discrete, or a combination thereof. Discrete capacitors are typically multilayer ceramic capacitors, while integrated capacitors are typically planar or trench capacitors. If the capacitors are integrated, then the capacitors may be integrated on the same wafer as their switches, or they may be integrated on a separate wafer, or a combination of the above. Additionally, if the capacitors and switches are on different wafers, then there are a variety of attachment methods, some of which eliminate the pin count limitation on the overall converter.

[0108] When a switched-capacitor power converter uses integrated or discrete capacitors, the ability to repurpose the pumping capacitors is beneficial. If discrete capacitors are used, then each capacitor uses at least one pin. Adding additional pins for the gate driver circuitry is very cumbersome because the pins on an integrated circuit have a limited supply for a given die area. On the other hand, integrated capacitors do not consume pin count, but they are expensive and have low capacitance per unit area, so it is valuable to limit their use.

[0109] Typically, a controller generates control signals for activating and deactivating the switches within a switched-capacitor power converter. For example, in most of the embodiments described above, the controller may have generated drive signals labeled with a prefix of "A" or "B". By controlling the on and off times of the respective switches, the controller may provide a number of functions. Some such functions include: the ability to regulate the output voltage, the ability to shut down the power converter in the case of a fault condition, and the ability to change the gain of the switchable capacitor network.

[0110] This document has described various features, aspects, and embodiments of a switched-capacitor power converter. The described features, aspects, and multiple embodiments are readily combinable with one another and are also readily variable and modifiable, as will be understood by those skilled in the art. Accordingly, the present disclosure should be regarded as encompassing such combinations, variations, and modifications. Additionally, the terms and expressions employed herein are for the purpose of illustration and not of limitation. There is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible, within the scope of the claims. Other modifications, variations, and alternative forms are also possible. Accordingly, the claims are intended to cover all such equivalents.

[0111] It will be understood that the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.

[0112] Regarding embodiments including the above-described embodiments, the following supplementary notes are also disclosed:

[0113] Supplementary Notes:

[0114] 1. A switched-capacitor power converter, comprising:

[0115] A first terminal configured to be coupled to a first external circuit at a substantially high voltage.

[0116] A second terminal configured to be coupled to a second external circuit at a substantially low voltage that is lower in magnitude than the high voltage.

[0117] A first plurality of active semiconductor switch elements configured to electrically interconnect capacitors to one another and / or to the first terminal or the second terminal in a continuous state, wherein the switch elements are configured to interconnect at least some of the capacitors to one another through a series of multiple said switch elements.

[0118] A plurality of switch driver circuits, each switch element being coupled to and configured to be controlled by a drive output of one of the switch driver circuits, each driver circuit having a control input, a power connection, and a drive output, the drive output being coupled to and configured to control one or more of the switch elements.

[0119] Wherein at least some of the switch driver circuits are configured to be powered from one or more of the capacitors via the power connection of the drive circuit, such that the voltage across the power connection of the drive circuit is substantially less than the high voltage.

[0120] 2. The switched-capacitor power converter according to supplementary note 1, further comprising:

[0121] A plurality of capacitors, the plurality of capacitors being coupled to the first plurality of switching elements and controllably coupled via the switching elements.

[0122] 3. The switched-capacitor power converter according to claim 1, further comprising a plurality of terminals coupled to the first plurality of switching elements for connection to the capacitors.

[0123] 4. The switched-capacitor power converter according to claim 1, wherein the converter is configured to provide a time-varying voltage relative to the low voltage to at least some of the drive circuits.

[0124] 5. The switched-capacitor power converter according to claim 1, wherein each switching element has a maximum rated voltage lower than the high voltage.

[0125] 6. The switched-capacitor power converter according to claim 5, wherein each of the series of the plurality of switching elements includes N switching elements, N>1, and wherein the maximum rated voltage of the switching elements is not greater than 2 / N times the low voltage.

[0126] 7. The switched-capacitor power converter according to claim 5, wherein the voltage across the power connection of the drive circuit is configured to be driven from the capacitor at less than or substantially equal to twice the low voltage.

[0127] 8. The switched-capacitor power converter according to claim 1, wherein each switching element in the series of the plurality of switching elements is driven by a corresponding drive circuit, and each of the drive circuits is configured to be powered from a different capacitor of the plurality of capacitors having different voltages in operation via the power connection of the drive circuit.

[0128] 9. The switched-capacitor power converter according to claim 1, wherein the switching elements and the capacitors are configured to form multiple separate charge transfer paths between the first terminal and the second terminal, and wherein at least some of the switching drive circuits that control one of the separate charge transfer paths are powered from the capacitors of one or more other charge transfer paths.

[0129] 10. The switched-capacitor power converter according to claim 9, wherein the separate charge transfer paths are out of phase during operation of the converter.

[0130] 11. A switched-capacitor power converter, comprising:

[0131] A first terminal for coupling to a first external circuit at a substantially high voltage;

[0132] a second terminal configured to couple to a second external circuit at a substantially low voltage that is lower in magnitude than the high voltage;

[0133] a plurality of active semiconductor switching elements configured to electrically interconnect the capacitors with each other and to the first terminal or the second terminal in a sequential state, wherein the switching elements and the capacitors are configured to form multiple separate charge transfer paths between the first terminal and the second terminal;

[0134] a plurality of switch drive circuits, each switching element being coupled to and configured to be controlled by a drive output of one of the switch drive circuits, each drive circuit having a control input, a power connection, and a drive output, the drive output being coupled to and configured to control one or more of the switching elements;

[0135] wherein at least some of the switch drive circuits are configured to be powered from one or more of the capacitors via the power connection of the drive circuit such that the voltage across the power connection of the drive circuit is substantially less than the high voltage,

[0136] wherein at least some of the switch drive circuits that control the switching elements of a respective charge transfer path are powered from the capacitors of one or more other charge transfer paths.

[0137] 12. The switched-capacitor power converter according to claim 11, wherein the separate charge transfer paths are out of phase during operation of the converter.

[0138] 13. The switched-capacitor power converter according to claim 11, further comprising:

[0139] a plurality of capacitors coupled to the plurality of switching elements and controllably coupled via the switching elements.

[0140] 14. The switched-capacitor power converter according to claim 13, wherein the capacitors and the switching elements are integrated in a monolithic device.

[0141] 15. The switched-capacitor power converter according to claim 11, further comprising a plurality of terminals coupled to the plurality of switching elements for connection to the capacitors.

[0142] 16. The switched-capacitor power converter according to claim 11, wherein the converter is configured to provide a time-varying voltage relative to the low voltage to at least some of the drive circuits.

[0143] 17. The switched-capacitor power converter according to Note 11, wherein at least some of the drive circuits include ramped gate drivers.

[0144] 18. The switched-capacitor power converter according to Note 11, wherein at least one of the drive circuits includes cascaded transistors.

[0145] 19. The switched-capacitor power converter according to Note 11, wherein at least one of the drive circuits includes a voltage follower.

[0146] 20. The switched-capacitor power converter according to Note 11, wherein each switching element includes a transistor or a network of transistors.

[0147] 21. The switched-capacitor power converter according to Note 11, wherein each switching element has a maximum rated voltage lower than the high voltage.

[0148] 22. The switched-capacitor power converter according to Note 11, wherein the switching elements are configured to interconnect at least some of the capacitors with each other through a series of a plurality of the switching elements.

[0149] 23. The switched-capacitor power converter according to Note 22, wherein each of the series of a plurality of the switching elements includes N switching elements, N>1, and wherein the maximum rated voltage of the switching elements is not greater than 2 / N times the low voltage.

[0150] 24. The switched-capacitor power converter according to Note 21, wherein the voltage across the power connection of the drive circuit is configured to be driven from the capacitor at less than or substantially equal to twice the low voltage.

[0151] 25. The switched-capacitor power converter according to Note 11, further comprising a phase shift generator including a second plurality of switching elements, the phase shift generator being configured to provide a time-varying voltage level to one terminal of each of the plurality of capacitors, wherein the phase shift generator is configured to use the voltage from capacitors in other charge transfer paths to generate the voltage level for at least one capacitor in one charge transfer path.

[0152] 26. The switched-capacitor power converter according to Note 11, wherein the converter includes a cascaded multiplier network.

[0153] 27. The switched-capacitor power converter according to Note 11, wherein the converter includes a series-parallel switched capacitor network.

[0154] 28. The switched-capacitor power converter according to Note 11 further includes a precharge circuit configured to limit the voltage across the switching element during the boost phase.

[0155] Regarding embodiments including the above embodiments, the following solutions are further disclosed:

[0156] 1. A device for power conversion, the device including a precharge circuit, a switch, and a gate driver circuit, wherein the switch includes an active semiconductor switching element, wherein the switch is configured to transition between a first state and a second state, the first state and the second state resulting in respective first and second electrical interconnections between a capacitor and at least one of a first terminal and a second terminal, wherein the first terminal is configured to be coupled to a first external circuit at a first voltage, wherein the second terminal is configured to be coupled to a second voltage, the magnitude of the second voltage being less than the magnitude of the first voltage, wherein the precharge circuit is coupled to at least one of the capacitors, wherein each gate driver circuit includes a control input, a power connection, and a drive output, wherein each switch is coupled to the drive output of one of the gate driver circuits and is controlled by the drive output of one of the gate driver circuits, wherein the gate driver circuit includes a first gate driver circuit, and wherein the first gate driver circuit receives power from at least one of the capacitors through its power connection.

[0157] 2. The device according to Solution 1, wherein the precharge circuit is configured to: initialize the voltage on the capacitor in the switched-capacitor network defined by the capacitor and the switch before the clocked operation of the switched-capacitor network.

[0158] 3. The device according to Solution 1, wherein the precharge circuit is configured to: maintain the source voltage across the selected switch within a desired limit during startup of the operation of the device.

[0159] 4. The device according to Solution 1, wherein the precharge circuit is configured to: provide charge to one or more of the capacitors to be used to power the gate drive circuit when starting the clocked operation of the device.

[0160] 5. The device according to Solution 1, wherein the precharge circuit includes a bias resistor that defines a resistive voltage divider that defines a precharge voltage for one or more of the capacitors during startup of the operation of the device, and the resistance of the resistor is selected to avoid exposing the switch to a voltage exceeding the threshold voltage, thereby avoiding damaging the switch during startup of the operation of the device.

[0161] 6. The apparatus according to embodiment 1 further includes a terminal coupled to the switch for connection to the capacitor.

[0162] 7. The apparatus according to embodiment 1, wherein the switch and the capacitor define a power converter configured to provide a time-varying voltage to at least a portion of the gate driver circuit.

[0163] 8. The apparatus according to embodiment 1, wherein each of the switches has a maximum rated voltage less than the first voltage.

[0164] 9. The apparatus according to embodiment 1, wherein the voltage across the power connection of the first gate driver circuit is not greater than twice the second voltage and less than the first voltage.

[0165] 10. The apparatus according to embodiment 1, wherein each switch is driven by a respective one of the gate driver circuits in the gate driver circuit, and the apparatus further includes a second gate driver circuit, wherein the second gate driver circuit receives power from at least another capacitor of the capacitors through its power connection, and wherein, in operation, the voltage of at least another capacitor of the capacitors is different from the voltage across at least one of the capacitors, and at least one of the capacitors drives the first gate driver circuit.

[0166] 11. The apparatus according to embodiment 11, wherein each of at least some of the capacitors includes a first terminal and a second terminal, wherein, during operation of the apparatus, the first terminal is at a voltage higher than the voltage of the second terminal, wherein the at least some of the capacitors include a first capacitor and a second capacitor, and wherein at least one of the switches connects the first terminal of the first capacitor to the first terminal of the second capacitor.

[0167] 12. The apparatus according to embodiment 11, wherein the second terminal of the first capacitor is connected to a first phase voltage, the second terminal of the second capacitor is connected to a second phase voltage, and the first phase voltage is different from the second phase voltage.

[0168] 13. The apparatus according to embodiment 1, wherein each capacitor has a first terminal and a second terminal, wherein, during operation of the apparatus, the first terminal is at a voltage higher than the voltage of the second terminal, and wherein the switch connects the first terminals to each other.

[0169] 14. The device according to Scheme 1, wherein the first gate driver circuit is configured to: make the voltage across the power connection of the first gate driver circuit less than the first voltage.

[0170] 15. The device according to Scheme 1 further includes a switched capacitor converter, wherein at least one of the first terminal and the second terminal and the switch are components of the switched capacitor converter.

[0171] 16. The device according to Scheme 15, wherein the terminal includes a capacitor terminal, and the capacitor terminal is coupled to the corresponding switch in the switch for connection to the capacitor.

[0172] 17. The device according to Scheme 15, wherein the switched capacitor converter is configured to: provide a time-varying voltage to at least some of the gate driver circuits with respect to the lowest voltage among the corresponding voltages.

[0173] 18. The device according to Scheme 15, wherein each switching element has a maximum rated voltage less than the highest voltage among the corresponding voltages.

[0174] 19. The device according to Scheme 18, wherein the gate driver circuit includes a first gate driver circuit, the first gate driver circuit includes a first power connection and a second power connection, wherein in operation, there is a voltage difference between the first power connection and the second power connection, wherein the voltage difference is at least partially generated by a capacitor connected to the first power connection, wherein the voltage difference is less than or equal to a specific voltage, and wherein the specific voltage is less than or substantially equal to twice the lowest voltage among the corresponding voltages.

[0175] 20. The device according to Scheme 15, wherein the gate driver circuit includes a first gate driver circuit and a second gate driver circuit, the switch includes a first switching element and a second switching element, the first switching element is driven by the first gate driver circuit, the first gate driver circuit is configured to be powered by a first capacitor having a first voltage, the second switching element is driven by the second gate driver circuit, the second gate driver circuit is configured to be powered by a second capacitor having a second voltage, and wherein the first voltage is different from the second voltage.

[0176] 21. The apparatus according to aspect 15 further includes a phase shift generator, wherein the phase shift generator includes a phase shift generator switch, wherein the phase shift generator is configured to provide a time-varying voltage level to one terminal of each of the capacitors, and wherein the phase shift generator is configured to use the voltage from the capacitors in the second charge transfer path to generate a voltage level for the capacitors in the first charge transfer path.

[0177] 22. The apparatus according to aspect 15, wherein the switch includes a first switch element and a second switch element, wherein the second switch element is in series with the first switch element, and wherein, in operation, the first switch and the second switch transition to a state in which the first switch and the second switch allow a steady flow of charge between the capacitors.

[0178] 23. The apparatus according to aspect 15, wherein each switch element has a maximum rated voltage that is less than the highest voltage among the respective voltages.

[0179] 24. The apparatus according to aspect 15, wherein the switched capacitor converter includes a cascaded multiplier network.

[0180] 25. The apparatus according to aspect 15, wherein the switched capacitor converter includes a series-parallel switched capacitor network.

[0181] 26. The apparatus according to aspect 15, wherein the gate driver circuit includes a first gate driver circuit, wherein the first gate driver circuit is configured to be powered by the charge stored in the capacitor bank through a power connection of the first gate driver circuit such that the voltage across the power connection is substantially less than a specific voltage, and wherein the specific voltage is the highest voltage among the respective voltages.

[0182] 27. The apparatus according to aspect 15 further includes a capacitor coupled to the switch, wherein the connection between the capacitors is controlled by the switch.

[0183] 28. A method for converting a first voltage to a second voltage, the method comprising: connecting a first terminal of a switched-capacitor power converter to a first external circuit; connecting a second terminal of the switched-capacitor power converter to a second external circuit; pre-charging a capacitor within the switched-capacitor power converter; providing a first control signal to a control input of a gate driver circuit of the power converter; providing a second control signal to the control input of the gate driver circuit, wherein the switched-capacitor power converter includes a switched-capacitor network in which capacitors are selectively interconnected by active semiconductor switches; connecting the second terminal of the switched-capacitor power converter to the second external circuit; causing the capacitors in the switched-capacitor network to provide power to the gate driver circuit through a power connection of the gate driver circuit; and causing there to be a voltage across the power connection of the gate driver circuit, wherein the voltage across the power connection of the gate driver circuit that exists is less than the greater of the first voltage and the second voltage, wherein pre-charging the capacitor within the switched-capacitor power converter includes: pre-charging the capacitor before starting normal operation of the switched-capacitor power converter, wherein the first control signal causes a first drive signal at a corresponding drive output of the gate driver circuit, wherein the first drive signal causes the active semiconductor switches to perform a first switch activation mode, wherein the second control signal causes a second drive signal at the corresponding drive output of the gate driver circuit, wherein the second drive signal causes the active semiconductor switches to perform a second switch activation mode, and wherein, in the first switch activation mode, a first series of active semiconductor switches connects a first capacitor and a second capacitor in the switched-capacitor network of the power converter to allow conduction current to flow between high-voltage terminals of the first capacitor and the second capacitor.

[0184] 29. A device, the device comprising a circuit and a controller for operating the circuit, wherein the circuit is a two-phase series-parallel switched capacitor circuit configured to be connected between a source and a load, wherein the circuit comprises a first charge transfer path and a second charge transfer path, a gate driver along the first charge transfer path, a first capacitor bank and a second capacitor bank, and a first transistor bank and a second transistor bank, wherein the first capacitor bank and the first transistor bank define a first phase, wherein the second capacitor bank and the second transistor bank define a second phase, wherein the capacitor bank powers the gate driver, wherein the capacitor bank comprises capacitors connected in series on one of the first charge transfer path and the second charge transfer path, wherein the controller causes the circuit to transition between a first state and a second state at a specific frequency, wherein, in the first state, the first capacitor bank is in parallel with the load, and the second capacitor bank is in series between the source and the load, and wherein, in the second state, the second capacitor bank is in parallel with the load, and the first capacitor bank is in series between the source and the load, such that the gate driver obtains power from the capacitors in both phases.

[0185] 30. The device according to claim 29, wherein at least some of the capacitors are integrated with the transistors in a substrate.

[0186] 31. The device according to claim 29, wherein at least some of the capacitors are integrated on a substrate separate from the substrate in which the transistors are integrated.

[0187] 32. The device according to claim 29, wherein at least one of the transistors comprises a terminal connected to a floating potential.

[0188] 33. The device according to claim 29, wherein at least one of the gate drivers is connected to a pair of serially connected voltage followers.

[0189] 34. The device according to claim 29, further comprising a precharge circuit connected for initializing the voltage on the capacitors before clocked operation of the circuit.

[0190] 35. The device according to claim 29, wherein at least one of the drivers is a ramping gate driver.

[0191] 36. The device according to claim 29, wherein at least one of the drivers comprises a plurality of inverters arranged in order of increasing size, wherein the sizes of the inverters define a geometric series.

[0192] 37. The device according to aspect 29, wherein the controller is configured to control the on-time and off-time of each of the transistors.

[0193] 38. The device according to aspect 29, wherein the controller is configured to change the gain of the circuit.

[0194] 39. The device according to aspect 29, wherein the controller is configured to regulate the output voltage of the circuit.

[0195] 40. The device according to aspect 29, wherein at least one of the drivers is a cascaded gate driver.

[0196] 41. The device according to aspect 29, wherein the source or the load is at a first voltage, and the voltage for driving the gate driver is below the first voltage.

[0197] 42. The device according to aspect 29, wherein the bi-phase series-parallel switched capacitor circuit is a component of a multi-phase power converter.

[0198] 43. A method, comprising: connecting a bi-phase switched capacitor circuit between a source and a load, and causing the circuit to transfer charge from the source to the load, wherein causing the circuit to transfer charge comprises: during a first phase, causing charge to transfer from the source to the load along a first charge transfer path; and during a second phase, causing charge to transfer from the source to the load along a second charge transfer path, wherein causing charge to transfer from the source to the load along the first charge transfer path comprises: applying a voltage to the gate of a first transistor that controls the flow of charge between a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor store charge when the charge passes through the first charge transfer path, and wherein applying the voltage to the gate comprises connecting the gate to a third capacitor, wherein the third capacitor is a capacitor that stores charge passing through the second charge transfer path.

[0199] 44. A device includes a circuit and a controller for operating the circuit, wherein the circuit is a two-phase series-parallel switched capacitor circuit configured to be connected between a source and a load, wherein the circuit includes a gate driver, a first capacitor bank and a second capacitor bank, and a first transistor group and a second transistor group, wherein the capacitors from the first capacitor bank and the transistors from the first transistor group define a first phase, wherein the capacitors from the second capacitor bank and the transistors from the second transistor group define a second phase, wherein the capacitor bank powers the gate driver, wherein the capacitor bank is from one of the first capacitor bank and the second capacitor bank, wherein the controller causes the circuit to transition between a first state and a second state at a specific frequency, wherein, in the first state, the capacitors from the first capacitor bank are in parallel with the load, and the capacitors from the second capacitor bank are in series between the source and the load, and wherein, in the second state, the capacitors from the second capacitor bank are in parallel with the load, and the capacitors from the first capacitor bank are in series between the source and the load, and wherein the gate driver obtains power from the capacitors in the capacitor bank of the two phases.

[0200] 45. A device includes a first plurality of switches, a second plurality of switches, a controller for controlling the first plurality of switches and the second plurality of switches, a gate driver for driving the switches in the first plurality of switches, and a first terminal and a second terminal configured to be coupled to a corresponding first external circuit and a second external circuit at corresponding first and second voltages, respectively, wherein, during operation, the controller causes the first plurality of switches to transition between consecutive states, each state being characterized by a switch activation pattern that defines which switches will be open and which switches will be closed during the state, the transition causing the second voltage to be maintained at a value that is a multiple of the first voltage, the controller causes the second plurality of switches to transition between consecutive states, each state being characterized by a switch activation pattern that defines which switches will be open and which switches will be closed during the state, the transition causing a capacitor to be coupled or decoupled from the second voltage, and the gate driver obtains charge from the capacitor to generate a voltage that enables driving the switches in the first plurality of switches.

[0201] 46. The device according to claim 45, wherein the maximum rated voltage of each switch in the first plurality of switches is less than the greater of the first voltage and the second voltage.

[0202] 47. The device according to embodiment 45, wherein the first gate driver in the gate driver includes a first power connection and a second power connection, and a voltage difference between the first power connection and the second power connection is less than or equal to twice the lower voltage of the first voltage and the second voltage.

[0203] 48. The device according to embodiment 45, wherein the first gate driver in the gate driver includes a first power connection and a second power connection, and the first power connection is coupled to one of the capacitors such that a voltage difference between the first power connection and the second power connection is less than the voltage with a higher magnitude of the first voltage and the second voltage.

[0204] 49. The device according to embodiment 45, wherein the switches in the second plurality of switches are implemented by transistors, each of the transistors having a gate voltage and a source voltage, and the device further includes a resistive voltage divider coupled to the second plurality of switches.

[0205] 50. The device according to embodiment 45, further including a resistive voltage divider coupled to the second plurality of switches, wherein the switches in the second plurality of switches are implemented by transistors, each of the transistors having a gate voltage and a source voltage, and the resistive voltage divider is configured to make the source voltage of each of the transistors at least a threshold voltage lower than the corresponding gate voltage of the transistor.

[0206] 51. The device according to embodiment 45, wherein the controller is configured to prohibit the operation of the second plurality of switches after an interval.

[0207] 52. The device according to embodiment 45, wherein the switches in the second plurality of switches are implemented by transistors, each of the transistors having a different gate voltage.

[0208] 53. A device includes a first switch group, a controller for controlling switches in the first switch group, a gate drive circuit for driving the gates of the switches, a first terminal and a second terminal, and a node for coupling the gate drive circuit to a power supply. The first terminal and the second terminal are configured to be coupled to a corresponding first external circuit and a second external circuit at corresponding first and second voltages. The power supply includes a capacitor that is part of a switched capacitor network coupled to the switches. During operation, the controller causes the switches in the first switch group to transition between successive states, each state characterized by a switch activation pattern that defines which switches will be open and which switches will be closed during that state. The transition causes the second voltage to be maintained at a value that is a multiple of the first voltage. The node couples the gate drive circuit to the capacitor.

[0209] 54. The device according to claim 53, wherein the first switch group includes a first switch arranged along a path between an anode of a first capacitor and an anode of a second capacitor, and wherein a voltage difference across the switch when the switch is open is less than a voltage difference between the anodes of the capacitors.

[0210] 55. The device according to claim 53, wherein the capacitor includes a first capacitor bank and a second capacitor bank, and the device further includes a second switch group that selectively couples the second terminal to capacitors in the first capacitor bank while decoupling the second terminal from capacitors in the second capacitor bank. Before starting steady-state operation of the power supply, the controller causes the switches in the second switch group to allow the second voltage to drive charge towards the capacitors of the power supply.

[0211] 56. The device according to claim 53, wherein the node couples the gate drive circuit to the anode of the capacitor.

[0212] 57. The device according to claim 53, wherein during steady-state operation of the power supply, the controller opens the second switch to prevent the second voltage from driving charge towards the capacitors of the power supply.

[0213] 58. The device according to claim 53, wherein the capacitors of the power supply include a first capacitor bank and a second capacitor bank, wherein the first bank includes capacitors with cathodes connected to a phase voltage, and the second bank includes capacitors with cathodes connected to a phase-shifted version of the phase voltage.

[0214] 59. The device according to claim 53, wherein the power supply includes a cascaded multiplier.

[0215] 60. The device according to embodiment 53, wherein the capacitor comprises a first capacitor and a second capacitor, and wherein the gate drive circuit comprises a first gate driver and a second gate driver for driving a respective first switch and a second switch in series such that all current passing through the first switch also passes through the second switch, wherein the first switch is connected to the anode of the first capacitor and the second switch is connected to the anode of the second capacitor.

[0216] 61. The device according to embodiment 53, wherein the capacitor comprises a first capacitor bank and a second capacitor bank, and the device further comprises a second switch bank that selectively couples the second terminal to the capacitors in the first bank while decoupling the second terminal from the capacitors in the second bank.

[0217] 62. A device comprising: a first switch bank; a controller for controlling the switches in the first switch bank; a gate drive circuit for driving the switches; a first terminal and a second terminal configured to be coupled to a first terminal and a second terminal of a switched capacitor network that transforms a first voltage into a second voltage to provide power to a load, wherein during operation, the controller causes the switches in the first switch bank to transition between successive states, each state characterized by a switch activation pattern that defines which switches are to be open and which switches are to be closed during the state, the transition causing the second voltage to be maintained at a value that is a multiple of the first voltage and causing charge to be transferred from the first terminal to the load, and the device further comprising means for diverting charge that is transferred from the switched capacitor network to the load such that the efficiency of power transfer to the load is reduced.

[0218] 63. The device according to embodiment 62, wherein the means for diverting charge is configured to divert the charge to the gate drive circuit.

[0219] 64. The device according to embodiment 62, wherein the means for diverting charge obtains the charge from a capacitor of the switched capacitor network.

Claims

1. An integrated circuit, comprising: a plurality of first power switches configured to be coupled to one or more first cross - pumping capacitors to form a first phase of a charge pump circuit; a plurality of second power switches configured to be coupled to one or more second cross - pumping capacitors to form a second phase of the charge pump circuit, wherein each first power switch of the plurality of first power switches corresponds to a respective second power switch of the plurality of second power switches, and wherein each first power switch and each second power switch are configured to be in an active state or a de - activated state; and a plurality of first gate driver circuits and a plurality of second gate driver circuits, the plurality of first gate driver circuits being respectively coupled to the first power switches, the plurality of second gate driver circuits being respectively coupled to the second power switches, wherein the first gate driver circuits in the first phase and the second gate driver circuits in the second phase are configured to operate simultaneously in response to out - of - phase control signals to provide corresponding gate voltages to activate or de - activate the plurality of first power switches and the plurality of second power switches; wherein one first gate driver circuit of the first gate driver circuits is configured to be connected to a positive terminal and a negative terminal of a corresponding first cross - pumping capacitor in the first phase, configured to receive a voltage at the negative terminal of the corresponding first cross - pumping capacitor, and configured to drive a first switch of the first power switches; wherein one second gate driver circuit of the second gate driver circuits is configured to be connected to a positive terminal and a negative terminal of a corresponding second cross - pumping capacitor in the second phase, configured to receive a voltage at the negative terminal of the corresponding second cross - pumping capacitor, and configured to drive a second switch of the second power switches.

2. The integrated circuit according to claim 1, wherein the first gate driver circuits in the first phase and the second gate driver circuits in the second phase are configured to operate simultaneously in response to out - of - phase control signals to provide corresponding gate voltages to activate or de - activate the plurality of first power switches and the plurality of second power switches such that each first power switch in the active state is in an opposite state relative to its corresponding second power switch, and each second power switch in the active state is in an opposite state relative to its corresponding first power switch, wherein another first gate driver circuit of the first gate driver circuits in the first phase is configured to receive an input voltage from a voltage source and is configured to drive a third switch of the first power switches.

3. The integrated circuit according to claim 1, wherein another first gate driver circuit of the first gate driver circuits in the first phase is configured to receive an output voltage provided to a load and is configured to drive a fourth switch of the first power switches.

4. The integrated circuit according to claim 3, wherein the fourth switch is connected to receive the phase voltage in the first phase and is configured to be driven such that the node of the fourth switch selectively connects the phase voltage to the ground voltage.

5. The integrated circuit according to claim 1, wherein one or more of the first gate driver circuits in the first gate driver circuit include transistors forming a tapered inverter chain, the tapered inverter chain including a plurality of inverters coupled in series.

6. The integrated circuit according to claim 5, wherein the size ratio between the inverters in each pair of consecutive inverters in the tapered inverter chain is constant.

7. The integrated circuit according to claim 5, wherein for each pair of consecutive inverters in the tapered inverter chain, the subsequent inverter is larger than the previous inverter.

8. The integrated circuit according to claim 7, wherein, For each pair of consecutive inverters in the tapered inverter chain, the gate width of the transistor forming the subsequent inverter is greater than the gate width of the transistor forming the previous inverter.

9. The integrated circuit according to claim 1, wherein the first switch in the first phase is configured to derive power from the second phase, wherein one of the first gate driver circuits in the first gate driver circuit is configured to receive the voltage at the positive terminal of the corresponding cross-pump capacitor, and wherein one of the second gate driver circuits in the second gate driver circuit is configured to receive the voltage at the positive terminal of the corresponding cross-pump capacitor.

10. The integrated circuit according to claim 1, wherein the first power switch includes a PMOS transistor coupled to a voltage source configured to provide an input voltage.

11. The integrated circuit according to claim 1, wherein the plurality of first gate driver circuits include a cascaded gate driver circuit, the cascaded gate driver circuit including a first high-side transistor and a second high-side transistor and a first low-side transistor and a second low-side transistor coupled in series.

12. The integrated circuit according to claim 11, wherein the cascaded gate driver circuit further includes a first gate driver and a second gate driver, the first gate driver coupled to the gate of the first high-side transistor, the second gate driver coupled to the gate of the second low-side transistor.

13. The integrated circuit according to claim 12, wherein the cascaded gate driver circuit further includes a voltage regulator coupled to the gate of the second high-side transistor and the gate of the first low-side transistor.

14. The integrated circuit according to claim 1, wherein one of the first gate driver circuits in the first gate driver circuit further includes a level shifter circuit.

15. The integrated circuit according to claim 1, wherein one of the first gate driver circuits in the first gate driver circuit further includes a delay circuit.

16. The integrated circuit according to claim 1, wherein: another one of the first gate driver circuits in the first gate driver circuit is configured to be coupled to an output terminal; and A power supply terminal of another second gate driver circuit in the second gate driver circuit is configured to be coupled to the power supply terminal of the another first gate driver circuit in the first gate driver circuit and to the output terminal.

17. The integrated circuit according to claim 1, wherein each of the voltage at the negative terminal of the corresponding first cross-coupled capacitor and the voltage at the negative terminal of the corresponding second cross-coupled capacitor has a respective voltage level that varies with respect to ground, wherein the charge pump circuit is a step-down charge pump circuit, wherein a negative power supply terminal of one first gate driver circuit in the first gate driver circuit and a negative power supply terminal of one second gate driver circuit in the second gate driver circuit are configured to receive an output voltage at the output terminal, and wherein a positive power supply terminal of one first gate driver circuit in the first gate driver circuit and a positive power supply terminal of one second gate driver circuit in the second gate driver circuit are configured to receive an input voltage from a voltage source.

18. The integrated circuit according to claim 1, wherein: The plurality of first power switches includes: A first group of first power switches configured to operate based on a corresponding gate voltage associated with a first control signal; and A second group of first power switches configured to operate based on a corresponding gate voltage associated with a second control signal, the second control signal being out of phase with the first control signal; The plurality of second power switches includes: A first group of second power switches configured to operate based on a corresponding gate voltage associated with the second control signal, wherein each first power switch in the first group of first power switches corresponds to a respective second power switch in the first group of second power switches; and A second group of second power switches configured to operate based on a corresponding gate voltage associated with the first control signal, wherein each first power switch in the second group of first power switches corresponds to a respective second power switch in the second group of second power switches.

19. The integrated circuit according to claim 18, wherein: A first power switch in the second group of first power switches is coupled to its corresponding second power switch in the second group of second power switches and to an input terminal; And A first power switch in the first group of first power switches is coupled to its corresponding second power switch in the first group of second power switches and to an output terminal.

20. The integrated circuit according to claim 18, wherein the first gate driver circuit in the first phase and the second gate driver circuit in the second phase are configured to operate simultaneously in response to out-of-phase control signals such that: In a first state of the integrated circuit: The first group of first power switches is configured to be in the deactivated state based on the corresponding gate voltage associated with the first control signal; The second set of first power switches is configured to be in the active state based on the corresponding gate voltage associated with the second control signal; The first set of second power switches is configured to be in the active state based on the corresponding gate voltage associated with the second control signal; and The second set of second power switches is configured to be in the deactivated state based on the corresponding gate voltage associated with the first control signal; and In a second state of the integrated circuit: The first set of first power switches is configured to be in the active state based on the corresponding gate voltage associated with the first control signal; The second set of first power switches is configured to be in the deactivated state based on the corresponding gate voltage associated with the second control signal; The first set of second power switches is configured to be in the deactivated state based on the corresponding gate voltage associated with the second control signal; and The second set of second power switches is configured to be in the active state based on the corresponding gate voltage associated with the first control signal.

21. The integrated circuit according to claim 18, wherein the second set of first power switches includes the first switch, and wherein the second set of second power switches includes the second switch.

22. An integrated circuit, comprising: A plurality of gate drivers configured to receive corresponding drive signals; And A plurality of switches respectively connected to the plurality of gate drivers and configured to be driven by the plurality of gate drivers, the plurality of switches including: A first switch configured to be driven by a first gate driver among the plurality of gate drivers and configured to be connected to a first terminal of a first cross-pump capacitor; A second switch configured to be driven by a second gate driver among the plurality of gate drivers and configured to be connected between the first terminal of the first cross-pump capacitor and an output terminal for outputting an output voltage; A third switch configured to be driven by a third gate driver among the plurality of gate drivers and configured to be connected to the output terminal and a second terminal of the first cross-pump capacitor, wherein a first power supply terminal of the third gate driver is configured to be connected to the first terminal of the first cross-pump capacitor to receive a voltage from the first terminal of the first cross-pump capacitor; A fourth switch configured to be driven by a fourth gate driver among the plurality of gate drivers and configured to be connected between the second terminal of the first cross-pump capacitor and a ground terminal; A fifth switch configured to be driven by a fifth gate driver among the plurality of gate drivers and configured to be connected to a first terminal of a second cross-pump capacitor; A sixth switch configured to be driven by a sixth gate driver among the plurality of gate drivers and configured to be connected between the first terminal of the second cross-pump capacitor and the output terminal; A seventh switch, configured to be driven by a seventh gate driver among the plurality of gate drivers, and configured to be connected to the output terminal and a second terminal of the second cross-pump capacitor, wherein a first power supply terminal of the seventh gate driver is configured to be connected to the first terminal of the second cross-pump capacitor to receive a voltage from the first terminal of the second cross-pump capacitor; and An eighth switch, configured to be driven by an eighth gate driver among the plurality of gate drivers, and configured to be connected between the second terminal of the second cross-pump capacitor and the ground terminal.

23. The integrated circuit according to claim 22, wherein the first switch, the second switch, the third switch, and the fourth switch are coupled to form a first phase of a charge pump circuit, and the fifth switch, the sixth switch, the seventh switch, and the eighth switch are coupled to form a second phase of the charge pump circuit, wherein the first phase of the charge pump circuit is configured to be operated simultaneously and out of phase with the second phase of the charge pump circuit, such that the first switch and the fifth switch are configured to be driven out of phase with respect to each other, and the third switch and the seventh switch are configured to be driven out of phase with respect to each other.

24. The integrated circuit according to claim 22, wherein a first power supply terminal of the fourth gate driver is configured to be connected to the output terminal, and a second power supply terminal of the fourth gate driver is configured to be connected to the ground terminal, and wherein a first power supply terminal of the eighth gate driver is configured to be connected to the output terminal, and a second power supply terminal of the eighth gate driver is configured to be connected to the ground terminal.

25. The integrated circuit according to claim 22, wherein a second power supply terminal of the third gate driver is configured to be connected to the second terminal of the first cross-pump capacitor, and wherein a second power supply terminal of the seventh gate driver is configured to be connected to the second terminal of the second cross-pump capacitor.

26. The integrated circuit according to claim 22, wherein one or more of the gate drivers include transistors forming a progressive inverter chain, the progressive inverter chain including a plurality of inverters coupled in series, wherein each of the inverters includes a high-side transistor and a low-side transistor connected in series between two power supply terminals, wherein the low-side transistor is an NMOS device, and wherein the high-side transistor is a PMOS device larger in size than the NMOS device.

27. The integrated circuit according to claim 26, wherein for each pair of consecutive inverters in the progressive inverter chain, the subsequent inverter is larger than the previous inverter.

28. The integrated circuit according to claim 22, wherein the first switch, the second switch, the third switch, and the fourth switch are coupled to form a first phase of a charge pump circuit, and the fifth switch, the sixth switch, the seventh switch, and the eighth switch are coupled to form a second phase of the charge pump circuit, wherein the first phase of the charge pump circuit is configured to be operated simultaneously and substantially out of phase with the second phase of the charge pump circuit.

29. The integrated circuit according to claim 28, wherein the first phase of the charge pump circuit is configured to be operated simultaneously and approximately 180° out of phase with the second phase of the charge pump circuit.

30. The integrated circuit according to claim 22, wherein positive supply terminals of the fourth gate driver and the eighth gate driver are configured to receive an output voltage at the output terminal.

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