Dynamic range control circuit, audio processing chip and audio processing method thereof

Abstract

The technical scheme of the present application provides a dynamic range control circuit, an audio processing chip and an audio processing method thereof, wherein the dynamic range control circuit has a plurality of parallel gain generation modules and an output module, and each gain generation module has a separate gain generator and a gain smoothing processing module. In the same gain generation module, the gain generator is used for gain processing of an input signal, and the gain smoothing processing module is used for setting the compression time and release time of the gain generation module based on the output gain of the gain generator. It can be seen that in each gain generation module, the compression time and release time of each gain generation module can be set by the respective smoothing processing module, so that the compression time and release time of different gain generation modules are separated, which can greatly improve the tuning of the audio power amplifier and the user's auditory perception.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sound processing, and more particularly to a dynamic range control circuit, an audio processing chip and an audio processing method thereof. BACKGROUND

[0002] Dynamic Range Control (DRC) is an algorithm commonly used for sound volume control, which performs different processing in different energy range intervals. Noise Gate, Expander, Compressor and Limiter are four node modules in the system from low to high energy.

[0003] When performing DRC processing, gain adjustment and smoothing processing need to be performed on the input data. In the prior art, only one gain adjustment method can be selected for each processing, and only one smoothing processing module can be set, which can only set one compression (attack) time or release (release) time, and cannot realize separate and independent compression (attack) time or release (release) time based on different gain settings. SUMMARY

[0004] Therefore, the present application provides a dynamic range control circuit, an audio processing chip and an audio processing method thereof, and the scheme is as follows:

[0005] A dynamic range control circuit comprises:

[0006] A plurality of parallel gain generation modules, each gain generation module having a separate gain generator and a gain smoothing processing module; the gain generation module is used for gain processing of the input signal received thereby to form an output gain, and setting a compression time and a release time based on the output gain; in the same gain generation module, the gain generator is used for gain processing of the input signal of the gain generation module, and the gain smoothing processing module is used for setting the compression time and the release time based on the output gain of the gain generator;

[0007] An output module, the output module is used for outputting target data based on the output gain of each gain generation module and the initial input data received by the dynamic range control circuit.

[0008] Preferably, in the above dynamic range control circuit, N gain generation modules are included, which are sequentially the first gain generation module to the Nth gain generation module, corresponding to the first output gain to the Nth output gain; N is a positive integer greater than 1; the output gain of each gain generation module belongs to a logarithmic domain:

[0009] If N=2, the output module is configured to calculate a sum of the first output gain and the second output gain, and calculate the target data based on the sum and the initial input data;

[0010] If N>2, the output module is configured to obtain a minimum value among the first output gain to the N-1th output gain, calculate a sum of the minimum value and the Nth output gain, and calculate the target data based on the sum and the initial input data.

[0011] Preferably, in the dynamic range control circuit, four gain generation modules are included, which are the first gain generation module to the fourth gain generation module, corresponding to the first output gain to the fourth output gain.

[0012] The output module is configured to generate the target data based on a minimum value among the first output gain to the third output gain, the fourth output gain, and the initial input data.

[0013] Preferably, in the dynamic range control circuit, if N=2, the output module is configured to calculate a sum of the first output gain and the second output gain, calculate a linear domain value corresponding to the sum based on an anti-log operation, and calculate a product of the linear domain value and the initial input data as the target data.

[0014] If N>2, the output module is configured to obtain a minimum value among the first output gain to the N-1th output gain, calculate a sum of the minimum value and the Nth output gain, calculate a linear domain value corresponding to the sum based on an anti-log operation, and calculate a product of the linear domain value and the initial input data as the target data.

[0015] Preferably, in the dynamic range control circuit, if N>2, the output module includes:

[0016] a comparator configured to obtain a minimum value among the first output gain to the N-1th output gain;

[0017] an adder configured to calculate a sum of the minimum value and the Nth output gain;

[0018] a multiplier configured to calculate a product of the linear domain value and the initial input data.

[0019] Preferably, in the dynamic range control circuit, the gain generators of the four gain generation modules are a limiter, a compressor, an expander, and a noise removal effecter, respectively.

[0020] The gain module to which the expander belongs is the fourth gain generation module.

[0021] Preferably, in the dynamic range control circuit, N gain generation modules are included, which are sequentially a first gain generation module to an Nth gain generation module, corresponding to a first output gain to an Nth output gain; N is a positive integer greater than 1; the output gain of each gain generation module belongs to a linear domain;

[0022] If N=2, the output module is configured to calculate the product of the first output gain, the second output gain and the initial input data as the target data.

[0023] If N>2, the output module is configured to obtain the minimum value among the first output gain to the (N-1)th output gain, and calculate the product of the minimum value, the Nth output gain and the initial input data as the target data.

[0024] Preferably, in the dynamic range control circuit, the gain generator is a compressor configured to start compressing the input signal when the input signal exceeds a first threshold value, to output the output gain of the gain generator to which the input signal belongs.

[0025] The degree of compression of the output gain with respect to the input signal is related to a first proportional parameter, and the smoothness of the output gain with respect to the input signal is related to a first smooth transition parameter.

[0026] Preferably, in the dynamic range control circuit, the gain generator is a limiter configured to compress the input signal to a fixed amplitude signal with an amplitude of a second threshold value when the input signal exceeds a second threshold value, to output the output gain of the gain generator to which the input signal belongs.

[0027] The smoothness of the output gain with respect to the input signal is related to a second smooth transition parameter.

[0028] Preferably, in the dynamic range control circuit, the gain generator is a noise removal effecter configured to start compressing the input signal when the input signal is less than a third threshold value, to output the output gain of the gain generator to which the input signal belongs.

[0029] The degree of compression of the output gain with respect to the input signal is related to a second proportional parameter, and the smoothness of the output gain with respect to the input signal is related to a third smooth transition parameter.

[0030] Preferably, in the dynamic range control circuit, the gain generator is an expander configured to start amplifying the input signal based on a set compensation gain and a third proportional parameter when the input signal exceeds a fourth threshold value, to output the output gain of the gain generator to which the input signal belongs.

[0031] The smoothness of the output gain with respect to the input signal is related to a fourth smooth transition parameter.

[0032] Preferably, in the dynamic range control circuit, an amplitude detection module is further included, which is configured to detect the amplitude of the initial input data as the input signal of each gain generation module.

[0033] The application further provides an audio processing chip, which comprises:

[0034] The dynamic range control circuit according to any one of the preceding embodiments.

[0035] The application further provides an audio processing method of an audio processing chip, wherein the dynamic range control circuit of the audio processing chip comprises a plurality of parallel gain generation modules.

[0036] The audio processing method comprises:

[0037] Each gain generation module performs gain processing on the input signal obtained by itself to form an output gain, and sets a compression time and a release time based on the output gain.

[0038] Based on the output gain of each gain generation module and the initial input data of the dynamic range control circuit, target data is output.

[0039] Preferably, in the audio processing method, the dynamic range control circuit comprises N gain generation modules, which are sequentially the first gain generation module to the Nth gain generation module, corresponding to the first output gain to the Nth output gain; N is a positive integer greater than 1; the output gain of each gain generation module belongs to a logarithmic domain.

[0040] The method for calculating the target data comprises:

[0041] If N=2, the output module is configured to calculate the sum of the first output gain and the second output gain, and calculate the target data based on the sum and the initial input data.

[0042] If N is greater than 2, the minimum value among the first output gain to the N-1th output gain is obtained, the sum of the minimum value and the Nth output gain is calculated, and the target data is calculated based on the sum and the initial input data.

[0043] Preferably, in the audio processing method, the dynamic range control circuit comprises N gain generation modules, which are sequentially the first gain generation module to the Nth gain generation module, corresponding to the first output gain to the Nth output gain; N is a positive integer greater than 1; the output gain of each gain generation module belongs to a linear domain.

[0044] The method for calculating the target data comprises:

[0045] If N=2, the product of the 1st output gain, the 2nd output gain and the initial input data is calculated as the target data.

[0046] If N is greater than 2, the minimum value of the 1st output gain to the N-1th output gain is obtained, and the product of the minimum value, the Nth output gain and the initial input data is calculated as the target data.

[0047] As can be seen from the above description, in the dynamic range control circuit, the audio processing chip and the audio processing method provided by the technical scheme, the dynamic range control circuit is provided with a plurality of parallel gain generation modules and output modules, and the gain generation module is provided with a separate gain generator and a gain smoothing processing module. In the same gain generation module, the gain generator is used for gain processing of an input signal, and the gain smoothing processing module is used for setting the compression time and the release time of the gain generation module based on the output gain of the gain generator. It can be seen that in each gain generation module, the compression time and the release time of each gain generation module can be set by the respective smoothing processing modules, so that the compression time and the release time of different gain generation modules are separated, which can greatly improve the tuning of the audio power amplifier and the user's auditory perception. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical scheme in the embodiments or related art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creating any creative labor.

[0049] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the defined conditions under which the present application can be implemented, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effect and purpose that the present application can produce, should still fall within the scope of the technical content disclosed by the present application.

[0050] Figure 1 It is a structural schematic diagram of a conventional DRC circuit;

[0051] Figure 2 It is a structural schematic diagram of a DRC circuit provided by an embodiment of the present application;

[0052] Figure 3 This is a schematic diagram of another DRC circuit provided in an embodiment of the present invention;

[0053] Figure 4 The gain conversion curve of the compressor in the DRC circuit described in this embodiment of the invention;

[0054] Figure 5 The gain transformation curve of the limiter in the DRC circuit described in this embodiment of the invention;

[0055] Figure 6 The gain transformation curve of the noise removal effector in the DRC circuit described in this embodiment of the invention;

[0056] Figure 7 The gain transformation curve of the expander in the DRC circuit described in this embodiment of the invention;

[0057] Figure 8 A comparison diagram of input and output data in the entire DRC circuit provided in this embodiment of the invention;

[0058] Figure 9 This is a flowchart illustrating an audio processing method provided in an embodiment of the present invention. Detailed Implementation

[0059] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0060] In the tuning and protection algorithms of digital audio power amplifiers, different gain layers need to be applied to input signals of different amplitudes to ensure that large signals do not exceed the speaker's tolerance range; the energy of small and medium signals is enhanced to improve the perceived loudness of the sound; and noise is effectively suppressed to improve the signal-to-noise ratio of the sound.

[0061] like Figure 1 As shown, Figure 1 This is a schematic diagram of a conventional DRC circuit. Figure 1 In the method shown, the input signal is amplitude detected by the peak calculation module or the root mean square calculation module to obtain the real-time amplitude of the input signal. The gain processing is performed by the interval judgment module through the noise removal effect, expander, compressor or limiter. The processed signal is smoothed by the smoothing module and then multiplied by the input signal processed by the delay module through the multiplier to generate the output signal.

[0062] The inventor discovered that, Figure 1In the shown mode, each data processing process can only select one gain processing mode through the interval judgment module, and the same smoothing processing module is used in each gain processing path, so that only one compression time and release time can be set, and the separation and independence of the compression time and release time of different gain adjustments cannot be realized.

[0063] Based on the above problems, the embodiment of the present application provides a DRC circuit, which can perform corresponding processing on initial input data through multiple parallel gain generation modules, any of the gain generation modules has a separate gain generator and a gain smoothing processing module, the gain generator in any gain generation module can be any one of a limiter, a compressor, an expander and a noise removal effecter, the multiple parallel gain generation modules are used to realize multi-node gain adjustment of an input signal, each gain generation module has an independent gain smoothing processing module, so that the time of each gain generation module is independent of each other. The structure of the DRC circuit is simple, and the calculation amount is saved.

[0064] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0065] As shown in Figure 2 , Figure 2 A structure schematic diagram of a DRC circuit provided by an embodiment of the present application is shown in Figure 2 The DRC circuit shown includes multiple parallel gain generation modules 11 and an output module 12.

[0066] Each of the gain generation modules 11 has a separate gain generator 111 and a gain smoothing processing module 112; the gain generation module 11 is used to perform gain processing on the input signal received thereby, to form an output gain, and to set a compression time and a release time based on the output gain; in the same gain generation module 11, the gain generator 111 is used to perform gain processing on the input signal of the gain generation module 11, and the gain smoothing processing module 112 is used to set a compression time and a release time based on the output gain of the gain generator 111. The output module 12 is used to output target data Dout based on the output gain of each of the gain generation modules 11 and the initial input data Din received by the DRC circuit. It is provided that the DRC circuit has N-stage gain generation modules 11, which are the first-stage gain generation module 11 to the N-stage gain generation module 11 in sequence, and have the first-stage output gain Gain(1) to the N-stage output gain Gain(N), respectively.

[0067] The DRC circuit in the embodiment of the present application can set different compression time and release time for each gain generation module 11 through the respective smoothing processing module 112, so that the compression time and release time of different gain generation modules 11 are separated, the processing of the digital audio signal is more flexible, the applicability is wider, and the tuning of the audio power amplifier and the user's auditory perception can be greatly improved.

[0068] Optionally, the DRC circuit comprises N gain generation modules 11, N is a positive integer greater than 1, each gain generation module corresponds to an output gain Gain, and the N gain generation modules 11 correspond to N output gains Gain, which are sequentially the first output gain Gain(1) to the Nth output gain Gain(N). The output gain of each gain generation module belongs to the logarithmic domain (i.e. log domain).

[0069] If N=2, the output module 12 is configured to calculate the sum of the first output gain and the second output gain, and calculate the target data Dout based on the sum and the initial input data Din. Specifically, the output module 12 is configured to calculate the sum of the first output gain Gain(1) and the second output gain Gain(2), calculate the linear domain value corresponding to the sum based on the anti-logarithm operation, calculate the product of the linear domain value and the initial input data Din, and take the product as the target data Dout.

[0070] If N is greater than 2, the output module 12 is configured to obtain the minimum value Min of the first output gain Gain(1) to the (N-1)th output gain Gain(N-1), calculate the sum of the minimum value Min and the Nth output gain Gain(N), and calculate the target data Dout based on the sum and the initial input data Din. Specifically, the output module 12 is configured to obtain the minimum value Min of the first output gain Gain(1) to the (N-1)th output gain Gain(N-1), calculate the sum of the minimum value Min and the Nth output gain Gain(N), calculate the linear domain value corresponding to the sum based on the anti-logarithm operation, calculate the product of the linear domain value and the initial input data Din, and take the product as the target data Dout.

[0071] In the embodiment of the present application, if N is greater than 2, each output gain Gain is in the log domain, and the initial input data Din is in the linear domain, so the minimum value is calculated first, then summed with the output gain Gain(N), and finally the summed value is multiplied by the initial input data Din to obtain the target data Dout. The unit of the log domain is dB, and the summation in the log domain is equivalent to multiplication in the linear domain, so the summation of the minimum value and the output gain Gain(N) is converted to the linear domain, and then multiplied by the initial input data Din to obtain the final target data Dout.

[0072] If each output gain Gain is in the linear domain, if N=2, the output module 12 is configured to calculate the product of the first output gain, the second output gain and the initial input data Din as the target data Dout; if N is greater than 2, the output module 12 is configured to obtain the minimum value of the first output gain to the (N-1)th output gain, calculate the product of the minimum value, the Nth output gain Gain(N) and the initial input data Din as the target data Dout. At this time, the target data Dout is equal to the product of the minimum value, the Nth output gain Gain(N) and the initial input data Din.

[0073] The implementation of the DRC circuit in the embodiment of the present application will be described below with the example that each output gain Gain is in the log domain. Obviously, the implementation of the DRC circuit corresponding to the linear domain can be obtained by making corresponding replacements based on the log domain.

[0074] As shown in Figure 3 , another structure of the DRC circuit provided in the embodiment of the present application is shown in Figure 3 , based on the mode shown in Figure 2 , the DRC circuit shown in Figure 3 has four gain generation modules 11, which are the first gain generation module to the fourth gain generation module, corresponding to the first output gain Gain(1) to the fourth output gain Gain(4). The output module 12 is configured to generate the target data Dout based on the minimum value Min of the first output gain Gain(1) to the third output gain Gain(3), the fourth output gain Gain(4) and the initial input data Din.

[0075] It should be noted that the number of parallel gain generation modules 11 in the DRC can be set based on requirements, and is not limited to four.

[0076] As shown in Figure 3As shown, the DRC circuit further includes an amplitude detection module 13, which detects the amplitude of the initial input data Din as the input signal for each of the gain generation modules 11. After the initial input data Din is input into the DRC circuit, it first passes through the amplitude detection module 13 to detect its amplitude in real time, and then sends the amplitude to each gain generation module 11. The amplitude detection module 13 may include a peak value calculation module for detecting the peak value of the initial input data Din; and / or a root mean square (RMS) calculation module for calculating the root mean square (RMS) value of the initial input data Din. The method for obtaining the amplitude of the initial input data Din can be set according to requirements, and this embodiment of the invention does not specifically limit it.

[0077] The output module 12 is used to calculate the minimum value Min based on the first output gain Gain (1) to the third output gain Gain (3), calculate the sum of the minimum value Min and the fourth output gain Gain (4), and calculate the product of the sum and the initial input data Din as the target data Dout.

[0078] like Figure 3 As shown, the output module 12 includes: a comparator 14, which is used to obtain the minimum value Min among the first output gain to the (N-1)th output gain; an adder 15, which is used to calculate the sum of the minimum value and the Nth output gain; and a multiplier 16, which is used to calculate the product of the linear domain value and the initial input data.

[0079] like Figure 4 As shown, if the DRC circuit has four gain generation modules 11, the gain generators (gain computers) 111 of the four gain generation modules 11 are respectively a limiter, a compressor, an expander, and a noise removal effector; the gain module to which the expander belongs is the fourth gain generation module.

[0080] In the DRC circuit described in this embodiment of the invention, the limiter, compressor, expander, and noise removal effect are processed simultaneously in parallel, and each of the limiter, compressor, expander, and noise removal effect has its own gain smoothing processing module 112. Each gain smoothing processing module 112 can be set with different compression and release times. The separation of different compression and release times has a significant improvement effect on the tuning of digital audio power amplifiers and the user's subjective listening experience.

[0081] The following sections will introduce the working principles of the limiter, compressor, expander, and noise removal effector in the DRC circuit, and compare their respective input and output gains.

[0082] The gain generator 111 is a compressor, including three parameters: a first threshold Threshold1, a first ratio parameter Ratio1, and a first knee parameter Knee1. The compressor is configured to start compressing an input signal thereof when the input signal exceeds the first threshold Threshold1, to output an output gain of the gain generator 111 thereof; wherein a degree of compression of the output gain relative to the input signal is related to the first ratio parameter Ratio1, and a smoothness of the output gain relative to the input signal is related to the first knee parameter Knee1. The first ratio parameter Ratio1 represents a slope of compressing the input signal, and the greater the first ratio parameter Ratio1, the greater the degree of compression. The first knee parameter Knee1 represents a smooth transition in a process of compressing the input signal, to ensure that a subjective listening effect of the processed signal is not too harsh.

[0083] As shown in Figure 4 , Figure 4 The gain transfer curve of the compressor in the DRC circuit according to the embodiments of the present application is shown in FIG. 4, wherein the horizontal axis represents an input amplitude, and the vertical axis represents an output amplitude. C1 represents an input signal, and the amplitude thereof is transferred from -100 dB to 0 dB. C2 represents an output gain after the input signal is processed by the compressor. Figure 5 It can be seen that, when the input signal is less than the first threshold Threshold1, the amplitude of the input signal is the same as that of the output gain, and C1 and C2 coincide. When the input signal is greater than the first threshold Threshold1, the output gain is compressed in proportion to the input signal at a slope of the first ratio parameter Ratio1. In the vicinity of the first threshold Threshold1, the output gain has a smooth transition part processed by the first knee parameter Knee1.

[0084] The gain generator 111 is a limiter, including two parameters: a second threshold Threshold2 and a second knee parameter Knee2. The limiter is configured to compress an input signal thereof into a fixed amplitude signal with an amplitude of the second threshold Threshold2 when the input signal exceeds the second threshold Threshold2, to output an output gain of the gain generator 111 thereof; wherein a smoothness of the output gain relative to the input signal is related to the second knee parameter Knee2. The second threshold Threshold2 represents a threshold for triggering the function of the limiter, and when the input signal exceeds the threshold, the limiter forcibly compresses the input signal into the fixed amplitude signal with the amplitude of the second threshold Threshold2. The second knee parameter Knee2 represents a smooth transition in a process of compressing the input signal, to ensure that a subjective listening effect of the processed signal is not too harsh.

[0085] As Figure 5 shown, Figure 5 the gain transform curve of the limiter in the DRC circuit described in the embodiments of the present application, the horizontal axis is the input amplitude, the vertical axis is the output amplitude, D1 represents the input signal, whose amplitude transforms from -100dB to 0dB, D2 represents the output gain after the limiter processing, by Figure 6 It can be seen that when the input signal is less than the second threshold Threshold2, the amplitude of the input signal and the output gain is the same, D1 and D2 coincide, when the input signal is greater than the second threshold Threshold2, the output gain is suppressed to a fixed amplitude signal, near the second threshold Threshold2, the output gain has a smooth transition part processed by the second smooth transition parameter Knee2.

[0086] The gain generator 111 is a noise removal effecter including three thresholds Threshold3, second ratio parameter Ratio2, third smooth transition parameter Knee3 and noise floor. The noise removal effecter is used to start suppressing the input signal when the input signal is less than the third threshold Threshold3, to output the output gain of its own gain generator 111; wherein the degree of suppression of the output gain relative to the input signal is related to the second ratio parameter number Ratio2, the smoothness of the output gain relative to the input signal is related to the third smooth transition parameter Knee3; the amplitude of the output gain is not less than the set minimum output gain amplitude. The third threshold Threshold3 represents the threshold that triggers the function of the noise removal effecter, less than the threshold, the noise removal effecter starts to suppress the output gain. The second ratio parameter number Ratio2 represents the slope of suppressing the input signal, the greater the second ratio parameter number Ratio2, the greater the degree of suppression. The third smooth transition parameter Knee3 represents the smooth transition of the signal in the process of being not suppressed and suppressed. The noise floor represents the minimum output output gain amplitude that the signal can be processed to.

[0087] As Figure 6 shown, Figure 6 the gain transform curve of the noise removal effecter in the DRC circuit described in the embodiments of the present application, the horizontal axis is the input amplitude, the vertical axis is the output amplitude, E1 represents the input signal, whose amplitude transforms from -100dB to 0dB, E2 represents the output gain after the noise removal effecter processing, by Figure 7It can be seen that when the input signal amplitude is less than the third threshold (Threshold3), the output gain begins to be suppressed according to the slope of the second proportional parameter (Ratio2). When the output gain is suppressed to the noise floor (-100dB), the output gain maintains the amplitude of the noise floor. When the input signal is greater than the third threshold (Threshold3), the output gain is the same as the input signal and remains unchanged. Near the third threshold (Threshold3), the output gain undergoes a smooth transition processed by the third smoothing transition parameter (Knee3).

[0088] The gain generator 111 is an extender, comprising four parameters: a fourth threshold (Threshold4), a compensation gain (MakeupGain), a fourth smooth transition parameter (Knee4), and a third proportional parameter (Ratio3). The extender, when its input signal exceeds the fourth threshold (Threshold4), amplifies the input signal based on the set compensation gain (MakeupGain) and the third proportional parameter (Ratio3) to output the gain of its corresponding gain generator 111. The smoothness of the output gain relative to the input signal is related to the fourth smooth transition parameter (Knee4). The fourth threshold (Threshold4) represents the threshold that triggers the extender's function; exceeding this threshold initiates the amplification of the input signal. The compensation gain (MakeupGain) represents the gain at which the input signal is amplified. The fourth smooth transition parameter (Knee4) represents the smooth transition between the signal not being amplified and the amplification process. The third proportional parameter (Ratio3) indicates that the input signal is gradually amplified at a certain slope until it reaches a compensation gain (MakeupGain).

[0089] like Figure 7 As shown, Figure 7 This is the gain transformation curve of the expander in the DRC circuit described in this embodiment of the invention. The horizontal axis represents the input amplitude, and the vertical axis represents the output amplitude. F1 represents the input signal, whose amplitude changes from -100dB to 0dB. F2 represents the output gain after processing by the expander. Figure 8 It can be seen that when the input signal amplitude is less than the fourth threshold (Threshold4), the output gain amplitude is the same as the input signal amplitude, and F1 and F2 coincide. When the input signal is greater than the fourth threshold (Threshold4), the output gain amplitude gradually increases relative to the input signal amplitude with the slope of the third proportional parameter (Ratio3) until the increase reaches a compensation gain (MakeupGain). At exactly the point where it increases to a compensation gain (MakeupGain), there is a smooth transition with an arc related to the fourth smoothing transition parameter (Knee4), ensuring a smooth transition at the inflection point of the output gain amplitude.

[0090] likeFigure 8 As shown in the figure, Figure 8 The input and output data comparison chart of the entire DRC circuit provided by the embodiment of the present application does not consider the influence of the gain smoothing processing module setting compression time and release time on gain adjustment, the horizontal axis is input amplitude, the vertical axis is output amplitude, G1 represents an input signal, and G2 represents the output gain of DRC processing in the multi-node DRC circuit. As shown in the figure, Figure 9 It can be seen that different amplitude input signals are processed by a noise removal effecter, an expander, a compressor, and a limiter. The number of noise removal effecters, expanders, compressors, and limiters is not limited, and the parallel order is not limited, so that the DRC circuit can realize multi-node output of the DRC circuit, has a simple structure, low calculation amount, and realizes the functions of the noise removal effecter, the expander, the compressor, and the limiter. The noise removal effecter, the expander, the compressor, and the limiter each have a separate gain smoothing processing module, so that the compression time and the release time thereof are independent of each other relative to other gain generators. In the tuning of a digital audio power amplifier, the sound signal can be processed in layers and at different speeds, greatly improving the subjective listening effect of the sound signal.

[0091] As can be seen from the above description, the DRC circuit described in the embodiment of the present application has a plurality of parallel gain generation modules 11, one gain generation module 11 corresponding to one node, constructing a single-stage DRC circuit with internal multi-node parallel connection, the compression time and the release time of each gain generation module 11 being independent of each other, the structure being simple, and the calculation amount being saved.

[0092] Based on the above various embodiments, another embodiment of the present application further provides an audio processing chip, which includes the DRC circuit of any one of the above embodiments, and the compression time and the release time of each gain generation module can be set separately through a plurality of parallel gain generation modules, the compression time and the release time of each gain generation module being independent of each other, the structure being simple, and the calculation amount being saved.

[0093] Based on the above various embodiments, another embodiment of the present application further provides an audio processing method, and the audio processing chip is the audio processing chip described in the above embodiments, and the dynamic range control circuit in the audio processing chip has a plurality of parallel gain generation modules.

[0094] The audio processing method is as shown in the figure, Figure 9 The audio processing method is as shown in the figure, ​ The flowchart of an audio processing method provided by the embodiment of the present application is shown, and the method includes:

[0095] Step S11: Each gain generation module performs gain processing on the input signal obtained by itself to form an output gain, and sets a compression time and a release time based on the output gain;

[0096] Step S12: Based on the output gain of each gain generation module and the initial input data of the dynamic range control circuit, output target data.

[0097] In the audio processing method, the dynamic range control circuit includes N gain generation modules, which are sequentially the first gain generation module to the Nth gain generation module, corresponding to the first output gain to the Nth output gain; N is a positive integer greater than 1.

[0098] If the output gain of each gain generation module belongs to a logarithmic domain, the method for calculating the target data includes: if N=2, calculating the sum of the first output gain and the second output gain, and calculating the target data based on the sum and the initial input data; if N is greater than 2, obtaining the minimum value among the first output gain to the N-1th output gain, calculating the sum of the minimum value and the Nth output gain, and calculating the target data based on the sum and the initial input data.

[0099] If the output gain of each gain generation module belongs to a linear domain, the method for calculating the target data includes: if N=2, calculating the product of the first output gain, the second output gain and the initial input data as the target data; if N is greater than 2, obtaining the minimum value among the first output gain to the N-1th output gain, calculating the product of the minimum value, the Nth output gain and the initial input data as the target data.

[0100] The implementation principle of the audio processing method can refer to the description of the above embodiments, which will not be repeated here. The audio processing method can set the compression time and the release time of each gain generation module through multiple parallel gain generation modules, and the compression time and the release time of each gain generation module are independent of each other, which is simple in structure and saves calculation amount.

[0101] Each embodiment in the specification is described in a progressive, parallel or combination of progressive and parallel manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other.

[0102] It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like are words of reference used to facilitate an understanding of the present application and do not connote orientations of the apparatus or elements thereof, unless otherwise indicated. When one component is said to be "connected" to another component, it can be directly connected to the other component or intervening components can be present therebetween.

[0103] It should also be noted that, as used in the present application, the terms "first", "second", etc. are used only to identify one entity from another, and do not imply a physical or logical relationship or order of such entities. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the a single element.

[0104] The above description of disclosed embodiments provides enabling disclosure sufficient for one of ordinary skill in the art to practice or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not to be limited to the embodiments set forth herein, but is to be accorded the widest scope consistent with the principles and novel features to a disclosed.

Claims

1. A dynamic range control circuit, characterized by, The application relates to a dynamic range control circuit, comprising: a plurality of parallel gain generation modules, each of which has a single gain generator and a gain smoothing processing module; the gain generation modules are used for gain processing of input signals received by the gain generation modules, forming output gains, and setting compression time and release time based on the output gains; in the same gain generation module, the gain generator is used for gain processing of input signals of the gain generation module, and the gain smoothing processing module is used for setting the compression time and the release time based on the output gain of the gain generator; an output module, which is used for outputting target data based on output gains of the gain generation modules and initial input data received by the dynamic range control circuit; the dynamic range control circuit specifically comprises N gain generation modules, which are sequentially the first gain generation module to the Nth gain generation module and correspond to the first output gain to the Nth output gain; N is a positive integer greater than 1; if the output gains of the gain generation modules belong to a logarithmic domain, if N=2, the output module is used for calculating the sum of the first output gain and the second output gain, calculating the target data based on the sum and the initial input data, if N is greater than 2, the output module is used for obtaining the minimum value among the first output gain to the N-1th output gain, calculating the sum of the minimum value and the Nth output gain, and calculating the target data based on the sum and the initial input data.

2. The dynamic range control circuit of claim 1, wherein, The application relates to a dynamic range control circuit, comprising: 4 gain generation modules, which are the first gain generation module to the fourth gain generation module and correspond to the first output gain to the fourth output gain; 3. The dynamic range control circuit of claim 1, wherein, the output module is used for generating the target data based on the minimum value among the first output gain to the third output gain, the fourth output gain and the initial input data. if N=2, the output module is used for calculating the sum of the first output gain and the second output gain, calculating the linear domain value corresponding to the sum based on an anti-logarithm operation, calculating the product of the linear domain value and the initial input data, and taking the product as the target data; 4. The dynamic range control circuit of claim 3, wherein, if N is greater than 2, the output module is used for obtaining the minimum value among the first output gain to the N-1th output gain, calculating the sum of the minimum value and the Nth output gain, calculating the linear domain value corresponding to the sum based on an anti-logarithm operation, calculating the product of the linear domain value and the initial input data, and taking the product as the target data. if N is greater than 2, the output module comprises: a comparator, which is used for obtaining the minimum value among the first output gain to the N-1th output gain; an adder, which is used for calculating the sum of the minimum value and the Nth output gain; 5. The dynamic range control circuit of claim 2, wherein, a multiplier, which is used for calculating the product of the linear domain value and the initial input data. the gain generators of the 4 gain generation modules are limiters, compressors, expanders and noise removal effectors respectively; 6. The dynamic range control circuit of claim 1, wherein, the gain generation module to which the expander belongs is the fourth gain generation module. if the output gains of the gain generation modules belong to a linear domain: If N=2, the output module is configured to calculate a product of the first output gain, the second output gain and the initial input data as the target data; If N is greater than 2, the output module is configured to obtain a minimum value among the first output gain to the (N-1)th output gain, calculate a product of the minimum value, the Nth output gain and the initial input data as the target data.

7. The dynamic range control circuit of claim 1, wherein, The gain generator is a compressor configured to start compressing the input signal when the input signal exceeds a first threshold value, to output the output gain of the gain generator to which the input signal belongs; wherein the degree of compression of the output gain relative to the input signal is related to a first proportional parameter, and the smoothness of the output gain relative to the input signal is related to a first smooth transition parameter.

8. The dynamic range control circuit of claim 1, wherein, The gain generator is a limiter configured to compress the input signal to a fixed amplitude signal with an amplitude of a second threshold value when the input signal exceeds a second threshold value, to output the output gain of the gain generator to which the input signal belongs; wherein the smoothness of the output gain relative to the input signal is related to a second smooth transition parameter.

9. The dynamic range control circuit of claim 1, wherein, The gain generator is a noise removal effecter configured to start compressing the input signal when the input signal is less than a third threshold value, to output the output gain of the gain generator to which the input signal belongs; wherein the degree of compression of the output gain relative to the input signal is related to a second proportional parameter, and the smoothness of the output gain relative to the input signal is related to a third smooth transition parameter.

10. The dynamic range control circuit of claim 1, wherein, The gain generator is an expander configured to start amplifying the input signal based on a set compensation gain and a third proportional parameter when the input signal exceeds a fourth threshold value, to output the output gain of the gain generator to which the input signal belongs; wherein the smoothness of the output gain relative to the input signal is related to a fourth smooth transition parameter.

11. Dynamic range control circuit according to any of the claims 1-10, characterized in that, Further comprising: An amplitude detection module configured to detect the amplitude of the initial input data as the input signal of each gain generation module.

12. An audio processing chip, characterized by Comprising: The dynamic range control circuit of claim 1-11.

13. An audio processing method of an audio processing chip, characterized by, The dynamic range control circuit in the audio processing chip has a plurality of parallel gain generation modules; The audio processing method comprises: Each gain generation module performs gain processing on the input signal obtained by itself to form an output gain, and sets a compression time and a release time based on the output gain; Based on the output gain of each gain generation module and the initial input data of the dynamic range control circuit, a target data is outputted; The dynamic range control circuit specifically comprises N gain generation modules, which are the first gain generation module to the Nth gain generation module in sequence, corresponding to the first output gain to the Nth output gain; N is a positive integer greater than 1. If the output gain of each of the gain generation modules belongs to a logarithmic domain, the method for calculating the target data comprises: if N=2, calculating the sum of the first output gain and the second output gain, and calculating the target data based on the sum and the initial input data; if N is greater than 2, obtaining the minimum value among the first output gain to the N-1th output gain, calculating the sum of the minimum value and the Nth output gain, and calculating the target data based on the sum and the initial input data.

14. The audio processing method of claim 13, wherein, If the output gain of each of the gain generation modules belongs to a linear domain; The method for calculating the target data comprises: If N=2, calculating the product of the first output gain, the second output gain and the initial input data as the target data; If N is greater than 2, obtaining the minimum value among the first output gain to the N-1th output gain, calculating the product of the minimum value, the Nth output gain and the initial input data as the target data.

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