Impedance matching circuit and GNSS module

Abstract

The present application provides an impedance matching circuit and a GNSS module, the circuit comprising: a first end is connected to the collector of a first transistor through a first inductor and a first resistor connected in series, and is connected to the base of the first transistor through a third resistor; the emitter of the first transistor is connected to the third end, is connected to ground through a second resistor and a second inductor connected in series, the base is grounded through a fourth resistor, and is connected to the collector of the second transistor; the second end is connected to the collector of the second transistor through a third inductor and a fifth resistor connected in series, and is connected to the base of the second transistor through a seventh resistor; the emitter of the second transistor is connected to the fourth end, is connected to ground through a sixth resistor and a fourth inductor connected in series, the base is grounded through an eighth resistor, and is connected to the collector of the first transistor; the collector of the first transistor is connected to the collector of the second transistor through a first capacitor. The present application can improve antenna performance and improve antenna efficiency on the basis of antenna miniaturization.

Description

Technical Field

[0001] The present application relates to the field of antennas, and in particular to an impedance matching circuit and a GNSS module. Background Art

[0002] The Global Navigation Satellite System (GNSS) includes the Global Positioning System (GPS), the BeiDou Navigation Satellite System (BDS), the GLONASS satellite navigation system, the Galileo satellite navigation system, etc. The antenna of the GNSS module in the mobile terminal is generally only used as a receiving end. Since the orbit altitude of the GNSS navigation satellite is very high, the signal it transmits becomes very weak when it reaches the mobile terminal, so the antenna performance of the GNSS module in the mobile terminal is very high.

[0003] The performance of an antenna is related to its electrical size. When the electrical size of an antenna decreases, the input reactance of the antenna increases, the radiation resistance decreases, and the quality factor Q value increases accordingly, which makes the antenna's operating frequency band narrower and its performance decreases. There are many ways to improve antenna performance, increase antenna efficiency and miniaturization. Commonly used technologies include loading technology, matching network technology, and conformal antenna technology. However, the above technologies have very limited effects on improving the impedance bandwidth of the antenna. Summary of the invention

[0004] The present application provides an impedance matching circuit and a GNSS module, which can improve antenna performance and increase antenna efficiency based on antenna miniaturization.

[0005] In a first aspect, an embodiment of the present application provides an impedance matching circuit, the circuit comprising:

[0006] The first end of the circuit is used to connect to a first DC voltage end and receive a DC voltage signal from the first DC voltage end;

[0007] The second end of the circuit is used to connect to the second DC voltage end and receive a DC voltage signal from the second DC voltage end;

[0008] The third end of the circuit is used to connect to a transmission line, and output a current signal through the transmission line;

[0009] The fourth end of the circuit is used to connect to the antenna and receive the current signal received by the antenna;

[0010] The first end of the circuit is connected to the collector of the first transistor through a first inductor and a first resistor connected in series, and is also connected to the base of the first transistor through a third resistor; the emitter of the first transistor is connected to the third end, and is also grounded through a second resistor and a second inductor connected in series; the base of the first transistor is grounded through a fourth resistor, and is also connected to the collector of the second transistor;

[0011] The second end of the circuit is connected to the collector of the second triode through the third inductor and the fifth resistor connected in series, and is connected to the base of the second triode through the seventh resistor; the emitter of the second triode is connected to the fourth end, and is also grounded through the sixth resistor and the fourth inductor connected in series; the base of the second triode is grounded through the eighth resistor, and is also connected to the collector of the first triode;

[0012] The collector of the first transistor is also connected to the collector of the second transistor via a first capacitor.

[0013] In a possible implementation manner, the first inductor and / or the second inductor and / or the third inductor and / or the fourth inductor are respectively implemented by two inductors connected in series.

[0014] The circuit can match the capacitive reactance of the antenna, thereby improving the antenna performance and the efficiency of the antenna on the basis of miniaturization of the antenna.

[0015] In a possible implementation manner, the circuit further includes:

[0016] The first terminal of the circuit is grounded via a second capacitor.

[0017] In a possible implementation manner, the circuit further includes:

[0018] A second terminal of the circuit is grounded via a third capacitor.

[0019] In a possible implementation manner, the emitter of the first transistor is connected to the third end, including:

[0020] The emitter of the first transistor is connected to the third end via a fourth capacitor.

[0021] In a possible implementation manner, the emitter of the second triode is connected to the fourth end, including:

[0022] The emitter of the second transistor is connected to the fourth end via a fifth capacitor.

[0023] In a possible implementation, the base of the first transistor is connected to the collector of the second transistor, including:

[0024] The base of the first transistor is connected to the collector of the second transistor via a sixth capacitor.

[0025] In a possible implementation, the base of the second transistor is connected to the collector of the first transistor, including:

[0026] The base of the second transistor is connected to the collector of the first transistor through a seventh capacitor.

[0027] In a possible implementation manner, the antenna is a PIFA antenna, and the fourth end of the circuit is used to connect the antenna, including:

[0028] The fourth terminal of the circuit is used to connect to the ground plane of the antenna.

[0029] In a second aspect, an embodiment of the present application further provides a GNSS module, comprising: an antenna, a receiver, and an impedance matching circuit as claimed in any one of claims 1 to 8, wherein:

[0030] The fourth end of the impedance matching circuit is connected to the antenna, and the third end is connected to the receiver through a transmission line.

[0031] In a possible implementation manner, the antenna is a PIFA antenna, and the fourth end of the impedance matching circuit is connected to the antenna, including: the fourth end of the impedance matching circuit is connected to the ground plane of the antenna. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 This is a schematic diagram of the Foster reactance function changing with frequency;

[0034] Figure 2A It is a schematic diagram of the relationship between the ideal negative inductive reactance and the frequency;

[0035] Figure 2B Schematic diagram of the relationship between the ideal negative capacitive reactance and frequency;

[0036] Figure 3A It is a performance diagram of a passive impedance matching network;

[0037] Figure 3B It is a performance diagram of non-Foster impedance matching network;

[0038] Figure 4A schematic structural diagram of an embodiment of a PIFA antenna applicable to the impedance matching circuit of the present application;

[0039] Figure 5 This is a schematic diagram of the structure of an embodiment of the impedance matching circuit of the present application;

[0040] Figure 6 This is a schematic structural diagram of another embodiment of the impedance matching circuit of the present application;

[0041] Figure 7 A schematic diagram of the circuit principle of the impedance matching circuit of the present application;

[0042] Figure 8 For this application Figure 7 An equivalent circuit diagram of the circuit principle diagram shown;

[0043] Fig. 9 This is a schematic diagram of the structure of an embodiment of a GNSS module of the present application. DETAILED DESCRIPTION

[0044] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0045] GNSS includes GPS, BDS, Glonass, Galileo and other systems. The antenna of the GNSS module in the mobile terminal is generally only used as the receiving end. Since the orbit altitude of the GNSS navigation satellite is very high, the signal it transmits becomes very weak when it reaches the mobile terminal, so the antenna performance of the GNSS module in the mobile terminal is very high.

[0046] The performance of an antenna is related to its electrical size. When the electrical size of an antenna decreases, the input reactance of the antenna increases, the radiation resistance decreases, and the quality factor Q value increases accordingly, making the antenna's operating frequency band narrower and the performance lower. There are many ways to improve antenna performance, increase antenna efficiency and miniaturization. Commonly used technologies include:

[0047] (1) Loading technology: placing reactance elements, impedance elements, dielectric materials, etc. in a certain part of the antenna to improve the current distribution in the antenna, thereby changing the resonant frequency of the antenna or reducing the height of the antenna at the same operating frequency, changing the antenna radiation pattern, and improving the antenna radiation efficiency.

[0048] (2) Matching network technology: Improve the matching between the antenna and the feeding system through lumped parameter networks, distributed parameter networks, and matching networks that combine lumped parameters and distributed parameters, thereby improving the matching bandwidth of the antenna;

[0049] (3) Composite antenna technology: Antennas of different frequency bands are organically combined and processed through back-end processing such as microwave circuits so that they can work normally within their respective frequency bands.

[0050] However, the above technical solutions are all passive solutions. Although they can be used for impedance matching of antennas and improving their impedance bandwidth, they are subject to the gain-bandwidth theory, namely the Bode-Fano criterion, and the effect of improving the impedance bandwidth of antennas is very limited.

[0051] To this end, the present application proposes an impedance matching circuit and an antenna, which can improve the impedance bandwidth of the antenna on the basis of miniaturization of the antenna, thereby improving the antenna performance and increasing the efficiency and miniaturization degree of the antenna.

[0052] The impedance matching circuit provided in the present application can be applied to electronic devices with GNSS modules, such as mobile phones, wearable devices (eg, smart watches, smart glasses, etc.), point of sales (POS) terminals, and car computers, etc. A GNSS module refers to a device used to support GNSS.

[0053] The impedance matching circuit provided in the present application is implemented using a Non-Foster circuit. The impedance matching circuit of the present application is a circuit structure that does not conform to the Foster reactance theorem and has an impedance conversion function. The circuit can offset the capacitive reactance of the antenna, thereby achieving good impedance matching, reducing energy loss caused by mismatch, and improving the receiving efficiency of the antenna; the smaller the size of the antenna, the larger the reactance, and the more difficult it is to do impedance matching. The impedance matching circuit of the present application can offset a large range of reactance, so when the impedance matching circuit of the present application is used as the matching circuit of the antenna, the antenna size can be greatly reduced while improving the performance and efficiency of the antenna.

[0054] The theoretical basis of the impedance matching circuit of this application is the non-Foster reactance theory, which is proposed on the basis of the Foster reactance theory. The Foster reactance theory means that the derivative of the reactance curve of the passive component with respect to the frequency is always a positive value, that is, they increase with the increase of the frequency, such as Figure 1 shown.

[0055] Reactive elements with non-Foster properties, such as negative inductance and negative capacitance, completely violate the Foster reactance theory. The relationship between the ideal negative inductive reactance and negative capacitive reactance and the frequency is as follows: Figure 2A and Figure 2B As shown, it can be seen that the non-Foster reactance element does not consume energy, it just realizes energy conversion. The non-Foster reactance element can only be equivalently generated by an active circuit, and the active circuit that can equivalently generate the non-Foster reactance element is also called a negative impedance converter (Negative Impedance Converter, NIC) circuit.

[0056] In order to further illustrate the advantages of non-Foster matching networks in impedance matching, this application provides a comparison between a passive impedance matching network and a non-Foster impedance matching network, such as Figure 3A and Figure 3B As shown in the figure. The matching objects of the two circuits are both electric dipole antennas. Figure 3A and Figure 3B In the figure, the black dotted line below the coordinate axis represents the capacitive reactance of the antenna, and the black solid line represents the matching results after using the two impedance matching methods. Figure 3A It means that the passive matching network with series inductance is used to match the impedance of the antenna. The matching result shows that the passive matching network can only make the reactance 0Ω at one frequency point, and the other frequency points still have a large reactance; Figure 3B The impedance matching results in show that the non-Foster impedance matching network can match the antenna reactance within the frequency band to make it 0Ω. Of course, the premise for obtaining this result is that it is assumed that the negative capacitive reactance equivalent to the non-Foster impedance matching network is in an ideal state, which is exactly the opposite of the antenna capacitive reactance.

[0057] Under ideal conditions, the non-Foster impedance matching network can completely transform the antenna input reactance, leaving only the resistance part of its input impedance. Although the non-Foster matching network cannot completely achieve complex conjugate matching for the antenna, it can transform the antenna into a pure resistance load, greatly improving the mismatch problem between the antenna and the signal source.

[0058] The impedance matching circuit of the present application can be used to match the capacitive reactance of an active planar inverted F (PIFA) antenna. In other words, the impedance matching circuit of the present application can be applied to a GNSS functional module provided with an active PIFA antenna.

[0059] Figure 4 The schematic diagram of the structure of an active PIFA antenna according to an embodiment of the present application is applicable to the impedance matching circuit, which includes: a ground plane 40 , a radiation unit 41 , a short-circuit metal sheet 42 and a probe 43 .

[0060] The radiation unit 41 is parallel to the ground plane 40 , the short-circuit metal sheet 42 connects the radiation unit 41 and the ground plane 40 , and the probe 43 is used for signal transmission.

[0061] It should be noted that Figure 4 The PIFA antenna structure shown is only an example, and the impedance matching circuit of the present application can also be applied to PIFA antennas of other structures.

[0062] Figure 5 A schematic diagram of the structure of the impedance matching circuit of the present application is shown in FIG. Figure 5 As shown, the circuit may include:

[0063] The first terminal A1 of the circuit is used to receive a DC voltage signal. Figure 5 In the embodiment, the first terminal A1 is connected to the positive electrode of the battery VCC1. Figure 5 In the example above, the battery VCC1 providing a DC voltage signal is used. In practical applications, the battery VCC1 may not be provided, but may be directly connected to a DC voltage terminal provided by the GNSS module, or a DC voltage terminal provided by the electronic device where the GNSS module is located.

[0064] The second terminal A2 of the circuit is used to receive a DC voltage signal. Figure 5 In the embodiment, the second terminal A2 is connected to the positive electrode of the battery VCC2. Figure 5 In the example above, the battery VCC2 providing a DC voltage signal is used. In practical applications, the battery VCC2 may not be provided, but may be directly connected to a DC voltage terminal provided by the GNSS module, or a DC voltage terminal provided by the electronic device where the GNSS module is located.

[0065] The third terminal A3 of the circuit is used to connect to the transmission line.

[0066] It should be noted that the above-mentioned transmission line can be used to connect the receiver of the GNSS module, so that the signal received by the antenna can be transmitted to the receiver through the transmission line.

[0067] It should be noted that the transmission line can also feed power into the impedance matching circuit through the third terminal A3. Figure 5 Indicated by AC power Pin.

[0068] The fourth terminal A4 of the circuit is used to connect to the antenna and receive the current signal received by the antenna. Figure 4 Taking the PIFA antenna shown as an example, the fourth terminal of the circuit may be connected to the ground plane 40 of the PIFA antenna.

[0069] The first terminal A1 is connected to the collector of the first transistor Q1 through the first inductor L1 and the first resistor R1 connected in series, and is connected to the base of the first transistor Q1 through the third resistor R3; the emitter of the first transistor Q1 is connected to the third terminal A3, and is also grounded through the second resistor R2 and the second inductor L2 connected in series; the base of the first transistor Q1 is grounded through the fourth resistor R4, and is also connected to the collector of the second transistor Q2;

[0070] The second end A2 is connected to the collector of the second triode Q2 through the third inductor L3 and the fifth resistor R5 connected in series, and is connected to the base of the second triode Q2 through the seventh resistor R7; the emitter of the second triode Q2 is connected to the fourth end A4, and is also grounded through the sixth resistor R6 and the fourth inductor L4 connected in series; the base of the second triode Q2 is grounded through the eighth resistor R8, and is also connected to the collector of the first triode Q1;

[0071] The collector of the first transistor Q1 is also connected to the collector of the second transistor Q2 via the first capacitor C1.

[0072] Optionally, the first inductor L1 and / or the second inductor L2 and / or the third inductor L3 and / or the fourth inductor L4 can be respectively realized by two inductors connected in series. Figure 6 In the embodiment, the first inductor L1 is realized by the inductor L11 and the inductor L12 connected in series, the second inductor L2 is realized by the inductor L21 and the inductor L22 connected in series, the third inductor L3 is realized by the inductor L31 and the inductor L32 connected in series, and the fourth inductor L4 is realized by the inductor L41 and the inductor L42 connected in series.

[0073] Alternatively, if Figure 6 As shown, the impedance matching circuit may further include: the first terminal A1 of the circuit is grounded via a second capacitor C2. The second capacitor C2 may play a role of direct current isolation.

[0074] Alternatively, if Figure 6 As shown, the impedance matching circuit may further include: the second end A2 of the circuit is grounded via a third capacitor C3. The third capacitor C3 may play a role of direct current isolation.

[0075] Alternatively, if Figure 6 As shown, the emitter of the first transistor Q1 is connected to the third terminal A3, which may include:

[0076] The emitter of the first transistor Q1 is connected to the third terminal A3 via the fourth capacitor C4.

[0077] Alternatively, if Figure 6 As shown, the emitter of the second transistor Q2 is connected to the fourth terminal A4, which may include:

[0078] The emitter of the second transistor Q2 is connected to the fourth terminal A4 via the fifth capacitor C5.

[0079] Alternatively, if Figure 6 As shown, the base of the first transistor Q1 is connected to the collector of the second transistor Q2, which may include: the base of the first transistor Q1 is connected to the collector of the second transistor Q2 via a sixth capacitor C6.

[0080] The sixth capacitor C6 can play a buffering role.

[0081] Alternatively, if Figure 6 As shown, the base of the second transistor Q2 is connected to the collector of the first transistor Q1 , which may include: the base of the second transistor Q2 is connected to the collector of the first transistor Q1 via a seventh capacitor C7 .

[0082] The seventh capacitor C7 can play a buffering role.

[0083] Alternatively, if Figure 6 As shown, the antenna connected to the fourth end A4 of the impedance matching circuit may be a PIFA antenna, and the fourth end A4 of the circuit is used to connect the antenna, which may include: the fourth end A4 of the circuit is connected to the ground plane of the PIFA antenna.

[0084] The working principle of the impedance matching circuit of the present application is described.

[0085] Figure 5 and Figure 6 The main structure of the impedance matching circuit of the present application is a floating negative impedance converter, that is, Figure 5 and Figure 6 The circuit diagram of this part of the circuit is shown below, excluding the antenna and AC power supply Pin. Figure 7 shown.

[0086] Figure 7 The equivalent circuit diagram of the circuit schematic shown is as follows Figure 8 shown.

[0087] right Figure 8 By analyzing the circuit, the following four formulas (1)(2)(3)(4) can be obtained by the node method:

[0088]

[0089]

[0090]

[0091]

[0092] Among them, Z L is the equivalent impedance of the circuit between the collector of the first transistor Q1 and the collector of the second transistor Q2, g m is the transconductance of the transistor (the first transistor or the second transistor), v1 is the voltage of the third terminal A3, v2 is the voltage of the fourth terminal A4, r e is the internal resistance of the transistor, i1 is the current received by the third terminal A3, i2 is the current received by the fourth terminal A4, v3 is the voltage at the collector of the first transistor Q1, and v3' is the voltage at the collector of the second transistor Q2.

[0093] Combining formulas (1), (2), (3), and (4) together, we can obtain the following formula (5). By analyzing formula (5), we can get Figure 8 As shown in the equivalent circuit diagram, when the transistor transconductance g m When the internal resistance of the transistor is large, e The transistor transconductance g m The reciprocal of each other, when the transistor transconductance g mWhen approaching infinity, it can be known from formula (5) that the input impedance is 0, that is, the floating negative impedance converter realizes the negative impedance conversion function.

[0094]

[0095] Among them, Z in is the equivalent impedance of the antenna and the impedance matching circuit at the third end A3.

[0096] The impedance matching circuit provided by the present application uses a non-Foster circuit with a non-Foster effect to match the PIFA antenna to achieve good impedance matching. Different PIFA antennas can have different design structures, and different structures must correspond to different impedances in the RF field. The impedance matching circuit provided by the present application only needs to adjust the capacitor in the circuit (for example, Figure 6 The fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, etc.), the inductor (for example Figure 6 Inductors L11 to L42, etc.) and resistors (e.g. Figure 6 The first resistor R1 to the ground resistor R8 in the circuit are used to adjust the capacitive negative impedance generated by the circuit, so that the impedance matching of the PIFA antenna can be achieved.

[0097] like Fig. 9 As shown, an embodiment of the present application provides a GNSS module 90, including: an antenna 91, an impedance matching circuit 92 and a receiver 93, wherein the fourth end of the impedance matching circuit 92 is connected to the antenna 91, and the third end is connected to the receiver 93 via a transmission line 94.

[0098] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0099] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0100] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0101] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory; hereinafter referred to as: ROM), random access memory (Random Access Memory; hereinafter referred to as: RAM), disk or optical disk, and other media that can store program codes.

[0102] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An impedance matching circuit, characterized in that: The circuit comprises: The first end of the circuit is used to connect to a first DC voltage end and receive a DC voltage signal from the first DC voltage end; The second end of the circuit is used to connect to the second DC voltage end and receive a DC voltage signal from the second DC voltage end; The third end of the circuit is used to connect to a transmission line, and output a current signal through the transmission line; The fourth end of the circuit is used to connect to the antenna and receive the current signal received by the antenna; The first end of the circuit is connected to the collector of the first transistor through a first inductor and a first resistor connected in series, and is also connected to the base of the first transistor through a third resistor; the emitter of the first transistor is connected to the third end, and is also grounded through a second resistor and a second inductor connected in series; the base of the first transistor is grounded through a fourth resistor, and is also connected to the collector of the second transistor; The second end of the circuit is connected to the collector of the second triode through the third inductor and the fifth resistor connected in series, and is also connected to the base of the second triode through the seventh resistor; the emitter of the second triode is connected to the fourth end, and is also grounded through the sixth resistor and the fourth inductor connected in series; the base of the second triode is grounded through the eighth resistor, and is also connected to the collector of the first triode; The collector of the first transistor is also connected to the collector of the second transistor via a first capacitor; Wherein, the antenna is a PIFA antenna, and the fourth end of the circuit is used to connect the antenna, including: The fourth terminal of the circuit is used to connect to the ground plane of the antenna.

2. The circuit according to claim 1, characterized in that The first inductor and / or the second inductor and / or the third inductor and / or the fourth inductor are respectively realized by two inductors connected in series.

3. The circuit according to claim 1, characterized in that The circuit further comprises: The first terminal of the circuit is grounded via a second capacitor.

4. The circuit according to claim 1, characterized in that The circuit further comprises: A second terminal of the circuit is grounded via a third capacitor.

5. The circuit according to claim 1, characterized in that The emitter of the first triode is connected to the third end, comprising: The emitter of the first transistor is connected to the third end via a fourth capacitor.

6. The circuit according to claim 1, characterized in that The emitter of the second triode is connected to the fourth end, comprising: The emitter of the second transistor is connected to the fourth end via a fifth capacitor.

7. The circuit according to claim 1, characterized in that The base of the first triode is connected to the collector of the second triode, comprising: The base of the first transistor is connected to the collector of the second transistor via a sixth capacitor.

8. The circuit according to claim 1, characterized in that The base of the second transistor is connected to the collector of the first transistor, comprising: The base of the second transistor is connected to the collector of the first transistor through a seventh capacitor.

9. A GNSS module, characterized in that: include: An antenna, a receiver and an impedance matching circuit as claimed in any one of claims 1 to 8, wherein: The fourth end of the impedance matching circuit is connected to the antenna, and the third end is connected to the receiver through a transmission line.

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