A dynamic component matching method and circuit suitable for SAR ADC

Abstract

The present invention discloses a dynamic element matching method and circuit suitable for SAR ADC, belonging to the field of integrated circuit technology. The dynamic element matching circuit includes: a quarter search module and a dynamic element selection circuit, the quarter search module is used to control the dynamic switching and jumping of sub-capacitors in the approximation process, and the dynamic element selection circuit is used to change the switching order of each sub-capacitor of the SAR ADC. The dynamic element selection circuit designed by the present invention has a simple structure and is easy to implement. It only needs to add a small number of gate circuits to realize the change of the connection order of the mismatched sub-capacitors in the circuit in a bit-by-bit cyclic manner with the clock; at the same time, combined with the quarter search module, compared with the traditional thermometer encoding method, it reduces the comparison cycle in the analog-to-digital conversion process, reduces the power consumption of the SAR ADC, and reduces the influence of the capacitor mismatch on the accuracy, making it more suitable for high-precision and low-power SAR ADC design scenarios.

Description

Technical Field

[0001] The present invention relates to a dynamic element matching method and circuit applicable to SAR ADC, belonging to the technical field of integrated circuits. Background Art

[0002] With the continuous development of signal processing technology, the conversion circuit between analog and digital signals has become a bottleneck restricting the performance of hybrid analog-digital systems. To meet the demand for low-power and high-precision analog-to-digital conversion, the Successive Approximation Register Analog-to-Digital Converter (SAR ADC) has become a research hotspot.

[0003] The common SAR ADC structure mainly includes the following parts: sampling switch, digital-to-analog converter (DAC) capacitor array, comparator and SAR logic control circuit.

[0004] The DAC capacitor array is a key module in SAR ADCs. It is typically composed of sub-capacitors with varying numbers of unit capacitors, with adjacent sub-capacitors forming a binary relationship and forming a capacitor array. Ideally, all capacitors are identical to their designed values. However, in real circuits, due to the inherent uncertainty in each manufacturing process, unit capacitors with the same design value may exhibit some mismatch, leading to capacitance mismatch between sub-capacitors. Capacitor mismatch can be categorized into two types based on the cause: systematic mismatch and random mismatch. Systematic mismatch refers to mismatch caused by process or environmental factors, resulting in capacitors with the same design value having the same effect. For example, manufacturing process parameters, including gate oxide thickness, lateral diffusion, oxide etching, and oxide doping charge, can cause variations, as well as mechanical stress and temperature gradients, leading to capacitance mismatch. Systematic mismatch can be estimated during the circuit design phase and is independent of capacitor size. It can be optimized or eliminated through certain layout techniques. Common layout techniques for eliminating systematic mismatch include symmetrical layout, interdigitated structures, and common centroid layout. Random mismatch refers to the completely random portion of mismatch. Random mismatch cannot be predicted during circuit design and is related to capacitor size. Generally speaking, the parameters of random mismatch follow a normal distribution. Larger capacitors reduce random mismatch, but excessively large capacitors increase area and power consumption. Therefore, for high-precision SAR ADCs, additional calibration of the DAC capacitor array mismatch is required.

[0005] Dynamic Element Matching (DEM) technology is a relatively common digital calibration method. It changes the connection method of actual non-ideal components so that the average value of the actual component values ​​over time is equal. By selecting the appropriate change method for the connection position of the mismatched components, the nonlinear distortion caused by the inherent mismatch between the actual components can be reduced or completely eliminated. According to the different processing methods, it is divided into deterministic DEM technology and random DEM technology. The former moves the distortion harmonic components outside the signal bandwidth, including clock averaging (CLA), digital weighted averaging (DWA) and individual averaging (ILA); the latter converts the distortion harmonic components into noise within the entire frequency band.

[0006] Among them, the CLA DEM technology periodically changes the action sequence of the mismatched components in the circuit in a rotating or jumping manner. The principle of the algorithm is shown in the attached Figure 1 As shown in the figure, after converting the upper three DAC bits into thermometer code, the capacitors for the upper three bits are composed of three identical sub-capacitors numbered 1 to 3. During the first analog-to-digital conversion, capacitors 2 and 3 represent the highest-order DAC capacitor, and capacitor 1 represents the second-highest-order sub-capacitor. During the second analog-to-digital conversion, capacitors 3 and 1 represent the highest-order DAC capacitor, and capacitor 2 represents the second-highest-order sub-capacitor. During the third analog-to-digital conversion, capacitors 1 and 2 represent the highest-order DAC capacitor, and capacitor 3 represents the second-highest-order sub-capacitor. And so on, after each three analog-to-digital conversions, the sub-capacitors that make up the upper three bits repeat. Over time, the matching error between the individual bits in the upper three bits will approach zero.

[0007] However, adopting this thermometer encoding method not only requires adding corresponding decoding circuits, but also adds a comparison process in each conversion cycle, which increases the power consumption of the system. Summary of the Invention

[0008] In order to solve the problems of increased conversion times and increased system power consumption in the prior art SAR ADC, the present invention provides a dynamic component matching method and circuit applicable to SAR ADC.

[0009] A first object of the present invention is to provide a dynamic element matching circuit suitable for a SAR ADC, for generating a switching signal for upper three-digit capacitors in a capacitor array of the SAR ADC and changing the switching order of the upper three-digit capacitors;

[0010] The dynamic element matching circuit includes: a four-way search module and a dynamic element selection circuit; the four-way search module and the dynamic element selection circuit are connected;

[0011] The four-point search module is used to obtain the ADC output binary code based on the comparison result of the SAR ADC, and generate a conversion clock signal and a comparison clock signal to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle;

[0012] The dynamic element selection circuit is configured to change the switching order of the sub-capacitors of the SAR ADC in a bit-by-bit cyclic manner based on the output result of the comparator and the conversion clock signal and comparison clock signal output by the quarter-search module, thereby causing the matching error between the sub-capacitors to approach zero over time.

[0013] Optionally, during the analog-to-digital conversion process, the quarter search module is used to generate a charge and discharge of VREF / 4 each time the sub-capacitor is switched, and to jump the comparison cycle, where VREF is a reference voltage of the SAR ADC;

[0014] The working process of the quadrant search module includes:

[0015] When the input voltage difference is less than VREF / 4, the output of the first comparison cycle is high, the first highest bit capacitor is switched to ground, the voltage at the comparator input is reduced by VREF / 4, and the output of the second comparison cycle is low; the switching of the upper three bits ends, and the switch jumps to the fourth bit.

[0016] When the input voltage difference is greater than or equal to VREF / 4 and less than VREF / 2, the output of the first comparison cycle is high, the first highest bit capacitor is switched to ground, and the comparator input voltage is reduced by VREF / 4; the output of the second comparison cycle is high, the second highest bit capacitor is switched to ground, and the comparator input voltage is reduced by VREF / 4; the output of the third comparison cycle is low, ending the switching of the upper three bits and jumping to switching from the fourth bit;

[0017] When the input voltage difference is greater than or equal to VREF / 2, the output of the first comparison cycle is high, the first highest sub-capacitor is switched to ground, and the voltage at the comparator input is reduced by VREF / 4; the output of the second comparison cycle is high, the second highest sub-capacitor is switched to ground, and the voltage at the comparator input is reduced by VREF / 4; the output of the third comparison cycle is high, the second highest sub-capacitor is switched to ground, and the voltage at the comparator input is reduced by VREF / 4, and the output of the fourth comparison cycle is low.

[0018] Optionally, the dynamic element selection circuit includes: a main cycle circuit and a sub-cycle circuit;

[0019] The main loop circuit includes: a ring shift register composed of a first flip-flop DFF1, a second flip-flop DFF2, and a third flip-flop DFF3;

[0020] The sub-cycle circuit includes: a ring shift register composed of a fourth flip-flop DFF4, a fifth flip-flop DFF5, and a sixth flip-flop DFF6;

[0021] The CLR terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the first clear signal CLR1, the CK terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the conversion clock signal CK1, the CLR terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the second clear signal CLR2, and the CK terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the comparison clock signal CK2;

[0022] The set signal A and the output signal Q3 of the third flip-flop DFF3 are connected to the D input terminal of the first flip-flop DFF1 through the first OR gate OR1;

[0023] The output signal Q1 of the first flip-flop DFF1 and the output signal of the sixth flip-flop DFF6 are connected to the D input terminal of the fourth flip-flop DFF4 through a second OR gate OR2; the output signal Q2 of the second flip-flop DFF2 and the output signal of the fourth flip-flop DFF4 are connected to the D input terminal of the fifth flip-flop DFF5 through a third OR gate OR3; the output signal Q3 of the third flip-flop DFF3 and the output signal of the fifth flip-flop DFF5 are connected to the input terminal of the sixth flip-flop DFF6 through a fourth OR gate OR4;

[0024] The output signals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are respectively the first switching signal clk1a, the second switching signal clk1b, and the third switching signal clk2 output by the dynamic element matching circuit, which are used to control the switching of the upper three capacitors of the capacitor array in the SAR ADC circuit.

[0025] Optionally, the set signal A, the first clear signal CLR1, the conversion clock signal CK1, the second clear signal CLR2, and the comparison clock signal CK2 are generated by the quarter search module.

[0026] Optionally, the working process of the dynamic element selection circuit includes:

[0027] Initial stage: under the action of the first clear signal CLR1 and the second clear signal CLR2 which are active at low levels, the output signals Q1, Q2, Q3 of the main cycle circuit and the output signals clk1a, clk1b, clk2 of the sub-cycle circuit are all at low levels;

[0028] First analog-to-digital conversion stage: the set signal A is high, the input of the first flip-flop DFF1 is high, and at the rising edge of the conversion clock signal CK1, the output signal Q1 of the first flip-flop DFF1 becomes high, and the main cycle output is 100;

[0029] S11: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 performs corresponding level switching according to the first comparison result;

[0030] S12: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the second comparison result;

[0031] S13: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the third comparison result;

[0032] Second analog-to-digital conversion stage: the output Q1 of the first flip-flop DFF1 is high, the input of the second flip-flop DFF2 is high, and at the rising edge of the conversion clock CK1, the output Q2 becomes high, and the main cycle output is 010;

[0033] S21: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the first comparison result;

[0034] S22: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the second comparison result;

[0035] S23: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the third comparison result;

[0036] The third analog-to-digital conversion stage: the output Q2 of the second flip-flop DFF2 is high, the input of the third flip-flop DFF3 is high, and at the rising edge of the conversion clock CK1, the output Q3 becomes high, and the main cycle output is 001;

[0037] S31: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the first comparison result;

[0038] S32: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the second comparison result;

[0039] S33: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 of the sub-cycle changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 performs corresponding level switching according to the third comparison result.

[0040] A second object of the present invention is to provide a dynamic element matching method suitable for a SAR ADC, wherein the dynamic element matching circuit switches high-three-digit capacitances of a capacitor array within an analog-to-digital conversion circuit. The method comprises:

[0041] First, a four-point search module is used to obtain an ADC output binary code based on the comparison result of the SAR ADC, and a conversion clock signal and a comparison clock signal are generated to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle;

[0042] Then, the dynamic element selection circuit changes the switching order of each sub-capacitor of the SAR ADC in a bit-by-bit cyclic manner based on the comparison result and the conversion clock signal and comparison clock signal output by the quadrant search module, so that the matching error between the sub-capacitors tends to zero over time.

[0043] The third object of the present invention is to provide a SAR analog-to-digital conversion circuit, which uses the above-mentioned dynamic element matching circuit to realize the switching of the upper three sub-capacitors of the capacitor array in the analog-to-digital conversion circuit, and uses SAR logic to switch the lower sub-capacitors except the upper three bits.

[0044] Optionally, the analog-to-digital conversion circuit includes: a P-side input terminal, a P-side capacitor array, a P-side action unit array; an N-side input terminal, an N-side capacitor array, an N-side action unit array; a comparator, a SAR logic module, a P-side sampling switch, and an N-side sampling switch;

[0045] The P-side action unit array and the N-side action unit array are composed of action switches, and realize the switching of the upper three-position sub-capacitors of the capacitor array according to the output signal of the dynamic element matching circuit, and control the switching of the lower sub-capacitors except the upper three-position sub-capacitors according to the output signal of the SAR logic module;

[0046] The lower plates of each sub-capacitor of the P-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the P-side action unit array, and the lower plates of each sub-capacitor of the N-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the N-side action unit array;

[0047] The P-side input terminal is respectively connected to the upper plate of each sub-capacitor of the P-side capacitor array and the positive input terminal of the comparator through the P-side sampling switch; the N-side input terminal is respectively connected to the upper plate of each sub-capacitor of the N-side capacitor array and the negative input terminal of the comparator through the N-side sampling switch.

[0048] Optionally, the high-position sub-capacitors of the P-side capacitor array include: a first high-position sub-capacitor CP1a on the P-side, a second high-position sub-capacitor CP1b on the P-side, and a third high-position sub-capacitor CP2 on the P-side;

[0049] The P-side first high-position sub-capacitor CP1a is switched between the reference voltage VREF and ground via the P-side first action switch SP1a; the P-side second high-position sub-capacitor CP1b is switched between the reference voltage VREF and ground via the P-side second action switch SP1b; the P-side third high-position sub-capacitor CP2 is switched between the reference voltage VREF and ground via the P-side third action switch SP2;

[0050] The P-side first action switch SP1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the P-side second action switch SP1b is switched according to the second switching signal clk1b; and the P-side third action switch SP2 is switched according to the third switching signal clk2.

[0051] Optionally, the upper three sub-capacitors of the N-side capacitor array include: an N-side first upper sub-capacitor CN1a, an N-side second upper sub-capacitor CN1b, and an N-side third upper sub-capacitor CN2;

[0052] The N-side first high-position sub-capacitor CN1a is connected to the reference voltage VREF and grounded via the N-side first action switch SN1a; the N-side second high-position sub-capacitor CN1b is connected to the reference voltage VREF and grounded via the N-side second action switch SN1b; the N-side third high-position sub-capacitor CN2 is connected to the reference voltage VREF and grounded via the N-side third action switch SN2;

[0053] The N-side first action switch SN1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the N-side second action switch SN1b is switched according to the second switching signal clk1b; and the N-side third action switch SN2 is switched according to the third switching signal clk2.

[0054] Optionally, when the sampling phase of the analog-to-digital conversion circuit ends and the P-terminal input voltage VIP is greater than the N-terminal input voltage VIN, the working process of the first analog-to-digital conversion phase of the analog-to-digital conversion circuit includes:

[0055] When VIP is less than VIN+(VREF / 4), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0056] When the input voltage of the capacitor array at the P terminal becomes VIP-(VREF / 4) less than VIN, the output of the second comparison cycle is low. The four-point search module controls the switching of the remaining two sub-capacitors CP1b and CP2 in the upper three bits and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the upper three digital outputs B1, B2, and B3 are 100.

[0057] When VIP is greater than or equal to VIN+(VREF / 4) and less than VIN+(VREF / 2), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0058] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND.

[0059] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is less than VIN. The output of the third comparison cycle is low. The four-point search module controls the switching of sub-capacitor CP2 and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the traditional binary SAR logic control method, and the output of the upper three digital outputs B1, B2, and B3 are 101;

[0060] When VIP is greater than or equal to VIN+(VREF / 2) and less than VIN+VREF, in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0061] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND.

[0062] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is greater than VIN. The output of the third comparison cycle is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND.

[0063] The input voltage of the P-terminal capacitor array becomes VIP-(VREF 3 / 4), and the output of the fourth comparison cycle is a high level or a low level; the four-point search module controls the switching of sub-capacitor CP3, and the subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the output of the upper three digital outputs B1, B2, and B3 are 111 or 110.

[0064] The beneficial effects of the present invention are:

[0065] By designing a dynamic component selection circuit, the switching order of the high-order three-bit sub-capacitors in the capacitor array of the SAR ADC is changed. The designed dynamic component selection circuit has a simple structure and is easy to implement. Only a small number of gate circuits are needed to change the connection order of the mismatched sub-capacitors in the circuit in a bit-by-bit manner according to the clock. At the same time, combined with the four-point search module, compared with the traditional thermometer encoding method, not only does it not require additional decoding circuits, but it also reduces the comparison cycle during the analog-to-digital conversion process, effectively reducing the power consumption of the SAR analog-to-digital conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0067] Figure 1 This is a schematic diagram of clock averaging dynamic component matching technology.

[0068] Figure 2 This is a schematic diagram of the structure of a dynamic element matching circuit provided in Example 1 of the present invention.

[0069] Figure 3 This is a schematic diagram of the structure of a dynamic element selection circuit provided in the second embodiment of the present invention.

[0070] Figure 4 This is a schematic diagram of the conversion logic of the quadrant search module provided in the second embodiment of the present invention.

[0071] Figure 5 This is a structural diagram of a SAR analog-to-digital conversion circuit provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0072] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0073] First, the basic theoretical knowledge involved in this application is introduced as follows:

[0074] A successive approximation analog-to-digital converter (SAR ADC) consists of four main modules: a sample-and-hold circuit, a comparator module, a DAC capacitor array, and a successive approximation logic module. The analog signal to be measured passes through the sample-and-hold circuit and is then compared with a reference analog signal at the negative input of the comparator. Based on the comparison result ("0" or "1"), the successive approximation logic module controls the switching of the DAC capacitor array, adjusting the output voltage of the DAC capacitor array. After N comparisons, the analog signal is converted into an N-bit digital output.

[0075] Dynamic element matching (DEM) technology is a commonly used digital calibration method. It changes the connection method of actual non-ideal components to make the average value of the actual component values ​​equal over time. By selecting the appropriate method to change the connection position of the mismatched components, the nonlinear distortion caused by the inherent mismatch between the actual components can be reduced or completely eliminated. Depending on the processing method, it can be divided into deterministic DEM technology and stochastic DEM technology. The former moves the distortion harmonic components outside the signal bandwidth, including clock averaging (CLA), digital weighted averaging (DWA), and individual averaging (ILA); the latter converts the distortion harmonic components into noise within the entire frequency band.

[0076] Example 1:

[0077] This embodiment provides a dynamic element matching circuit suitable for a SAR ADC, which is used to generate a switching signal for upper three-digit capacitors in a capacitor array of the SAR ADC and change the switching order of the upper three-digit capacitors;

[0078] The dynamic element matching circuit includes: a four-way search module and a dynamic element selection circuit; the four-way search module and the dynamic element selection circuit are connected;

[0079] The four-point search module is used to obtain the ADC output binary code based on the comparison result of the SAR ADC, and generate a conversion clock signal and a comparison clock signal to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle;

[0080] The dynamic element selection circuit is configured to change the switching order of the sub-capacitors of the SAR ADC in a bit-by-bit cyclic manner based on the output result of the comparator and the conversion clock signal and comparison clock signal output by the quarter-search module, thereby causing the matching error between the sub-capacitors to approach zero over time.

[0081] Example 2

[0082] This embodiment provides a dynamic element matching circuit suitable for a SAR ADC, which is used to generate a switching signal for upper three-digit capacitors in a capacitor array of the SAR ADC and change the switching order of the upper three-digit capacitors;

[0083] The dynamic element matching circuit includes: a four-division search module and a dynamic element selection circuit; the four-division search module and the dynamic element selection circuit are connected;

[0084] The quadrant search module is implemented using Verilog code, which is synthesized into a digital circuit for obtaining an ADC output binary code based on the comparison result of the SAR ADC, and generating a conversion clock signal and a comparison clock signal to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle;

[0085] During the analog-to-digital conversion process, the quarter-search module is used to generate a charge and discharge of VREF / 4 each time the sub-capacitor is switched, and to jump the comparison cycle. The VREF is the reference voltage of the SAR ADC.

[0086] The working process of the quarter search module includes:

[0087] When the input voltage difference is less than VREF / 4, the output of the first comparison cycle is high, the first highest bit capacitor is switched to ground, the voltage at the comparator input decreases by VREF / 4, and the output of the second comparison cycle is low. The switching of the upper three bits ends, and the circuit jumps to switching starting from the fourth bit. In this case, two comparison cycles are reduced compared to the thermometer encoding method.

[0088] When the input voltage difference is greater than or equal to VREF / 4 and less than VREF / 2, the output of the first comparison cycle is high, the first highest-order capacitor is switched to ground, and the voltage at the comparator input is reduced by VREF / 4; the output of the second comparison cycle is high, the second highest-order capacitor is switched to ground, and the voltage at the comparator input is reduced by VREF / 4; the output of the third comparison cycle is low, ending the switching of the upper three bits and jumping to switching starting from the fourth bit; in this case, one comparison cycle is reduced compared to the thermometer encoding method.

[0089] When the input voltage difference is greater than or equal to VREF / 2, the output of the first comparison cycle is high, switching the first highest-order capacitor to ground, and reducing the comparator input voltage by VREF / 4. The output of the second comparison cycle is high, switching the second highest-order capacitor to ground, and reducing the comparator input voltage by VREF / 4. The output of the third comparison cycle is high, switching the second highest-order capacitor to ground, and reducing the comparator input voltage by VREF / 4. The output of the fourth comparison cycle is low. In this case, the comparison cycle is encoded in the same way as a thermometer.

[0090] Therefore, in the first and second cases, the comparison cycle of this scheme is shorter than that of the thermometer encoding method, and the power consumption is correspondingly reduced.

[0091] The dynamic element selection circuit is used to change the switching order of each sub-capacitor of the SAR ADC in a bit-by-bit cyclic manner based on the output result of the comparator and the conversion clock signal and comparison clock signal output by the quarter-search module, so that the matching error between the sub-capacitors tends to zero over time.

[0092] The dynamic element selection circuit includes: a main cycle circuit and a sub-cycle circuit;

[0093] The main loop circuit includes: a ring shift register composed of a first flip-flop DFF1, a second flip-flop DFF2, and a third flip-flop DFF3;

[0094] The sub-cycle circuit includes: a ring shift register composed of a fourth flip-flop DFF4, a fifth flip-flop DFF5, and a sixth flip-flop DFF6;

[0095] The CLR terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the first clear signal CLR1, the CK terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the conversion clock signal CK1, the CLR terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the second clear signal CLR2, and the CK terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the comparison clock signal CK2;

[0096] The set signal A and the output signal Q3 of the third flip-flop DFF3 are connected to the D input terminal of the first flip-flop DFF1 through the first OR gate OR1;

[0097] The output signal Q1 of the first flip-flop DFF1 and the output signal of the sixth flip-flop DFF6 are connected to the D input terminal of the fourth flip-flop DFF4 through the second OR gate OR2; the output signal Q2 of the second flip-flop DFF2 and the output signal of the fourth flip-flop DFF4 are connected to the D input terminal of the fifth flip-flop DFF5 through the third OR gate OR3; the output signal Q3 of the third flip-flop DFF3 and the output signal of the fifth flip-flop DFF5 are connected to the input terminal of the sixth flip-flop DFF6 through the fourth OR gate OR4;

[0098] The output signals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are respectively the first switching signal clk1a, the second switching signal clk1b, and the third switching signal clk2 output by the dynamic element matching circuit, which are used to control the switching of the upper three capacitors of the capacitor array in the SAR ADC circuit.

[0099] The set signal A, the first clear signal CLR1, the conversion clock signal CK1, the second clear signal CLR2, and the comparison clock signal CK2 are generated by the quarter search module.

[0100] The working process of the dynamic component selection circuit includes:

[0101] Initial stage: under the action of the first clear signal CLR1 and the second clear signal CLR2 which are active at low levels, the output signals Q1, Q2, Q3 of the main cycle circuit and the output signals clk1a, clk1b, clk2 of the sub-cycle circuit are all at low levels;

[0102] First analog-to-digital conversion stage: the set signal A is high, the input of the first flip-flop DFF1 is high, and at the rising edge of the conversion clock signal CK1, the output signal Q1 of the first flip-flop DFF1 becomes high, and the main cycle output is 100;

[0103] S11: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 performs corresponding level switching according to the first comparison result;

[0104] S12: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the second comparison result;

[0105] S13: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the third comparison result;

[0106] Second analog-to-digital conversion stage: the output Q1 of the first flip-flop DFF1 is high, the input of the second flip-flop DFF2 is high, and at the rising edge of the conversion clock CK1, the output Q2 becomes high, and the main cycle output is 010;

[0107] S21: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the first comparison result;

[0108] S22: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the second comparison result;

[0109] S23: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the third comparison result;

[0110] The third analog-to-digital conversion stage: the output Q2 of the second flip-flop DFF2 is high, the input of the third flip-flop DFF3 is high, and at the rising edge of the conversion clock CK1, the output Q3 becomes high, and the main cycle output is 001;

[0111] S31: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the first comparison result;

[0112] S32: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the second comparison result;

[0113] S33: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 of the sub-cycle changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 performs corresponding level switching according to the third comparison result.

[0114] Similarly, after every three analog-to-digital conversions, the sub-capacitors that make up the upper three digits are repeated.

[0115] Example 3

[0116] This embodiment provides a SAR analog-to-digital conversion circuit, such as Figure 3 As shown, the dynamic element matching circuit described in the second embodiment is used to switch the upper three sub-capacitors of the capacitor array in the analog-to-digital conversion circuit, and SAR logic is used to switch the lower sub-capacitors except the upper three sub-capacitors.

[0117] The analog-to-digital conversion circuit of this embodiment includes:

[0118] P-side input terminal, P-side capacitor array, P-side action unit array; N-side input terminal, N-side capacitor array, N-side action unit array; comparator, SAR logic module, P-side sampling switch, N-side sampling switch;

[0119] The P-side action unit array and the N-side action unit array are composed of action switches, and realize the switching of the upper three-position sub-capacitors of the capacitor array according to the output signal of the dynamic element matching circuit, and control the switching of the lower sub-capacitors except the upper three-position sub-capacitors according to the output signal of the SAR logic module;

[0120] The lower plates of each sub-capacitor of the P-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the P-side action unit array, and the lower plates of each sub-capacitor of the N-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the N-side action unit array;

[0121] The P-side input terminal is respectively connected to the upper plate of each sub-capacitor of the P-side capacitor array and the positive input terminal of the comparator through the P-side sampling switch; the N-side input terminal is respectively connected to the upper plate of each sub-capacitor of the N-side capacitor array and the negative input terminal of the comparator through the N-side sampling switch.

[0122] The high three-position sub-capacitor of the P-side capacitor array includes: a P-side first high-position sub-capacitor CP1a, a P-side second high-position sub-capacitor CP1b, and a P-side third high-position sub-capacitor CP2;

[0123] The P-side first high-position sub-capacitor CP1a is switched between the reference voltage VREF and ground via the P-side first action switch SP1a; the P-side second high-position sub-capacitor CP1b is switched between the reference voltage VREF and ground via the P-side second action switch SP1b; the P-side third high-position sub-capacitor CP2 is switched between the reference voltage VREF and ground via the P-side third action switch SP2;

[0124] The P-side first action switch SP1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the P-side second action switch SP1b is switched according to the second switching signal clk1b; and the P-side third action switch SP2 is switched according to the third switching signal clk2.

[0125] The high three-position sub-capacitor of the N-side capacitor array includes: an N-side first high-position sub-capacitor CN1a, an N-side second high-position sub-capacitor CN1b, and an N-side third high-position sub-capacitor CN2;

[0126] The N-side first high-position sub-capacitor CN1a is connected to the reference voltage VREF and grounded via the N-side first action switch SN1a; the N-side second high-position sub-capacitor CN1b is connected to the reference voltage VREF and grounded via the N-side second action switch SN1b; the N-side third high-position sub-capacitor CN2 is connected to the reference voltage VREF and grounded via the N-side third action switch SN2;

[0127] The N-side first action switch SN1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the N-side second action switch SN1b is switched according to the second switching signal clk1b; and the N-side third action switch SN2 is switched according to the third switching signal clk2.

[0128] When the P-terminal input voltage VIP is greater than the N-terminal input voltage VIN, the working process of the analog-to-digital conversion circuit of this embodiment is as follows:

[0129] The first analog-to-digital conversion stage:

[0130] When VIP is less than VIN+(VREF / 4), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0131] When the input voltage of the capacitor array at the P terminal becomes VIP-(VREF / 4) less than VIN, the output of the second comparison cycle is low. The four-point search module controls the switching of the remaining two sub-capacitors CP1b and CP2 in the upper three bits and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the upper three digital outputs B1, B2, and B3 are 100.

[0132] When VIP is greater than or equal to VIN+(VREF / 4) and less than VIN+(VREF / 2), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0133] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND.

[0134] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is less than VIN. The output of the third comparison cycle is low. The four-point search module controls the end of the switching of sub-capacitor CP2 and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the traditional binary SAR logic control method, and the output of the upper three digital outputs B1, B2, and B3 are 101;

[0135] When VIP is greater than or equal to VIN+(VREF / 2) and less than VIN+VREF, in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND;

[0136] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND.

[0137] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is greater than VIN. The output of the third comparison cycle is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND.

[0138] The input voltage of the P-terminal capacitor array becomes VIP-(VREF 3 / 4), and the output of the fourth comparison cycle is a high level or a low level; the four-point search module controls the switching of sub-capacitor CP3, and the subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the output of the upper three digital outputs B1, B2, and B3 are 111 or 110.

[0139] Second analog-to-digital conversion stage:

[0140] When VIP is less than VIN+(VREF / 4), in the first comparison cycle, the comparator output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND;

[0141] When the input voltage of the capacitor array at the P terminal becomes VIP-(VREF / 4) less than VIN, the output of the second comparison cycle is low. The four-point search module controls the switching of the remaining two sub-capacitors CP1a and CP2 in the upper three bits and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the upper three digital outputs B1, B2, and B3 are 100.

[0142] When VIP is greater than or equal to VIN+(VREF / 4) and less than VIN+(VREF / 2), in the first comparison cycle, the comparator output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND;

[0143] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND.

[0144] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is less than VIN. The output of the third comparison cycle is low. The four-point search module controls the end of switching of sub-capacitor CP1a and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the traditional binary SAR logic control method, and the output of the upper three digital outputs B1, B2, and B3 are 101;

[0145] When VIP is greater than or equal to VIN+(VREF / 2) and less than VIN+VREF, in the first comparison cycle, the comparator output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND;

[0146] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND.

[0147] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is greater than VIN. The output of the third comparison cycle is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND.

[0148] The input voltage of the P-terminal capacitor array becomes VIP-(VREF 3 / 4), and the output of the fourth comparison cycle is a high level or a low level; the four-point search module controls the switching of sub-capacitor CP3, and the subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the output of the upper three digital outputs B1, B2, and B3 are 111 or 110.

[0149] The third analog-to-digital conversion stage:

[0150] When VIP is less than VIN+(VREF / 4), in the first comparison cycle, the comparator output is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND;

[0151] When the input voltage of the capacitor array at the P terminal becomes VIP-(VREF / 4) less than VIN, the output of the second comparison cycle is low. The four-point search module controls the switching of the remaining two sub-capacitors CP1a and CP1b in the upper three bits and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the upper three digital outputs B1, B2, and B3 are 100.

[0152] When VIP is greater than or equal to VIN+(VREF / 4) and less than VIN+(VREF / 2), in the first comparison cycle, the comparator output is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND;

[0153] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND.

[0154] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is less than VIN. The output of the third comparison cycle is low. The four-point search module controls the end of switching of sub-capacitor CP1b and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the traditional binary SAR logic control method, and the output of the upper three digital outputs B1, B2, and B3 are 101;

[0155] When VIP is greater than or equal to VIN+(VREF / 2) and less than VIN+VREF, in the first comparison cycle, the comparator output is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND;

[0156] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND.

[0157] The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is greater than VIN. The output of the third comparison cycle is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND.

[0158] The input voltage of the P-terminal capacitor array becomes VIP-(VREF 3 / 4), and the output of the fourth comparison cycle is a high level or a low level; the four-point search module controls the switching of sub-capacitor CP3, and the subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the output of the upper three digital outputs B1, B2, and B3 are 111 or 110.

[0159] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0160] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dynamic element matching circuit suitable for SAR ADC, characterized in that: Used to generate a switching signal for the upper three-digit capacitors in the capacitor array of the SAR ADC and change the switching order of the upper three-digit capacitors; The dynamic element matching circuit includes: a four-way search module and a dynamic element selection circuit; the four-way search module and the dynamic element selection circuit are connected; The four-point search module is used to obtain the ADC output binary code based on the comparison result of the SAR ADC, and generate a conversion clock signal and a comparison clock signal to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle; The dynamic element selection circuit is configured to change the switching order of the sub-capacitors of the SAR ADC in a bit-by-bit cyclic manner based on the comparison result and the conversion clock signal and comparison clock signal output by the quarter-search module, so that the matching error between the sub-capacitors tends to zero over time; The dynamic element selection circuit includes: a main cycle circuit and a sub-cycle circuit; The main loop circuit includes: a ring shift register composed of a first flip-flop DFF1, a second flip-flop DFF2, and a third flip-flop DFF3; The sub-cycle circuit includes: a ring shift register composed of a fourth flip-flop DFF4, a fifth flip-flop DFF5, and a sixth flip-flop DFF6; The CLR terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the first clear signal CLR1, the CK terminals of the first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are connected to the conversion clock signal CK1, the CLR terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the second clear signal CLR2, and the CK terminals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are connected to the comparison clock signal CK2; The set signal A and the output signal Q3 of the third flip-flop DFF3 are connected to the D input terminal of the first flip-flop DFF1 through the first OR gate OR1; The output signal Q1 of the first flip-flop DFF1 and the output signal of the sixth flip-flop DFF6 are connected to the D input terminal of the fourth flip-flop DFF4 through a second OR gate OR2; the output signal Q2 of the second flip-flop DFF2 and the output signal of the fourth flip-flop DFF4 are connected to the D input terminal of the fifth flip-flop DFF5 through a third OR gate OR3; the output signal Q3 of the third flip-flop DFF3 and the output signal of the fifth flip-flop DFF5 are connected to the D input terminal of the sixth flip-flop DFF6 through a fourth OR gate OR4; The output signals of the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the sixth flip-flop DFF6 are respectively the first switching signal clk1a, the second switching signal clk1b, and the third switching signal clk2 output by the dynamic element matching circuit, which are used to control the switching of the upper three capacitors of the capacitor array in the SAR ADC circuit.

2. The dynamic element matching circuit according to claim 1, wherein: During analog-to-digital conversion, the four-point search module is used to generate a charge and discharge of VREF / 4 each time the sub-capacitor is switched, and to jump the comparison cycle, where VREF is the reference voltage of the SAR ADC; The working process of the quadrant search module includes: When the input voltage difference of the SAR ADC is less than VREF / 4, the output of the first comparison cycle is high, the first highest bit capacitor is switched to ground, the voltage at the comparator input is reduced by VREF / 4, and the output of the second comparison cycle is low; the switching of the upper three bits ends, and the switch jumps to the fourth bit. When the SAR ADC input voltage difference is greater than or equal to VREF / 4 and less than VREF / 2, the output of the first comparison cycle is high, the first highest bit capacitor is switched to ground, and the comparator input voltage decreases by VREF / 4; the output of the second comparison cycle is high, the second highest bit capacitor is switched to ground, and the comparator input voltage decreases by VREF / 4; the output of the third comparison cycle is low, ending the switching of the upper three bits and jumping to switching from the fourth bit. When the input voltage difference of the SAR ADC is greater than or equal to VREF / 2, the output of the first comparison cycle is high, the first highest sub-capacitor is switched to ground, and the comparator input voltage is reduced by VREF / 4; the output of the second comparison cycle is high, the second highest sub-capacitor is switched to ground, and the comparator input voltage is reduced by VREF / 4; the output of the third comparison cycle is high, the second highest sub-capacitor is switched to ground, and the comparator input voltage is reduced by VREF / 4, and the output of the fourth comparison cycle is low. In this case, no jump is required, and the bits are switched from high to low in sequence. 3 . The dynamic element matching circuit according to claim 2 , wherein the set signal A, the first clear signal CLR1 , the conversion clock signal CK1 , the second clear signal CLR2 , and the comparison clock signal CK2 are generated by the quarter search module.

4. The dynamic element matching circuit according to claim 3, characterized in that: The working process of the dynamic element selection circuit includes: Initial stage: under the action of the first clear signal CLR1 and the second clear signal CLR2 which are active at low levels, the output signals Q1, Q2, Q3 of the main cycle circuit and the output signals clk1a, clk1b, clk2 of the sub-cycle circuit are all at low levels; First analog-to-digital conversion stage: the set signal A is high, the input of the first flip-flop DFF1 is high, and at the rising edge of the conversion clock signal CK1, the output signal Q1 of the first flip-flop DFF1 becomes high, and the main cycle output is 100; S11: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 performs corresponding level switching according to the first comparison result; S12: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the second comparison result; S13: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the third comparison result; Second analog-to-digital conversion stage: the output Q1 of the first flip-flop DFF1 is high, the input of the second flip-flop DFF2 is high, and at the rising edge of the conversion clock CK1, the output Q2 becomes high, and the main cycle output is 010; S21: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 switches its level accordingly according to the first comparison result; S22: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the second comparison result; S23: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the third comparison result; The third analog-to-digital conversion stage: the output Q2 of the second flip-flop DFF2 is high, the input of the third flip-flop DFF3 is high, and at the rising edge of the conversion clock CK1, the output Q3 becomes high, and the main cycle output is 001; S31: In the first comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the sixth flip-flop DFF6 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the sixth flip-flop DFF6 switches its level accordingly according to the first comparison result; S32: In the second comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fourth flip-flop DFF4 changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fourth flip-flop DFF4 switches its level accordingly according to the second comparison result; S33: In the third comparison cycle, at the rising edge of the comparison clock CK2, the output signal of the fifth flip-flop DFF5 of the sub-cycle changes from a low level to a high level, and the sub-capacitor controlled by the output signal of the fifth flip-flop DFF5 performs corresponding level switching according to the third comparison result.

5. A dynamic component matching method suitable for SAR ADC, characterized in that: The dynamic element matching circuit according to any one of claims 1 to 4 is used to implement switching of high-three-digit capacitances of a capacitance array in an analog-to-digital conversion circuit, the method comprising: First, a four-point search module is used to obtain an ADC output binary code based on the comparison result of the SAR ADC, and a conversion clock signal and a comparison clock signal are generated to act on the dynamic element selection circuit to control the dynamic switching of the approximation process and jump the comparison cycle; Then, the dynamic element selection circuit changes the switching order of each sub-capacitor of the SAR ADC in a bit-by-bit cyclic manner based on the comparison result and the conversion clock signal and comparison clock signal output by the quadrant search module, so that the matching error between the sub-capacitors tends to zero over time.

6. A SAR analog-to-digital conversion circuit, characterized in that: The dynamic element matching circuit according to claim 4 is used to switch the upper three sub-capacitors of the capacitor array in the analog-to-digital conversion circuit, and the SAR logic is used to switch the lower sub-capacitors except the upper three sub-capacitors; The analog-to-digital conversion circuit includes: a P-side input terminal, a P-side capacitor array, a P-side action unit array; an N-side input terminal, an N-side capacitor array, and an N-side action unit array; Comparator, SAR logic module, P-side sampling switch, N-side sampling switch; The P-side action unit array and the N-side action unit array are composed of action switches, which realize the switching of the high-order sub-capacitors of the capacitor array according to the output signal of the dynamic element matching circuit, and control the switching of the low-order sub-capacitors except the high-order sub-capacitors according to the output signal of the SAR logic module; The lower plates of each sub-capacitor of the P-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the P-side action unit array, and the lower plates of each sub-capacitor of the N-side capacitor array are connected to a reference voltage VREF or a ground GND via an action switch in the N-side action unit array; The P-side input terminal is respectively connected to the upper plate of each sub-capacitor of the P-side capacitor array and the positive input terminal of the comparator through the P-side sampling switch; the N-side input terminal is respectively connected to the upper plate of each sub-capacitor of the N-side capacitor array and the negative input terminal of the comparator through the N-side sampling switch.

7. The analog-to-digital conversion circuit according to claim 6, wherein the high-three-digit capacitors of the P-side capacitor array comprise: P-side first high-position sub-capacitor CP1a, P-side second high-position sub-capacitor CP1b, P-side third high-position sub-capacitor CP2; The P-side first high-position sub-capacitor CP1a is switched between the reference voltage VREF and ground via the P-side first action switch SP1a; the P-side second high-position sub-capacitor CP1b is switched between the reference voltage VREF and ground via the P-side second action switch SP1b; the P-side third high-position sub-capacitor CP2 is switched between the reference voltage VREF and ground via the P-side third action switch SP2; The P-side first action switch SP1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the P-side second action switch SP1b is switched according to the second switching signal clk1b; and the P-side third action switch SP2 is switched according to the third switching signal clk2.

8. The analog-to-digital conversion circuit according to claim 6, wherein the high-three-digit capacitors of the N-side capacitor array comprise: N-side first high-position sub-capacitor CN1a, N-side second high-position sub-capacitor CN1b, N-side third high-position sub-capacitor CN2; The N-side first high-position sub-capacitor CN1a is connected to the reference voltage VREF and grounded via the N-side first action switch SN1a; the N-side second high-position sub-capacitor CN1b is connected to the reference voltage VREF and grounded via the N-side second action switch SN1b; the N-side third high-position sub-capacitor CN2 is connected to the reference voltage VREF and grounded via the N-side third action switch SN2; The N-side first action switch SN1a is switched according to the first switching signal clk1a output by the dynamic element matching circuit; the N-side second action switch SN1b is switched according to the second switching signal clk1b; and the N-side third action switch SN2 is switched according to the third switching signal clk2.

9. The analog-to-digital conversion circuit according to claim 6, wherein: When the sampling phase of the analog-to-digital conversion circuit ends and the P-terminal input voltage VIP is greater than the N-terminal input voltage VIN, the working process of the first analog-to-digital conversion phase of the analog-to-digital conversion circuit includes: When VIP is less than VIN+(VREF / 4), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND; When the input voltage of the capacitor array at the P terminal becomes VIP-(VREF / 4) less than VIN, the output of the second comparison cycle is low. The four-point search module controls the switching of the remaining two sub-capacitors CP1b and CP2 in the upper three bits and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the upper three digital outputs B1, B2, and B3 are 100. When VIP is greater than or equal to VIN+(VREF / 4) and less than VIN+(VREF / 2), in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND; The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND. The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is less than VIN. The output of the third comparison cycle is low. The four-point search module controls the end of the switching of sub-capacitor CP2 and directly switches sub-capacitor CP3. Subsequent sub-capacitors are switched using the traditional binary SAR logic control method, and the output of the upper three digital outputs B1, B2, and B3 are 101; When VIP is greater than or equal to VIN+(VREF / 2) and less than VIN+VREF, in the first comparison cycle, the comparator output is high, the first switching signal clk1a becomes high, and the action unit SP1a connects the lower plate of the sub-capacitor CP1a to GND; The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 4), which is greater than VIN. The second comparison cycle output is high, the second switching signal clk1b becomes high, and the action unit SP1b connects the lower plate of the sub-capacitor CP1b to GND. The input voltage of the P-terminal capacitor array becomes VIP-(VREF / 2), which is greater than VIN. The output of the third comparison cycle is high, the third switching signal clk2 becomes high, and the action unit SP2 connects the lower plate of the sub-capacitor CP2 to GND. The input voltage of the P-terminal capacitor array becomes VIP-(VREF 3 / 4), and the output of the fourth comparison cycle is a high level or a low level; the four-point search module controls the switching of sub-capacitor CP3, and the subsequent sub-capacitors are switched using the control method of traditional binary SAR logic, and the output of the upper three digital outputs B1, B2, and B3 are 111 or 110.

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