Optoelectronic semiconductor chip and method for manufacturing an optoelectronic semiconductor chip

Abstract

The invention describes an optoelectronic semiconductor chip (20) having: a first region (21) doped with a first dopant; a second region (22) doped with a second dopant; an activation region (23) between the first region (21) and the second region (22); a first contact layer (24) having a conductive material and covering the first region (21); an insulating layer (25) covering the first contact layer (24) and having a first opening (26); and a second contact layer (27) having a conductive material and covering the insulating layer (25) and the first opening (26), wherein the first opening (26) completely penetrates the insulating layer (25), and the second contact layer (27) has a second opening (28) and / or a third contact layer (29) having a conductive material is arranged between the second contact layer (27) and the insulating layer (25) in the first opening (26) respectively. The invention also describes a method for manufacturing an optoelectronic semiconductor chip (20).

Description

Field of the Invention

[0001] The present invention relates to an optoelectronic semiconductor chip and a method for manufacturing an optoelectronic semiconductor chip. Summary of the Invention

[0002] The technical problem to be solved by the present invention is to describe an optoelectronic semiconductor chip that can operate effectively. Another technical problem to be solved is to describe a method for manufacturing an optoelectronic semiconductor chip that can operate effectively.

[0003] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes a first region doped with a first dopant. The first region may include one or more semiconductor layers. The first dopant may be a p-type dopant. The first region may be formed of a semiconductor material, such as a III-V compound semiconductor material. For example, the first region has GaN (gallium nitride). The first region may be a three-dimensional body that at least approximately has the shape of a cuboid or a cylinder. The main extension plane of the first region extends parallel to one of the top surfaces of the cuboid or the cylinder.

[0004] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes a second region doped with a second dopant. The second region may include one or more semiconductor layers. The second dopant may be an n-type dopant. The second region may be formed of a semiconductor material, such as a III-V compound semiconductor material. For example, the second region has GaN. The second region may be a three-dimensional body that at least approximately has the shape of a cuboid or a cylinder. The main extension plane of the second region extends parallel to one of the top surfaces of the cuboid or the cylinder.

[0005] The first region and the second region may be arranged on a substrate. The substrate may have or consist of sapphire (Al2O3).

[0006] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes an active region between the first region and the second region. The active region is designed to emit and / or detect electromagnetic radiation during the operation of the optoelectronic semiconductor chip. The active region may have at least one quantum well structure. The semiconductor chip relates, for example, to a light-emitting diode chip, such as an illumination diode chip or a laser diode chip, or to a photodiode.

[0007] According to at least one embodiment of an optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes a first contact layer having a conductive material and covering a first region. The first contact layer particularly completely covers the first region. The first contact layer is conductive. In addition, the first contact layer is at least partially in direct contact with the first region. The first contact layer may follow the first region in the growth direction. The first contact layer has, for example, a TCO (transparent conductive oxide) material, such as indium tin oxide.

[0008] According to at least one embodiment of an optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes an insulating layer covering the first contact layer and having a first opening. The insulating layer has an electrically insulating material. The insulating layer is electrically insulating. The insulating layer has, for example, silicon dioxide (SiO2). The insulating layer may be arranged directly on the first region. It is also possible that the insulating layer is arranged spaced apart from the first region. The insulating layer has a plurality of first openings. The first opening may be a trench extending through the insulating layer. This means that the insulating layer has an interruption in the region of the first opening. The first opening has, for example, a circular shape in a top view. However, other shapes of the first opening are also possible.

[0009] According to at least one embodiment of an optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes a second contact layer having a conductive material and covering the insulating layer and the first opening. The second contact layer is conductive. In addition, the second contact layer may be at least partially in direct contact with the insulating layer. The second contact layer may follow the insulating layer in the growth direction. The second contact layer has, for example, indium tin oxide.

[0010] According to at least one embodiment of an optoelectronic semiconductor chip, the first opening completely penetrates the insulating layer. This may mean that a layer arranged below the insulating layer is exposed in the first opening. Thus, the insulating layer is completely removed in the region of the first opening.

[0011] According to at least one embodiment of an optoelectronic semiconductor chip, the second contact layer has a second opening, and / or a third contact layer having a conductive material is respectively arranged between the second contact layer and the insulating layer in the first opening. The second opening may be a trench extending through the second contact layer. This means that the second contact layer has an interruption in the region of the second opening. The second opening may completely extend through the second contact layer. This means that the second contact layer is completely removed in the region of the second opening. The second opening has, for example, a circular shape in a top view. However, other shapes of the second opening are also possible. The second opening may be arranged to be spaced apart from the first opening in a lateral direction, where the lateral direction extends parallel to the main extension plane of the first region.

[0012] The third contact layer is conductive. In addition, the third contact layer is at least partially in direct contact with the insulating layer. In addition, the third contact layer is at least partially in direct contact with the second contact layer. In the first opening region, the third contact layer may be partially in direct contact with the first contact layer. The third contact layer may partially or completely cover the first opening respectively. Between the first openings, the third contact layer is at least partially not disposed between the insulating layer and the second contact layer. This means that the third contact layer has an interruption between the first openings. Therefore, the third contact layer has a plurality of sub-regions, which are respectively disposed in the first openings and are not in direct contact with each other. The third contact layer may follow the insulating layer in the growth direction. In the growth direction, the third contact layer may have a greater thickness than the second contact layer. The third contact layer has indium tin oxide, for example.

[0013] According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip includes a first region doped with a first dopant, a second region doped with a second dopant, an activation region between the first region and the second region, a first contact layer having a conductive material and covering the first region, an insulating layer covering the first contact layer and having a first opening, and a second contact layer having a conductive material and covering the insulating layer and the first opening, wherein the first opening completely penetrates the insulating layer, and the second contact layer has a second opening and / or a third contact layer is respectively disposed in the first opening between the second contact layer and the insulating layer, and the third contact layer has a conductive material.

[0014] The optoelectronic semiconductor chip described herein is based, among other things, on the idea that the brightness of the optoelectronic semiconductor chip during operation can be increased by reducing absorption in the semiconductor chip. The first contact layer, the second contact layer, and the third contact layer may each have a transparent conductive oxide. As the layer thickness decreases, these layers have increased transparency to the radiation emitted by the activation region. However, in order to be able to effectively apply current to the first region, the layer thicknesses of the first contact layer and the second contact layer cannot be arbitrarily reduced.

[0015] By introducing the second opening into the second contact layer, the second contact layer requires less material overall. This means that the overall volume of the second contact layer can be reduced. Therefore, less radiation is absorbed in the second contact layer overall. Therefore, the brightness of the optoelectronic semiconductor chip during operation can be increased.

[0016] By arranging the third contact layer in the first opening region, the layer thickness of the second contact layer can be reduced. The layer thickness of the third contact layer can be selected such that the third contact layer completely covers the first opening and thus establishes electrical contact with the first contact layer. Accordingly, the entire second contact layer does not have to have a layer thickness that can completely cover the first opening. Thus, the layer thickness of the second contact layer can be selected to be smaller. Thereby, the absorption of the radiation emitted by the activation region during operation in the second contact layer is reduced. Thus, the brightness of the optoelectronic semiconductor chip during operation can be increased.

[0017] The brightness of the optoelectronic semiconductor chip during operation can be increased either by introducing a second opening or by using a third contact layer. By combining these two features, i.e., by introducing a second opening and simultaneously using a third contact layer, the brightness of the optoelectronic semiconductor chip during operation can be further increased.

[0018] According to at least one embodiment of the optoelectronic semiconductor chip, the second openings each completely penetrate the second contact layer. This means that the second openings extend completely through the second contact layer. The second openings can extend through the second contact layer in a vertical direction, where the vertical direction extends perpendicular to the main extension plane of the first region. In the second opening region, there is no second contact layer in the insulating layer. Since the second openings each completely penetrate the second contact layer, generally less material is required for the second contact layer of the optoelectronic semiconductor chip. Accordingly, the absorption in the optoelectronic semiconductor chip is reduced and the brightness of the optoelectronic semiconductor chip during operation is increased.

[0019] According to at least one embodiment of the optoelectronic semiconductor chip, the first contact layer and / or the second contact layer and / or the third contact layer have a transparent conductive oxide. For example, the first contact layer and / or the second contact layer and / or the third contact layer have indium tin oxide or ZnO (zinc oxide). Advantageously, the transparent conductive oxide is at least partially transparent to the radiation emitted in the activation region. At the same time, the transparent conductive oxide has high conductivity, so that charge carriers can be effectively applied to the first region.

[0020] According to at least one embodiment of the optoelectronic semiconductor chip, the first contact layer and the second contact layer are formed of the same material. For example, the first contact layer and the second contact layer are both formed of the same transparent conductive oxide (especially indium tin oxide). Since the first contact layer and the second contact layer are formed of the same material, the manufacturing of the optoelectronic semiconductor chip is simplified. In addition, the contact resistance between the first contact layer and the second contact layer is reduced.

[0021] According to at least one embodiment of the optoelectronic semiconductor chip, the first, second, and third contact layers are formed of the same material. For example, the first, second, and third contact layers are formed of the same transparent conductive oxide (especially indium tin oxide).

[0022] According to at least one embodiment of the optoelectronic semiconductor chip, the third contact layer completely covers the first opening respectively. The first opening may have side walls and a bottom surface respectively. The third contact layer may completely cover the side walls and the bottom surface of the first opening respectively. This enables a reliable electrical contact between the second contact layer and the first contact layer. Therefore, charge carriers can be effectively applied into the first region via the second contact layer and the first contact layer.

[0023] According to at least one embodiment of the optoelectronic semiconductor chip, the third contact layer partially covers the upper side of the insulating layer facing away from the first region. The third contact layer partially covers the upper side of the insulating layer in a region arranged adjacent to the first opening. This means that the third contact layer can completely cover the side walls of the first opening and can partially cover the upper side of the insulating layer adjacent to the side walls. The third contact layer can also completely cover the edge of the insulating layer in the first opening region. Thus, it is ensured that the first opening is completely covered by the third contact layer. This enables a reliable electrical contact between the second contact layer and the first contact layer.

[0024] According to at least one embodiment of the optoelectronic semiconductor chip, the third contact layer is in direct contact with the first contact layer in the first opening. The first contact layer may form the bottom surface in the first opening. The third contact layer can be directly applied to the bottom surface of the first opening. Therefore, the third contact layer is in direct contact with the first contact layer in the bottom surface region of the first opening. Therefore, a reliable electrical contact between the second contact layer and the first contact layer is advantageously achieved.

[0025] According to at least one embodiment of the optoelectronic semiconductor chip, the first openings are respectively arranged between two second openings in the lateral direction. Here, the lateral direction extends parallel to the main extension plane of the first region. In a top view of the optoelectronic semiconductor chip, the first openings are respectively arranged between two second openings in the lateral direction. This means that the optoelectronic semiconductor chip alternately has first openings and second openings along the lateral direction. This enables charge carriers to be uniformly applied into the first region through the second contact layer via the first openings.

[0026] According to at least one embodiment of the optoelectronic semiconductor chip, at least two of the first openings in the first opening are arranged at the grid points of a one-dimensional grid along the lateral direction. This means that the first openings have the same spacing from each other along the lateral direction. Due to the uniform spacing of the first openings, charge carriers are applied more uniformly into the first region. This results in a uniform radiation characteristic of the optoelectronic semiconductor chip.

[0027] According to at least one embodiment of the optoelectronic semiconductor chip, at least two of the second openings are arranged at grid points of a one-dimensional grid along a lateral direction. This means that the second openings have the same spacing from one another along the lateral direction. If the second openings are arranged respectively in the middle between two first openings along the lateral direction, the flow of charge carriers via the second contact layer into the first region is less affected. In this case, the second openings are arranged at a location where the current density in the second contact layer is low during operation of the semiconductor chip. Thus, charge carriers can be more effectively supplied to the first region via the second contact layer, and absorption of the radiation emitted by the activation region during operation in the second contact layer is reduced.

[0028] According to at least one embodiment of the optoelectronic semiconductor chip, the first dopant is a p-type dopant and the second dopant is an n-type dopant. It is particularly advantageous if the first region and the second region have gallium nitride.

[0029] According to at least one embodiment of the optoelectronic semiconductor chip, the second contact layer has a layer thickness of at most 90 nm along a growth direction extending perpendicular to the main extension plane of the first region. In particular when the third contact layer is arranged in the first opening, the layer thickness of the second contact layer can be at most 90 nm. In the case of a layer thickness in this range, charge carriers can continue to be effectively supplied to the first region via the second contact layer, and additionally absorption of the radiation from the activation region in the second contact layer is reduced.

[0030] According to at least one embodiment of the optoelectronic semiconductor chip, the third contact layer has a layer thickness of at least 50 nm along a growth direction extending perpendicular to the main extension plane of the first region. The layer thickness of the third contact layer is, for example, at most 200 nm. With this layer thickness of the third contact layer it is ensured that the third contact layer completely covers the first opening and thus establishes a reliable electrical contact between the second contact layer and the first contact layer.

[0031] A method for manufacturing an optoelectronic semiconductor chip is also described. The optoelectronic semiconductor chip can preferably be manufactured by the method described herein. In other words, all features disclosed for the optoelectronic semiconductor chip are also disclosed for the method for manufacturing an optoelectronic semiconductor chip, and vice versa.

[0032] According to at least one embodiment of the method for manufacturing an optoelectronic semiconductor chip, the method comprises a method step in which a first region is provided on a second region, where the first region is doped with a first dopant and the second region is doped with a second dopant, and an activation region is arranged between the first region and the second region. The first region can be grown on the second region.

[0033] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, the method includes a method step in which a first contact layer is applied to a first region, wherein the first contact layer has a conductive material. The first contact layer can be applied directly to the first region. An etch stop layer can be applied to the first contact layer. The etch stop layer can in particular have or consist of Al2O3.

[0034] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, the method includes a method step in which an insulating layer is applied. The insulating layer is applied to the first contact layer or the etch stop layer.

[0035] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, the method includes a method step in which a first opening is etched in the insulating layer, wherein the first opening completely penetrates the insulating layer. The first opening is etched in a dry chemical or wet chemical manner. The first opening can be etched from the upper side of the insulating layer in the direction of the first contact layer. Here, the insulating layer is completely removed in the region of the first opening. The first opening thus extends from the upper side of the insulating layer up to the first contact layer or up to the etch stop layer. The etch stop layer can be removed in the region of the first opening.

[0036] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, the method includes a method step in which a second contact layer is applied to the insulating layer and the first opening, wherein the second contact layer has a conductive material. The second contact layer can completely cover the first opening.

[0037] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, the method includes a method step in which a second opening is etched in the second contact layer and / or a third contact layer is applied to the first opening before applying the second contact layer, wherein the third contact layer has a conductive material. The second opening can be etched in the second contact layer such that the second opening completely penetrates the second contact layer. Thus, the second contact layer is etched from the side facing away from the insulating layer in the direction of the insulating layer. The third contact layer can completely cover the first opening. The third contact layer can be applied directly to the insulating layer and the first contact layer in the region of the first opening.

[0038] The optoelectronic semiconductor chip manufactured in this way can operate effectively because the absorption of the radiation emitted by the active region in the optoelectronic semiconductor chip can be reduced. On the one hand, the absorption in the second contact layer is reduced because the second contact layer has a second opening. Alternatively or additionally, the absorption in the second contact layer is reduced because if the third contact layer is arranged in the first opening, the layer thickness of the second contact layer can be reduced. Thus, the brightness of the optoelectronic semiconductor chip during operation is increased.

[0039] According to at least one embodiment of a method for manufacturing an optoelectronic semiconductor chip, an etch stop layer is applied to a first contact layer. The etch stop layer acts as an etch stop layer for an insulating layer used for etching a first opening. Description of the Drawings

[0040] The optoelectronic semiconductor chip described herein and the method for manufacturing an optoelectronic semiconductor chip described herein will be explained in more detail below in conjunction with embodiments and the associated drawings.

[0041] Figure 1A A top view of an embodiment of an optoelectronic semiconductor chip is shown.

[0042] Figure 1B A top view of an example of an optoelectronic semiconductor chip is shown.

[0043] Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D and Figure 2E A top view of an embodiment of an optoelectronic semiconductor chip is shown.

[0044] Figure 3A and Figure 3B Schematic cross-sections of an optoelectronic semiconductor chip according to an embodiment are shown respectively.

[0045] Figure 4A and Figure 4B Schematic cross-sections of an optoelectronic semiconductor chip according to an embodiment are shown.

[0046] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E Embodiments of a method for manufacturing an optoelectronic semiconductor chip are shown.

[0047] Elements that are the same, similar, or have the same function are provided with the same reference numerals in the drawings. The shapes and dimensional ratios of the elements shown in the drawings should not be regarded as being to scale with each other. Rather, for better visibility and / or better comprehensibility, individual elements may be shown disproportionately large. Detailed Description of the Embodiments

[0048] Using Figure 1A and Figure 1B The current density distribution of an optoelectronic semiconductor chip 20 according to an embodiment is compared with an example of an optoelectronic semiconductor chip. Here, Figure 1B The scale shown beside applies to both of the drawings.

[0049] Figure 1A A top view of an embodiment of the optoelectronic semiconductor chip 20 is shown. The optoelectronic semiconductor chip 20 has a first contact 34 and a second contact 35. For example, the first contact 34 is an n-side contact and the second contact 35 is a p-side contact. The first contact 34 and the second contact 35 are each connected to a contact web 36. The contact web 36 has two contact areas which are arranged one on top of the other and are electrically isolated from each other. The two contact areas are each provided for supplying current to different areas of the optoelectronic semiconductor chip 20.

[0050] The optoelectronic semiconductor chip 20 has a first region 21 which is doped with a first dopant, in this case a p-type dopant. The optoelectronic semiconductor chip 20 also has a second region 22 which is doped with a second dopant, in this case an n-type dopant. In the growth direction R, the first region 21 is arranged above the second region 22, where the growth direction extends perpendicular to the main extension plane of the first region 21. A first contact layer 24 made of a conductive material is arranged on the first region 21. An insulating layer 25 is arranged on the first contact layer 24. The insulating layer 25 has a first opening 26 which is shown as a point in Figure 1A is shown.

[0051] A second contact layer 27 made of a conductive material is arranged on the insulating layer 25 and in the first opening 26. The second contact layer 27 is conductively connected to one of the contact areas of the contact web 36. Thus, charge carriers can be supplied to the first region 21 via the contact web 36, the second contact layer 27 and the first contact layer 24.

[0052] The second contact layer 27 has a second opening 28. The second opening 28 is arranged spaced apart from the first opening 26. The first opening 26 and the second opening 28 do not necessarily lie in one plane, but are shown side by side in Figure 1A is shown. The second opening 28 has a circular cross-section.

[0053] The second contact layer 27 does not extend over the entire surface of the optoelectronic semiconductor chip 20, but only in the region where the first opening 26 is arranged. The first contact layer 24 and the second contact layer 27 each have indium tin oxide.

[0054] In the transverse direction x which extends parallel to the main extension plane of the first region 21, the first opening 26 is arranged between two second openings 28 respectively. Here, the first opening 26 is arranged at the grid points of a one-dimensional grid along the transverse direction x. In addition, the second openings 28 are arranged at the grid points of a one-dimensional grid along the transverse direction x. A plurality of rows formed by the first opening 26 and the second openings 28 are arranged side by side.

[0055] Figure 1AAlso shown is a simulation of the current density distribution during operation of the optoelectronic semiconductor chip 20. For this purpose, Figure 1B the scale next to it indicates the current density in A / cm 2 units. The higher the current density, the higher the intensity of the radiation emitted by the optoelectronic semiconductor chip 20. The simulation shows that the current density is highest in the vicinity of the first opening 26 and in the vicinity of the first contact 34 and the second contact 35. As the distance from the contact web 36 becomes greater, the current density decreases.

[0056] For comparison, Figure 1B a top view of an example of an optoelectronic semiconductor chip is shown. Different from the embodiment shown in Figure 1A the optoelectronic semiconductor chip in Figure 1B does not have a second opening 28. Figure 1B The current density distribution of the example of Figure 1A differs only slightly from the current density distribution of the embodiment shown in Figure 1A Therefore, a similar current intensity can be applied in both cases. Due to the second opening 28 in the second contact layer 27, Figure 1B the absorption in the optoelectronic semiconductor chip 20 of Figure 1A is significantly reduced. The area of the second contact layer 27 can be reduced by approximately 28%, for example. This results in a significant reduction in the absorption of radiation in the second contact layer 27. Therefore, compared to the example of

[0057] Figure 2A a top view of an optoelectronic semiconductor chip 20 according to an embodiment is shown. Here, as in Figure 1A the simulated current density distribution is shown. The optoelectronic semiconductor chip 20 has a first opening 26 and a second opening 28, which are distributed over the entire area of the second contact layer 27. The diameter of the second opening 28 is significantly larger than the diameter of the first opening 26.

[0058] Figure 2B a top view of an optoelectronic semiconductor chip 20 according to another embodiment is shown. As in Figure 1A the simulated current density distribution is shown. Compared to the embodiment shown in Figure 2A the second opening 28 has a smaller diameter. The larger the diameter of the second opening 28, the more the forward voltage of the optoelectronic semiconductor chip 20 increases, and the less radiation is absorbed in the second contact layer 27. Therefore, the size of the second opening 28 can be matched to these two parameters. For the one shown in Figure 2B compared to Figure 2ACompared to the second opening 28 with a smaller diameter, the forward voltage increases less strongly, but the absorption of the second contact layer 27 is greater than that in the Figure 2A embodiment.

[0059] Figure 2C The top view of a optoelectronic semiconductor chip 20 according to another embodiment is shown in. As in Figure 1A shown, the simulated current density distribution is shown. Compared to the embodiment shown in Figure 2A The second opening 28 is only arranged near the contact web 36. This enables a more uniform current distribution. This results in more uniform radiation characteristics of the optoelectronic semiconductor chip 20.

[0060] Figure 2D The top view of a optoelectronic semiconductor chip 20 according to another embodiment is shown in. As in Figure 1A shown, the simulated current density distribution is shown. Compared to the embodiment shown in Figure 2A The second opening 28 is only arranged at the center and the edge of the optoelectronic semiconductor chip 20. This also enables a more uniform current distribution.

[0061] Figure 2E The top view of a optoelectronic semiconductor chip 20 according to another embodiment is shown in. As in Figure 1A shown, the simulated current density distribution is shown. Compared to the embodiment shown in Figure 2A The optoelectronic semiconductor chip 20 has generally fewer second openings 28. In addition, the second opening 28 does not have a circular cross-section, but has different elongated shapes. Thereby, the current density and thus the intensity of the emitted radiation are higher in the region of the contact web 36 than at the center and the edge of the optoelectronic semiconductor chip 20.

[0062] Figure 3A The cross-section of a optoelectronic semiconductor chip 20 according to an embodiment is shown in. The first region 21 is arranged on the second region 22. The activation region 23 for generating electromagnetic radiation is arranged between the first region 21 and the second region 22. The first contact layer 24 is arranged on the first region 21 and completely covers the first region. The insulating layer 25 is arranged on the first contact layer 24 and covers the first contact layer. The insulating layer 25 has a first opening 26. Figure 3AThe first opening 26 is exemplarily shown therein. The first opening 26 completely penetrates the insulating layer 25. In the first opening 26, the third contact layer 29 covers the insulating layer 25 and the first contact layer 24. Thus, the third contact layer 29 completely covers the first opening 26. In addition, the third contact layer 29 is in direct contact with the first contact layer 24 in the first opening 26. The third contact layer 29 also partially covers the upper side 30 of the insulating layer 25 facing away from the first region 21. The third contact layer 29 covers the upper side 30 of the insulating layer 25 adjacent to the first opening 26. The third contact layer 29 has a conductive material. For example, the first contact layer 24, the second contact layer 27, and the third contact layer 29 have indium tin oxide.

[0063] The second contact layer 27 covers the insulating layer 25 and the first opening 26. Thus, the second contact layer 27 also covers the third contact layer 29. This means that the third contact layer 29 is arranged between the second contact layer 27 and the insulating layer 25 in the first opening 26.

[0064] In the growth direction R extending perpendicular to the main extension plane of the first region 21, the third contact layer 29 has a greater thickness than the second contact layer 27.

[0065] Figure 3B A cross-section of the optoelectronic semiconductor chip 20 according to another embodiment is shown therein. Different from the embodiment shown in Figure 3A The second contact layer 27 has a second opening 28. Figure 3B The second opening 28 is exemplarily shown therein. The second opening 28 is arranged to be spaced apart from the first opening 26 in the lateral direction x. In addition, the second opening 28 completely penetrates the second contact layer 27. This means that the second opening 28 extends through the second contact layer 27 up to the insulating layer 25. A passivation layer 32 is arranged on the second contact layer 27.

[0066] Figure 4A A cross-section of the optoelectronic semiconductor chip 20 according to another embodiment is shown. The optoelectronic semiconductor chip 20 has the structure shown in Figure 3A In addition, a passivation layer 32 is arranged on the second contact layer 27.

[0067] Figure 4B A fragment of the cross-section of Figure 4A is shown therein. It is shown here that the third contact layer 29 has a greater thickness than the second contact layer 27 in the growth direction R. Since the thickness of the second contact layer 27 can be small, absorption of radiation from the active region 23 in the second contact layer 27 can be reduced and thus the brightness of the optoelectronic semiconductor chip 20 can be increased.

[0068] In combination with Figure 5A 、 Figure 5B 、 Figure 5C 、Figure 5D and Figure 5E describes an embodiment of a method for manufacturing an optoelectronic semiconductor chip 20. The steps described can be carried out in the order illustrated.

[0069] Figure 5A A schematic cross-section is shown in. In a first step of the method, a first region 21 is provided on a second region 22. A first contact layer 24 is applied to the first region 21. An etch stop layer 31 is applied to the first contact layer 24. An insulating layer 25 is applied to the etch stop layer 31. In order to etch a first opening 26, a mask 33 is applied to the insulating layer 25. The insulating layer 25 is etched in regions where the mask 33 is not arranged. Here, the etch stop layer 31 acts as an etch stop layer 31 for the insulating layer 25, such that the insulating layer 25 is completely removed down to the etch stop layer 31. Thereby, the first opening 26 is formed.

[0070] Figure 5B As shown in, in a next step, the mask 33 is partially removed around the first opening 26. For this purpose, the mask 33 can be treated with an oxygen plasma. Furthermore, the etch stop layer 31 in the region of the first opening 26 is removed by wet chemical etching.

[0071] Figure 5C As shown in, in a next step, a third contact layer 29 is applied to the mask 33, the insulating layer 25, and the first opening 26.

[0072] Figure 5D As shown in, in a next step, the mask 33 is removed.

[0073] Figure 5E As shown in, in a next step, a second contact layer 27 is applied to the insulating layer 25 and the third contact layer 29 and thus also to the first opening 26. Subsequently, a second opening 28 can be formed in the second contact layer 27 by etching.

[0074] The features and embodiments described in connection with the figures can be combined with each other according to other embodiments, even if not all combinations are explicitly described. Furthermore, the embodiments described in connection with the figures alternatively or additionally have other features according to the description in the general part.

[0075] This patent application claims the priority of German patent application 102019113119.7, the disclosure of which is incorporated herein by reference.

[0076] The invention is not limited to this embodiment by the description according to the embodiment. Rather, the invention includes each new feature and each combination of features, which in particular includes each combination of features in the claims, even if the feature or the combination itself is not explicitly stated in the claims or in the embodiment.

[0077] List of reference numerals

[0078] 20: Optoelectronic semiconductor chip

[0079] 21: First region

[0080] 22: Second region

[0081] 23: Activation region

[0082] 24: First contact layer

[0083] 25: Insulating layer

[0084] 26: First opening

[0085] 27: Second contact layer

[0086] 28: Second opening

[0087] 29: Third contact layer

[0088] 30: Upper side

[0089] 31: Etch stop layer

[0090] 32: Passivation layer

[0091] 33: Mask

[0092] 34: First contact

[0093] 35: Second contact

[0094] 36: Contact web

[0095] R: Growth direction

[0096] x: Lateral direction

Claims

1. A optoelectronic semiconductor chip (20), having: - A first region (21), which is doped with a first dopant, - A second region (22), which is doped with a second dopant, - An active region (23) between the first region (21) and the second region (22), - A first contact layer (24), which has a conductive material and covers the first region (21), - An insulating layer (25), which covers the first contact layer (24) and has a first opening (26), and - A second contact layer (27), which has a conductive material and the second contact layer covers the insulating layer (25) and the first opening (26), wherein, - The first opening (26) completely penetrates the insulating layer (25), - The second contact layer (27) has a second opening (28) and / or a third contact layer (29) is respectively arranged between the second contact layer (27) and the insulating layer (25) in the first opening (26), and the third contact layer has a conductive material, - The first contact layer (24) has a transparent conductive oxide, and - The first opening (26) is respectively arranged between two second openings (28) in the transverse direction (x).

2. The optoelectronic semiconductor chip (20) according to claim 1, wherein, The second openings (28) respectively completely penetrate the second contact layer (27).

3. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The second contact layer (27) and / or the third contact layer (29) has a transparent conductive oxide.

4. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The first contact layer and the second contact layer (24, 27) are formed of the same material.

5. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The first contact layer, the second contact layer and the third contact layer (24, 27, 29) are formed of the same material.

6. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The third contact layer (29) respectively completely covers the first opening (26).

7. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The third contact layer (29) partially covers the upper side (30) of the insulating layer (25) facing away from the first region (21).

8. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The third contact layer (29) is in direct contact with the first contact layer (24) in the first opening (26).

9. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, At least two of the first openings in the first opening (26) are arranged at the grid points of a one-dimensional grid along the transverse direction (x).

10. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, At least two of the second openings in the second opening (28) are arranged at the grid points of a one-dimensional grid along the transverse direction (x).

11. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The first dopant is a p-type dopant and the second dopant is an n-type dopant.

12. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The second contact layer (27) has a layer thickness of at most 90 nm along the growth direction (R), and the growth direction extends perpendicular to the main extension plane of the first region (21).

13. The optoelectronic semiconductor chip (20) according to claim 1 or 2, wherein, The third contact layer (29) has a layer thickness of at least 50 nm along the growth direction (R), and the growth direction extends perpendicular to the main extension plane of the first region (21).

14. A method for manufacturing an optoelectronic semiconductor chip (20), having steps: - Provide a first region (21) on a second region (22), wherein, The first region (21) is doped with a first dopant and the second region (22) is doped with a second dopant, and an active region (23) is arranged between the first region (21) and the second region (22), - Apply a first contact layer (24) to the first region (21), wherein the first contact layer (24) has a conductive material, - Apply an insulating layer (25). - Etch a first opening (26) in the insulating layer (25), wherein the first opening (26) completely penetrates the insulating layer (25), - Apply a second contact layer (27) to the insulating layer (25) and the first opening (26), wherein the second contact layer (27) has a conductive material, and - Etch a second opening (28) in the second contact layer (27) and / or apply a third contact layer (29) to the first opening (26) before applying the second contact layer (27), wherein the third contact layer (29) has a conductive material, wherein the first opening (26) is arranged between two second openings (28) in the transverse direction (x).

15. The method according to claim 14, wherein, Apply an etch stop layer (31) to the first contact layer (24).

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