Micro-electromechanical device and method for forming the same

Abstract

The present invention discloses a micro-electromechanical device and a method for forming the same. The micro-electromechanical device includes a substrate, a groove, an interconnection structure, and a mass block. The substrate has a first surface and a second surface opposite to the first surface. The groove is provided in the substrate and extends between the first surface and the second surface. The interconnection structure is provided on the first surface of the substrate and is located above the groove. The mass block is provided in the groove and connected to the interconnection structure, and the thickness of the mass block is less than the thickness of the substrate. The formation method includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a groove in the substrate, the groove extending between the first surface and the second surface; forming an interconnection structure on the first surface of the substrate, the interconnection structure being located above the groove; and forming a mass block in the groove, the mass block being connected to the interconnection structure.

Description

Technical Field

[0001] The present invention relates to a micro-electromechanical device and a method for forming the same, and in particular to a micro-electromechanical device applied in the field of acoustics and a method for forming the same. Background Art

[0002] Micro-electromechanical systems (MEMS) devices are tiny mechanical components manufactured using existing semiconductor processes. Micron-sized mechanical components are achieved through semiconductor techniques such as depositing or selectively etching material layers. MEMS devices can operate using electromagnetic, electrostrictive, thermoelectric, piezoelectric, or piezoresistive effects, combining both electronic and mechanical functions. Therefore, they are often used in the field of microelectronics, such as accelerometers, gyroscopes, mirrors, and acoustic sensors.

[0003] In recent years, the rapid development of true wireless stereo (TWS) wireless Bluetooth headsets has enabled the use of MEMS accelerometers (MEMS) products to sense sound vibrations, opening up new possibilities for acoustic transducers. Incorporating a MEMS accelerometer into a wireless Bluetooth headset allows it to effectively capture sound even in noisy or high-noise environments. However, because MEMS accelerometers are currently more commonly used in mobile phones, their structural designs tend to be thick and bulky, making them inadequate for the miniaturization required for wireless Bluetooth headsets. Consequently, a new MEMS accelerometer design is currently needed for acoustic applications. Summary of the Invention

[0004] The present invention provides a micro-electromechanical device and a method for forming the same. The micro-electromechanical device has a miniaturized proof mass whose thickness is relatively smaller than that of a substrate. Therefore, the micro-electromechanical device can be applied to wireless Bluetooth headsets to assist the voice vibration of a microphone.

[0005] To achieve the above-mentioned objectives, one embodiment of the present invention provides a micro-electromechanical system (MEMS) device, comprising: a substrate having a first surface and a second surface opposite to the first surface; a trench disposed in the substrate and extending between the first surface and the second surface; an interconnect structure disposed on the first surface of the substrate and located above the trench; and a proof mass disposed in the trench and connected to the interconnect structure, wherein the thickness of the proof mass is less than the thickness of the substrate.

[0006] To achieve the above-mentioned objectives, another embodiment of the present invention provides a method for forming a micro-electromechanical system (MEMS) device, comprising: providing a substrate having a first surface and a second surface opposite to the first surface; forming a trench in the substrate, the trench extending between the first surface and the second surface; forming an interconnect structure on the first surface of the substrate, the interconnect structure being located above the trench; and forming a proof mass in the trench, the proof mass being connected to the interconnect structure, the thickness of the proof mass being less than the thickness of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a cross-sectional view of a micro-electromechanical device (MEMS device) after forming an interconnection structure according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic cross-sectional view of a micro-electromechanical system device according to the present invention after a shielding layer is formed.

[0009] Figure 3 FIG. 1 is a schematic cross-sectional view of a micro-electromechanical system device according to the present invention after an etching process.

[0010] Figure 4 FIG. 4 is a schematic cross-sectional view of a micro-electromechanical system device according to the present invention after undergoing another etching process.

[0011] Figure 5 FIG. 4 is a cross-sectional view of a micro-electromechanical system device according to the present invention after the device is released.

[0012] Figure 6 FIG. 1 is a schematic cross-sectional view of a micro-electromechanical system (MEMS) device according to the present invention after forming an interconnection structure.

[0013] Figure 7 FIG. 1 is a schematic cross-sectional view of a micro-electromechanical system device according to the present invention after an etching process.

[0014] Figure 8 FIG. 4 is a cross-sectional view of a micro-electromechanical system device according to the present invention after the device is released.

[0015] Description of reference numerals:

[0016] 100: Base

[0017] 101, 301: first surface

[0018] 102, 302: Second surface

[0019] 103, 303: Groove

[0020] 103a, 120a, 303a, 313a: Open

[0021] 105, 305: mass block

[0022] 110, 320: oxide layer

[0023] 111, 313c, 321: Undercut

[0024] 120: First shielding layer

[0025] 130, 330: protective layer

[0026] 140: Second shielding layer

[0027] 140a, 313b: Pattern

[0028] 200: Interconnection structure

[0029] 210: Suspension area

[0030] 201: Dielectric layer

[0031] 203: Metal layer

[0032] 205: Connection pad

[0033] 207: Perforation

[0034] 300: Silicon-coated insulating substrate

[0035] 311: First semiconductor layer

[0036] 313: Insulation layer

[0037] 315: Second semiconductor layer

[0038] 340: Shielding layer

[0039] T1, T2, T3, T4, T5, T2': thickness DETAILED DESCRIPTION

[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0041] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with accompanying drawings, to describe in detail the technical solutions, technical problems solved, and technical effects achieved by the present invention. Furthermore, those skilled in the art can, without departing from the spirit of the present invention, refer to the following embodiments and replace, reorganize, or combine features from different embodiments to create other embodiments.

[0042] In the present invention, the statement "a first component is formed on or above a second component" may mean "the first component is in direct contact with the second component" or "another component is present between the first component and the second component", so that the first component and the second component are not in direct contact. In addition, various embodiments of the present invention may use repeated component numbers and / or text annotations. The use of these repeated component numbers and text annotations is for the purpose of making the description more concise and clear, and is not used to indicate the relationship between different embodiments and / or configurations. In addition, for the spatially related descriptive terms mentioned in the present invention, such as "below...", "above...", "low", "high", "below", "above", "under", "above", "bottom", "top" and similar terms, for convenience of description, their usage is to describe the relative relationship between one component or feature and another (or multiple) components or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during the manufacturing process, use and operation. For example, when a semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will now be positioned "below" the other components. Therefore, as the orientation of the semiconductor device changes (rotated 90 degrees or at other angles), spatially relative descriptions used to describe its orientation should be interpreted accordingly.

[0043] Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not themselves imply or represent any preceding ordinal number of the elements, nor do they represent the order in which one element is arranged relative to another element, or the order in which one element is manufactured. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0044] The terms "about" or "substantially" mentioned in the present invention generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, even if "about" or "substantially" is not specifically stated, the meaning of "about" or "substantially" may still be implied.

[0045] Please refer to Figures 1 to 5 , depicts a schematic diagram of the process of forming a micro-electromechanical device in a first embodiment of the present invention. First, as Figure 1 As shown, a substrate 100 is provided, such as a bulk silicon substrate. The substrate 100 comprises, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, or other suitable materials. In one embodiment, the thickness T1 of the substrate 100 may be approximately 400 micrometers (μm) to 500 micrometers, but is not limited thereto. The substrate 100 has two opposite surfaces, such as Figure 1 As shown in the first surface 101 and the second surface 102, an oxide layer 110 and an interconnect structure 200 are sequentially formed on the first surface 101 of the substrate 100. The oxide layer 110 may include, for example, silicon oxide (SiO) or silicon dioxide (SiO2), and the interconnect structure 200 may be any suitable semiconductor structure manufactured using existing semiconductor processes such as deposition and / or selective etching of material layers. In one embodiment, the interconnect structure 200 includes at least one dielectric layer 201 stacked on the first surface 101, at least one metal layer 203 embedded in the at least one dielectric layer 201, and at least one connection pad 205 electrically connected to the at least one metal layer 203, as shown in FIG. Figure 1 As shown, at least one dielectric layer 201 includes a dielectric material such as silicon nitride (SiN), aluminum nitride (AlN) or silicon oxynitride (SiON), and at least one metal layer 203 includes a metal material such as copper (Cu), molybdenum (Mo), tungsten (W) or aluminum (Al), but is not limited thereto.

[0046] It should be noted that the interconnect structure 200 further includes a through-hole 207 disposed within a suspension region 210. This allows a structure disposed within the suspension region 210 to be partially separated from the substrate 100 during subsequent manufacturing processes, thereby forming a suspended structure (not shown). For example, the suspended structure may further include a top electrode (not shown), a piezoelectric layer (not shown), and a bottom electrode (not shown) stacked sequentially within the interconnect structure 200 from top to bottom, thereby enabling vibration at a specific frequency during subsequent manufacturing processes. In this embodiment, the suspended structure may include a cantilever, a diaphragm, or similar structures, but is not limited thereto.

[0047] Next, a protective layer 130 is formed on the top surface of the interconnect structure 200. The protective layer 130 comprises, for example, silicon oxide or silicon dioxide, for protecting the components disposed within the interconnect structure 200. Furthermore, a first shielding layer 120 and a second shielding layer 140 are sequentially formed on the second surface of the substrate 100. Figure 2 Specifically, the first shielding layer 120 has an opening 120a, which corresponds to the suspension area 210 of the interconnect structure 200 disposed on the first surface 101. Thus, a portion of the second surface 102 corresponding to the suspension area 210 can be exposed from the opening 120a. Figure 2 As shown. In one embodiment, the size or diameter of the opening 120a is, for example, about 100 microns to 150 microns, but is not limited thereto. The second shielding layer 140 is stacked on the first shielding layer 120, and the second shielding layer 140 includes a pattern 140a disposed within the opening 120a. In other words, a portion of the second shielding layer 140 is directly disposed on the first shielding layer 120 and completely overlaps the top surface of the first shielding layer 120, while another portion of the second shielding layer 140 is disposed on the exposed portion of the first shielding layer 120, as shown in FIG. Figure 2 As shown. In this embodiment, the first shielding layer 120 preferably comprises a material having a different etching selectivity than the material of the second shielding layer 140. For example, the first shielding layer 120 may comprise silicon oxide, while the second shielding layer 140 may comprise a photoresist material, but the present invention is not limited thereto. Furthermore, the material of the first shielding layer 120 is preferably the same as that of the oxide layer 110, or has the same etching selectivity as that of the oxide layer 110.

[0048] like Figure 3As shown, an etching process, such as an anisotropic dry etching process, is performed on the back side of the substrate 100, i.e., the side where the second surface 102 is located, and a portion of the substrate 100 is removed to a certain depth through the first shielding layer 120 and the second shielding layer 140. It should be noted that under the coverage of the second shielding layer 140, the substrate 100 covered by the pattern 140a will not be removed during the etching process, so a partially protruding outline can be formed within the range of the opening 120a, as shown in FIG. Figure 3 Preferably, the depth of the removed portion is substantially equal to the predetermined thickness of the mass block to be formed subsequently. In one embodiment, the depth of the removed portion is, for example, about 50 microns to 100 microns, thereby, Figure 3 The protruding profile shown has a thickness T4 of approximately 50 to 100 microns, but is not limited thereto. Those skilled in the art will readily appreciate that the depth achieved by the aforementioned etching process can be further adjusted based on the desired thickness of the subsequently formed proof mass, and is not limited to the aforementioned values.

[0049] Then, if Figure 4 As shown, the second shielding layer 140 is removed, and another etching process, such as an anisotropic dry etching process, is performed on the back side of the substrate 100 (i.e., the side where the second surface 102 is located). The etching is further performed downward along the aforementioned protruding profile, removing the substrate 100 until the oxide layer 110 underneath is exposed. As a result, a trench 103 is formed in the substrate 100. The trench 103 extends between the two opposite surfaces of the substrate 100 (the first surface 101 and the second surface 102) and has a depth equal to the thickness T1 of the substrate 100. Furthermore, a proof mass 105 is formed in the trench 103 through the aforementioned protruding profile. In this way, the trench 103 and the proof mass 105 can be formed simultaneously, and both the trench 103 and the proof mass 105 can correspond to the suspension region 210 of the interconnect structure 200 disposed on the first surface 101, as shown in FIG. Figure 4 The thickness T2 of the mass block 105 is approximately 50 micrometers to 100 micrometers, and the groove 103 has an opening 103 a at the bottom surface adjacent to the suspension region 210 .

[0050] Subsequently, another etching process is performed using an etching selectivity relative to the proof mass 105 and the substrate 100 to simultaneously remove the first shielding layer 120 and the oxide layer 110 exposed from the substrate 100 and the proof mass 105, thereby exposing the bottom surface of the suspended region 210 located therebelow. For example, the etching selectivity ratio of the material of the first shielding layer 120 and the oxide layer 110 (e.g., silicon oxide) relative to the material of the proof mass 105 and the substrate 100 (e.g., silicon) is, for example, greater than 10, and is approximately 10 to 20, but is not limited thereto. In this manner, the bottom surface of the suspended region 210 can be partially exposed from the trench 103, as shown in FIG. Figure 5 As shown, the mass block 105 can be disposed on the bottom surface of the suspension region 210, so that a portion of the oxide layer 110 is sandwiched between the suspension region 210 and the mass block 105. It should be noted that in the process of completely removing the first shielding layer 120 and partially removing the oxide layer 110, the sidewalls of the remaining oxide layer 110 can also be slightly removed, thereby forming Figure 5 The undercut portion 111 is shown. In addition, during the process of removing the first shielding layer 120 and the oxide layer 110, the top of the mass block 105 will also be slightly removed. Therefore, after the other etching process is performed, the mass block 105 may have a smaller thickness T2'. Preferably, the thickness T2' is reduced by no more than 1 to 10% compared to the original thickness T2, so as to avoid excessively affecting the overall weight of the mass block 105. Then, the protective layer 130 is further removed to release the suspension structure located in the suspension area 210 of the interconnect structure 200, so that one side of the suspension structure is not connected to the substrate 100 and is in a state of being suspended at one end, as shown in FIG. Figure 5 In one embodiment, the protective layer 130 can be removed during the process of removing the first shielding layer 120 and the oxide layer 110, but the present invention is not limited thereto. In another embodiment, the protective layer 130 can be removed after the first shielding layer 120 and the oxide layer 110 are removed, and then performed in another etching process.

[0051] Thus, the MEMS device of the first embodiment of the present invention is formed. In this embodiment, the MEMS device includes a suspension structure, grooves 103, and a mass 105 disposed within the suspension region 210 of the interconnect structure 200. Thus, it can function as a MEMS accelerometer. The piezoelectric layer disposed within the suspension structure generates corresponding vibrations upon receiving an acoustic wave or electrical signal. The mass 105 adjusts the suspension structure to a resonant frequency that meets the desired audio frequency range for sensing. Notably, the mass 105 of this embodiment is formed from a portion of the substrate 100, and thus has the same material as the substrate 100 but is smaller in size than the substrate 100. This results in a thickness T2' of the mass 105 that is significantly thinner than the thickness T1 of the substrate 100, for example, approximately 1 / 4 to 1 / 8 of the thickness T1 of the substrate 100. Thus, the MEMS device of the present invention with the miniaturized mass 105 can be used in wireless Bluetooth headsets to assist in the voice vibration of the microphone.

[0052] Those skilled in the art will also appreciate that the MEMS device and its formation method of the present invention are not limited to those described above and may have other aspects or variations. The following describes other embodiments and variations of the MEMS device and its formation method of the present invention. For simplicity, the following description primarily details the differences between the various embodiments and does not reiterate the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with the same reference numerals to facilitate cross-reference between the various embodiments.

[0053] Another embodiment of the present invention further provides a micro-electromechanical device and a method for forming the same to further improve the accuracy of the groove size or the mass size, and also to make the positioning of the mass in the groove more precise. Since the present invention uses a one-time etching process to directly remove part of the substrate 100 from the second surface 102 of the substrate 100 to a certain depth, forming a groove with a depth of about 300 microns to 350 microns in one go, in some cases, when forming a groove such as Figure 4 as well as Figure 5 When the trench 103 and the proof mass 105 are shown, the size or dimension of the trench 103 may vary significantly during the etching process. The trench 103 may be formed as follows: Figure 4 as well as Figure 5The inclined sidewall shown in the figure, and the change in the inclination angle of the inclined sidewall will cause the size variation of the opening 103a of the groove 103. For example, if the inclination angle of the sidewall of the groove 103 differs by 1 degree, the aperture of the opening 103a of the groove 103 at the first surface 101 of the substrate 100 will differ by more than 10 microns, which may lead to problems such as poor sensitivity or poor sensing accuracy. On the other hand, the reduction of the thickness T2' of the mass block 105 may sometimes also lead to the problem of reduced sensing accuracy. If the thickness of the mass block 105 is too large, or the thickness is not consistent, then according to the following formula (I), the minimum sensing signal (a) of the micro-electromechanical device min In this case, the MEMS device obtained by the above-mentioned formation method will face the impact of inconsistent groove or mass block size variations, which makes it impossible to efficiently carry out large-scale mass production.

[0054]

[0055] In formula (I), κ B is Boltzmann's constant; T is absolute temperature; ω0 is the resonant frequency; m i is the mass of the sensor; Q is the quality coefficient.

[0056] Please refer to Figures 6 to 8 , depicts a schematic diagram of a method for forming a micro-electromechanical system (MEMS) device according to a second embodiment of the present invention. The steps of the method of forming this embodiment are generally similar to those of the previous embodiment, and the similarities are not repeated here. The main difference between this embodiment and the previous embodiment is that this embodiment provides a silicon-on-insulator substrate (SOI substrate) 300 to form the MEMS device.

[0057] like Figure 6As shown, first, a silicon-on-insulator substrate 300 is provided, which further includes a first semiconductor layer 311, an insulating layer 313, and a second semiconductor layer 315 stacked in order from bottom to top. The first semiconductor layer 311 and the second semiconductor layer 315 may comprise, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, or other suitable materials, while the insulating layer 313 may comprise, for example, silicon oxide or silicon dioxide. Specifically, the thickness of the silicon-on-insulator substrate 300 is preferably the same as that of the substrate 100 in the aforementioned embodiment, and thus, the thickness is also represented by T1, which is approximately 400 to 500 microns. The thickness T3 of the first semiconductor layer 311 is, for example, approximately 350 to 400 microns, and the thickness T5 of the second semiconductor layer 315 is approximately 50 to 100 microns, but the present invention is not limited thereto. In one embodiment, the silicon-on-insulator substrate 300 can be formed by the following method. First, the surfaces of two semiconductor layers (not shown) are separately oxidized, the oxidized surfaces of the two semiconductor layers are then bonded together, and one of the two semiconductor layers is thinned to a predetermined thickness, such as, but not limited to, approximately 50 to 100 microns. Preferably, the thickness T5 of the second semiconductor layer 315 can be equal to the predetermined thickness of the subsequently formed mass block, such as, but not limited to, 50 microns. Those skilled in the art will readily appreciate that the thickness of the second semiconductor layer 315 can be further adjusted based on the desired sensing sensitivity of the actual product (according to the aforementioned formula (I)) and is not limited to the aforementioned value.

[0058] In addition, the silicon-on-insulator substrate 300 has two opposite surfaces, such as Figure 6 The first surface 301 and the second surface 302 are shown. An oxide layer 320 and an interconnection structure 200 are also formed in sequence on the first surface 301. The oxide layer 320 preferably comprises a material having the same etching selectivity as the insulating layer 313, such as silicon oxide or silicon dioxide, but is not limited thereto, and the oxide layer 320 and the insulating layer 313 may also have the same thickness. Next, a protective layer 330 is formed on the top surface of the interconnection structure 200 to protect the components arranged in the interconnection structure 200, and the protective layer 330 may also comprise materials such as silicon oxide or silicon dioxide. It should be noted that the detailed features of the interconnection structure 200 in this embodiment are generally the same as those in the aforementioned first embodiment and will not be repeated here. It should also be noted that an opening 313a and a pattern 313b are also provided in the insulating layer 313 of the silicon-coated insulating substrate 300, and the locations of the opening 313a and the pattern 313b correspond to the suspension area 210 of the interconnection structure 200, as shown in FIG. Figure 6As shown. The opening 313a is used to define a trench to be formed in subsequent processes. Therefore, the size of the opening 313a is preferably the predetermined size of the trench, for example, approximately 100 to 150 microns, but not limited thereto. The pattern 313b is disposed within the opening 313a and is used to define the formation position of a proof mass to be formed in subsequent processes. Therefore, the size of the pattern 313b is preferably the predetermined size of the proof mass. In other words, this embodiment integrates the opening 120a of the first shielding layer 120 used to define the trench 103 in the aforementioned embodiment and the pattern 140a of the second shielding layer 140 used to define the proof mass 105 into a single layer, namely, within the insulating layer 313 of the silicon-on-insulator substrate 300. Furthermore, in this embodiment, the shielding layer used to form the trench and the proof mass is pre-formed before other components (such as the interconnect structure 200 or the oxide layer 320) are formed. This formation is even prior to bonding the two semiconductor layers (the first semiconductor layer 311 and the second semiconductor layer 315) together to form the silicon-on-insulator substrate 300. In one embodiment, the insulating layer 313 of the silicon-on-insulator substrate 300 can be formed by first oxidizing the surfaces of the two semiconductor layers (not shown), then patterning the oxidized surfaces of the two semiconductor layers, and finally bonding the oxidized surfaces of the two semiconductor layers together to form the silicon-on-insulator substrate 300.

[0059] Next, a shielding layer 340 is formed on the second surface 302 of the silicon-on-insulator substrate 300. The shielding layer 340 has an opening (not shown) corresponding to the suspension region 210 for forming a trench in the silicon-on-insulator substrate 300. In one embodiment, the size of the opening may be approximately 100 to 150 microns, but is not limited thereto. The shielding layer 340 may comprise, for example, silicon oxide or silicon dioxide, but is not limited thereto. In another embodiment, the shielding layer 340 may also comprise other suitable materials.

[0060] Then, if Figure 7As shown, an etching process, such as an anisotropic dry etching process, is performed through the mask layer 340 to remove the portion of the silicon-on-insulator substrate 300 from the back side, i.e., the side where the second surface 302 is located, to a predetermined depth until the oxide layer 320 or the pattern 313b of the underlying insulating layer 313 is exposed. In other words, the etching process utilizes the oxide layer 320 and the insulating layer 313 as an etch stop layer to form a trench 303 in the silicon-on-insulator substrate 300, such that the trench 303 extends between two opposing surfaces (the first surface 301 and the second surface 302) of the silicon-on-insulator substrate 300 and corresponds to the overhang region 210 of the interconnect structure 200 disposed on the first surface 301. Thus, the trench 303 can have a depth equal to the thickness T1 of the silicon-on-insulator substrate 300, and the trench 303 has an opening 303a adjacent to the bottom surface of the suspension region 210. Moreover, the size of the opening 303a can be accurately controlled to be approximately 100 microns to 150 microns. Simultaneously, during the etching process, a portion of the second semiconductor layer 315 is shielded under the pattern 313b of the insulating layer 313, and a mass block 305 can be formed in the trench 303. Figure 7 In this configuration, the thickness T2 of the mass block 305 (approximately 50 μm to 100 μm) can be accurately controlled by the thickness of the second semiconductor layer 315 , and the location of the mass block 305 can also be accurately controlled by the location of the pattern 313 b within the insulating layer 313 .

[0061] Subsequently, another etching process, such as an isotropic wet etching process, is performed to simultaneously remove the shielding layer 340, the pattern 313b, and the partially exposed oxide layer 320, so that the bottom surface of the suspension region 210 of the underlying interconnect structure 200 can be further exposed and connected to the trench 303. Figure 8 As shown. In this way, the mass block 305 is disposed on the bottom surface of the suspension region 210, so that a portion of the oxide layer 320 is sandwiched between the suspension region 210 and the mass block 305. It should be noted that when performing the other etching process, the remaining oxide layer 320 and the sidewall of the insulating layer 313 can be slightly removed, thereby forming Figure 8 Then, the protective layer 330 is removed to release the suspension structure in the suspension region 210 of the interconnect structure 200, so that one side of the suspension structure is not connected to the silicon-on-insulator substrate 300 and is suspended at one end. Figure 8 In one embodiment, the protection layer 330 can be removed together with the isotropic wet etching process, but is not limited thereto. In another embodiment, the protection layer 330 can also be removed separately by another etching process.

[0062] Thus, the MEMS device of the second embodiment of the present invention is formed. In this embodiment, the MEMS device includes a suspension structure, a groove 303, and a mass 305 disposed within the suspension region 210 of the interconnect structure 200. This device can also function as a MEMS accelerometer. The piezoelectric layer disposed within the suspension structure causes the device to vibrate upon receiving an acoustic wave or electrical signal. The mass 305 adjusts the suspension structure to achieve a resonant frequency within the desired audio frequency range. It is worth noting that in this embodiment, the shielding layer defining the groove 303 and the mass 305 is pre-integrated into the insulating layer 313 of the silicon-on-insulator substrate 300 at the beginning of the manufacturing process. This allows for more precise control of the dimensions of the groove 303 and the mass 305, as well as the position of the mass 305 within the groove 303, thereby improving the sensitivity and sensing accuracy of the MEMS device. Furthermore, the mass block 305 of this embodiment is also made of a portion of the silicon-on-insulator substrate 300, and has the same material as the silicon-on-insulator substrate 300 (i.e., the first semiconductor layer 311 of the silicon-on-insulator substrate 300). It is also smaller in size than the silicon-on-insulator substrate 300, for example, approximately 1 / 4 to 1 / 8 the thickness of the silicon-on-insulator substrate 300. Therefore, the micro-electromechanical system device with the miniaturized mass block 305 of the present invention can be used in wireless Bluetooth headsets to assist in the voice vibration of the microphone.

[0063] In summary, the present invention provides a microelectromechanical device with a miniaturized proof mass. The proof mass is formed from a portion of a substrate, thereby utilizing the same material and possessing a significantly smaller size. The proof mass is approximately one-quarter to one-eighth the size of the substrate. Therefore, the microelectromechanical device with a miniaturized proof mass can be used in wireless Bluetooth headsets to assist in the voice vibration of a microphone.

[0064] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. Those skilled in the art will recognize that several equivalent substitutions or obvious variations can be made without departing from the scope of the present invention, and that any equivalent performance or application should be considered to fall within the scope of protection of the present invention.

Claims

1. A micro-electromechanical device, characterized in that: include: A substrate having a first surface and a second surface opposite to the first surface; a groove disposed in the substrate and extending between the first surface and the second surface; an interconnect structure disposed on the first surface of the substrate and located above the trench; and a mass block disposed in the groove and connected to the interconnection structure, wherein the thickness of the mass block is less than the thickness of the substrate; The interconnection structure includes a suspension area, which includes a suspension structure and is provided with a through-hole. The through-hole passes through the interconnection structure. One end of the suspension structure is connected to the base, and the other end of the suspension structure is adjacent to the through-hole. The setting position of the suspension structure corresponds to the groove and the mass block, and the mass block is located between the one end and the other end of the suspension structure.

2. The micro-electromechanical device according to claim 1, wherein: The substrate comprises a block-shaped silicon substrate; the material of the mass block is the same as that of the block-shaped silicon substrate.

3. The micro-electromechanical system device according to claim 1, wherein: The substrate comprises a silicon-on-insulation substrate, which comprises a first semiconductor layer, an insulation layer and a second semiconductor layer stacked from bottom to top; the material of the mass block is the same as that of the second semiconductor layer.

4. The micro-electromechanical device according to claim 3, wherein: The thickness of the proof block is the same as the thickness of the second semiconductor layer.

5. The micro-electromechanical system device according to claim 1, wherein: The depth of the groove is greater than the thickness of the proof block.

6. The micro-electromechanical system device according to claim 1, wherein: The thickness of the mass block is 1 / 4 to 1 / 8 of the thickness of the substrate.

7. A method for forming a micro-electromechanical device, characterized in that: include: Providing a substrate having a first surface and a second surface opposite to the first surface; forming a groove in the substrate, the groove extending between the first surface and the second surface; forming an interconnect structure on the first surface of the substrate, the interconnect structure including a hanging region, and forming a through-hole in the hanging region of the interconnect structure, the through-hole penetrating the interconnect structure, the hanging region of the interconnect structure including a hanging structure above the groove, one end of the hanging structure connected to the substrate, and the other end of the hanging structure adjacent to the through-hole; and A mass block is formed in the groove, the mass block is connected to the suspension structure, the mass block is located between the one end and the other end of the suspension structure, and the thickness of the mass block is less than the thickness of the substrate.

8. The method for forming a micro-electromechanical system according to claim 7, wherein: Also includes: Before forming the interconnect structure, forming an oxide layer on the first surface, the oxide layer being located between the interconnect structure and the substrate; as well as, After the trench and the proof mass are formed, the oxide layer is removed to partially expose a bottom surface of the interconnect structure.

9. The method for forming a micro-electromechanical system according to claim 8, wherein: After the trench and the proof-block are formed, a portion of the oxide layer between the interconnect structure and the proof-block is removed.

10. The method for forming a micro-electromechanical system according to claim 7, wherein: The substrate comprises a bulk silicon substrate, and the forming method further comprises: forming a first shielding layer on the second surface, the first shielding layer comprising an opening to define the groove; and A second shielding layer is formed on the second surface. The second shielding layer includes a pattern to define the mass block. The pattern is located in the opening.

11. The method for forming a micro-electromechanical system according to claim 10, wherein: The pattern is formed directly on the second surface.

12. The method for forming a micro-electromechanical system according to claim 10, wherein: Also includes: performing a first etching process on the second surface through the first shielding layer and the second shielding layer; After the first etching process is performed, removing the second masking layer; and A second etching process is performed on the second surface through the first shielding layer to form the trench and the proof mass.

13. The method for forming a micro-electromechanical system according to claim 12, wherein: The proof mass is formed from a portion of the bulk silicon substrate.

14. The method for forming a micro-electromechanical system according to claim 7, wherein: The substrate includes a silicon-on-insulation substrate, which includes a first semiconductor layer, an insulation layer and a second semiconductor layer stacked from bottom to top.

15. The method for forming a micro-electromechanical system according to claim 14, wherein: Also includes: Before the interconnection structure is formed, an opening and a pattern are formed in the insulation layer.

16. The method for forming a micro-electromechanical system according to claim 15, wherein: Also includes: forming the proof mass by utilizing the pattern in the insulating layer as an etching mask; as well as, A portion of the trench is formed using the opening in the insulating layer.

17. The method for forming a micro-electromechanical system according to claim 15, wherein: Also includes: After the proof-block is formed, the pattern in the insulating layer is removed.

18. The method for forming a micro-electromechanical system device according to claim 15, wherein: The proof mass is formed by a portion of the second semiconductor layer.

19. The method for forming a micro-electromechanical system device according to claim 14, wherein: The thickness of the proof block is the same as the thickness of the second semiconductor layer.

20. The method for forming a micro-electromechanical system according to claim 7, wherein: Also includes: Before forming the trench, forming the through hole in the suspension region of the interconnect structure, and forming a protection layer to cover the interconnect structure; and After the trench is formed, the protection layer is completely removed to release the suspended structure of the interconnect structure.

Images