Integrated circuit, method for resetting and computer program product

Abstract

The present application relates to an integrated circuit, a method for resetting, and a computer program product. The integrated circuit includes a first part and a second part. The first part includes: a reset input terminal configured to receive a reset signal; an activation module connected to the reset input terminal. The activation module is configured to activate the second part once the reset signal is received. The first part includes a transmitting module configured to send a regeneration reset signal. The second part can be selectively activated or deactivated. The second part includes: a reset input terminal configured to receive a regeneration reset signal from the transmitting module; a determination module configured to determine that the time elapsed from the activation of the second part of the circuit exceeds a threshold.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuits that include several portions, some of which can be selectively placed in a standby type operating mode (hereinafter referred to as the standby operating mode) or in an active type operating mode (hereinafter referred to as the active operating mode). Background Art

[0002] An integrated circuit, also called an electronic chip, is an electronic component that includes a single wafer of semiconductor material. An integrated circuit is typically configured to perform several functions and, for this purpose, usually includes several types of basic electronic components.

[0003] An integrated circuit generally has the form of a rectangular solid housing provided on one or more sides or even on one face with pins which enable it to establish an electrical connection with components outside the housing.

[0004] A portion of an integrated circuit can be selectively placed in an active operating mode or a standby operating mode. The standby operating mode is also known as a low power mode. In the standby operating mode, the supply voltage of the portion of the integrated circuit is therefore reduced relative to the supply voltage used when the portion of the integrated circuit is in the active operating mode.

[0005] The first supply voltage is usually fixed to be sufficient to enable information recorded in the memory to be retained in the portion of the integrated circuit powered by the voltage. The first supply voltage is also sufficient to allow the portion of the integrated circuit powered by the voltage to be reset.

[0006] Alternatively, a second supply voltage lower than the first voltage may also be used, the second supply voltage also being sufficient to ensure that the information recorded in the memory is retained in the portion of the integrated circuit powered by the second supply voltage.

[0007] However, the second voltage may not be sufficient to reset the portion of the integrated circuit powered by the voltage.

[0008] Then, in the case where a part of the integrated circuit is powered by a voltage comprised between the first voltage and the second voltage (for example comprised between 0.66 V and 0.9 V), a problem arises when this part of the integrated circuit receives a reset signal, in which case this part of the integrated circuit is not actually reset.

[0009] Therefore, there is a need for an integrated circuit that allows resetting of a portion of the integrated circuit when the portion of the integrated circuit is powered by a voltage that is normally insufficient for resetting, such as a voltage comprised between 0.66V and 0.9V. Summary of the invention

[0010] In one embodiment, an integrated circuit includes a first part and a second part. The first part includes a reset input terminal configured to receive a reset signal, and an activation module connected to the reset input terminal. The activation module is configured to activate the second part once the reset signal is received. The first part includes a transmitting module configured to send a regeneration reset signal. The second part can be selectively activated or deactivated. The second part includes a reset input terminal configured to receive a regeneration reset signal of the transmitting module, and a determination module configured to determine that the time elapsed from the activation of the second part of the circuit exceeds a threshold. The integrated circuit enables the transmitting module to be configured to send a regeneration reset signal when the reset signal is received, and the transmitting module is configured to stop sending the regeneration reset signal when the threshold is exceeded.

[0011] The integrated circuit according to the first aspect of the present disclosure facilitates the resetting of the second part even if the reset signal is received during the period when the second part is in standby. In fact, after receiving the reset signal, the first part activates the second part. After this activation, the first part issues a regeneration reset signal. This issuance is performed for a sufficiently long time so that the second part can be activated and the second part is in a state that allows it to be reset at the moment of issuing the regeneration reset signal.

[0012] In one embodiment, the transmitting module includes a trigger. The trigger is configured to be selectively in a storage state or in an erase state. The trigger includes a clock input terminal connected to a reset input terminal of the first part, a data input terminal receiving an activation signal, and an erase input terminal connected to an output terminal of the determination module. The determination module is configured to send an overrun signal at its output terminal when a threshold is exceeded. The trigger is configured to switch to a storage state upon receiving an edge of a reset signal, and the output terminal of the trigger is configured to send an activation state signal when the trigger is in the storage state. The trigger is configured to switch to an erase state when the overrun signal is valid. The output terminal of the trigger is configured to send a non-valid state signal when the trigger is in the erase state.

[0013] In one embodiment, the transmitting module includes a logic gate. The logic gate includes a first input terminal configured to receive a state signal of an output terminal of a trigger, a second input terminal configured to receive a reset signal, and an output terminal connected to the output terminal of the transmitting module and configured to send a regeneration reset signal. The logic gate is configured so that the regeneration reset signal is valid if the state signal is valid or if the reset signal is valid.

[0014] In one embodiment, the second part includes a clock configured to send a clock signal when the second part is valid. The determination module includes a first trigger and a second trigger. The first trigger includes a clock input configured to receive a clock signal, a data input configured to receive a non-valid signal, and an output configured to send an intermediate output signal. The first trigger is configured so that after a first edge of the clock signal, the intermediate output signal switches to an activated state. The second trigger includes a clock input configured to receive a clock signal, a data input connected to an output of the first trigger, and an output connected to an output of the determination module and configured to send an override signal. The second trigger is configured so that after a second edge of the clock signal after the first edge, the override signal switches to an activated state.

[0015] In an embodiment, the integrated circuit includes a first logic gate, the first logic gate includes an input terminal connected to the output terminal of the transmitting module of the first part, an output terminal connected to the reset input terminal of the second part, and a control input terminal connected to the isolated output terminal of the activation module. The integrated circuit includes a second logic gate, the second logic gate includes an input terminal connected to the transcending output terminal of the determination module, an output terminal connected to the transcending input terminal of the transmitting module of the first part, and a control input terminal connected to the isolated output terminal of the activation module. The activation module is configured to send an isolation signal at its isolated output terminal. The first logic gate is configured to be turned on when its control input terminal receives the isolation signal. The second logic gate is configured to be turned on when its control input terminal receives the isolation signal.

[0016] According to another aspect, a method for resetting a second part of an integrated circuit by a first part of the integrated circuit is provided. The method comprises the following steps:

[0017] Receiving a reset signal from the first part (PART1);

[0018] Activate the second part;

[0019] Sending a regeneration reset signal from the first part to the second part;

[0020] determining that the time elapsed since activation of the second portion has exceeded a threshold; and ceasing to issue the regeneration reset signal when the time elapsed since activation of the second portion exceeds the threshold.

[0021] In one embodiment, the method for resetting includes a step of electrically connecting the first part and the second part. The connecting step is performed between the activating step and the issuing step.

[0022] According to another aspect, an integrated circuit is provided, comprising a first part and a second part. The first part is used to implement the above-mentioned method for resetting.

[0023] In one embodiment, an integrated circuit includes: a first circuit device; and a second circuit device coupled to the first circuit device, wherein the first circuit device, when operating, responds to a reset signal by: generating an activation signal; and generating a regeneration reset signal; a second circuit device, when operating: being activated in response to the activation signal; being reset in response to the regeneration reset signal; and generating an indication of whether a threshold time period has passed since activation of the second circuit device, wherein the first circuit device, when operating, disables the regeneration reset signal in response to the generated indication that the threshold time period has passed.

[0024] In one embodiment, a method includes: generating an activation signal using a first circuit device of an integrated circuit in response to a reset signal; generating a regeneration reset signal using the first circuit device; activating a second circuit device of the integrated circuit in response to the activation signal; resetting the second circuit device in response to the regeneration reset signal; generating, by the second circuit device, an indication as to whether a threshold time period has passed since activation of the second circuit device; and disabling, by the first circuit device, the regeneration reset signal in response to the generated indication that the threshold time period has passed.

[0025] In one embodiment, a system includes: a main circuit, which generates a reset signal when in operation; and an integrated circuit coupled to the main circuit, the integrated circuit including an activation circuit device and a functional circuit device coupled to the activation circuit device, wherein the integrated circuit, when in operation: generates an activation signal using the activation circuit device to respond to a reset signal received from the main circuit; generates a regeneration reset signal using the activation circuit device; activates the functional circuit device of the integrated circuit in response to the activation signal; resets the functional circuit device of the integrated circuit in response to the regeneration reset signal; generates an indication using the functional circuit device as to whether a threshold time period has passed since the activation of the functional circuit device; and interrupts the regeneration reset signal in response to the generated indication that the threshold time period has passed.

[0026] In one embodiment, the contents of a non-transitory computer readable medium configure an integrated circuit to perform a method comprising: responding to a reset signal by generating an activation signal; generating a replicated reset signal; activating a functional circuit device of the integrated circuit in response to the activation signal; resetting the functional circuit device in response to the regeneration reset signal; generating an indication as to whether a threshold time period has elapsed since activation of the functional circuit device; disabling the regeneration reset signal in response to the generated indication that the threshold time period has elapsed BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present disclosure will emerge from the following description, which is for purposes of illustration only and not limitation, and which must be read in conjunction with the accompanying drawings, in which:

[0028] Figure 1An integrated circuit according to an embodiment of the present disclosure is schematically shown;

[0029] Figure 2 An integrated circuit according to another embodiment of the present disclosure is schematically shown;

[0030] Figure 3 a timing diagram showing various signals exchanged between various components of an integrated circuit according to an embodiment of the present disclosure; and

[0031] Figure 4 A method for resetting according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] Figure 1 An integrated circuit CINT according to an embodiment of the present disclosure is diagrammatically shown.

[0033] Note that in the drawings, a solid square represents an input or output, while a solid circle represents an electrical connection between two cables or lines.

[0034] In the following, inputs are indicated by reference numerals beginning with the number 1, and outputs are indicated by reference numerals beginning with the number 2.

[0035] The integrated circuit CINT comprises a first part or circuit arrangement PART1 and a second part or circuit arrangement PART2.

[0036] The second part PART2 can optionally have two operating modes:

[0037] Valid operating modes, and

[0038] Standby operating mode.

[0039] The supply voltage of the second part PART2 is typically 0.6 V when it is in standby mode. The supply voltage of the second part PART2 is typically 0.9 V when it is active.

[0040] The supply voltage of the first part PART1 is usually 3.0V when it is in standby mode.

[0041] When the supply voltage of the second part PART2 is changed to switch it from a standby operating voltage to an active operating voltage, the second part PART2 is considered to be active.

[0042] The first part PART1 and the second part PART2 each include several modules or circuits. These modules exchange logic signals between them. Each logic signal is represented by an electrical signal that can have two levels, a high level ("H") and a low level ("L") . The voltage of the high level is greater than the voltage of the low level. The switching of the electrical signal from the low level to the high level is called a rising edge. The switching of the electrical signal from the high level to the low level is called a falling edge.

[0043] The effective level is defined as the level that enables it to perform the function assigned to the signal. In one embodiment, a low level (L) can be arbitrarily selected as the effective level. The signal is then said to be effective. If the signal is at another level (H), the signal is said to be invalid. Similarly, an effective edge is defined as the edge or transition of the signal that triggers the function assigned to the signal. In other embodiments, a high level can be the effective level.

[0044] In the following description, the rising edge is arbitrarily selected as the effective edge of the clock signal. In other embodiments, the falling edge can be the effective edge of the clock signal. Simply put, when the signal is received at an effective level, it is said that the signal is received, and when it is sent at an effective level, it is said that the signal is sent; when the signal is received at an invalid level, it is said that the signal is not received, and when the signal is sent at an invalid level, it is said that the signal is not sent or that the signal stops being sent.

[0045] The first part PART1 includes an input terminal 11A (reset input terminal) for receiving a reset signal RST1. Consider that the reset signal RST1 has 3.0V for a high level and 0V for a low level. The reset input terminal 11A can usually be electrically connected to another device, such as a third-party device 2, and receive the reset signal RST1 of the third-party device. The third-party device is, for example, a push button for resetting the integrated circuit CINT, or another "master" circuit for issuing the reset signal RST1.

[0046] Typically this can be a simple push button for an emergency reset, or the signal can be controlled by another "master" circuit in the application.

[0047] The first part PART1 comprises an output terminal 21A configured to issue an activation signal ACTIV1 (described below) to the second part PART2.

[0048] The first part PART1 includes an output terminal 21B, which is configured to send a regeneration reset signal RST2 (described below) to the second part PART2. Consider that when the second part PART2 is in an active operation mode, the regeneration reset signal RST2 has 0.9V for a high level and 0V for a low level. Consider that when the second part PART2 is in a standby operation mode, the regeneration reset signal RST2 has 0.66V for a high level and 0V for a low level.

[0049] Normally, resetting is performed when the reset signal RST1 has a low level (L), and thus the active level of the reset signal is a low level.

[0050] The first part PART1 comprises an input terminal 11B configured to receive an override signal DEPAS (described below) of the second part PART2 .

[0051] The first part PART1 comprises an activation module or circuit ACTIV, which is configured to activate the second part PART2. The activation module ACTIV comprises an input 12, which is electrically connected to the reset input 11A; an output 22, which is connected to the output 21A of the first part PART1 to provide an activation signal ACTIV1 to the second part PART2. The activation module ACTIV is then configured to activate the second part PART2 of the integrated circuit CINT by sending the activation signal ACTIV1 when the reset signal has a low level.

[0052] When the reset signal RST1 has a low level, the activation module ACTIV may also be configured to control an increase in a voltage supplying power to the second part PART2 .

[0053] The first part PART1 includes a transmitting module or circuit EMI, which is configured to send a regeneration reset signal RST2. The transmitting module EMI includes an input terminal 13A (reset input terminal), which is coupled to the input terminal 11A to receive the signal RST1. The transmitting module EMI includes an input terminal 13B (override input terminal), which is coupled to the input terminal 11B to receive the override signal DEPAS of the second part PART2. The transmitting module EMI includes an output terminal 23, which is connected to the output terminal 21B of the first part PART1, and sends a regeneration reset signal RST2.

[0054] The transmitting module EMI is configured to issue a regeneration reset signal RST2 at a low level (active level) upon receiving the reset signal RST1 , and to issue a regeneration reset signal RST2 at a high level (inactive level) upon receiving the override signal DEPAS.

[0055] The second part PART2 comprises a clock CLK, a determination module or circuit DET and a processing module or circuit UNIT of the processor type.

[0056] The second part PART2 comprises: an input terminal 14A (activation input terminal) for receiving an activation signal ACTIV1; an input terminal 14B (reset input terminal) for receiving a regeneration reset signal RST2. The second part PART2 comprises an output terminal 24, through which an overrun signal DEPAS is sent. The output terminal 24 is connected to the input terminal 11B of the first part PART1 and to the input terminal 13B of the transmitting module EMI, so as to allow the transmitting module EMI to receive the overrun signal DEPAS.

[0057] The processing module UNIT comprises an input terminal 17 (reset input). The input terminal 17 is connected to the input terminal 14B of the second part PART2, to the output terminal 21B of the first part PART1, to the output terminal 23 of the transmitting module EMI, to receive the regeneration reset signal RST2. The processing module UNIT of the second part PART2 is then configured to be reset when the regeneration reset signal RST2 is at a low level (active level).

[0058] The clock CLK comprises: an input terminal 15 connected to the input terminal 14A of the second part PART2, receiving the activation signal ACTIV1 of the first part PART1; and an output terminal 25, on which the clock signal CLK is emitted. The clock signal CLK is an oscillating electrical signal, which provides the clock signal of the second part PART2 of the circuit.

[0059] Typically, the oscillating electrical signal is of the time slot or pulse type and has a series of rising edges followed by falling edges. The period of the oscillating electrical signal is called a clock period. The clock CLOCK is turned off when the second part PART2 is in standby and does not send out the clock signal CLK. The clock CLOCK is turned on when the second part PART2 is active. When the clock CLOCK receives the activation signal ACTIV1 at its input terminal 15, it sends out the clock signal CLK.

[0060] The determination module or circuit DET comprises an input 16 and an output 26. It receives the clock signal CLK at its input 16 and is configured to count the number of edges (rising or falling) of the clock signal CLK. When the number of edges exceeds an edge threshold (e.g. two edges), the elapsed time exceeds a time threshold.

[0061] The determination module DET thus determines that the time which has elapsed since the activation of the second part PART2 exceeds the time threshold value and, after this exceeding, outputs an exceeding signal DEPAS at its output 26 .

[0062] The determination module DET is electrically connected to the first part PART1. More specifically, the output terminal 26 of the determination module DET is electrically connected to the output terminal 24 of the second part PART2 and to the input terminal 11B of the first part PART1 to transmit the override signal DEPAS to the transmission module EMI.

[0063] Thus, when the transmitting module EMI receives the override signal DEPAS, the transmitting module EMI stops issuing the regeneration reset signal RST2 by switching the level of the signal to a high level (invalid level). In one embodiment, it is generally considered that the override signal DEPAS is received when the override signal has a high level.

[0064] The second part PART2 may also include another internal circuit ( Figure 1 ), which is connected to the input terminal 14A and is configured to receive the activation signal ACTIV1.

[0065] Figure 2 The integrated circuit CINT is shown in more detail.

[0066] As about Figure 1 As depicted, the integrated circuit CINT comprises a first part or circuit arrangement PART1, a second part or circuit arrangement PART2, and modules or circuits ACTIV, EMI, DET, CLOCK and UNIT.

[0067] The transmitting module EMI comprises a logic gate G of the “logical AND” type and a flip-flop BASC.

[0068] The trigger BASC is a logic circuit. The trigger BASC includes an input terminal 13F (clock input terminal), which is connected to the input terminal 13A of the transmitting module EMI, connected to the input terminal 11A of the first part PART1, to receive the reset signal RST1. The trigger BASC includes an input terminal 13G (erase input terminal), which is connected to the input terminal 13B of the transmitting module EMI, connected to the input terminal 11B of the first part PART1, to receive the transcendence signal DEPAS. The trigger BASC includes an input terminal 13E (data input terminal) to receive a signal in a low state L. The trigger BASC finally includes an output terminal 23B to provide a state signal ETAT.

[0069] The state signal ETAT changes with the receipt of the falling edge of the reset signal RST1 (received at the clock input of the flip-flop). At the moment of the falling edge, the level of the state signal ETAT adopts the level of the signal received at the data input. The level of the state signal ETAT is then not changed as long as the falling edge of the reset signal RST1 does not occur again. The data input is at a low level, so with the falling edge of the signal at the clock input, the state signal ETAT switches to a low level. The erase input 13G allows the flip-flop BASC to be erased. When a low level signal is applied to the erase input 13G of the flip-flop BASC, the signal emitted at the output 23B of the flip-flop BASC is set back to a high level.

[0070] Consider that when the output terminal 23B of the flip-flop BASC sends a low-level signal L, the flip-flop BASC is in a storage state, and when the output terminal 23B of the flip-flop BASC sends a high-level signal H, the flip-flop BASC is in an erase state.

[0071] The logic gate G comprises a first input terminal 13C connected to the input terminal 13A of the transmitting module EMI to receive the reset signal RST1. The logic gate G comprises a second input terminal 13D connected to the output terminal 23B of the flip-flop BASC. The logic gate G comprises an output terminal 23A connected to the output terminal 23 of the transmitting module EMI to issue a regeneration reset signal RST2.

[0072] As long as the first input terminal 13C and the second input terminal 13D receive a high level signal, the regeneration reset signal RST2 issued at the output terminal 23A of the logic gate G is at a high level. If the first input terminal 13C or the second input terminal 13D receives a low level signal, the regeneration reset signal RST2 issued at the output terminal 23A is at a low level.

[0073] Therefore, considering that the low level is an effective level, when the reset signal RST1 is effective or the state signal ETAT is effective, the regeneration reset signal RST2 is effective.

[0074] In an embodiment where the high level is the valid level of the reset signal RST1, the logic gate G is a "logic OR" type gate, so that when the reset signal RST1 is valid (high level) or the status signal ETAT is valid (high level), the regeneration reset signal RST2 is valid (high level).

[0075] The determination module DET comprises a first flip-flop BASC1 and a second flip-flop BASC2 .

[0076] The first flip-flop BASC1 is a logic circuit. The first flip-flop BASC1 includes an input terminal 16A (clock input terminal), which is connected to the input terminal 16 of the determination module DET and to the output terminal 25 of the clock CLOCK to receive the clock signal CLK. The first flip-flop BASC1 includes an input terminal 16B (data input terminal), which receives a high level signal (therefore an invalid signal). The first flip-flop BASC1 includes an output terminal 26A to send an intermediate output signal.

[0077] The second flip-flop BASC2 is a logic circuit. The second flip-flop BASC2 includes an input terminal 16C (clock input terminal), which is connected to the input terminal 16 of the determination module DET to receive the clock signal CLK. The second flip-flop BASC2 includes an input terminal 16D (data input terminal), which is connected to the output terminal 26A of the first flip-flop BASC1 to receive the intermediate output signal. The second flip-flop BASC2 includes an output terminal 26B, which is connected to the output terminal 26 of the determination module DET to send the exceedance signal DEPAS.

[0078] Therefore, immediately following the activation of the second part PART2 and the reactivation of the clock CLOCK of the second part PART2, the first falling edge appearing on the clock signal CLK received on the input terminal 16A of the first flip-flop BASC1 switches the level of the intermediate output signal emitted on the output terminal 26A of the first flip-flop BASC1 from a low level to a high level. The second falling edge appearing on the clock signal CLK received on the input terminal 16C of the second flip-flop BASC2 switches the level of the overrun signal DEPAS emitted on the output terminal 26B of the second flip-flop BASC2 from a low level to a high level. The overrun signal DEPAS is then inverted at the output terminal 29 of the logic gate G2 so as to obtain a low level at the erase input terminal 13G of the flip-flop BASC. The reception of the low-level overrun signal DEPAS causes the flip-flop BASC of the transmitting module EMI to switch to the erase state. This switching causes the transmitting module EMI to stop the emission of the regeneration reset signal RST2.

[0079] Figure 2 The integrated circuit CINT and Figure 1 The integrated circuit CINT differs in that the output terminal 21B of the first part PART1 and the input terminal 14B of the second part PART2 are selectively connected or electrically isolated from each other by an inserted logic gate G1.

[0080] Likewise, the output terminal 24 of the second part PART2 and the input terminal 11B of the first part PART1 are selectively connected to each other or electrically isolated by the interposed logic gate G2.

[0081] The logic gate G1 is a follower type gate having an output terminal selectively connected to an input terminal or electrically isolated from the input terminal.

[0082] The logic gate G2 is an inverting follower type gate having an output terminal selectively connected to an input terminal or electrically isolated from the input terminal. In addition, the logic gate inverts the level of the signal emitted by the output terminal relative to the signal received by the input terminal. Therefore, if the logic gate G2 receives a high level signal H, it emits a low level signal L, and if the logic gate G2 receives a low level signal L, it emits a high level signal H.

[0083] The logic gate G1 includes an input terminal 18A connected to the output terminal 21B of the first part PART1 and an output terminal 28 connected to the input terminal 14B of the second part PART2. The logic gate G1 includes an input terminal 18B (control input terminal) which receives an isolation signal ISO, as described below. The isolation signal ISO controls the logic gate G2 so that its input terminal 18A and output terminal 28 are connected or isolated.

[0084] Similarly, the logic gate G2 includes: an input terminal 19A, which is connected to the output terminal 24 of the first part PART1; an output terminal 29, which is connected to the input terminal 11B of the second part PART2. The logic gate G2 includes an input terminal 19B (control input terminal), which receives the isolation signal ISO. The isolation signal ISO controls the logic gate G2 so that its input terminal 19A and output terminal 29 are connected or isolated.

[0085] In the presence of logic gates G1 and G2, the activation module ACTIV also includes an output 22A (isolated output), which is connected to the output 21C of the first part PART1, respectively connected to the input 18B of the logic gate G1 and the input 19B of the logic gate G2, to provide an isolated signal ISO that can control the logic gates G1 and G2. The isolated signal ISO is valid as long as the supply voltage of the second part PART2 is less than a value that guarantees the full functionality of the second part PART2, for example 0.81V. The goal is to ensure that as long as the supply voltage of the second part PART2 is less than 0.81V:

[0086] The input 14B of the second part PART2 receives a signal with a static level. In fact, the signal that changes at the output 21B of the first part PART1 is not transmitted due to the first logic gate G1. In fact, at a voltage below 0.81V, it is impossible to ensure the influence of dynamic activities on the reset signal in the domain Part2, and only a storage function can be provided.

[0087] The input terminal 11B of the first part PART1 receives a signal with a static level. In fact, the signal that changes at the output terminal 24 of the second part PART2 is not transmitted due to the second logic gate G2. The transmission of the signal from the first part PART1 to the second part PART2 is performed more complicatedly so that the difference between the supply voltages of the first part PART1 and the second part PART2 is very high. Specifically, only when the supply voltage of the second part PART2 is greater than 0.81V, it is possible to transmit the signal of the second part PART2 to the first part PART1.

[0088] In one embodiment, the logic gate G1 is configured to connect its input terminal 18A and its output terminal 28 when the isolation signal ISO received at the control input terminal 18B has a low level L. The logic gate G1 is configured to isolate its input terminal 18A and its output terminal 28 when the isolation signal ISO received at the control input terminal 18B has a high level H.

[0089] Likewise, the logic gate G2 is configured to connect its input terminal 19A and its output terminal 29 when the isolation signal ISO received at the control input terminal 19B has a low level L. The logic gate G2 is configured to isolate its input terminal 19A and its output terminal 29 when the isolation signal ISO received at the control input terminal 19B has a high level H.

[0090] Therefore, when the isolation signal ISO has the high level H, the regeneration reset signal RST2 and the override signal DEPAS are not transmitted between the first part PART1 and the second part PART2.

[0091] The first flip-flop BASC1 of the determination module DET may comprise an input 16E (erase input) connected to an input 16G of the determination module DET, to an input 14C of the second part PART2, to an output 21C of the first part PART1 to receive the isolation signal ISO.

[0092] Likewise, the second flip-flop BASC2 may include an input terminal 16F (erase input terminal) connected to the input terminal 16G of the determination module DET to receive the isolation signal ISO.

[0093] The receipt of the high-level isolation signal ISO at the input terminal 16E of the first flip-flop BASC1 results in erasure of the first flip-flop BASC1 and switching to a low level of the signal emitted at the output terminal 26A of the first flip-flop BASC1. Similarly, the receipt of the high-level isolation signal ISO at the input terminal 16F of the second flip-flop BASC2 results in erasure of the second flip-flop BASC2 and switching to a low level of the signal emitted at the output terminal 26B of the second flip-flop BASC2.

[0094] Therefore, following the issuance of the high level isolation signal, the cessation of the isolation between the first part PART1 and the second part PART2 is controlled, and the flip-flops BASC1 and BASC2 of the determination module DET are reset in anticipation of a future reception cycle of the regenerative reset signal RST2.

[0095] Figure 3 Shown in Figure 2 Timing diagram of the various signals exchanged between the various components of the integrated circuit CINT described in FIG.

[0096] The figure is divided into three parts (from left to right): part A, in which the second part PART2 is active; part B, in which the second part PART2 is on standby; and part C, in which the second part PART2 is reactivated.

[0097] Starting from the top, the signals shown are as follows:

[0098] The signal of the clock CLK of the second part PART2, the clock signal CLK is first valid (part A), then the signal is invalid (part B), and finally the signal becomes valid again following the reactivation of the second part PART2 (part C).

[0099] Reset signal RST1, which is received between two times t1 and t2 when the second part PART2 is invalid (part B). Between these two times, the first part PART1 is isolated from the second part PART2, the second part PART2 is in standby and the duration of the reset signal RST1 is less than the duration required for the reactivation of the second part PART2. Therefore, the second part PART2 cannot be reset using the reset signal RST1.

[0100] The isolation signal ISO is set to a high state H by the activation module ACTIV when the second part PART2 is in standby (part B) to electrically isolate the first part PART1 from the second part PART2.

[0101] The regeneration reset signal RST2 is sent by the transmitting module EMI after receiving the reset signal RST1 (starting from the time t1) and until the two edges of the clock of the second part PART2 are received (until the time t4). Therefore, the regeneration reset signal RST2 is sent in the time interval included between the time t1 and t4 to make it possible that the second part PART2 is activated (starting at the time t3), and the second part PART2 receives the regeneration reset signal RST2 when it is reactivated.

[0102] The override signal DEPAS is issued when two edges of the clock of the second part PART2 are received. Following the reception of the override signal, at time t4, the transmitting module EMI stops issuing the regeneration reset signal.

[0103] Regeneration reset signal RST2', which is received by the second part PART2, for example. The logic gate G1 is in isolation mode until the moment t3 marking the start of activation of the second part PART2. Therefore, during the time interval comprised between t1 and t3, the regeneration reset signal RST2 emitted at the output 21B of the first part PART1 is not received at the input 14B of the second part PART2 due to the isolation of the logic gate G1. Starting from the moment t3 (marking the end of the isolation between the first part PART1 and the second part PART2) and until the moment t4 (marking the end of the emission of the regeneration reset signal RST2), the regeneration reset signal RST2 is received by the second part PART2.

[0104] Figure 4 A method 400 for resetting according to an aspect of the present disclosure is shown.

[0105] More specifically, the method 400 is a method for resetting a second part PART2 of an integrated circuit CINT through a first part PART1 of the integrated circuit CINT.

[0106] The method includes the following steps 401 to 406:

[0107] Step 401 - receiving a reset signal RST1 by the first part PART1;

[0108] Step 402 - Activate the second part PART2;

[0109] Step 403 - electrical connection between the first part PART1 and the second part PART2;

[0110] Step 404 - the first part PART1 sends a regeneration reset signal RST2 to the second part PART2;

[0111] Step 405 - determining that the time elapsed since activation of the second part PART2 has exceeded a threshold; and

[0112] Step 406 —When the time elapsed since the activation of the second part PART2 has exceeded the threshold, stop issuing the regeneration reset signal RST2 .

[0113] If the first part PART1 and the second part PART2 are permanently electrically connected together, the connecting step 403 is not required.

[0114] Embodiment examples are described below and include example references to the accompanying drawings.

[0115] The integrated circuit (CINT) can be summarized as comprising a first part (PART1) and a second part (PART2); the first part (PART1) comprises a reset input terminal (11A) configured to receive a reset signal (RST1), an activation module (ACTIV) connected to the reset input terminal (11A), the activation module (ACTIV) being configured to activate the second part (PART2) upon receiving the reset signal, and a transmitting module (EMI) configured to emit a regenerative reset signal (RST2); the second part (PART2) can be Selectively activated or deactivated, the second part (PART2) includes a reset input terminal (14B) configured to receive a regeneration reset signal (RST2) of a transmitting module (EMI), a determination module (DET) configured to determine whether the elapsed time from the activation of the second part of the circuit exceeds a threshold; the integrated circuit (CINT) causes the transmitting module (EMI) to be configured to issue a regeneration reset signal (RST2) once the reset signal (RST) is received, and the transmitting module (EMI) is configured to stop issuing the regeneration reset signal (RST2) when the threshold is exceeded.

[0116] The transmitting module (EMI) may include a trigger (BASC), the trigger (BASC) being configured to be selectively in a storage state or in an erase state, the trigger (BASC) comprising: a clock input terminal (13F) connected to a reset input terminal (11A) of the first part (PART1), a data input terminal (13E) receiving an activation signal, and an erase input terminal (13G) connected to an output terminal (26) of a determination module (DET); the determination module (DET) being configured to send a surpassing signal (D ) at its output terminal (26) when a threshold value is surpassed. The invention relates to a method for storing a memory chip of a storage device and a memory chip of a storage device. The method comprises the following steps: a first trigger (BASC) is configured to switch to a storage state upon receiving an edge of a reset signal (RST), and an output terminal (23B) of the trigger (BASC) is configured to send an activation state signal (ETAT) when the trigger (BASC) is in the storage state; a second trigger (BASC) is configured to switch to an erasure state when an override signal (DEPAS) is valid, and an output terminal (23B) of the trigger (BASC) is configured to send an invalid state signal (ETAT) when the trigger (BASC) is in the erasure state.

[0117] The transmitting module (EMI) may include a logic gate (G); the logic gate (G) includes: a first input terminal (13D) configured to receive a state signal (ETAT) of an output terminal (23B) of a trigger (BASC); a second input terminal (13C) configured to receive a reset signal (RST); and an output terminal (23A) connected to an output terminal (23) of the transmitting module (EMI) and configured to send a regeneration reset signal (RST2); the logic gate (G) is configured to enable the regeneration reset signal (RST2) to be valid when the state signal (ETAT) is valid or when the reset signal (RST) is valid.

[0118] The second part (PART2) may include: a clock (CLOCK) configured to send a clock signal (CLK) when the second part (PART2) is valid; a determination module (DET) including a first trigger (BASC1) and a second trigger (BASC2); the first trigger (BASC1) includes: a clock input terminal (16A) configured to receive the clock signal (CLK), a data input terminal (16B) configured to receive an invalid signal, and an output terminal (26A) configured to send an intermediate output signal; the first trigger (BASC1) is configured to send a clock signal (CLK) when the second part (PART2) is valid; After an edge, the intermediate output signal switches to a valid state; the second flip-flop (BASC2) comprises: a clock input terminal (16C) configured to receive a clock signal (CLK), a data input terminal (16D) connected to an output terminal (26A) of the first flip-flop (BASC1), and an output terminal (26B) connected to an output terminal (26) of a determination module (DET) and configured to send an override signal (DEPAS); the second flip-flop (BASC2) is configured to switch the override signal (DEPAS) to a valid state after a second edge of the clock signal (CLK) after the first edge.

[0119] The integrated circuit may include: a first logic gate (G1) and a second logic gate (G2), the first logic gate (G1) including: an input terminal (18A) connected to an output terminal (23) of a transmitting module (EMI) of a first part (PART1); an output terminal (28) connected to a reset input terminal (14B) of a second part (PART2); a control input terminal (18B) connected to an isolated output terminal (22A) of an activation module (ACTIV); the second logic gate (G2) including: an input terminal (19A) connected to an override output terminal (26) of a determination module (DET); an output terminal (28) connected to a reset input terminal (14B) of a second part (PART2); and a control input terminal (18B) connected to an isolated output terminal (22A) of an activation module (ACTIV). The invention relates to a first logic gate (G1) and a second logic gate (G2). The invention relates to a first logic gate (G2) and a second logic gate (G3) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention. The invention relates to a first logic gate (G1) and a second logic gate (G2) provided in accordance with the present invention.

[0120] A method for resetting a second part (PART2) of an integrated circuit (CINT) by means of a first part (PART1) of the integrated circuit (CINT), the method being summarized as comprising the steps of receiving (401) a reset signal (RST) by the first part (PART1), activating (402) the second part (PART2), sending (404) a regeneration reset signal (RST2) by the first part (PART1) to the second part (PART2), determining (405) the time elapsed since the activation of the second part (PART2), and ceasing (406) sending the regeneration reset signal (RST2) when the time elapsed since the activation of the second part (PART2) has exceeded a threshold value.

[0121] The method for resetting may further comprise a step of electrical connection (403) between the first part (PART1) and the second part (PART2); the connection step (403) being performed between the activation step (402) and the issuing step (404).

[0122] The integrated circuit (CINT) can be summarized as comprising a first part (PART1) and a second part (PART2), the first part (PART1) being configured for the implementation of the method of resetting.

[0123] The computer program product may be summarized as comprising program code instructions which, when they are executed by the integrated circuit (CINT), cause the implementation of the method for resetting.

[0124] In one embodiment, an integrated circuit includes: a first circuit device; and a second circuit device coupled to the first circuit device, wherein the first circuit device, when in operation, responds to a reset signal by: generating an activation signal, and generating a regeneration reset signal; the second circuit device, when in operation, is activated in response to the activation signal, is reset in response to the regeneration reset signal, and generates an indication of whether a threshold time period has passed since the second circuit device was activated, wherein the first circuit device, when in operation, disables the regeneration reset signal in response to the generated indication that the threshold time period has passed. In one embodiment, the first circuit device includes a flip-flop, the flip-flop including: a clock input terminal, which, when in operation, receives the reset signal; a data input terminal, which, when in operation, receives a valid signal; and an erase input terminal, which, when in operation, receives the generated indication of whether the threshold time period has passed, wherein the flip-flop, when in operation, switches to a storage operation state and issues an activation state signal at an output of the flip-flop in response to receiving an edge of the reset signal; and switches to an erase operation state and issues an invalid state signal at an output of the flip-flop in response to the generated indication that the threshold time period has passed. In one embodiment, the first circuit device includes a logic gate having: a first input terminal coupled to an output terminal of a flip-flop; a second input terminal receiving a reset signal when in operation; and an output terminal issuing a regeneration reset signal when in operation, wherein the regeneration reset signal is valid if the state signal is valid or the reset signal is valid. In one embodiment, wherein the second circuit device includes: a clock, which generates a clock signal when in operation when the second circuit device is valid; the first flip-flop includes: a clock input terminal receiving the clock signal when in operation; a data input terminal receiving an invalid signal when in operation; and an output terminal issuing an intermediate output signal when in operation, wherein the first flip-flop switches the intermediate output signal to an effective state in response to a first edge of the clock signal when in operation; the second flip-flop includes: a clock input terminal receiving the clock signal when in operation; a data input terminal connected to the output terminal of the first flip-flop; and an output terminal issuing a generated indication of whether a threshold time period has passed since the activation of the second circuit device when in operation, wherein the second flip-flop switches the generated indication to an effective state in response to a second edge of the clock signal after the first edge when in operation. In one embodiment, an integrated circuit includes an isolation circuit device coupled between a first circuit device and a second circuit device, wherein the isolation circuit device, when operating, selectively causes: a regeneration reset signal to be transmitted from the first circuit device to the second circuit device; and a generated indication of whether a threshold time period has passed to be transmitted from the second circuit device to the first circuit device in response to an isolation signal generated by the first circuit device.In one embodiment, an isolation circuit device includes: a first logic gate having: an input terminal coupled to the first circuit device, which receives a regeneration reset signal from the first circuit device when in operation; an output terminal coupled to a reset input terminal of a second circuit device; and a control input terminal, which receives an isolation control signal when in operation; a second logic gate having: an input terminal coupled to the second circuit device, which receives an indication generated from the second circuit device as to whether a threshold time period has passed when in operation; an output terminal coupled to the first circuit device; and a control input terminal, which receives an isolation control signal when in operation, wherein the first circuit device generates the isolation control signal when in operation.

[0125] In one embodiment, a method includes: generating an activation signal by using a first circuit device of an integrated circuit in response to a reset signal; generating a regeneration reset signal using the first circuit device; activating a second circuit device of the integrated circuit in response to the activation signal; resetting the second circuit device in response to the regeneration reset signal; generating an indication by the second circuit device whether a threshold time period has passed since the activation of the second circuit device; disabling the regeneration reset signal by the first circuit device in response to the generated indication that the threshold time period has passed. In one embodiment, the method includes: electrically coupling the first circuit device and the second circuit device after generating the activation signal and before generating the regeneration reset signal. In one embodiment, electrically coupling the first circuit device and the second circuit device includes controlling an isolation circuit device coupled between the first circuit device and the second circuit device. In one embodiment, the first circuit device receives the reset signal. In one embodiment, the first circuit device generates the reset signal.

[0126] In one embodiment, a system includes: a main circuit that generates a reset signal when in operation; and an integrated circuit coupled to the main circuit, the integrated circuit including an activation circuit device and a functional circuit device coupled to the activation circuit device, wherein the integrated circuit when in operation: responds to a reset signal received from the main circuit by generating the activation signal using the activation circuit device; generates a regeneration reset signal using the activation circuit device; activates the functional circuit device of the integrated circuit in response to the activation signal; resets the functional circuit device of the integrated circuit in response to the regeneration reset signal; generates an indication of whether a threshold time period has passed since the activation of the functional circuit device using the functional circuit device; and interrupts the regeneration reset signal in response to the generated indication that the threshold time period has passed. In one embodiment, the activation circuit device includes a flip-flop, the flip-flop including: a clock input terminal that receives the reset signal when in operation; a data input terminal that receives a valid signal when in operation; and an erase input terminal that receives the generated indication of whether the threshold time period has passed when in operation, wherein the flip-flop when in operation: switches to a storage operation state and issues a valid state signal at an output of the flip-flop in response to receiving an edge of the reset signal; and switches to an erase operation state and issues an invalid state signal at an output of the flip-flop in response to the generated indication that the threshold time period has passed. In one embodiment, the activation circuit device includes a logic gate having: a first input terminal coupled to an output terminal of a flip-flop; a second input terminal receiving a reset signal when in operation; and an output terminal emitting a regenerative reset signal when in operation, wherein the regenerative reset signal is active when the state signal is active or when the reset signal is active. In one embodiment, the functional circuit device includes: a clock, which generates a clock signal when in operation when the functional circuit device is active; a first flip-flop having: a clock input terminal receiving the clock signal when in operation; a data input terminal receiving an invalid signal when in operation; and an output terminal emitting an intermediate output signal when in operation, wherein the first flip-flop switches the intermediate output signal to an active state in response to a first edge of the clock signal when in operation; a second flip-flop having: a clock input terminal receiving the clock signal when in operation; a data input terminal connected to the output terminal of the first flip-flop; and an output terminal emitting a generated indication of whether a threshold time period has passed since the functional circuit device was activated when in operation, wherein the second flip-flop switches the generated indication to an active state in response to a second edge of the clock signal after the first edge when in operation. In one embodiment, an integrated circuit includes an isolation circuit device coupled between an activation circuit device and a functional circuit device, wherein the isolation circuit device, when operated, selectively allows the following to pass in response to an isolation signal generated by the first circuit device: a regenerated reset signal from the activation circuit device to the functional circuit device; and an indication generated from the functional circuit device to the activation circuit device as to whether a threshold time period has passed.In one embodiment, the isolation circuit device comprises: a first logic gate and a second logic gate; the first logic gate has: an input terminal coupled to the activation circuit device, which receives the regeneration reset signal from the first circuit device when in operation; an output terminal coupled to the reset input terminal of the functional circuit device; and a control input terminal, which receives the isolation control signal when in operation; and the second logic gate has: an input terminal coupled to the functional circuit device, which receives the indication generated from the functional circuit device when in operation whether the threshold time period has passed; an output terminal coupled to the activation circuit device; and a control input terminal, which receives the isolation control signal when in operation, wherein the activation circuit device generates the isolation control signal when in operation. In one embodiment, the main circuit comprises a switch.

[0127] In one embodiment, the contents of a non-transitory computer readable medium configure an integrated circuit to perform a method comprising: responding to a reset signal by generating an activation signal; generating a regeneration reset signal; activating a functional circuit device of the integrated circuit in response to the activation signal; resetting the functional circuit device in response to the regeneration reset signal; generating an indication as to whether a threshold time period has passed since activation of the functional circuit device; disabling the regeneration reset signal in response to the generated indication that the threshold time period has passed. In one embodiment, the method comprises: electrically coupling the activation circuit device and the functional circuit device of the integrated circuit after generating the activation signal and before generating the regeneration reset signal. In one embodiment, the contents comprise instructions executed by processing circuit devices of the integrated circuit.

[0128] The various embodiments described above can be combined to provide further embodiments.Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

[0129] In light of the above detailed description, these and other changes can be made to the embodiments. Generally speaking, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents granted by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated circuit, comprising: a first circuit arrangement; as well as a second circuit arrangement; as well as an isolation circuit device coupled between the first circuit device and the second circuit device, wherein The first circuit arrangement, when in operation, responds to a reset signal by: generating an activation signal; and generating a regeneration reset signal; and When the second circuit arrangement is in operation: activating in response to the activation signal; resetting in response to the regeneration reset signal; as well as generating an indication as to whether a threshold time period has elapsed since activation of the second circuit arrangement, wherein the first circuit arrangement is operative to disable the regeneration reset signal in response to the generated indication that the threshold time period has elapsed; and wherein the isolation circuit device, in response to an isolation signal generated by the first circuit device, selectively: transferring the regeneration reset signal from the first circuit device to the second circuit device; as well as The generated indication of whether a threshold time period has elapsed is communicated from the second circuit arrangement to the first circuit arrangement.

2. The integrated circuit of claim 1 , wherein the isolation circuit device comprises: The first logic gate has: an input terminal coupled to the first circuit device and operable to receive the regeneration reset signal from the first circuit device; an output terminal coupled to a reset input terminal of the second circuit device; and a control input terminal, which receives the isolated signal when in operation; as well as The second logic gate has: an input coupled to the second circuit device and operable to receive from the second circuit device a generated indication of whether a threshold time period has elapsed; an output terminal coupled to the first circuit device; as well as A control input is operable to receive the isolated signal, wherein the first circuit arrangement is operable to generate the isolated signal.

3. An integrated circuit comprising: a first circuit arrangement; as well as A second circuit device is coupled to the first circuit device, wherein The first circuit arrangement, when in operation, responds to a reset signal by: generating an activation signal; as well as generating a regeneration reset signal; and When the second circuit arrangement is in operation: activating in response to the activation signal; resetting in response to the regeneration reset signal; as well as generating an indication of whether a threshold time period has elapsed since activation of the second circuit arrangement, wherein the first circuit arrangement is operative to disable the regeneration reset signal in response to the generated indication that the threshold time period has elapsed, wherein: The first circuit device comprises a trigger, wherein the trigger comprises: a clock input terminal, which receives the reset signal during operation; a data input terminal which receives a valid signal when in operation; and an erase input that, when operative, receives the generated indication of whether the threshold time period has elapsed, wherein the trigger, when operative: In response to receiving an edge of the reset signal, switching to a storage operation state and issuing a valid state signal at an output of the flip-flop; and Responsive to the generated indication that the threshold time period has elapsed, switching to an erase operation state and asserting an invalid state signal at the output of the flip-flop.

4. The integrated circuit of claim 3, wherein: The first circuit arrangement comprises a logic gate having: A first input terminal coupled to the output terminal of the trigger; a second input terminal, which receives the reset signal during operation; as well as An output terminal sends out the regeneration reset signal when in operation, wherein the regeneration reset signal is valid when the state signal is valid or when the reset signal is valid.

5. The integrated circuit of claim 3 , comprising an isolation circuit device coupled between the first circuit device and the second circuit device, wherein the isolation circuit device, in operation, in response to an isolation signal generated by the first circuit device, selectively: transferring the regeneration reset signal from the first circuit device to the second circuit device; and The generated indication of whether a threshold time period has elapsed is communicated from the second circuit arrangement to the first circuit arrangement.

6. The integrated circuit of claim 5, wherein the isolation circuit device comprises: The first logic gate has: an input terminal coupled to the first circuit device and operable to receive the regeneration reset signal from the first circuit device; an output terminal coupled to a reset input terminal of the second circuit device; as well as a control input terminal, which receives the isolated signal when in operation; as well as The second logic gate has: an input coupled to the second circuit device and operable to receive from the second circuit device a generated indication of whether a threshold time period has elapsed; an output terminal coupled to the first circuit device; as well as A control input is operable to receive the isolated signal, wherein the first circuit arrangement is operable to generate the isolated signal.

7. An integrated circuit comprising: a first circuit arrangement; as well as A second circuit device is coupled to the first circuit device, wherein The first circuit arrangement, when in operation, responds to a reset signal by: generating an activation signal; as well as generating a regeneration reset signal; and When the second circuit arrangement is in operation: activating in response to the activation signal; resetting in response to the regeneration reset signal; as well as generating an indication as to whether a threshold time period has elapsed since activation of the second circuit arrangement, wherein the first circuit arrangement is operative to disable the regeneration reset signal in response to the generated indication that the threshold time period has elapsed, wherein the second circuit arrangement comprises: a clock that, when operative, generates a clock signal when the second circuit device is active; The first trigger includes: a clock input terminal, which receives the clock signal during operation; a data input terminal which receives an invalid signal when in operation; and an output terminal that emits an intermediate output signal when in operation, wherein the first flip-flop when in operation switches the intermediate output signal to an active state in response to a first edge of the clock signal; and The second trigger includes: a clock input terminal, which receives the clock signal during operation; a data input terminal connected to the output terminal of the first flip-flop; and An output terminal, which when operated issues a generated indication of whether a threshold time period has passed since the second circuit device was activated, wherein the second flip-flop when operated switches the generated indication to an active state in response to a second edge of the clock signal after the first edge.

8. The integrated circuit of claim 7, comprising an isolation circuit device coupled between the first circuit device and the second circuit device, wherein the isolation circuit device, in operation, in response to an isolation signal generated by the first circuit device, selectively: transferring the regeneration reset signal from the first circuit device to the second circuit device; and The generated indication of whether a threshold time period has elapsed is communicated from the second circuit arrangement to the first circuit arrangement.

9. The integrated circuit of claim 8, wherein the isolation circuit device comprises: The first logic gate has: an input terminal coupled to the first circuit device and operable to receive the regeneration reset signal from the first circuit device; an output terminal coupled to a reset input terminal of the second circuit device; as well as a control input terminal which, when in operation, receives an isolated control signal; as well as The second logic gate has: an input coupled to the second circuit device and operable to receive from the second circuit device a generated indication of whether a threshold time period has elapsed; an output terminal coupled to the first circuit device; as well as A control input is operable to receive the isolated control signal, wherein the first circuit device is operable to generate the isolated control signal.

10. A method for resetting, comprising: generating an activation signal in response to the reset signal by using a first circuit device of the integrated circuit; generating a regenerative reset signal using the first circuit arrangement; activating a second circuit device of the integrated circuit in response to the activation signal; resetting the second circuit device in response to the regeneration reset signal; generating, by the second circuit arrangement, an indication as to whether a threshold time period has elapsed since activation of the second circuit arrangement; as well as disabling, by the first circuit arrangement, the regeneration reset signal in response to the generated indication that the threshold time period has elapsed, wherein: The method includes: after generating the activation signal and before generating the regeneration reset signal, electrically coupling the first circuit device and the second circuit device, Electrically coupling the first circuit device and the second circuit device includes: controlling an isolation circuit device coupled between the first circuit device and the second circuit device to selectively: transferring the regeneration reset signal from the first circuit device to the second circuit device; and The generated indication of whether a threshold time period has elapsed is communicated from the second circuit arrangement to the first circuit arrangement. The method of claim 10 , wherein the first circuit device receives the reset signal.

12. A system for resetting, comprising: a main circuit which generates a reset signal when in operation; as well as an integrated circuit coupled to the main circuit, the integrated circuit comprising an activation circuit device and a functional circuit device coupled to the activation circuit device, wherein the integrated circuit, when in operation: generating an activation signal by using the activation circuit arrangement in response to a reset signal received from the main circuit; generating a regeneration reset signal using the activation circuit device; activating the functional circuit device of the integrated circuit in response to the activation signal; resetting the functional circuit device of the integrated circuit in response to the regeneration reset signal; using the functional circuitry, generating an indication as to whether a threshold time period has elapsed since activation of the functional circuitry; as well as In response to the generated indication that the threshold time period has elapsed, interrupting the regeneration reset signal, wherein: The integrated circuit includes isolation circuitry coupled between the activation circuitry and the functional circuitry; and The isolation circuit device, in response to the isolation signal generated by the activation circuit device, is operable to selectively: transmitting the regeneration reset signal from the activation circuit device to the functional circuit device; as well as The generated indication of whether a threshold time period has elapsed is communicated from the functional circuitry to the activation circuitry.

13. The system of claim 12, wherein the activation circuit device comprises a trigger, the trigger comprising: a clock input terminal, which receives the reset signal during operation; A data input terminal, which receives a valid signal during operation; as well as an erase input that, when operative, receives the generated indication of whether the threshold time period has elapsed, wherein the trigger, when operative: In response to receiving an edge of the reset signal, switching to a storage operation state and issuing a valid state signal at an output of the flip-flop; as well as Responsive to the generated indication that the threshold time period has elapsed, switching to an erase operation state and asserting an invalid state signal at the output of the flip-flop.

14. The system of claim 13, wherein the activation circuit device comprises a logic gate having: A first input terminal coupled to the output terminal of the trigger; a second input terminal, which receives the reset signal during operation; as well as An output terminal sends out the regeneration reset signal when in operation, wherein the regeneration reset signal is valid when the state signal is valid or when the reset signal is valid.

15. The system of claim 12, wherein the functional circuit device comprises: a clock which, when in operation, generates a clock signal when the functional circuit device is active; The first trigger has: a clock input terminal, which receives the clock signal during operation; a data input terminal which receives an invalid signal during operation; as well as an output terminal that, when in operation, issues an intermediate output signal, wherein the first flip-flop, when in operation, switches the intermediate output signal to an active state in response to a first edge of the clock signal; The second trigger has: a clock input terminal, which receives the clock signal during operation; a data input terminal connected to the output terminal of the first trigger; as well as An output terminal, which when operated issues a generated indication of whether a threshold time period has passed since the functional circuit device was activated, wherein the second flip-flop when operated switches the generated indication to an active state in response to a second edge of the clock signal after the first edge.

16. The system of claim 12, wherein the isolation circuit device comprises: The first logic gate has: an input terminal coupled to the activation circuit device and operable to receive the regeneration reset signal from the activation circuit device; an output terminal coupled to a reset input terminal of the functional circuit device; and a control input terminal which, when in operation, receives an isolated control signal; as well as The second logic gate has: an input coupled to the functional circuitry and operable to receive from the functional circuitry a generated indication of whether a threshold time period has elapsed; an output terminal coupled to the activation circuit device; as well as A control input is operable to receive the isolation control signal, wherein the activation circuit arrangement is operable to generate the isolation control signal.

17. The system of claim 12, wherein the main circuit comprises a switch.

18. A non-transitory computer readable medium having content that configures an integrated circuit to perform a method comprising: generating an activation signal in response to a reset signal by using a first circuit device of the integrated circuit; generating a regenerative reset signal using the first circuit arrangement; activating a functional circuit device of the integrated circuit in response to the activation signal; resetting the functional circuit device in response to the regeneration reset signal; generating an indication of whether a threshold time period has elapsed since activation of the functional circuitry; In response to the generated indication that the threshold time period has elapsed, disabling the regeneration reset signal, wherein The method includes: after generating the activation signal and before generating the regeneration reset signal, electrically coupling the first circuit device and the functional circuit device, Electrically coupling the first circuit device and the functional circuit device includes: controlling an isolation circuit device coupled between the first circuit device and the functional circuit device to selectively: passing the regeneration reset signal from the first circuit device to the functional circuit device; and The generated indication of whether a threshold time period has elapsed is communicated from the functional circuitry to the first circuitry.

19. The non-transitory computer-readable medium of claim 18, wherein the content comprises instructions executed by processing circuitry of the integrated circuit.

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