Method for updating boot program and data processing device

Abstract

The embodiment of the present disclosure provides a method for updating a boot program and a data processing device, wherein the method includes: in response to the SPI of the first device, the second device, the first memory, and the second memory being connected to the CPLD, the data processing device is powered on and started. The first memory stores the boot program of the first device, and the second memory stores the boot program of the second device; in response to the boot program stored in the first memory being abnormal, causing the first device to hang while the second device is successfully started, a corresponding relationship between the second device and the first memory is established according to the first update mapping information in the CPLD; the second device updates the new boot program to the first memory. The technical solution of the embodiment of the present disclosure avoids the time-consuming and labor-intensive problem of removing the memory with the abnormal boot program after power off and re-burning in the existing technical solution, saving time and labor costs.

Description

Technical Field

[0001] The technical solution disclosed herein relates to the field of Internet technology, and in particular to a method for updating a boot program and a data processing device. Background Art

[0002] In the internet age, data transmission and reception, traffic exchange, and data processing are essential. Data processing equipment plays a crucial role in these processes. With the increasing demand for information exchange and the rapid development of the internet, the speed and volume of data traffic exchange are increasing rapidly. A single CPU (Central Processing Unit) system's data processing equipment is increasingly struggling to handle this large volume and high rate of traffic. This has led to the emergence of multi-CPU system data processing equipment.

[0003] In existing multi-CPU system designs, the memory equipped with the bootloader is directly connected to the SPI (Serial Peripheral Interface) of the corresponding CPU. Under this structure, each CPU can only read and write the corresponding memory. When one of the CPUs in the multi-CPU system becomes stuck due to an abnormal bootloader, the other CPUs in the multi-CPU system cannot process the abnormal bootloader and can only remove the abnormal memory after powering off and re-program it. This is not only time-consuming and labor-intensive, but also requires the presence of corresponding programming equipment and operators on site, increasing the cost. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a method for updating a boot program and a data processing device.

[0005] Specifically, the embodiments of the present disclosure are implemented through the following technical solutions:

[0006] According to a first aspect of the present disclosure, a method for updating a boot program is provided, the method comprising:

[0007] In response to the SPIs of the first device, the second device, the first memory, and the second memory being connected to the CPLD, the data processing device is powered on and started, wherein the first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program for the first device, and the second memory stores a boot program for the second device;

[0008] In response to a boot program stored in the first memory being abnormal, causing the corresponding first device to hang while the second device is successfully started, establishing a correspondence between the second device and the first memory according to first updated mapping information in the CPLD;

[0009] The second device updates the new boot program into the first memory.

[0010] According to a second aspect of the present disclosure, a data processing device is provided, comprising:

[0011] A plurality of devices containing SPI, a CPLD, and a plurality of memories containing SPI, wherein the plurality of devices containing SPI include a first device and a second device, the plurality of memories containing SPI include a first memory and a second memory, and the SPIs of the first device, the second device, the first memory, and the second memory are all connected to the CPLD, wherein the first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program for the first device, and the second device stores a boot program for the second device;

[0012] The CPLD is configured to, in response to a boot program stored in the first memory being abnormal, causing the corresponding first device to be hung while the second device is successfully started, establish a correspondence between the second device and the first memory according to the first updated mapping information in the CPLD;

[0013] The second device is used to update the new boot program into the first memory.

[0014] The method and data processing device for updating the boot program provided by the embodiments of the present disclosure enable, when one of the devices in a system composed of multiple devices becomes hung due to an abnormal boot program stored in its corresponding memory, while the other devices start normally, a correspondence between the normally started device and the memory with the abnormal boot program is established through the CPLD (Complex Programmable Logic Device), and a new boot program is written to the memory with the abnormal boot program using the normally started device, thereby improving the flexibility and compatibility of the system composed of the multiple devices, avoiding the time-consuming and labor-intensive problem of removing the memory with the abnormal boot program after power off and re-burning in the existing technical solution, and saving time and labor costs.

[0015] The embodiments of the present disclosure are further described in detail below through the accompanying drawings and implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in one or more embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings described below are only some embodiments described in one or more embodiments of the present disclosure. Those skilled in the art can also derive other drawings based on these drawings without inventive work.

[0017] Figure 1 is a flowchart of a method for updating a boot program according to an exemplary embodiment of the present disclosure;

[0018] Figure 2 is a flowchart of another method for updating a boot program provided according to an exemplary embodiment of the present disclosure;

[0019] Figure 3 It is a structural diagram of a data processing device provided according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0021] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0022] The terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0024] The method of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0025] Figure 1 A flowchart of a method for updating a boot program provided by an exemplary embodiment of the present disclosure is provided. The method is used for a data processing device, wherein the data processing device includes multiple devices containing SPI, a CPLD, and multiple memories containing SPI, wherein the multiple devices containing SPI include a first device and a second device, and the multiple memories containing SPI include a first memory and a second memory, such as Figure 1 As shown, the exemplary embodiment method may include the following processing:

[0026] Step S101 : in response to the SPIs of the first device, the second device, the first memory, and the second memory being connected to the CPLD, the data processing device is powered on and started.

[0027] The first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program of the first device, and the second memory stores a boot program of the second device.

[0028] In order to make the description of the method in this embodiment clearer, the basic concepts of the SPI, CPLD and boot program are first further introduced in detail.

[0029] SPI, short for Serial Peripheral Interface (SPI), is a high-speed, synchronous communication bus that occupies only four pins on a chip, saving chip pins, layout space, and ease of use. In this embodiment, since multiple devices and memories require booting and updating programs, the SPI interface is used as the communication interface for these devices and memories.

[0030] CPLD is the abbreviation of Complex Programmable Logic Device in English, which means complex programmable logic device in Chinese. It is a high-density, high-speed and low-power complex programmable logic device constructed by programming technologies such as CMOS EPROM, EEPROM, flash memory and SRAM.

[0031] A bootloader is a utility program. It's a short program that the system automatically enters after a computer starts up to complete the boot process. After a computer starts up, the device inputs a small amount of instructions and data, which are then used to enter other programs.

[0032] In an optional example, the plurality of devices containing SPI are a plurality of devices containing SPI of the same model.

[0033] For example, the multiple devices with the same model and containing SPI may be multiple CPUs. For another example, the multiple devices with the same model and containing SPI may be multiple BMCs (Baseboard Manager Controllers).

[0034] Since the multiple devices containing SPI have the same model, the boot programs corresponding to the multiple devices containing SPI are also the same.

[0035] In the data processing device, the first device must read the boot program stored in the first memory corresponding to the first device, and the second device must read the boot program stored in the second memory corresponding to the second device before it can successfully start. In this example, because the first device and the second device are of the same model, the boot programs stored in the first and second memories are also the same. In other words, the first device can successfully start by reading the boot program stored in the second memory, and the second device can also successfully start by reading the boot program stored in the first memory.

[0036] Step S102 , in response to the boot program stored in the first memory being abnormal, causing the corresponding first device to hang while the second device is successfully started, establishing a corresponding relationship between the second device and the first memory according to the first updated mapping information in the CPLD.

[0037] Because the boot program stored in the first memory is abnormal, the corresponding first device cannot read the boot program stored in the first memory, resulting in a startup failure of the first device, which is the so-called "hanging" situation. However, the boot program stored in the second memory is normal, so the second device successfully starts.

[0038] In an optional example, a corresponding relationship between the second device and the first memory may be established based on register data written into the CPLD.

[0039] The data written into the register is 8-bit binary data. Generally, the first four bits of the 8-bit binary data written into the register can be referred to as the upper four bits, and the last four bits can be referred to as the lower four bits. In this example, the upper four bits can correspond to the multiple SPI-containing devices of the same model, and the lower four bits can correspond to the multiple SPI-containing memories. Furthermore, different meanings represented by the upper four bits and lower four bits can be pre-set, and then by inputting different upper four bits and lower four bits of information into the register, i.e., the register data, a correspondence between the second device and the first memory can be established.

[0040] For example, it can be preset that when the upper four bits of the written register data are 0001b, it corresponds to the first device, and when the upper four bits are 0010b, it corresponds to the second device. It can also be preset that when the lower four bits of the written register data are 0001b, it corresponds to the first memory, and when the lower four bits are 0010b, it corresponds to the second memory.

[0041] The “b” is used to indicate that the input register data is binary data.

[0042] When the data processing device is powered on and started, the register data is the default value 00010001b. The first device corresponds to the first memory, and the second device corresponds to the second memory. At this point, the CPLD only serves as a basic logical connection. The first memory can be considered directly connected to the SPI interface of the corresponding first device, and the second memory can be considered directly connected to the SPI interface of the corresponding second device. After the first device reads the boot program from the first memory corresponding to the first device, and the second device reads the boot program from the second memory corresponding to the second device, both the first device and the second device can successfully start.

[0043] If, after the data processing device is powered on and starts up, the first device fails to start up, but the second device successfully starts up, this indicates that there is an error in the boot program stored in the first memory corresponding to the first device. In this case, register data in the form of 00100001b can be written, where 0010b corresponds to the second device and 0001b corresponds to the first memory. After the CPLD receives the written register data, it can establish a correspondence between the second device and the first memory.

[0044] Among them, the provisions that the upper four bits of the register data input into the CPLD correspond to the multiple devices with the same model containing SPI, and the lower four bits correspond to the multiple memories containing SPI, and when the register data input into the CPLD is 00100001b, the provisions for establishing the correspondence between the second device and the first memory are merely schematic. In specific implementation, relevant technical personnel in this field can make specific settings according to specific circumstances.

[0045] In an optional example, a corresponding relationship between the second device and the first memory may be established according to a level input to the CPLD.

[0046] The corresponding relationships between different devices and different memories corresponding to several levels input to the CPLD in different level forms can be preset.

[0047] For example, the number of levels input to the CPLD can be preset to 4, and when all four levels input to the CPLD are low, the first device corresponds to the first memory, and the second device corresponds to the second memory. When the first input level is high and the other three levels are low, the second device corresponds to the first memory. When the second input level is high and the other three levels are low, the first device corresponds to the second memory.

[0048] When the data processing device is powered on and started, the four levels of the CPLD are all defaulted to low levels, the first device corresponds to the first memory, the second device corresponds to the second memory, the first device reads the boot program from the first memory corresponding to the first device, and the second device reads the boot program from the second memory corresponding to the second device. Then, both the first device and the second device can be successfully started.

[0049] If, after the data processing device is powered on and starts up, the first device fails to start up, but the second device successfully starts up, this indicates that there is an abnormality in the boot program stored in the first memory corresponding to the first device. In this case, four levels can be input to the CPLD, and except for the first input level being a high level, the other three levels are all low levels, so that the second device corresponds to the first memory.

[0050] If, after the data processing device is powered on and booted, the second device fails to boot, but the first device successfully boots, this indicates that there is an abnormality in the boot program stored in the second memory corresponding to the second device. In this case, four levels can be input to the CPLD, and except for the second level being high, the other three levels are all low, so that the first device corresponds to the second memory.

[0051] In this example, the relationship between the number of levels input to the CPLD and the different devices and memories corresponding to different level forms is merely illustrative. In actual applications, the number of levels input to the CPLD may be 5, 8, or the like. Furthermore, when the first input level is high and the other input levels are low, it may indicate that an abnormality has occurred in the boot program stored in the second memory. In specific implementations, those skilled in the art may make specific settings based on specific circumstances.

[0052] The register data written into the CPLD and the level input into the CPLD are the first update mapping information.

[0053] Step S103: the second device updates the new boot program into the first memory.

[0054] The method for updating the boot program of this embodiment enables, when one of multiple devices hangs due to an abnormal boot program stored in its corresponding memory, while the other devices successfully start up, a correspondence between the normally started device and the memory with the abnormal boot program is established through the CPLD, and a new boot program is written to the memory with the abnormal boot program using the successfully started device. Furthermore, the CPLD is a device already existing in existing data processing equipment, and no new device is introduced in this embodiment. Therefore, the flexibility and compatibility of the data processing equipment can be improved without changing the BOM (Bill of Materials) cost, avoiding the time-consuming and labor-intensive problem of removing the memory with the abnormal boot program after powering off and re-burning in the existing technical solution, thereby saving time and labor costs.

[0055] Figure 2 This is a flowchart of another method for updating a boot program provided by an exemplary embodiment of the present disclosure. The method is used for a data processing device, and the data processing device includes a plurality of devices containing SPI, a plurality of management ports corresponding to the plurality of devices containing SPI, a CPLD, and a plurality of memories containing SPI. Among them, the plurality of management ports corresponding to the plurality of devices containing SPI include a first management port and a second management port, the plurality of devices containing SPI include a first device and a second device, and the plurality of memories containing SPI include a first memory and a second memory. Among them, in the description of this embodiment, the same steps as in any of the aforementioned embodiments will be briefly described and will not be described in detail. For details, please refer to any of the aforementioned embodiments. Figure 2 As shown, the method of this embodiment may include the following processing:

[0056] Step S201 : In response to the SPIs of the first device, the second device, the first memory, and the second memory being connected to the CPLD, the data processing device is powered on and started.

[0057] The first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program of the first device, and the second memory stores a boot program of the second device.

[0058] In an optional example, the CPLD may include 4 or 5 logic blocks, and each logic block may establish an independent electrical level.

[0059] For example, the CPLD includes five logic blocks, wherein the voltage levels of the five logic blocks are the same, that is, 1.8V.

[0060] The SPI of the first device is at the same voltage level as the SPI of the first memory corresponding to the first device, and the SPI of the second device is at the same voltage level as the SPI of the second memory corresponding to the second device. Since the first device and the second device are of the same model, the SPI of the first device and the SPI of the second device are at the same voltage level, for example, both are 1.8V as described above. Therefore, the first device and the first memory corresponding to the first device, and the second device and the second memory corresponding to the second device can be directly connected to any logic block of the CPLD.

[0061] Step S202 , in response to the boot program stored in the first memory being abnormal, causing the corresponding first device to hang while the second device is successfully started, establishing a corresponding relationship between the second device and the first memory according to the first updated mapping information in the CPLD.

[0062] Step S203: The second device receives the new boot program from the management port corresponding to the second device and stores the new boot program in the memory of the second device.

[0063] In this embodiment, the first device has a first management port corresponding thereto, and the second device has a second management port corresponding thereto. The boot program corresponding to the first device can be transmitted to the first device through the first management port, and the boot program corresponding to the second device can be transmitted to the second device through the second management port. Since the first device and the second device in this embodiment have the same model, the boot programs corresponding to them are also the same. Therefore, when the second device that has been successfully started needs to update the new boot program for the first memory whose boot program is damaged, the new boot program is directly received from the second management port corresponding to the second device and saved in the memory of the second device, preparing for the next step of updating the new boot program to the first memory whose boot program is damaged.

[0064] Step S204: the second device updates the new boot program in the memory to the first memory.

[0065] Step S205 , in response to the second device updating the new boot program into the first memory, establishing a correspondence between the first device and the first memory, and a correspondence between the second device and the second memory according to the second updated mapping information in the CPLD.

[0066] In an optional example, when the second device updates the new boot program to the first memory, that is, writes register data in the form of 00010001b, when the CPLD receives the register data, it establishes a correspondence between the first device and the first memory, and a correspondence between the second device and the second memory.

[0067] In an optional example, when the second device updates the new boot program to the first memory, it inputs 4 levels, and the 4 levels are all low levels. When the CPLD receives the 4 levels, it establishes a correspondence between the first device and the first memory, and a correspondence between the second device and the second memory.

[0068] The register data written into the CPLD and the level input into the CPLD are the second update mapping information.

[0069] Step S206 : The first device is restarted, and a boot program stored in a first memory corresponding to the first device is loaded.

[0070] The method for updating the boot program of this embodiment is to directly receive the new boot program transmitted from the second management port corresponding to the second device through the successfully started second device, and update the received new boot program to the first memory in which the boot program is damaged. This avoids the time-consuming and labor-intensive problem of removing the first memory with the abnormal boot program after power off and re-burning in the existing technical solution, thereby saving time and labor costs.

[0071] Corresponding to the aforementioned embodiment of the method for updating a boot program, the present disclosure also provides an embodiment of a data processing device.

[0072] Figure 3 is a structural diagram of a data processing device in an exemplary embodiment of the present disclosure, such as Figure 3 As shown, the data processing device includes:

[0073] A plurality of devices containing SPI, a CPLD 31, and a plurality of memories containing SPI, wherein the plurality of devices containing SPI include a first device 32 and a second device 33, the plurality of memories containing SPI include a first memory 34 and a second memory 35, and the SPIs of the first device 32, the second device 33, the first memory 34, and the second memory 35 are all connected to the CPLD, wherein the first device 32 corresponds to the first memory 34, the second device 33 corresponds to the second memory 35, and the first memory 34 stores a boot program of the first device 32, and the second memory 35 stores a boot program of the second device 33;

[0074] The CPLD 31 is configured to establish a correspondence between the second device 33 and the first memory 34 according to the first updated mapping information in the CPLD 31 in response to a boot program abnormality stored in the first memory 34, which causes the corresponding first device 32 to be hung but the second device 33 to be successfully started;

[0075] The second device 33 is used to update the new boot program into the first memory 34 .

[0076] Optionally, the device further includes: a plurality of management ports corresponding to the plurality of devices including SPIs; the second device 33, when used to update the new boot program to the first memory 34, includes:

[0077] The second device 33 receives the new boot program from the management port corresponding to the second device 33 and stores the new boot program in the memory of the second device 33;

[0078] The second device 33 updates the new boot program in the memory to the first memory 34 .

[0079] Optionally, when the CPLD 31 is used to establish a corresponding relationship between the second device 33 and the first memory 34 according to the first updated mapping information in the CPLD 31, the method includes:

[0080] Receiving register data written into the CPLD 31 or receiving a level input into the CPLD 31;

[0081] A corresponding relationship between the second device 33 and the first memory 34 is established according to the register data or the level.

[0082] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely illustrative. Some or all of the devices can be selected according to actual needs to achieve the purpose of the technical solution of the present disclosure. Those of ordinary skill in the art can understand and implement them without expending any creative work.

[0083] Although this specification includes many specific implementation details, these should not be interpreted as limiting the scope of any invention or the scope of protection claimed, but are mainly used to describe the features of specific embodiments of specific inventions. Certain features described in multiple embodiments within this specification may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may work in certain combinations as described above and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may point to a sub-combination or a variation of the sub-combination.

[0084] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for updating a boot program, characterized in that: The method is used for a data processing device, which includes a plurality of devices including serial peripheral interfaces (SPIs), a complex programmable logic device (CPLD), and a plurality of memories including SPIs, wherein the plurality of devices including SPIs include a first device and a second device of the same model, and the plurality of memories including SPIs include a first memory and a second memory. The method includes: In response to the SPIs of the first device, the second device, the first memory, and the second memory being connected to the CPLD, the data processing device is powered on and started, wherein the first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program for the first device, and the second memory stores a boot program for the second device; In response to a boot program stored in the first memory being abnormal, causing the corresponding first device to hang while the second device is successfully started, establishing a correspondence between the second device and the first memory according to first updated mapping information in the CPLD; The second device updates the new boot program into the first memory.

2. The method according to claim 1, characterized in that The first device and the second device are a central processing unit (CPU) or a baseboard management controller (BMC).

3. The method according to claim 1, characterized in that The data processing device further includes: a plurality of management ports corresponding to the plurality of devices including SPIs, wherein the second device updates the new boot program into the first memory, including: The second device receives the new boot program from the management port corresponding to the second device and stores the new boot program in the memory of the second device; The second device updates the new boot program in the memory to the first memory.

4. The method according to claim 1, wherein The establishing a corresponding relationship between the second device and the first memory according to the first updated mapping information in the CPLD includes: receiving register data written into the CPLD or receiving a level input into the CPLD; A corresponding relationship between the second device and the first memory is established according to the register data or the level.

5. The method according to claim 1, wherein After the second device updates the new boot program into the first memory, the method further includes: Establishing a corresponding relationship between the first device and the first memory, and a corresponding relationship between the second device and the second memory according to the second updated mapping information in the CPLD; The first device is restarted and the new boot program stored in the first memory corresponding to the first device is loaded.

6. The method according to claim 5, characterized in that The establishing, according to the second updated mapping information in the CPLD, a correspondence between the first device and the first memory, and a correspondence between the second device and the second memory, includes: receiving register data written into the CPLD or receiving a level input into the CPLD; A corresponding relationship between the first device and the first memory, and a corresponding relationship between the second device and the second memory are established according to the register data or the level.

7. A data processing device, characterized in that: The device comprises: A plurality of devices containing SPI, a CPLD, and a plurality of memories containing SPI, wherein the plurality of devices containing SPI include a first device and a second device of the same model, the plurality of memories containing SPI include a first memory and a second memory, and the SPIs of the first device, the second device, the first memory, and the second memory are all connected to the CPLD, wherein the first device corresponds to the first memory, the second device corresponds to the second memory, the first memory stores a boot program for the first device, and the second device stores a boot program for the second device; The CPLD is configured to, in response to an abnormality in the boot program stored in the first memory, cause the corresponding first device to become hung while the second device is successfully started, establish a correspondence between the second device and the first memory according to the first updated mapping information in the CPLD; The second device is used to update the new boot program into the first memory.

8. The device according to claim 7, characterized in that The device further includes: a plurality of management ports corresponding to the plurality of devices including SPIs; the second device, when used to update the new boot program into the first memory, includes: The second device receives the new boot program from the management port corresponding to the second device and stores the new boot program in the memory of the second device; The second device updates the new boot program in the memory to the first memory.

9. The device according to claim 7, characterized in that The CPLD, when used to establish a corresponding relationship between the second device and the first memory according to the first updated mapping information in the CPLD, includes: receiving register data written into the CPLD or receiving a level input into the CPLD; A corresponding relationship between the second device and the first memory is established according to the register data or the level.

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