Logic synthesis method, device and storage medium

Abstract

Embodiments of the present invention disclose a logic synthesis method, device, and storage medium, belonging to the field of communications technology. The method includes: obtaining integrated input data of a target module based on module integrated configuration information in a target configuration file; sending the integrated input data of the target module and a startup command for a logic synthesis tool to a first target server; obtaining a netlist file and a first report file after executing the logic synthesis tool on the first target server to perform logic synthesis on the integrated input data of the target module; and, when it is determined that the first report file satisfies the integrated result tracking information in the target configuration file, sending the netlist file to a second target server and sending the netlist file and integrated input data to a third target server. This logic synthesis method improves the efficiency of logic synthesis.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of chip design in integrated circuits, and in particular to a logic synthesis method, device, and storage medium. Background Art

[0002] Integrated circuit technology is a key technology in modern information technology. With the rapid development of communications technology, performance requirements for integrated circuits are becoming increasingly stringent, and the logic scale of integrated circuits is increasing. However, design cycles are becoming increasingly shorter due to market competition. How to shorten the integrated circuit R&D cycle while ensuring success rates has become a major challenge for integrated circuit designers. The field of digital integrated circuit design is generally divided into digital front-end design and digital back-end design. Digital front-end design includes algorithms, hardware architecture design and analysis, register-transfer level (RTL) circuit code implementation, RTL circuit code review and functional verification, logic synthesis, static timing analysis, and formal verification.

[0003] Currently, logic synthesis, static timing analysis and formal verification are achieved through the following steps: obtain the RTL circuit code completed by the front end; manually start the logic synthesis tool, use the synthesis tool to implement logic synthesis, map the RTL circuit code to a netlist file related to the process library and obtain the relevant output report file; after confirming that the logic synthesis tool has been completed, manually start the static timing analysis tool, the static timing analysis tool performs static timing analysis through the netlist file, process library file and the written constraint file, and obtains the relevant timing analysis report; after confirming that the static timing analysis tool has been completed, manually start the formal verification tool, the formal verification tool verifies the correctness of the netlist file through the netlist file and the RTL circuit code, and obtains the formal verification report; manually confirm whether the netlist file, timing analysis related report and formal verification report and other related files generated by the RTL circuit code after logic synthesis, static timing analysis and formal verification meet the design conditions. If the design conditions are met, the above-mentioned related files will be delivered.

[0004] However, in the above process, the logic synthesis tool needs to be started manually, which consumes a lot of manpower to confirm whether the logic synthesis tool has been completed, resulting in low efficiency of logic synthesis. Summary of the Invention

[0005] The main purpose of the embodiments of the present invention is to provide a logic synthesis method, device and storage medium, aiming to achieve the function of improving the efficiency of logic synthesis.

[0006] To achieve the above object, an embodiment of the present invention provides a logic synthesis method, which includes the following steps:

[0007] Obtain comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file;

[0008] Sending the synthesis input data of the target module and a start command of a logic synthesis tool to the first target server;

[0009] Obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool to perform logic synthesis on the synthesis input data of the target module;

[0010] When it is determined that the first report file satisfies the synthesis result tracking information in the target configuration file, the netlist file is sent to a second target server, and the netlist file and the synthesis input data are sent to a third target server.

[0011] To achieve the above-mentioned purpose, an embodiment of the present invention further proposes a logic synthesis device, which includes a memory, a processor, a program stored on the memory and executable on the processor, and a data bus for realizing connection and communication between the processor and the memory. When the program is executed by the processor, the steps of the aforementioned method are implemented.

[0012] To achieve the above objectives, an embodiment of the present invention provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the aforementioned method.

[0013] The logic synthesis method, device, and storage medium proposed in this embodiment include: obtaining the target module's integrated input data based on the module integrated configuration information in the target configuration file, sending the target module's integrated input data and a startup command for the logic synthesis tool to a first target server, obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool, performing logic synthesis on the integrated input data of the target module, and, when it is determined that the first report file satisfies the integrated result tracking information in the target configuration file, sending the netlist file to a second target server and sending the netlist file and the integrated input data to a third target server. This logic synthesis method, on the one hand, can automatically start the logic synthesis tool and obtain the netlist file and the first report file generated after the logic synthesis tool is completed, thereby improving the efficiency of logic synthesis. On the other hand, it can automatically verify the first report file based on the target configuration file to confirm whether the next step of the process can be carried out, further improving the efficiency of logic synthesis. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A flowchart of a logic synthesis method provided by an embodiment;

[0015] Figure 2 A flowchart of a logic synthesis method provided in another embodiment;

[0016] Figure 3 A flowchart of a logic synthesis method provided in yet another embodiment;

[0017] Figure 4 A schematic diagram of a file structure of a logic synthesis platform provided by an embodiment;

[0018] Figure 5 A schematic structural diagram of a logic synthesis device provided by an embodiment;

[0019] Figure 6 A schematic diagram of the structure of a logic synthesis device provided by an embodiment. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0021] In the subsequent description, suffixes such as "module," "component," or "unit" used to represent elements are used only to facilitate the description of the embodiments of the present invention and have no specific meaning. Therefore, "module," "component," or "unit" may be used interchangeably.

[0022] Figure 1 This is a flow chart of a logic synthesis method provided in one embodiment. This embodiment is applicable to scenarios where logic synthesis is performed in integrated circuit design. The basic circuit in this embodiment refers to a microelectronic device or component. This embodiment can be executed by a logic synthesis device, which can be implemented in software and / or hardware, and can be integrated into a computer device. Figure 1 As shown, the logic synthesis method provided in this embodiment includes the following steps:

[0023] Step 101: Obtain comprehensive input data of a target module according to the module comprehensive configuration information in the target configuration file.

[0024] For today's increasingly complex VLSI designs, the traditional top-down logic synthesis approach is no longer suitable. Bottom-up logic synthesis is currently being adopted. This not only allows for parallel synthesis of all parts of the entire design, reducing synthesis time, but also facilitates comprehensive optimization of each module, reducing memory requirements. This embodiment is implemented based on block-based synthesis, parallelizing the corresponding logic synthesis operation flow and logic synthesis delivery for each block-based module.

[0025] The target configuration file in this embodiment is a file pre-written and pre-installed in the logic synthesis device. The target configuration file is a configuration file corresponding to the target project. The target project in this embodiment refers to the project to be subjected to logic synthesis. The target project in this embodiment includes at least one target module. The purpose of performing logic synthesis in this embodiment is to describe the RTL circuit code of the target module as a gate-level netlist file.

[0026] The target configuration file includes comprehensive configuration information. The comprehensive configuration information in this embodiment may include: the name of the target module and the version number of the corresponding RTL circuit code.

[0027] Optionally, the logic synthesis device may execute step 101 upon external triggering or automatically. Based on the module synthesis configuration information, the logic synthesis device may retrieve the target module's synthesis input data from a pre-defined storage area storing RTL circuit code. In this embodiment, the retrieved target module's synthesis input data may include at least the target module's RTL circuit code. Furthermore, the synthesis input data may also include the target module's constraint file.

[0028] Step 102: Sending the synthesis input data of the target module and the start command of the logic synthesis tool to the first target server.

[0029] In one embodiment, the first target server is a pre-configured server.

[0030] In another embodiment, the first target server is a server determined from a server cluster. Figure 3 The illustrated embodiments are described in detail.

[0031] After acquiring the synthesis input data of the target module, the logic synthesis device may automatically execute step 102: sending the synthesis input data of the target module and a start command of the logic synthesis tool to the first target server.

[0032] In order to complete the logic synthesis process, the startup command of the logic synthesis tool may also include other files required for logic synthesis, such as the constraint file of the target module and the running script file of the logic synthesis tool.

[0033] Optionally, the logic synthesis tool in this embodiment may be a Design Compiler (DC).

[0034] The first target server has been pre-installed with a logic synthesis tool. After receiving a start command of the logic synthesis tool, the first target server can start the logic synthesis tool and run the logic synthesis tool to perform logic synthesis on the synthesis input data of the target module.

[0035] Step 103: Obtain a netlist file and a first report file after a logic synthesis tool is run on the first target server to perform logic synthesis on the synthesis input data of the target module.

[0036] In this embodiment, the logic synthesis device can determine whether the first target server has completed execution at a preset frequency. Upon determining that the first target server has completed execution, the device obtains a netlist file and a first report file resulting from logic synthesis on the first target server. The netlist file in this embodiment, also known as a gate-level netlist file, is a file used to describe the interconnections between circuit components.

[0037] For example, the logic synthesis device may read the work log of the first target server at a preset frequency, and determine that the operation of the first target server is complete when it is determined that the work log indicates that the netlist file of the target module has been generated.

[0038] In one implementation, the startup command of the logic synthesis tool includes parameter information of the logic synthesis tool. The parameter information of the logic synthesis tool in this embodiment includes the version of the logic synthesis tool and the operating mode of the logic synthesis tool. By setting the parameter information of the logic synthesis tool in the startup command of the logic synthesis tool, it is possible to easily start the logic synthesis tool that matches the target module and operate the logic synthesis tool in the matching mode, thereby improving the scalability and flexibility of the logic synthesis process.

[0039] The first report file in this embodiment includes timing information during the logic synthesis process and other information related to logic synthesis.

[0040] Step 104: When it is determined that the first report file satisfies the synthesis result tracking information in the target configuration file, the netlist file is sent to the second target server, and the netlist file and synthesis input data are sent to the third target server.

[0041] The target configuration file in this embodiment also includes synthesis result tracking information. The synthesis result tracking information is used to indicate the required form of the report file after logic synthesis. When it is determined that the first report file meets the synthesis result tracking information in the target configuration file, it means that the netlist file of the target module obtained can be used for the next step of timing analysis and formal verification. The specific report analysis process can be: according to the filtering information in the synthesis result tracking information of the target configuration file, the warnings and errors that can be ignored in the first report file are filtered out, and then the filtered information is judged and a conclusion is drawn on whether the entire logic synthesis process is successful or not.

[0042] In one implementation, synthesis result tracking information includes general synthesis result tracking information and target module-specific synthesis result tracking information. To further improve efficiency, when the first report file meets both the general synthesis result tracking information and the target module-specific synthesis result tracking information, the netlist file can be sent to the second target server in parallel, while the netlist file and synthesis input data can be sent to the third target server. This dual information filtering further ensures that the first report file meets the required format, improving the efficiency of subsequent timing analysis and formal verification.

[0043] In this embodiment, the second target server may be a server running a timing analysis tool, and the third target server may be a server running a formal verification tool.

[0044] The timing analysis in this embodiment may be static timing analysis. The timing analysis tool in this embodiment may be PrimeTime, and the formal verification tool may be Formality.

[0045] In one embodiment, the second target server and the third target server are pre-configured servers.

[0046] In another embodiment, the second target server and the third target server are servers determined from the server cluster. Figure 3 The illustrated embodiments are described in detail.

[0047] In the field of integrated circuit design, after completing RTL circuit code inspection and functional verification, it is usually necessary to convert the RTL circuit code into a correct netlist file. Logic synthesis is used to convert the RTL code into a netlist file. Timing analysis verifies the timing information of the netlist file. Formal verification verifies the consistency between the netlist file and the RTL circuit code. After all these steps are correct, the processed netlist file and report file are delivered to the digital backend for the next step of design.

[0048] The logic synthesis method provided in this embodiment includes: obtaining the synthesis input data of the target module based on the module synthesis configuration information in the target configuration file, sending the synthesis input data of the target module and the startup command of the logic synthesis tool to a first target server, obtaining the netlist file and the first report file after the first target server runs the logic synthesis tool, performing logic synthesis on the synthesis input data of the target module, and when it is determined that the first report file meets the synthesis result tracking information in the target configuration file, sending the netlist file to a second target server and sending the netlist file and the synthesis input data to a third target server. This logic synthesis method can, on the one hand, automatically start the logic synthesis tool and obtain the netlist file and the first report file generated after the logic synthesis tool is completed, thereby improving the efficiency of logic synthesis. On the other hand, it can automatically verify the first report file based on the target configuration file to confirm whether the next step of the process can be carried out, further improving the efficiency of logic synthesis.

[0049] Figure 2 A flow chart of a logic synthesis method provided in another embodiment. Figure 1 Based on the embodiment shown and various optional solutions, the steps after step 104 are described in detail. Figure 2 As shown, the logic synthesis method provided in this embodiment also includes the following steps:

[0050] Step 105: Send a startup command of the timing analysis tool to the second target server.

[0051] Step 106: Send a startup command of the formal verification tool to the third target server.

[0052] In one implementation, a timing tool startup command may be sent to the second target server simultaneously with sending the netlist file to the second target server, and a formal verification tool startup command may be sent to the third target server simultaneously with sending the netlist file and synthesis input data to the third target server.

[0053] The second target server has been pre-installed with a timing analysis tool. After receiving a startup command for the timing analysis tool, the second target server can start the timing analysis tool and run the timing analysis tool to calculate and estimate the timing of the netlist file.

[0054] Optionally, in order to implement timing analysis, the startup command of the timing analysis tool may further include other files required for timing analysis, such as a process library file and a constraint file of a target module.

[0055] The third target server has been pre-installed with a formal verification tool. After receiving a startup command for the formal verification tool, the third target server can start the formal verification tool and run the formal verification tool to verify the netlist file.

[0056] Optionally, in order to implement formal verification, the startup command of the formal verification tool may further include other files required for formal verification, such as comprehensive input data of the target module.

[0057] In one implementation, the startup command of the timing analysis tool may further include parameter information of the timing analysis tool. The startup command of the formal verification tool may further include parameter information of the formal verification tool.

[0058] It should be noted that static timing analysis in this embodiment refers to the workflow of calculating and predicting the timing of digital circuits. Formal verification in this embodiment refers to the process of mathematically proving or verifying whether the circuit implementation scheme actually achieves the functions described by the circuit design. The process library in this embodiment is a file provided by the chip manufacturer that indicates the various units in the integrated circuit processing process. The constraint file in this embodiment can constrain the timing, area, and power consumption of the circuit. It is the lifeblood of the design and determines whether the chip meets the design specifications.

[0059] It should be noted that there is no time sequence relationship between step 105 and step 106.

[0060] Step 107: Obtain a second report file obtained by executing a timing analysis tool on the second target server to perform timing analysis on the netlist file.

[0061] In this embodiment, the logic synthesis device can determine whether the second target server has completed operation at a preset frequency. When it is determined that the second target server has completed operation, a second report file is obtained after the second target server runs a timing analysis tool and performs timing analysis on the netlist file.

[0062] For example, the logic synthesis device may read the work log of the second target server at a preset frequency, and determine that the operation of the second target server is complete when it is determined in the work log that the second report file of the target module has been generated.

[0063] Optionally, the second report file in this embodiment includes result information of the timing analysis.

[0064] Step 108: Obtain a third report file after the third target server runs the formal verification tool to perform formal verification on the netlist file.

[0065] In this embodiment, the logic synthesis device can determine whether the third target server has completed execution at a preset frequency. When determining that the third target server has completed execution, a third report file is obtained after the third target server executes a formal verification tool to perform formal verification on the netlist file.

[0066] For example, the logic synthesis device may read the work log of the third target server at a preset frequency, and determine that the operation of the third target server is complete when it is determined in the work log that the third report file indicating the target module has been generated.

[0067] Optionally, the third report file in this embodiment includes result information of the formal verification.

[0068] Step 109: When it is determined that both the second report file and the third report file meet the result judgment information in the target configuration file, the netlist file is delivered.

[0069] The target configuration file in this embodiment also includes result judgment information. The result judgment information is used to indicate the required form of the report file after timing analysis and formal verification, that is, the standards that the project needs to meet, such as the requirements for timing information, the requirements for area information, the results of formal verification and other conditions. The specific report analysis process can be: according to the filtering information in the result judgment information of the target configuration file, the warnings and errors that can be ignored in the second report file and the third report file are filtered out, and then the judgment is made based on the filtered information to draw a conclusion on whether the timing analysis and formal verification process are successful or not. When it is determined that the second report file and the third report file both meet the result judgment information in the target configuration file, it means that the netlist file function of the target module is correctly implemented, and the netlist file can be delivered to the back end. Optionally, according to actual needs, at least one of the first report file, the second report file and the third report file can also be delivered to the back end.

[0070] It should be noted that there is no time sequence relationship between step 107 and step 108.

[0071] Furthermore, after steps 107 and 108, the logic synthesis method provided in this embodiment further includes the steps of: displaying at least one of the netlist file, the first report file, the second report file, and the third report file; and / or sending at least one of the netlist file, the first report file, the second report file, and the third report file to an email address in a pre-set email list. The above-mentioned method of visually displaying at least one of the netlist file, the first report file, the second report file, and the third report file can facilitate integrated circuit designers to analyze these output files, thereby improving the efficiency of integrated circuit design.

[0072] The logic synthesis method provided in this embodiment also includes: sending a startup command of a timing analysis tool to a second target server, sending a startup command of a formal verification tool to a third target server, obtaining a second report file after the second target server runs the timing analysis tool and performs timing analysis on the netlist file, obtaining a third report file after the third target server runs the formal verification tool and performs formal verification on the netlist file, and when it is determined that the second report file and the third report file both meet the result judgment information in the target configuration file, delivering the netlist file. This logic synthesis method, on the one hand, can automatically start the next step of the timing analysis tool and the formal verification tool after the logic synthesis, saving the startup time of each tool; on the other hand, it can automatically obtain the second report file formed after the timing analysis tool is completed, and automatically obtain the third report file formed after the formal verification tool is completed, so that the steps of the current logic synthesis environment are seamlessly connected, and the processing between input and output does not require manual intervention, thereby improving the efficiency of integrated circuit design and saving labor costs; on the other hand, the second report file and the third report file can be automatically verified according to the target configuration file, and whether the next delivery process can be carried out can be automatically confirmed, without the need for manual confirmation of whether delivery can be carried out, further improving the efficiency of integrated circuit design and ensuring the accuracy, efficiency and standardization of delivery.

[0073] Figure 3 A flow chart of a logic synthesis method provided in another embodiment. Figure 1 and Figure 2 Based on the embodiment shown and various optional solutions, the steps before step 102, the steps after step 102 and the steps before step 104 are described in detail. Figure 3 As shown, the logic synthesis method provided in this embodiment includes the following steps:

[0074] Step 301: Obtain comprehensive input data of a target module according to the module comprehensive configuration information in the target configuration file.

[0075] The implementation process and technical principle of step 301 are similar to those of step 101 and will not be repeated here.

[0076] Step 302: Determine a server in the server cluster whose corresponding load meets a first preset condition as a first target server.

[0077] The first preset condition in this embodiment may be a screening condition such as the load being less than a preset threshold. The load in this embodiment may be measured by parameters such as the utilization rate of the server and unused memory.

[0078] Optionally, the specific implementation process of step 302 may be as follows: determining servers in a server cluster that are in normal status; sorting the servers in normal status in ascending order of utilization, and determining the servers that rank first in a preset number of utilization rates; sorting the servers that rank first in a preset number of utilization rates in ascending order of unused memory, and determining the servers that rank second in a preset number of unused memory rates; and determining the servers that rank second in a preset number of unused memory rates as the first target servers. The first target server determined in this manner can ensure efficient operation of the logic synthesis tool, thereby improving the efficiency of logic synthesis.

[0079] Step 303: Sending the synthesis input data of the target module and the start command of the logic synthesis tool to the first target server.

[0080] The implementation process and technical principle of step 303 are similar to those of step 102 and will not be repeated here.

[0081] In one implementation, there are multiple target modules. The implementation process of step 302 is specifically as follows: multiple servers in the server cluster whose corresponding loads meet the first preset condition are determined as multiple first target servers, and the mapping relationship between the first target servers and the target modules is determined. Based on this implementation, the implementation process of step 302 is specifically as follows: the integrated input data of the corresponding target modules and the startup command of the logic synthesis tool are sent to the first target servers in batches. This implementation can realize batch logic synthesis of multiple target modules when there are multiple target modules, thereby improving the efficiency of logic synthesis.

[0082] Step 304: Query the working status of the first target server at a preset frequency.

[0083] Step 305: If it is determined that the working status of the first target server is in the running state, determine to execute step 307.

[0084] Step 306: If it is determined that the working status of the first target server is not running, return to step 302.

[0085] In steps 304 to 306, the logic synthesis device may query the operating status of the first target server at a preset frequency. If the operating status of the first target server is determined to be running, step 307 is executed. If the operating status of the first target server is determined to be not running, it indicates that the startup command of the logic synthesis tool submitted to the first target server has failed, and it is necessary to return to step 302 and redetermine the first target server.

[0086] The implementation of steps 304 to 306 enables monitoring of the working status of the first target server and improves the success rate of logic synthesis.

[0087] Step 307: Obtain a netlist file and a first report file after the first target server runs a logic synthesis tool to perform logic synthesis on the synthesis input data of the target module.

[0088] The implementation process and technical principle of step 307 are similar to those of step 103 and will not be repeated here.

[0089] Step 308: When it is determined that the first report file meets the comprehensive result tracking information in the target configuration file, the server in the server cluster whose corresponding load meets the second preset condition is determined as the second target server, and the server in the server cluster whose corresponding load meets the third preset condition is determined as the third target server.

[0090] Similar to step 302, in step 308, when it is determined that the first report file meets the comprehensive result tracking information in the target configuration file, the second target server and the third target server can be determined to ensure the efficient execution of the timing analysis tool and the formal verification tool, thereby improving the efficiency of the timing analysis and formal verification.

[0091] The specific determination process is similar to the process of determining the first target server in step 302 and will not be repeated here.

[0092] Step 309: Send the netlist file and the startup command of the timing analysis tool to the second target server, and send the netlist file, synthesis input data and the startup command of the formal verification tool to the third target server.

[0093] The implementation process and technical principle of step 309 are similar to those of step 104, step 105 and step 106, and will not be repeated here.

[0094] Step 310: Obtain a second report file obtained by executing a timing analysis tool on the second target server to perform timing analysis on the netlist file.

[0095] In one implementation, the operating status of the second target server may be queried at a preset frequency before step 310. If the operating status of the second target server is determined to be in the running state, step 310 is executed. If the operating status of the second target server is determined to be in the non-running state, the process returns to step 308.

[0096] Step 311: Obtain a third report file after the third target server runs the formal verification tool to perform formal verification on the netlist file.

[0097] In one implementation, the operating status of the third target server may be queried at a preset frequency before step 311. If the operating status of the third target server is determined to be running, step 311 is executed. If the operating status of the third target server is determined to be not running, the process returns to step 308.

[0098] Step 312: When it is determined that both the second report file and the third report file satisfy the result judgment information in the target configuration file, the netlist file is delivered.

[0099] The implementation process and technical principle of step 312 are similar to those of step 109 and will not be repeated here.

[0100] The logic synthesis method provided in this embodiment establishes an effective synchronous communication mechanism at each stage by introducing a full-process target configuration file, enabling seamless integration between steps. This process is automated through rational process control, monitoring and submitting tool progress through a server-based traversal method, and monitoring the output of each tool in real time. All tools are automatically connected, and reports are analyzed and processed, achieving fully automated processing and delivery. This ensures that each step is not only accurate and efficient, but also significantly improves design efficiency through standardized operations.

[0101] The logic synthesis method provided in this embodiment can, on the one hand, determine the first target server, the second target server, and the third target server that meet the conditions, thereby improving the operating efficiency of each tool and thus improving the efficiency of logic synthesis. On the other hand, it can monitor the working status of each server and improve the success rate of logic synthesis.

[0102] Figure 4 This is a schematic diagram of the file structure of a logic synthesis platform provided in an embodiment. The logic synthesis platform provided in this embodiment can be used to implement Figures 1 to 3 The logic synthesis method provided by the embodiment shown is as follows. Figure 4 As shown, the logic synthesis platform is implemented by scripts, which include the following scripts: an automated logic synthesis platform main script, an automated logic synthesis platform initialization script, a platform sub-script folder, and a platform log folder.

[0103] Among them, the automated logic synthesis platform main script parses the initialization script of the automated logic synthesis platform and controls various sub-scripts.

[0104] The platform log folder stores four types of log files generated during platform operation. The comprehensive version log contains various files related to the comprehensive process. The platform result upload log contains logs generated during the data delivery process. The web dashboard upload log includes files generated during the upload of the required project content. The email sending log contains files generated during the sending of project emails.

[0105] The platform sub-script folder contains the following eight scripts.

[0106] (1) Parse the version information script, parse the version information file provided by the front end, and obtain the version information of the RTL circuit code and the information of the module that needs to be integrated, such as the name of the module.

[0107] (2) Move the constraint file script, which will update the latest constraint file and move the constraint file to the platform.

[0108] (3) Code acquisition script, which updates the code file and generates the code file required by the platform according to the version information of the RTL circuit code.

[0109] (4) One-click parallel execution of comprehensive process script is the core script of this platform, and its functions are as follows:

[0110] 1. Launch multiple modules in parallel to achieve one-click operation of logic synthesis tools, timing analysis tools, and formal verification tools.

[0111] 2. Before running the tool, sort the servers. First, select servers with normal status. Then sort the selected servers according to server utilization. Finally, re-sort the servers with the same utilization according to unused memory. When running the tool, submit the tool process according to the server sorting and monitor whether the submitted process is successful. If the submission fails, close the failed process and traverse the servers to continuously submit the corresponding process until the submission process is successful.

[0112] 3. Using threads to achieve parallel operation of various tools, no new terminal will be opened, and no terminal resources will be occupied. The terminal in this embodiment refers to a terminal of the Linux system.

[0113] 4. Control the versions of all tools and select the mode of logic synthesis tools.

[0114] 5. Use tool enable signals to select the tools you need to use to reduce server resource usage.

[0115] (5) Comprehensive result analysis script reduces manual analysis of comprehensive results. Logs or reports are analyzed through dual information filtering, general filtering information and special module filtering information. If all information is filtered, the result is correct; if there is any remaining information, manual confirmation is required.

[0116] (6) Comprehensive data delivery script to deliver the various data files generated.

[0117] (7) Generate scripts for web page dashboard data, generate data files required for the web page, and upload them.

[0118] (6) Generate and send scripts for email data, generate the data files required for email, and upload them.

[0119] This logic synthesis platform automatically implements the above-mentioned operation process through reasonable process control, monitors and submits tool processes by traversing the server, and monitors the output results of each tool in real time. It automatically connects all tools and analyzes and processes reports to achieve full-process automated processing and delivery. This makes each step not only accurate and efficient, but also the standardized operation greatly improves design efficiency.

[0120] Figure 5 This is a schematic diagram of the structure of a logic synthesis device provided by an embodiment. Figure 5 As shown, the logic synthesis device provided by this embodiment includes the following modules: a first acquisition module 51 , a sending module 52 and a second acquisition module 53 .

[0121] The first acquisition module 51 is configured to acquire the comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file.

[0122] The sending module 52 is configured to send the synthesis input data of the target module and the start command of the logic synthesis tool to the first target server.

[0123] Optionally, the startup command of the logic synthesis tool includes parameter information of the logic synthesis tool.

[0124] The second acquisition module 53 is configured to acquire a netlist file and a first report file after the first target server runs a logic synthesis tool to perform logic synthesis on the synthesis input data of the target module.

[0125] The sending module 52 is further configured to send the netlist file to the second target server and send the netlist file and the synthesis input data to the third target server when it is determined that the first report file meets the synthesis result tracking information in the target configuration file.

[0126] Optionally, the integrated result tracking information includes: general integrated result tracking information and integrated result tracking information dedicated to the target module.

[0127] Optionally, the sending module 52 may also be configured to send a start command of the timing analysis tool to the second target server.

[0128] Optionally, the sending module 52 may also be configured to send a start command of the formal verification tool to the third target server.

[0129] Optionally, the device further includes: a third acquisition module, a fourth acquisition module and a delivery module.

[0130] The third acquisition module is configured to acquire a second report file obtained by executing a timing analysis tool on the second target server to perform timing analysis on the netlist file.

[0131] The fourth acquisition module is configured to acquire a third report file obtained by executing a formal verification tool on a third target server to perform formal verification on the netlist file.

[0132] The delivery module is configured to deliver the netlist file when it is determined that both the second report file and the third report file meet the result judgment information in the target configuration file.

[0133] Optionally, the device further includes a first determining module.

[0134] In one embodiment, the first determining module is configured to determine a server in the server cluster whose corresponding load meets a first preset condition as the first target server.

[0135] Optionally, the first determination module is specifically used to: determine the servers in the server cluster that are in normal status; sort the servers in normal status in ascending order of utilization, and determine the servers that rank in the first preset number of utilizations; sort the servers that rank in the first preset number of utilizations in ascending order of unused memory, and determine the servers that rank in the first preset number of unused memory; determine the servers that rank in the first preset number of unused memory as the first target servers.

[0136] In one embodiment, the first determination module is further configured to determine a server in the server cluster whose corresponding load meets a second preset condition as the second target server. The first determination module is further configured to determine a server in the server cluster whose corresponding load meets a third preset condition as the third target server.

[0137] In one embodiment, the device further includes: a query module and a second determination module.

[0138] The query module is configured to query the working status of the first target server at a preset frequency.

[0139] The second determination module is configured to, if it is determined that the working status of the first target server is in the running state, determine to execute the step of obtaining the first target server running the logic synthesis tool, and performing logic synthesis on the synthesis input data of the target module and the first report file when it is determined that the operation of the first target server is completed; if it is determined that the working status of the first target server is in the non-running state, return to execute the step of determining the server in the server cluster whose corresponding load meets the first preset condition as the first target server.

[0140] Optionally, there are multiple target modules. The first determination module is specifically configured to: determine multiple servers in the server cluster whose corresponding loads meet a first preset condition as multiple first target servers, and determine a mapping relationship between the first target servers and the target modules. Based on this implementation, the sending module is specifically configured to: batch send the integrated input data of the corresponding target modules and the startup command of the logic synthesis tool to the first target servers.

[0141] In one embodiment, the device further includes: a display module and / or an email sending module.

[0142] The display module is configured to display at least one of the netlist file, the first report file, the second report file, and the third report file.

[0143] The mail sending module is configured to send at least one of the netlist file, the first report file, the second report file and the third report file to an email address in a preset mailing list.

[0144] The logic synthesis device provided in this embodiment is used to execute the logic synthesis method of any of the above embodiments. The implementation principle and technical effects of the logic synthesis device provided in this embodiment are similar and will not be repeated here.

[0145] Figure 6 FIG. 1 is a schematic diagram of the structure of a logic synthesis device provided in an embodiment. Figure 6 As shown, the logic synthesis device includes a processor 61 and a memory 62; the number of processors 61 in the logic synthesis device can be one or more. Figure 6 In the example of a processor 61, the processor 61 and the memory 62 in the logic synthesis device can be connected by a bus or other means. Figure 6 The bus connection is taken as an example.

[0146] The memory 62, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the logic synthesis method in the embodiments of the present application (for example, the first acquisition module 51, the sending module 52, and the second acquisition module 53 in the logic synthesis device). The processor 61 executes the software programs, instructions, and modules stored in the memory 62, thereby implementing various functional applications and logic synthesis of the logic synthesis device, that is, implementing the aforementioned logic synthesis method.

[0147] The memory 62 may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application program required for a function; the data storage area may store data created by using a logic synthesis device. Furthermore, the memory 62 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device.

[0148] An embodiment of the present application further provides a storage medium containing computer-executable instructions. When the computer-executable instructions are executed by a computer processor, the computer-executable instructions are used to perform a logic synthesis method, the method comprising:

[0149] Obtain comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file;

[0150] Sending the synthesis input data of the target module and a start command of a logic synthesis tool to the first target server;

[0151] Obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool to perform logic synthesis on the synthesis input data of the target module;

[0152] When it is determined that the first report file satisfies the synthesis result tracking information in the target configuration file, the netlist file is sent to a second target server, and the netlist file and the synthesis input data are sent to a third target server.

[0153] Of course, the storage medium provided by the present application contains computer-executable instructions, and its computer-executable instructions are not limited to the method operations described above, but can also execute related operations in the logic synthesis method provided by any embodiment of the present application.

[0154] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application.

[0155] In general, various embodiments of the present application may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.

[0156] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0157] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0158] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the invention is not limited thereby. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the invention should be within the scope of the invention.

Claims

1. A logic synthesis method, characterized in that: The method comprises: Obtain comprehensive input data of the target module according to the module comprehensive configuration information in the target configuration file; Sending the synthesis input data of the target module and a startup command of a logic synthesis tool to a first target server; wherein the startup command of the logic synthesis tool includes parameter information of the logic synthesis tool, and the parameter information includes a version of the logic synthesis tool and an operating mode of the logic synthesis tool, so that the first target server starts the logic synthesis tool that matches the target module and operates the logic synthesis tool in the matching mode; Obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool to perform logic synthesis on the synthesis input data of the target module; When it is determined that the first report file satisfies the synthesis result tracking information in the target configuration file, the netlist file is sent to a second target server, and the netlist file and the synthesis input data are sent to a third target server.

2. The method according to claim 1, characterized in that The method further comprises: Sending a startup command of a timing analysis tool to the second target server; Sending a startup command of a formal verification tool to the third target server; Obtaining a second report file after the second target server runs the timing analysis tool to perform timing analysis on the netlist file; Obtaining a third report file after the third target server runs the formal verification tool to perform formal verification on the netlist file; When it is determined that both the second report file and the third report file meet the result judgment information in the target configuration file, the netlist file is delivered.

3. The method according to claim 1, characterized in that Before sending the synthesis input data of the target module and the start command of the logic synthesis tool to the first target server, the method further includes: A server in the server cluster whose corresponding load meets a first preset condition is determined as the first target server.

4. The method according to claim 3, characterized in that The step of determining, in the server cluster, a server whose corresponding load satisfies a first preset condition as the first target server includes: Determine a server in the server cluster that is in a normal state; Sorting the servers in normal status in ascending order of utilization rate, and determining the servers with the first preset number of utilization rates being ranked first; Sorting the servers whose utilization rates rank first among the preset number in ascending order of unused memory to determine the servers whose unused memory rank first among the preset number; The servers whose unused memory is ranked before a second preset number are determined as the first target servers.

5. The method according to claim 3 or 4, characterized in that After sending the synthesis input data of the target module and the start command of the logic synthesis tool to the first target server, the method further includes: querying the working status of the first target server at a preset frequency; If it is determined that the working state of the first target server is in the running state, determining to execute the step of obtaining a netlist file and a first report file after the first target server runs the logic synthesis tool and performs logic synthesis on the synthesis input data of the target module when it is determined that the first target server has completed the operation; If it is determined that the working state of the first target server is not running, the process returns to the step of determining a server in the server cluster whose corresponding load meets the first preset condition as the first target server.

6. The method according to claim 3 or 4, characterized in that There are multiple target modules. The step of determining, in the server cluster, a server whose corresponding load satisfies a first preset condition as the first target server includes: Determining, in the server cluster, a plurality of servers whose corresponding loads meet a first preset condition as a plurality of first target servers, and determining a mapping relationship between the first target servers and target modules; The sending of the integrated input data of the target module and the start command of the logic synthesis tool to the first target server includes: Sending the synthesis input data of the corresponding target modules and the start-up command of the logic synthesis tool to the first target server in batches.

7. The method according to any one of claims 2 to 4, characterized in that After obtaining the third report file obtained by executing the formal verification tool on the third target server to perform formal verification on the netlist file, the method further includes: displaying at least one of the netlist file, the first report file, the second report file, and the third report file; and / or, At least one of the netlist file, the first report file, the second report file, and the third report file is sent to an email address in a preset email list.

8. The method according to any one of claims 1 to 4, characterized in that Before sending the netlist file to the second target server and sending the netlist file and the synthesis input data to the third target server, the method further includes: Determine a server in the server cluster whose corresponding load meets the second preset condition as the second target server; A server in the server cluster whose corresponding load meets the third preset condition is determined as the third target server.

9. The method according to any one of claims 1 to 4, characterized in that The comprehensive result tracking information includes: general comprehensive result tracking information and comprehensive result tracking information dedicated to the target module.

10. A logic synthesis device, characterized in that The device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection and communication between the processor and the memory. When the program is executed by the processor, the steps of the logic synthesis method according to any one of claims 1 to 9 are implemented.

11. A storage medium for computer-readable storage, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the logic synthesis method according to any one of claims 1 to 9.

Images