Method and device for eliminating functional errors and Trojans in FPGA implementation circuits

Abstract

A method for transforming the function of a programmable circuit such as an FPGA to eliminate functional errors or hardware Trojans is provided, including: providing a lookup table mapping circuit representation derived from a programmable circuit, the programmable circuit being implemented using a first register transfer level RTL document having an original specification; providing a second RTL document having a revised specification modified from the original specification and having functions transformed from the original specification; converting the lookup table mapping circuit representation into a shadow netlist corresponding to a gate-level netlist representing the lookup table mapping circuit representation; generating a second gate-level netlist from the second RTL document; generating a functional ECO patch circuit to be fully merged into the lookup table mapping circuit representation based on a comparison of the shadow netlist with the second gate-level netlist; and transforming the function of the programmable circuit by merging the ECO patch circuit into the lookup table mapping circuit representation. The present invention reduces the time spent on ECO iterations in constructing programmable circuits and minimizes the programmable circuit chip area occupied after adding the patch circuit.

Description

[0001] Declaration of benefit of using prior application

[0002] This application claims the benefit of U.S. continuation-in-part application No. 17 / 005337, entitled "Methods and Apparatus for Eliminating Functional Errors and Hardware Trojans in Integrated Circuits Implemented by Field Programmable Gate Arrays (FPGAs)", filed on August 28, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates generally to circuit design and, more particularly, to methods and apparatus for improving the efficiency of switching integrated circuit functions. Background Art

[0004] Modern circuits, such as integrated circuits (ICs), are very complex. For example, an average desktop computer chip can have more than 1 billion transistors. Due to the complexity and high cost, IC design is often outsourced to third parties to complete the circuit design. This outsourcing approach provides attackers with the opportunity to damage the designed IC by introducing malicious changes or hardware Trojans (HTs), which leads to serious security issues, especially for critical applications such as military applications. HTs may cause malfunctions or damage to the circuits in which they are embedded, reducing circuit reliability and leaking confidential information.

[0005] There is an urgent need for new methods and devices for verifying and improving circuit safety.

[0006] In addition, when designing a very large scale integrated circuit (VLSI), it may be necessary to change the function of the IC at some point after the initial design of the IC for various reasons, such as improving its performance, introducing new functions, or masking HT. Such changes are usually achieved by performing an engineering change order (ECO). However, existing ECO techniques are slow and inefficient. Therefore, new methods and devices for changing the function of an IC are needed. Summary of the invention

[0007] An exemplary embodiment is proposed herein, which provides a method for detecting, locating and shielding functional hardware Trojans (HT) in an arithmetic circuit to improve circuit security. The method detects and eliminates the HT in the second netlist by comparing a standard arithmetic circuit (referred to as a first netlist) with a circuit infected by HT (referred to as a second netlist).

[0008] This paper extracts arithmetic macro modules from the first netlist and the second netlist respectively, and then compares the extracted arithmetic macro modules. The arithmetic macro modules are used to locate the position of HT in the second netlist, and patch circuits are added in the second netlist to shield HT to improve circuit security.

[0009] An example embodiment provides a method for transforming the function of a circuit. The method provides a first register transfer level (RTL) file of an original specification and a second RTL file of a revised specification, generates a first gate level (GTL) netlist and a second GTL netlist, compares the two RTL files to identify instances to be modified, locates the instances to be modified in the first GTL netlist, and transforms the function of the circuit by patching the circuit so that the patched first GTL netlist is equivalent to the second GTL netlist.

[0010] One example embodiment provides a method of transforming functionality of a programmable circuit (eg, an FPGA). The method includes: providing a lookup table (LUT) mapping circuit representation derived from a programmable circuit, the programmable circuit being implemented using a first register transfer level (RTL) file, the first RTL file having an original specification; providing a second RTL file of the programmable circuit, the second RTL file having a revised specification, wherein the revised specification is modified from the original specification and has a function transformed from the original specification; converting the LUT mapping circuit representation into a shadow netlist, the shadow netlist corresponding to a gate level (GTL) netlist representing the LUT mapping circuit representation; generating a second GTL netlist from the second RTL file; generating an engineering change (ECO) patch circuit to be fully merged into the LUT mapping circuit representation based on a comparison of the shadow netlist with the second GTL netlist; and transforming the function of the programmable circuit by merging the ECO patch circuit into the LUT mapping circuit representation, wherein the merged LUT mapping circuit representation is equivalent to the second GTL netlist to perform the same function, thereby enabling the programmable circuit to be reprogrammed according to the revised specification by utilizing the free merge cost characteristic of the LUT structure.

[0011] Other exemplary embodiments are also discussed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A diagram illustrating a situation where a hardware Trojan (HT) is implanted during a circuit design process according to an exemplary embodiment.

[0013] Figure 2A A gate level (GTL) circuit diagram according to an exemplary embodiment is shown.

[0014] Figure 2B A circuit diagram after HT implantation in a GTL circuit according to an exemplary embodiment is shown.

[0015] Figure 2C A modified GTL circuit diagram according to an exemplary embodiment is shown.

[0016] Figure 2D An HT diagnostic report according to an exemplary embodiment is shown.

[0017] Figure 3 A flow chart of an example method according to an exemplary embodiment is shown.

[0018] Figure 4A A composition diagram of a multiplier according to an exemplary embodiment is shown.

[0019] Figure 4B A composition diagram of a multiplier according to an exemplary embodiment is shown.

[0020] Figure 5 A schematic diagram of a XOR forest is shown according to an exemplary embodiment.

[0021] Figure 6 A flow chart of an example reverse engineering technique is shown in accordance with an illustrative embodiment.

[0022] Fig. 7A A schematic diagram of checking a netlist according to an exemplary embodiment is shown.

[0023] Figure 7B A schematic diagram of a target netlist according to an exemplary embodiment is shown.

[0024] Figure 7C A schematic diagram of a pruned mesh is shown according to an exemplary embodiment.

[0025] Fig. 8A A schematic diagram is shown before adding a patch circuit according to an exemplary embodiment.

[0026] Figure 8B A schematic diagram is shown after adding a patch circuit according to an exemplary embodiment.

[0027] Fig.9A A schematic diagram is shown before adding conservative patches according to an exemplary embodiment.

[0028] Fig. 9B A schematic diagram is shown after adding conservative class patches according to an exemplary embodiment.

[0029] Fig. 10A A schematic diagram is shown before adding an aggressive class patch according to an exemplary embodiment.

[0030] Fig. 10B A schematic diagram is shown after adding an aggressive class patch according to an exemplary embodiment.

[0031] Fig.11A A circuit diagram is shown before optimizing a patch circuit using an Add-First rewiring transformation according to an exemplary embodiment.

[0032] Fig. 11BA circuit diagram is shown after optimizing a patch circuit using an Add-First rewiring transformation according to an exemplary embodiment.

[0033] Fig. 12A A circuit diagram is shown before optimizing a patch circuit using a Cut-First rewiring transformation according to an exemplary embodiment.

[0034] Fig. 12B A circuit diagram is shown after optimizing a patch circuit using a Cut-First rewiring transformation according to an exemplary embodiment.

[0035] Fig.13 A test case information table according to an exemplary embodiment is shown.

[0036] Fig.14 A table of experimental results according to an example method is shown.

[0037] Fig.15 A computer system is shown in accordance with an exemplary embodiment.

[0038] Fig.16 A flow chart is shown of an example method of transforming circuit functionality according to an exemplary embodiment.

[0039] Fig.17 A diagram illustrating an example method of generating a netlist to be patched according to an example embodiment.

[0040] Fig.18 A diagram illustrating an example method of obtaining instances, module ports, and signals to be patched according to an exemplary embodiment.

[0041] Fig.19 A diagram illustrating an example of an ECO process according to an exemplary embodiment.

[0042] Fig. 20A A diagram illustrating a legacy netlist in a non-programmable circuit before ECO according to an exemplary embodiment.

[0043] Fig. 20B According to an exemplary embodiment, Fig. 20A Figure 1. A diagram of the corresponding ECO netlist in the non-programmable circuit.

[0044] Fig.21A A diagram illustrating a legacy netlist in a programmable circuit before ECO according to an exemplary embodiment.

[0045] Fig. 21B According to an exemplary embodiment, Fig.21A A diagram of the corresponding ECO netlist in the programmable circuit.

[0046] Fig. 22 A flow chart is shown of an example method of transforming functionality of a programmable circuit according to an example embodiment.

[0047] Fig.23 A flow chart illustrating an example process of LUT-directed ECO according to an embodiment is shown. DETAILED DESCRIPTION

[0048] Example embodiments relate to methods and apparatus for improving safety of electrical circuits.

[0049] Circuits (e.g., integrated circuits (ICs)) or chips are very complex to design and manufacture. Modern ICs typically include millions of tiny electronic components, such as gates, transistors, and diodes (e.g., an average desktop computer chip can now have more than 1 billion transistors), which makes it impossible for people to design such circuits or chips using paper and pencil or manually. Hardware, such as computer devices or systems with corresponding software installed, such as electronic design automation (EDA) or computer-aided design (CAD) tools, is usually used to accomplish these tasks.

[0050] As the complexity of IC design and manufacturing has increased significantly, designs are often outsourced using third-party intellectual property (3PIP) from suppliers. The possibility of an attacker (e.g., an untrusted person or dishonest engineer or spy) injecting a hardware Trojan (HT) or bug (e.g., unexpected or unauthorized functional hardware insertion, malicious hardware insertion, or unauthorized design modification) into the circuit has increased significantly. In addition, unreliable manufacturers can also install unexpected functions into the circuit or chip during the hardware production stage.

[0051] HT or errors can harm circuits or chips in many ways. For example, HT maliciously changes or modifies the function of a circuit by adding, deleting, or modifying one or more components of the circuit (e.g., logic gates, transistors, diodes, etc.). As another example, HT indirectly changes the function of a circuit by modifying one or more parameters to be sent to the circuit. HT can interrupt a circuit (e.g., an IC) or modify the function of a normal circuit. As an example, HT causes the IC to malfunction and / or perform one or more functions that constitute a security attack. HT can also be designed or implanted by a spy to retrieve sensitive data or information, or designed to change host circuit specifications such as latency, power consumption, and reliability. For example, if HT is implanted or embedded in a circuit, a circuit or chip that is specified to work properly for ten years may be reduced to only one year of reliability.

[0052] Therefore, in industries such as IC design, verification and manufacturing, consumer products and military applications, it is very important to detect the presence of HT or defects in circuits (such as arithmetic circuits, such as ICs) and to mask or kill such HT. And detecting and removing such HT or errors to improve circuit security is of great significance in these industries. Undetected HT in a circuit such as an IC can put the circuit at great risk in multiple aspects such as leakage of sensitive information. Existing detection algorithms are inefficient (such as high runtime or time complexity) in detecting and removing HT, greatly extending the product design cycle, and increasing the time to market and endangering profit margins. In addition, the unsatisfactory efficiency or runtime complexity of the existing algorithms requires computer equipment to provide more resources (such as memory usage) with high performance (such as high processing power and speed), and also increases network consumption when data is transmitted to a remote server over a network. Therefore, unsatisfactory methods or schemes for HT detection and capture not only endanger many industries (such as the IC industry and other industries related to or dependent on the IC industry) technically and economically, but also require expensive computer hardware, requiring a large amount of resource consumption, such as memory usage and high processing speed.

[0053] Existing or conventional methods have difficulties and deficiencies in detecting and killing HT in circuits. On the one hand, this is because the presence of HT is not easy to detect. HT may reside within the test circuit of the chip to avoid being detected during normal operation and occasionally be activated to perform malicious operations. In addition, the number of logic gates in modern ICs or chips is so large that exhaustive testing is not feasible. On the other hand, existing methods are inherently deficient in one or more aspects.

[0054] For example, many existing methods can only extract simple logic patterns, such as gates, from gate-level (GTL) netlists, but cannot handle complex but basic arithmetic modules, such as adders and multipliers. Some existing methods use simulation tools to identify logic gates with low activation probabilities, however, the activation probabilities are inaccurate. Some existing methods use functional formal verification techniques based on satisfiability (SAT) to detect HT in circuits, however, they cannot verify certain arithmetic logic designed in different styles (e.g., non-Booth multipliers and Booth multipliers). The main reason why existing SAT-based functional formal verification techniques do not work well is that existing SAT algorithms are highly dependent on successfully locating internal equivalent points of comparison logic. When a small number of internal equivalent points are found, even for relatively small circuits, the solution time increases exponentially in the worst case (e.g., when comparisons are performed between multipliers designed in different styles (e.g., non-Booth and Booth)). Existing SAT algorithms also show inability to work in terms of equivalent checking of circuits (e.g., arithmetic circuits), such as being unable to prove equality between two arithmetic circuits. Furthermore, existing methods cannot detect and locate where the body and boundaries of HT are, thus preventing chip owners or designers from analyzing the circuits for expected damage in HT.

[0055] Therefore, the existing methods or schemes are inefficient in detecting and masking or removing circuits or arithmetic circuits (e.g., ICs, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), digital signal processors (DSPs), etc.). From a computer technology perspective, the existing methods or schemes are also disadvantageous: because the less efficient process of detecting and masking HT consumes a large amount of time (e.g., tens of hours or days, or even does not converge (the subject problem is still left unsolved after a large amount of running time)); requires large resource usage (e.g., memory usage and network consumption); and expensive computer equipment (e.g., high processing power).

[0056] The exemplary embodiments solve the above problems by providing technical solutions in new methods and devices that function in unconventional ways to benefit the circuit industry and the computer industry. The exemplary embodiments have significantly improved or enhanced efficiency in preventing (e.g., detecting, locating, and masking or removing) HT, increasing circuit production (e.g., yield) and life by reducing or preventing circuit failures and malfunctions caused by HT. On the other hand, circuit security is improved by avoiding leakage of sensitive data or by avoiding circuits or devices or machines containing such circuits to prevent circuits from being taken over by attackers or spies. The exemplary embodiments further benefit computer technology by reducing resource consumption (e.g., memory usage and network consumption). The exemplary methods can be performed by computer devices or systems with lower hardware requirements and thus reduce the need for expensive computers with expensive chips, memories, and other internal electronic components.

[0057] The exemplary embodiments solve the above problems by providing technical solutions in new methods and apparatus. The new methods and apparatus can detect one or more functional differences between a problem circuit and a correct circuit caused by one or more HTs or errors, can locate or display the differences to correct the HTs or investigate tampering intentions or purposes, and kill, mask or remove the HTs by restoring the functions to the original specifications (e.g., correct specifications). As an example, the exemplary embodiments restore the functions of the circuit or chip back to the original specifications with minimal circuit changes to avoid significantly affecting the performance of the circuit or chip (such as clock and timing, etc.). The exemplary embodiments improve circuit security by preventing intentional or drawn damage to the circuit at an early stage and find out the source of the spy by revealing the HT intentions.

[0058] As an example, the exemplary embodiment solves the above problems by providing a combined technology solution with reverse engineering, formal verification, functional engineering change (ECO), and logic rewiring algorithms. As an example, the exemplary embodiment can automatically process multiple HTs to ensure that 100% of the existing HTs are captured in the circuit.

[0059] As an example, an exemplary embodiment combines reverse engineering and formal verification (referred to as a complementary coupled (CC) formal verification scheme) to overcome the problem that the SAT algorithm cannot be used in arithmetic verification. The example reverse engineering performs well in verifying proofs of equality, while the example SAT solver performs well in verifying proofs of inequality. The coupling of reverse engineering and SAT techniques can simultaneously utilize the advantages of reverse engineering and SAT, and obtain a combined advantage, which improves HT detection, reduces runtime complexity, and improves the ability to verify circuit correctness. As an example, an exemplary embodiment can compare a netlist of a correct or standard design with a netlist that may be embedded or implanted with an HT circuit.

[0060] In an exemplary embodiment, when a functional difference between the actual generated circuit and the standard circuit is detected, a functional ECO technique is used to locate the HT, and a patch circuit is inserted or added to cover or eliminate the HT. In another exemplary embodiment, a logic rewiring technique is applied to optimize the patch circuit to minimize the size of the circuit. This technique minimizes the difference between the performance of the circuit after correction and the performance before correction.

[0061] As an example, an exemplary embodiment for detecting, locating, and masking multiple HTs (there is no limit on the number of HTs) in an IC with millions of logic gates may run in minutes, whereas existing methods may take hours or even days.

[0062] Exemplary embodiments include computer systems with specific software, and such computer systems embedded in a network. The example computer systems solve technical problems caused in circuit industries such as the IC industry by executing the example methods herein. When executing the example methods, the example computer systems improve hardware performance by reducing resource usage such as memory usage and network consumption.

[0063] Figure 1 A diagram showing a scenario of HT injection during a circuit design process according to an exemplary embodiment. Diagram 100 includes a customer 110 , a design factory 120 , a chip manufacturing factory 130 , and a spy or attacker 140 .

[0064] As an example, customer 110 has a plan or proposed specifications (e.g., microarchitecture and system-level specifications, etc.) for designing a new circuit or chip (e.g., IC, ASIC, FPGA, DSP, etc.) to suit the industry field. As an example, a register transfer level (RTL) specification language (such as Verilog or VHDL) is used to specify the design function or specification. Then, design factory 120 undergoes a long design process based on the specified design function provided by customer 110, in which the design team uses hardware (such as a computer) including software (such as an EDA or CAD tool) to perform circuit design. Customer 110 is equivalent to outsourcing the specific circuit design to design factory 120.

[0065] As an example, the design process performed in the design factory 120 includes logic synthesis and physical placement and routing (P&R). Figure 1 As shown, the RTL level circuit 122 is converted into a gate level (GTL) circuit 124, which is then converted into a circuit level circuit 126. The finalized circuit design is handed over to a chip manufacturer 130 for production.

[0066] like Figure 1 As shown, a spy 140 (e.g., an untrusted person or a dishonest engineer) maliciously inserts or embeds HT or errors into a circuit or chip during the design phase of the design factory 120. As an example, HT can be introduced into the circuit at any intermediate stage in the design factory 120, such as the design process of the RTL level circuit 122, the gate level circuit 124, and the circuit level circuit 126.

[0067] Client 110 must be able to detect and remove HT effectively and efficiently (e.g., detect HT 100% of the time within practical time limits, such as within polynomial time or even linear time). Otherwise, spy 140 with injected HT may cause circuit or chip failure, damage the chip's system, or steal confidential information. Client 110 may also prefer a less expensive HT capture process (e.g., lower requirements on hardware such as computer equipment).

[0068] Figures 2A-2D Schematic diagram of HT injection in a gate level (GTL) circuit according to an exemplary embodiment is shown. For illustration purposes only, Figure 2A The original GTL circuit 210 is shown, which includes an 8-AND gate 214 with an input vector 212, 212 has 8 inputs represented as in[7:0], and an AND gate 216 has an output 218 (out) and two inputs: one is the output of the 8-AND gate 214, and the other is the input 213 (s).

[0069] As an example, Figure 2A The GTL circuit 210 in is the original netlist of the circuit. As an example, the input 213 receives a redundant internal signal s, which is a fixed logic 1 during a normal operating mode or normal operation.

[0070] Figure 2B A netlist 220 including malicious logic or HT 225 is shown according to an example embodiment. As a result, Figure 2A The AND gate 216 in the circuit is replaced or changed into a multiplexer (MUX) 226. The added malicious logic 225 is not triggered in the normal operating mode and therefore cannot be detected by using conventional methods such as normal input test vectors.

[0071] Figure 2C A patched netlist 230 according to an exemplary embodiment is shown. As shown, the patched netlist 230 includes a patch or patch logic 235 that masks or kills the malicious logic or HT 225. In an exemplary embodiment, the size of the patch 235 is minimized to reduce the performance loss of the target circuit or chip. As an example, the target circuit or chip is a final product with the HT removed or masked.

[0072] Figure 2D An HT diagnostic report 240 is shown according to an exemplary embodiment. The HT diagnostic report 240 includes a first portion 242 showing the netlist of the patch 235 and a second portion 244 showing the MUX 236 after correction with the patch 235.

[0073] Figures 2A-2D A flow chart for improving circuit safety by an exemplary method of detecting, locating and masking or killing inserted or implanted HTs or defects in a circuit is shown. The inserted HTs are masked by introducing a patch so that the circuit can be restored back to a correct circuit according to the original or correct specification.

[0074] Figure 3A flowchart according to an exemplary embodiment is shown. Flowchart 300 represents an example method performed by a computer with relevant software installed or a device incorporating the computer. Computers include electronic devices such as computer systems or electronic systems, wearable electronic devices, servers, portable electronic devices, handheld portable electronic devices, and hardware (e.g., processors, processing units, digital signal processors, controllers, memory, etc.).

[0075] The exemplary method solves one or more prior art problems in the circuit industry as described above by improving the effectiveness and efficiency of circuit design (e.g., reducing run-time complexity) when executed by a computer. The exemplary method also improves the performance of a computer executing the exemplary method by consuming less resources (e.g., memory, processor, and network usage such as bandwidth).

[0076] Block 302 depicts a first netlist of an arithmetic circuit used by the example method.

[0077] For example, the first netlist is an original specified (standard or correct) netlist that meets the specifications of the customer's or individual's plan or suggestion. As an example, the first netlist is a gate level (GTL) netlist converted from a standard register transfer level (RTL) circuit.

[0078] Block 304 depicts a second netlist of an arithmetic circuit used by the example method.

[0079] For example, the second netlist is the netlist to be checked. As an example, the second netlist is modified by the HT generated by the spy or attacker. In order to improve the circuit security, it is necessary to check whether the second netlist has the same function as the first netlist.

[0080] Block 306 indicates extracting arithmetic macrocells from the first netlist to obtain a first or plurality of arithmetic macros. Block 308 depicts extracting arithmetic macrocells from the second netlist to obtain one or more arithmetic macros.

[0081] As an example, a macro or arithmetic macro is defined as a logic block, which is a building block in a circuit (e.g., IC), such as an adder, a multiplier, a multiplexer (MUX), or a function such as (A+B)×C can all be considered a macro.

[0082] In an exemplary embodiment, an example reverse engineering (RE) technique is applied to extract and compare all arithmetic macros, such as adders and multipliers. Arithmetic macros are usually composed of many basic components "1-bit adders", which include 1-bit half adders (HA) and / or 1-bit full adders (FA). The reverse engineering technique (RE) first identifies all these basic components from the entire circuit. Then, RE constructs a 1-bit adder diagram, in which the output of one adder is the input of another adder. The functions of different arithmetic macros can be obtained from the different composition styles of the constructed adder diagrams.

[0083] As an example, arithmetic components (such as adders and multipliers) are implemented in various styles such as CLA adders, Ripple adders, Booth multipliers, and Non-Booth multipliers composed of 1-bit adders. Figure 4A-4B Two different types of multipliers 410 and 420 are shown, where FA represents a 1-bit full adder and HA represents a 1-bit half adder. As shown in the figure, both multiplier 410 and multiplier 420 include some common structural units (eg, a 1-bit adder).

[0084] In an exemplary embodiment, all 1-bit adders are first extracted. A 1-bit full adder (FA) has 3 input signals (e.g., a, b, and c) and 2 output signals (e.g., sum and carry (also called co)). The functions of a 1-bit full adder are as follows:

[0085]

[0086] FAco=a&b+b&c+a&c (1)

[0087] in Also known as the "XOR" operation represents the Boolean "XOR" function, "+" represents the Boolean "OR" function, and "&" represents the Boolean "AND" function.

[0088] A 1-bit half adder (HA) has two input signals (e.g. a and b) and 2 output signals (e.g. sum and carry (also called co)). The functions of a 1-bit half adder are as follows:

[0089]

[0090] HAco=a&b

[0091] For example, both adders and multipliers are composed of one or more 1-bit adders. For example, the third output of a 4-bit multiplier of the Non-Booth type is represented as:

[0092]

[0093] As an example, the fourth bit output of a non-Booth 4-bit multiplier is represented as:

[0094]

[0095]

[0096] Where FAco and HAco are the output signals of other 1-bit adders

[0097] In an exemplary embodiment, in order to calculate a 1-bit adder graph, all 1-bit adders are first identified. In order to calculate a 1-bit adder, all 2-input single-output subcircuits whose function is exclusive OR (XOR) are first identified. Then, one or more XOR trees are identified. The XOR tree contains one or more 2-input XOR subcircuits and the output of each 2-input XOR subcircuit is an input signal of another XOR subcircuit. The input of one or more XOR trees is the initial input of the adder and multiplier or the carry signal of the internal 1-bit adder. Based on one or more XOR trees, the correct carry signal can be derived, so that one or more XOR trees can be connected together to form a XOR forest. As an example, a XOR forest is also considered to be a 1-bit adder graph. The construction of the 1-bit adder graph according to the exemplary embodiment is Figure 5 Shown in.

[0098] Figure 6 A flow chart of a reverse engineering technique according to an example embodiment is shown. The example method shown in Table 600 includes: identifying or determining multiple 2-input XOR subcircuits; establishing one or more XOR trees; determining a carry signal; connecting multiple XOR trees to form an XOR forest such as a 1-bit adder graph; determining the logic function of an arithmetic macro and the circuit boundary of the arithmetic macro based on the 1-bit adder graph. In an example embodiment, after forming or constructing a 1-bit adder graph (also called an XOR forest), the XOR forest is used to determine arithmetic logic functions such as addition, subtraction, and multiplication, as well as more complex arithmetic logic (such as a combination of adders and multipliers (e.g., (a+b)×c, a×b+c×d, etc.)).

[0099] Return to Figure 3 , block 310 detects HT by comparing the first arithmetic macro with the second arithmetic macro.

[0100] In an exemplary embodiment, the process as described in block 310 is considered global HT localization because it globally determines in which region or regions the HT is located. In another exemplary embodiment, to improve the efficiency of globally localizing one or more HTs, a pruning technique is applied to the process.

[0101] For example, using pruning techniques, equivalent subcircuit pairs can be identified and stripped from the circuit, with all HTs existing only inside non-equivalent subcircuit regions. As an example, if the first part of the first circuit and the second part of the second circuit are an equivalent subcircuit pair, the first part and the second part have the same function, or they are functionally equivalent. If the first part and the second part have different functions, they are functionally non-equivalent rather than an equivalent subcircuit pair. As another example, a first arithmetic macro consists of part A1 and part B1, and a second arithmetic macro consists of part A2 and part B2. Part A1 and part A2 are functionally equivalent, and part B1 and part B2 are functionally non-equivalent. As an example, A2 is removed from the second arithmetic macro so that the HT is determined to be located in B2 of the second arithmetic macro.

[0102] As an example, Figures 7A-7C A diagram illustrating a pruning process according to an example embodiment is shown. Fig. 7A A check netlist 710 (or second netlist) containing HT is shown. The netlist 710 being checked includes a portion 714 having a 6-XOR subcircuit (i.e., implementing a 6-input XOR function) and a portion 712 indicating other portions of the netlist 710 being checked. Figure 7B A standard or correct netlist 720 (or first netlist) is shown. The standard netlist 720 includes a portion 724 having a 6-XOR subcircuit and other portions 722 indicative of the standard netlist 720. The portions 714 and 724 have the same function or are functionally equivalent, but have different implementation styles.

[0103] like Figure 7C As shown, the equivalent pairs (portion 714 and portion 724) are trimmed or stripped from the corresponding netlist to obtain a pruned netlist 730. In an exemplary embodiment, the pruning or stripping process is repeatedly performed to minimize the non-equivalent circuit portions. In another exemplary embodiment, the pruning or stripping process is iteratively performed until no equivalent subcircuit pairs or equivalent pairs are found between the check netlist 710 and the standard netlist 720.

[0104] Return to Figure 3 , block 312 uses a functional engineering change (ECO) engine to locate HTs in the second netlist.

[0105] As an example, an ECO engine or technique is applied to locate and mask the HT.

[0106] Block 314 uses the ECO engine to mask the HT by adding patches in the second netlist, thereby improving the security of the arithmetic circuit.

[0107] As an example, the ECO engine represents a set of inputs (PI) in the circuit as a set of Boolean variables X = {x1, ..., xn}. F(X) = {f1(X), f2(X), ..., fm(X)} represents the logic function in the second netlist; G(X) = {g1(X), g2(X), ..., gm(X)} represents the logic function in the first netlist.

[0108] For a pair of logic function fi and gi in the check netlist and the standard netlist, the diff-set represents a set of circuit inputs under which the functions fi and gi have opposite values ​​and is defined as follows:

[0109]

[0110] The ECO engine minimizes the diff-set of each function pair by incrementally adding patch logic or circuits until all diff-sets are empty, which means that the checked function has the same logical function as the standard function, that is, HT has been completely cleared. In an exemplary embodiment, patch logic is continuously inserted into the circuit to minimize the diff-set.

[0111] For example, for an internal signal r in a circuit to be patched, assuming that the function of r is t(X), the function corresponding to PO is fi and the function value is affected by the r signal, the care-set of r is defined as follows:

[0112]

[0113] Care-set represents a set of circuit inputs under which any change in signal r can be observed at output function fi. In an exemplary embodiment, all circuit inputs are divided into two partitions according to the inclusion relationship between diff-set and care-set:

[0114] (i) care-out-diff: a set of circuit inputs for which the value of care-set is 1 and the circuit input is not included in the diff-set. And:

[0115] (ii) care-in-diff: a set of circuit inputs that are included in both the care-set and the diff-set.

[0116] As an example, if the value of the function fi in care-out-diff is changed, the diff-set will be enlarged, thereby increasing the harm of HT. Therefore, the patch function p(X) that attempts to eliminate HT must satisfy the following constraints:

[0117]

[0118] On the other hand, to minimize the diff-set, we need to change the value of t in care-in-diff:

[0119]

[0120] Therefore, if p(X) and diff-set satisfy the following conditions,

[0121]

[0122] This means

[0123]

[0124] Then p(X) can completely clear diffi(X) and complete the golden function gi. Specifically, for example, when r = PO i hour, is always satisfied, which means that a patch function can be found that satisfies the constraint equation (8), which completely empties diffi(X) and completes the golden function gi (e.g., gi is directly used as a patch function).

[0125] Figures 8A-8B A patch function creation diagram according to an exemplary embodiment is shown. Fig. 8A A graph 810 before patching is shown. Graph 810 includes care-set 812 and diff-set 814 with overlap 816 (ie, care-in-diff). Care-set 812 that does not include care-in-diff 816 is care-out-diff. Figure 8B A graph 820 after adding the patch function is shown. The area of ​​the diff-set in the graph 820 is reduced, indicating that the impact and harm caused by HT are also relatively reduced.

[0126] As an example, the constraints Equations (6-8) are considered when creating a patch or patch function. If the signal r drives only a single output, the corresponding patch function must satisfy Equations (6) and (7). In an example embodiment, in order to enhance the possibility of creating a valid patch while avoiding an exhaustive search, the method proposes to generate two types of patch schemes: conservative patches and aggressive patches.

[0127] Figures 9A-9B A conservative class patch generated according to an exemplary embodiment is shown. Fig.9A A care-set and diff-set area graph 910 is shown before creating a patch. Fig. 9B An area graph 920 is shown after the patch is created.

[0128] In the strategy of generating conservative patches, the patch generated at signal r will ensure that the diff-set area corresponding to any PO is not increased. Therefore, the conservative patch satisfies constraint equation (6) for all POs. For example, a subset of POs is selected from the PO set {PO1, PO2, ..., POm}. The subset {POi1, POi2, ..., POil} is called the improved PO set. The patch function created at r satisfies constraint equation (7). In other words, for each PO in the set, constraint equation (7) is satisfied. For example, as the logic patching proceeds, the selection of POs and the size of the improved PO set are dynamically adjusted. The smaller the size of the improved PO set, the easier it is to create a satisfactory patch.

[0129] like Figures 9A-9B As shown, the patch generated by 9B can minimize the area of ​​the diff-set.

[0130] Figures 10A-10B A schematic diagram of generating an aggressive class patch according to an exemplary embodiment. Fig. 10A A care-set and diff-set area graph 1010 is shown before generating an aggressive class patch. Fig. 10B An area graph 1020 is shown after the aggressive class patches are generated.

[0131] As an example, the diff-set at the output signal o1 is completely eliminated (or improved), while the diff-set area at the output signal o2 is enlarged (deteriorated). In one example, the PO set is divided into three subsets:

[0132] (i) Ignore the set: The diff-set of the POs in the set is not considered during the process of generating the patch function, and in an exemplary embodiment, the diff-set of such POs may become worse after the patch function is generated.

[0133] (ii) No Change Set: The diff-set of the POs in this set will not change. In an exemplary embodiment, the difference set of the POs in this set will not improve either. For each PO in this set, equation (6) is satisfied. POs that have been fixed in previous iterations (e.g., their diff-sets are empty) will be assigned to this set so that they will not become unfixed again.

[0134] (iii) Improved set: The diff-set of POs in this set is improved by the created patch. It satisfies the constraints Equations (6) and (7). In addition, for at least one PO in this set, constraint Equation (8) is satisfied, which means that the created patch function can completely eliminate at least one HT.

[0135] like Figures 10A-10BAs shown, the HT of o1 can be completely eliminated while the diff-set of o2 can be expanded.

[0136] In an exemplary embodiment, an example method includes using a functional engineering change (ECO) engine to improve the efficiency of locating HT in a netlist. The example method first generates conservative class patch candidates and aggressive class candidates, and then selects the candidate with a smaller size as the actual patch circuit.

[0137] In some exemplary embodiments, the patch circuit is optimized by using logic rewiring technology to minimize the patch circuit and improve circuit performance. As an example, the patch optimization process includes Add-First rewiring transformation and Cut-First rewiring transformation.

[0138] Figures 11A-11B is a schematic diagram of an Add-first rewiring transformation according to an exemplary embodiment. Fig.11A The circuit diagram 1110 in shows the patch circuit before the Add-First rewiring transformation; Fig. 11B Circuit diagram 1120 in shows the patch circuit after the Add-First rewiring transformation.

[0139] As shown in the figure, for the Add-First rewiring transformation, a redundant connection 1112 is first added to the patch circuit (e.g., the connection line from g5 to g9 in the figure). Then, several connection lines and logic gates (e.g., g4, g6, and g7) become redundant logic and can be removed. The circuit after removal is as follows: Fig. 11B As shown. It can be seen that the size of the optimized patch circuit is greatly reduced. The detailed implementation of this rewiring transformation is described in the paper "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal" written by LA Entrena and K.-T Cheng (published in the 1995 IEEE transaction on Computer-Aided Design Conference).

[0140] Figures 12A-12B Schematic diagram of a Cut-First rewiring transformation according to an exemplary embodiment. Fig. 12A The circuit diagram 1210 in FIG. 1 is a patch circuit before rewiring conversion; Fig. 12B Diagram of the patch circuit after rewiring conversion.

[0141] like Fig. 12AAs shown in the Cut-First rewiring conversion method, the wire from b to g6 is first removed, and then by adding additional logic at g8 and g9, the converted logic function can be kept unchanged, while the converted patch circuit only needs fewer logic gates and connecting wires. The converted circuit is as follows Fig. 12B As shown. The implementation of the Cut-First rewiring transformation is described in detail in the paper "ECR: a lowcomplexity generalized error cancellation rewiring scheme" by Xiao Qing Yang, Tak-Kei Lam, and Yu-Liang Wu, which was published in the Proceedings of the 47th Design Automation Conference in 2010. For example, to design a series of Internet of Things (IoT) chips with slight differences, assuming that each chip takes 3 months to complete the placement and routing process, the existing method requires 3+3=6 months to complete the design of two chips. In contrast, the example method according to some example embodiments completes the same task in 3 months + 10 minutes.

[0142] Fig.13 1300 shows a table of arithmetic macromodules that can be obtained according to an exemplary embodiment. In table 1300, B in the "Style" column represents a Booth multiplier and NB represents a non-Booth multiplier. As shown, in addition to the basic multiplier, some more complex arithmetic macromodules (see the "Function" column in table 1300) also exist in the benchmark.

[0143] In Table 1300, the first column is the name of the case suite. Each suite includes 13 test circuits that implement similar arithmetic functions but have different bit widths of operands. The example extracted arithmetic logic and its design style and bit width of operands are shown in columns 3-5. The example method can successfully extract the vast majority (97%) of the arithmetic macromodules, with only suites ut36 and hid10 failing. In the case of successful extraction of arithmetic logic, exemplary formal verification techniques can be used with the functional ECO engine to detect whether one or more HTs are present in the circuit. For example, each of these benchmarks is a gate-level (GTL) combinational circuit that includes arithmetic logic. Example reverse engineering techniques are used to locate arithmetic logic from a flat circuit (such as a "sea of ​​gates") without knowing the component input / output (I / O) and boundaries. Table 1300 shows that formulas were successfully extracted using the example method.

[0144] Fig.14 A table comparing the results according to the example methods is shown.

[0145] In Table 1400, the first three columns show the basic information of the test cases. Each case has two circuits g1 and g2, which have logical differences. As an example, g1 is a circuit that has been tampered with by HT, and g2 is a standard or correct circuit. The next 4 columns show the size of the patch circuits generated using the two example methods and the time used to generate the patch circuits. The last two columns show the number of patch circuits and the size of the patch circuits at runtime using two example methods (i.e., Example Method 1 and Example Method 2). As shown in the figure, the patch circuit generated by the example method can be reduced by 40% and the running time is reduced by 86%.

[0146] Fig.15 A computer system or electronic system according to an exemplary embodiment is shown. Computer system 1500 includes one or more computers or electronic devices (e.g., one or more servers) 1510, which includes a processor or processing unit 1512 (such as one or more processors, microprocessors and / or microcontrollers), one or more component computer readable media (CRM) or memory 1514, and a circuit safety enhancer 1518.

[0147] The memory 1514 stores instructions that, when executed, cause the processor 1512 to perform the methods discussed herein and / or one or more blocks discussed herein. The circuit safety enhancer 1518 is an example of specialized hardware and / or software that helps improve the performance of a computer and / or perform the methods discussed herein and / or one or more blocks discussed herein. Figure 3 Discuss example functionality of a circuit safety enhancer.

[0148] In an example embodiment, computer system 1500 includes memory or storage 1530 , a portable electronic device or PED 1540 that communicates via one or more networks 1520 .

[0149] The memory 1530 may include one or more memories or databases storing one or more of image files, audio files, video files, software applications, and other information discussed herein. As an example, the memory 1530 stores images, instructions, or software applications retrieved by the server 1510 via the network 1520 so that the methods discussed herein and / or one or more blocks discussed herein are performed.

[0150] PED 1540 includes a processor or processing unit 1542 (such as one or more processors, microprocessors and / or microcontrollers), one or more components of computer readable media (CRM) or memory 1544 , one or more displays 1546 , and a circuit safety enhancer 1548 .

[0151] PED 1540 can perform the methods discussed herein and / or one or more blocks discussed herein and display images or files (e.g., netlists) for viewing. Alternatively or additionally, PED 1540 can retrieve files such as images and files and software instructions from memory 1530 via network 1520 and perform the methods discussed herein and / or one or more blocks discussed herein.

[0152] In an example embodiment, computer system 1500 includes a PED 1550 that includes a processor or processing unit 1552 (such as one or more processors, microprocessors and / or microcontrollers), one or more components 1554 of computer readable media (CRM) or memory, and one or more displays 1556.

[0153] As an example, PED 1550 communicates with server 1510 and / or memory 1530 via network 1520 so that the methods discussed herein and / or one or more blocks discussed herein are executed by server 1510 and the results are sent back to PED 1550 for output, storage and review.

[0154] The network 1520 may include a cellular network, a public switched telephone network, the Internet, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), a home area network (HAM), and other public and / or private networks. In addition, the electronic devices do not need to communicate with each other through a network. As an example, the electronic devices may be coupled together via one or more lines (e.g., a direct wired connection). As another example, the electronic devices may communicate directly via a wireless protocol such as Bluetooth, near field communication (NFC), or other wireless communication protocols.

[0155] In some exemplary embodiments, the methods described herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as non-transitory computer-readable and / or machine-readable storage media, physical or tangible media, and / or temporary storage media. These storage media include different forms of memory, including semiconductor memory devices such as DRAM or SRAM, erasable and programmable read-only memory (EPROM), electrically erasable and programmable read-only memory (EEPROM) and flash memory; disks such as fixed and removable disks; other magnetic media including tapes; optical media such as compact disks (CDs) or digital versatile disks (DVDs). Note that the instructions of the above software can be provided on a computer-readable or machine-readable storage medium, or can be provided on multiple computer-readable or machine-readable storage media distributed in a large system with possibly multiple nodes. Such computer-readable or machine-readable media are considered to be part of an article (or manufactured article). An article or article of manufacture can refer to a single component or multiple components of a manufacture.

[0156] The blocks and / or methods discussed herein may be executed on the processors, controllers, and other hardware discussed herein. In addition, the blocks and / or methods discussed herein may be automatically executed with or without user instructions.

[0157] In another aspect of the present invention, a method and apparatus for transforming circuit functionality is disclosed.

[0158] When an IC chip is designed, the design follows a specific specification. However, in many cases, the design must be revised to another specification at some point after the initial design. Revisions can be made for a variety of reasons, such as detecting errors that affect circuit operation or reliability, meeting new requirements, or improving performance by reducing the use of resources used to perform a function, adding new features, or performing a function using another method.

[0159] Changes to be made to an existing design are called engineering changes (ECOs). ECOs work by adding patch circuits to the original specifications to produce transformed specifications for the circuit. ECOs can be performed manually or using automated ECO tools, but existing ECO tools do not produce optimized ECO results and may therefore affect the characteristics and performance of the circuit. This impact may be sufficient to prevent the circuit from meeting performance, safety, or usage requirements.

[0160] In other embodiments, a method for transforming circuit functionality is disclosed. Fig.16 In the method 1600, a first register transfer level (RTL) file is provided for a circuit in block 1602. The first RTL file has an original specification or implementation, which is the circuit before any engineering changes are made.

[0161] In block 1604, a second RTL file is provided for the circuit, the second RTL file having the revised specification. Since the revised specification is designed by the user, the second RTL file is known and can be provided. In a preferred embodiment, both the first and second RTL files are golden specifications.

[0162] In block 1606, a first gate-level (GTL) netlist is generated or synthesized from the first RTL file. In block 1608, a second GTL netlist is generated or synthesized from the second RTL file. The netlist may be a synthesized netlist or a placed and routed netlist.

[0163] In block 1610, the first RTL document is compared with the second RTL document. By comparing the RTL documents, instances to be modified can be extracted and identified. In general, only a portion of the instance is modified and the rest remains unchanged, because certain functions of the initial design are retained to make the ECO effective and efficient. In this way, the comparison step eliminates unnecessary instances to be ECOed, thereby minimizing the modified instances, thereby optimizing the operation of the ECO or functional transformation. As in the context of this specification, instances include module ports, sequential instances, and signals.

[0164] In block 1612, instances to be modified in the first RTL document are located in the first GTL netlist. Based on the located instances, modules in the first GTL netlist to be ECOed are identified. In one embodiment, modules to be patched by ECOs are defined as a first module list, and modules not affected by ECOs or retained in ECO operations are defined as a second module list. By retaining the second module list that is not patched, resource usage of the ECO engine can be reduced, and the ECO process can be completed faster.

[0165] In block 1614, ECO is performed on the first module list. The ECO engine first refers to the second GTL netlist to determine how the module should be patched, and then applies the ECO patch circuit to the first module list to transform the circuit function so that the first GTL netlist after ECO is equivalent or the same as the second GTL netlist, which also means that the patched circuit is functionally equivalent to the revised design. In one embodiment, the implementation of the necessary changes may include at least one of rewiring, rewriting, technology mapping, cut and clear, and any other logic synthesis technology.

[0166] In other embodiments, a hardware description language (HDL) is used to further specify the instances to be modified in the first GTL netlist. The HDL can be used to specify the signals that need to be modified in the first netlist and can also identify the corresponding signals in the second GTL netlist. This allows the computer system to further optimize the ECO process when the location of the instances in the first RTL document is not ideal.

[0167] In other embodiments, the modules to be modified in the first netlist are determined by iteration. First, a first set of modules is identified as the modules in which the instances to be modified reside. Next, the first set of modules is traversed forward and backward, identifying all other modules affected by the patch circuit. These other modules are defined as a second set of modules. The traversal process is repeated using the newly affected modules identified as input, and the iteration ends when no more affected modules are found.

[0168] In other embodiments, the multi-bit registers in the first netlist are retained in the ECO process. In existing ECO technology, multi-bit registers are only treated as multiple separate unit registers. These multi-bit registers are generally split into unit registers when their functions need to be modified. However, this type of modification causes significant changes in circuit characteristics, such as logical characteristics and physical characteristics. By retaining multi-bit registers, even if functions such as clock functions, clock gating functions or data functions must be modified, changes in circuit characteristics are minimized and formal verification checks are allowed.

[0169] Fig.17 A diagram 1700 is shown illustrating an example method of generating a netlist to be patched according to an example embodiment.

[0170] Reference Fig.17 , the old RTL document 1701 is a document describing the original specification, wherein the original specification is the definition and requirement about the circuit design before any ECO process. The old synthesis netlist 1702 is the netlist after the synthesis of the old RTL document 1701. The old post-APR netlist 1703 is the netlist after the old synthesis netlist 1702 is placed and routed. In an example embodiment, the old synthesis netlist 1702 and the old post-APR netlist 1703 are also referred to as "old netlists" individually or collectively.

[0171] The new RTL file 1704 is a document describing the revised specification, wherein the revised specification is about the circuit design after the ECO process, that is, the definition and requirements of the target circuit design. The new synthesis netlist 1705 is the netlist after the new RTL file 1704 is synthesized.

[0172] In the method shown in Figure 1700, first, an old RTL document 1701 and a new RTL document 1704 are generated to describe the original specification and the revised specification respectively. The old RTL document 1701 and the new RTL document 1704 are further synthesized into an old synthesis netlist 1702 and a new synthesis netlist 1705. Then, the old RTL document 1701 and the new RTL document 1704 are compared to generate an ECO netlist 1706. The ECO netlist 1706 is a list of modules that need to be repaired in the original circuit design. After repairing the module list, the repaired old netlist is functionally equivalent to the new RTL netlist 1704.

[0173] In an exemplary embodiment, old synthesized netlist 1702 is a GTL netlist generated from old RTL document 1701. New synthesized netlist 1705 is a GTL netlist generated from new RTL document 1704.

[0174] In an example embodiment, depending on the implementation of the engineering change, a patch circuit is applied to the old synthesis netlist 1702 or the old post-APR netlist 1703 to make the old netlist functionally equivalent to the new RTL netlist 1704 .

[0175] In one example embodiment, the old RTL document 1701 and the new RTL document 1704 are compared to identify signals that need to be modified in the old synthesis netlist so that the revised specification can be implemented. The identified signals to be modified allow for the minimum amount of changes to modify the old netlist to the new netlist.

[0176] In one example embodiment, a hardware description language (HDL) is used to further fine-tune the signals to be modified. The signals in the old synthesis netlist 1702 whose functions need to be changed and the corresponding signals in the new synthesis netlist 1705 are respectively specified in the HDL. This information will then be used to further precisely locate the signals to be modified in the old synthesis netlist 1702.

[0177] In an example embodiment, the signals to be modified are searched in the old netlist (the old synthesis netlist 1702 or the old post-APR netlist 1703, as required). These signals may reside in one or more modules. We refer to this group of modules as the first group of modules. Since the initial set of signals to be modified may affect other signals before or after it, the set of signals to be modified may be larger than the initial set.

[0178] In one embodiment, the fan-in and fan-out cones of the signals to be modified are established, and a first list of modules that need to be patched is recursively identified in the fan-in and fan-out cones of the signals to be modified. As the modules affected by the ECO are traversed, the list of signals to be modified is automatically populated. All other sub-modules that are not affected by the modification are identified as a second list of modules and will not be modified. Afterwards, the new netlist is analyzed and used as a reference to make necessary and accurate changes (i.e., patch circuits) in the old netlist.

[0179] In one example embodiment, multi-bit registers in the old netlist are retained during the implementation of the necessary changes. Even if their functions (clock functions, clock gating functions, or data functions) must be modified, the multi-bit registers are not divided into single-bit registers. This allows for minimal changes in the logical and physical characteristics of the circuit. In addition to minimizing the disturbance to the circuit characteristics, this approach also facilitates formal verification checks.

[0180] In one example embodiment, the repair / modification is implemented by performing an engineering change. The implementation of the engineering change may involve rewiring, rewriting, technology mapping, cut and remove, and / or any other logic synthesis technique.

[0181] In one example embodiment, the circuits referred to herein are arithmetic circuits.

[0182] By adopting the above steps, the present invention effectively verifies the ECO results, makes small fixes and minimal changes to circuit characteristics, and reduces calculation time.

[0183] Fig.18 A diagram 1800 is shown illustrating an example method of obtaining instances, module ports, and signals to be patched in a circuit according to an example embodiment.

[0184] exist Fig.18 In the example, an old RTL document 1801 and a new RTL document 1802 are generated to describe the original specification and the revised specification, i.e., the target specification, respectively. Then, the old RTL document 1801 and the new RTL document 1802 are input into a formal verification tool 1803 for verification. The formal verification tool 1803 compares the old RTL document 1801 and the new RTL document 1802, and indicates with high precision at which point there is a difference between the old RTL document 1801 and the new RTL document 1802. Finally, the formal verification tool 1803 outputs a module port 1804 to be modified, a sequence instance 1805 to be modified, and / or a signal to be modified.

[0185] In an example embodiment, the formal verification tool 1803 is a logic equivalence checking (LEC) tool that exhaustively verifies the GTL, which is much faster than traditional gate-level simulation and can reduce the risk of missing critical errors through independent verification techniques.

[0186] Fig.19 A diagram 1900 is shown illustrating an example of an ECO process according to an example embodiment.

[0187] exist Fig.19 In the figure, non-equivalent module ports 1901, non-equivalent sequential instances 1902, old synthesis netlist 1903, old post-APR netlist 1904 and new synthesis netlist 1905 are provided to ECO tool 1906 to generate ECO netlist 1907, wherein non-equivalent module ports 1901 and non-equivalent sequential instances 1902 are generated by comparing the old RTL document with the new RTL document.

[0188] In another aspect of the present invention, a method and apparatus for transforming the functionality of a circuit is disclosed, particularly a method and apparatus for transforming the functionality of a programmable circuit such as an FPGA. As an example, an FPGA is an efficient implementation medium for prototyping and verification of SoC designs, and it is also a cheaper option for smaller quantities of electronic products and achieves shorter turnaround times.

[0189] In many cases, a circuit design must be revised to another specification at some point after the initial design or after physical layout and routing (P&R). There may be many reasons for the revision, such as detecting errors that affect circuit operation or reliability or problematic functionality caused by some maliciously injected hardware trojan (HT) circuits, meeting new requirements, or improving performance by reducing resource usage used to perform functions, adding new features, or performing functions in another way. As described above, in addition to generating and inserting a repair circuit patch to implement a design change (i.e., ECO) in the circuit design, the patch can also be used to mask and eliminate problematic (buggy) functionality caused by some maliciously injected HT circuits. For clarity, "buggy" refers to an error, defect, or vulnerability in a hardware or software program that interferes with the expected results of the program.

[0190] However, the current design flow for programmable circuits (e.g., FPGAs) contains certain flow differences compared to the design flow for non-programmable circuits (e.g., ASICs). For example, in development cycles where functional ECO iterations need to be frequently called, it takes longer and it is difficult to eliminate HT in completed designs. In the embodiments discussed in detail below, methods and systems can reduce the time spent on ECO iterations in building programmable circuit prototypes (e.g., FPGAs) and minimize the allocated programmable circuit chip area after adding patch circuits that eliminate ECO / HT. This solution can be used to both speed up the ECO process and eliminate HT in programmable designs.

[0191] To simplify the description, ASIC circuit design is used as an example of non-programmable circuits, and FPGA circuit design is used as an example of programmable circuits. It should be understood that other existing or future non-programmable or programmable circuits may also be applicable.

[0192] In the case where the problematic (i.e., old) design has completed the placement and routing stage, the ECO and HT elimination process may be different and difficult under the FPGA design flow compared to the ASIC design flow. In contrast, if the user needs to modify the function of the ASIC circuit design that has completed physical placement and routing, it can be processed as follows according to some embodiments: (a) modify the problematic old RTL document to generate a corrected new RTL document; (b) synthesize the new RTL document to generate a new netlist; (c) compare the new netlist with the implemented old netlist that has completed placement and routing, and generate a "repair circuit patch" to be inserted into the old netlist to make its function the same as the corrected new netlist, and then complete the ECO process.

[0193] On the other hand, if the user needs to modify the function of the FPGA design that has completed placement and routing, the ECO design iteration involves the following process: (a) modify the problematic old RTL document to generate a corrected new RTL document; (b) synthesize the new RTL document to generate a new netlist; (c) perform technology mapping on the entire new netlist, where the new netlist will be mapped to a K-input lookup table (LUTK), where the LUTK can be used to implement any K-input function, which can also be called a lookup table (Truth Table); (d) re-place and route the entire LUTK; (e) recompile the design into a bitstream; (f) reprogram the FPGA using the bitstream. That is, since the old netlist has been converted into the LUTK mapping format, the netlist-to-netlist operation technology cannot be performed in this case. Therefore, in each ECO iteration for the completed placement and routing, the work done is almost the same as repeating the entire FPGA design process from scratch, and the efficiency of ECO is not satisfactory. Even if only one line in the old RTL file is changed, each ECO iteration for an FPGA chip with, say, 0.5M LUT6s can take tens of hours, not to mention that contemporary FPGA chips can hold millions of LUT6s. Without further modification, this FPGA flow may not achieve the intended goal of capturing and eliminating hidden HT in the old design.

[0194] FIG. 20A to FIG. 20B A diagram showing a legacy netlist and its corresponding ECOed netlist in a non-programmable ASIC or chip according to an example embodiment. Fig. 20A Figure 2010 in FIG. 2 shows an old netlist of an ASIC containing 3 cells. The old netlist has 4 inputs {a, b, c, d} and the function result is at output f. Fig. 20B Figure 2020 in FIG. 1 shows an ECO netlist of an ASIC containing 5 cells. The ECO netlist also has 4 inputs {a, b, c, d}, and the function result is at the output f'. A patch circuit 2021 has been inserted to make the functions of the two ASICs the same. The patch circuit 2021 can be generated or produced in the manner described above.

[0195] Figures 21A-21B A diagram showing an old netlist and its corresponding ECOed netlist in a programmable circuit or chip according to an example embodiment is shown. Fig.21A Figure 2110 in Figure 2110 shows the old netlist of the FPGA containing LUT4. Fig. 20A For the same function in ASIC, the old netlist of FPGA uses LUT4. Fig. 21B As shown in Figure 1, after patching the circuit, the ECO netlist of the FPGA can still use LUT4. Unlike ASIC design, since LUT4 can implement any 4-input function regardless of its complexity, Fig. 21B As shown, when two functions are merged into the same set of supported variables (e.g., {a, b, c, d}) in the same LUT4, if the IO pin connections of the LUT4 do not change, it will not lead to an increase in the silicon area allocated to the FPGA, and even no incremental placement and routing is required.

[0196] To fully exploit the free merge cost characteristics of the LUT structure, a good remapping algorithm can successfully merge the patch circuit into the existing allocated LUTK even without a large amount of incremental placement and routing work, and can greatly save precious runtime and area loss (even timing).

[0197] In some embodiments, a method performed by a computer system to transform the function of a programmable circuit to improve the circuit function and the performance of the computer system is disclosed. Fig. 22 In the method 2200, in block 2202, a LUT-mapped circuit representation derived from a programmable circuit is provided, wherein the programmable circuit has been implemented using a first RTL file. The first RTL file may be an original specification of the circuit before any engineering change (ECO) request is accepted.

[0198] In this embodiment, the first RTL document has been implemented in the programmable circuit. For example, its physical layout and routing have been completed in the FPGA, which means that the first RTL document has been converted into a LUT-mapped format. Therefore, the LUT-mapped circuit representation for the programmed circuit can be retrieved and made available in various ways. As an example, the LUT-mapped circuit representation can include a bit mask for each LUT and / or a functional expression for each LUT.

[0199] However, this initial design may have issues or be affected by HT, or for some other reason, it may require an ECO design iteration to transform the functionality of the FPGA according to the revised specifications.

[0200] In block 2204, a second RTL file of the programmable circuit is provided. The second RTL file may be a revised specification that is modified from the original specification and has functions transformed from the original specification. Since the revised specification is designed by the user, the second RTL file is known and can be provided.

[0201] In block 2206, the LUT-mapped circuit representation is converted to a shadow netlist, where the shadow netlist corresponds to a gate-level (GTL) netlist representing the provided LUT-mapped circuit representation.

[0202] According to one embodiment, the bit mask of each 6-input LUT is recorded. In addition, the simplest logical expression corresponding to the bit mask of all 6-input LUTs is also recorded. In this way, the function of each LUT in the LUT mapping circuit representation can be easily mapped to its corresponding shadow netlist in linear time, and the shadow netlist is an equivalent gate-level circuit.

[0203] In block 2208, a second GTL netlist is generated or synthesized from the second RTL document. It should be understood that although the above operations or method steps are described in a specific order, these operations do not necessarily have to be performed in the above specific order. For example, some operations can be performed in a multi-tasking manner or in parallel.

[0204] In block 2210, at least one engineering change (ECO) patch circuit is generated to be fully merged in the LUT-mapped circuit representation based on the comparison of the shadow netlist with the second GTL netlist, so that when the LUT-mapped circuit representation is patched with the generated ECO patch circuit, it can perform the same function as the second GTL netlist. This LUT-directed ECO process exploits the free (logic) merge cost characteristics of the LUT structure to maximize the benefits of any FPGA design cost target.

[0205] The following exemplary LUT-directed ECO implementation achieves minimization of allocated silicon area and development cycle time, according to some embodiments. Fig.23 An example process 2300 of LUT-directed ECO according to an embodiment is shown. At 2302, a comparison operation between a shadow netlist and a new netlist (i.e., a second GTL netlist) may be performed in the manner described above. For example, the result generated by comparing the shadow netlist with the second GTL netlist may include a module or a list of modules to be ECOed together with a corresponding ECO patch circuit (hereinafter referred to as "ECO patch circuit") in the LUT-mapped circuit representation. The result generated by comparing the shadow netlist with the second GTL netlist may also include the location of an insertion point in the LUT-mapped circuit representation, at which the corresponding ECO patch circuit should be inserted. At 2304, locate or identify the LUT containing the insertion point in the LUT-mapped circuit representation to insert its corresponding patch circuit.

[0206] It is then determined whether the generated patch circuit is ideal for the ECO. As an example, at 2306, it is determined whether the generated patch circuit can be completely merged into the LUT containing the insertion point. If so, the LUT-directed ECO process is completed and the ECO patch circuit is identified as the ECO patch circuit to be merged. The generated patch circuit is identified as the ECO patch circuit for this ECO design iteration. In this case, the LUT mapping circuit representation with the merged patch circuit will be equivalent to the second GTL netlist to perform the same function, so that the programmable circuit can be reprogrammed according to the revised specification. At this point, the merged LUT mapping diagram will represent functionality that is completely equivalent to the new netlist, that is, the HTs that have been completed or hidden by the ECO are all eliminated.

[0207] In another embodiment, if the generated patch circuit can be completely merged into an unallocated empty or spare LUT or in more than one unallocated empty or spare LUT, the LUT-directed ECO process can also be considered completed, and the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging. The generated patch circuit is identified as the ECO patch circuit of the ECO design iteration. In this way, it achieves cost-effectiveness in terms of time and allocated silicon area. That is, as an example, process 2300 may further include determining at 2308 whether the generated patch circuit can be completely merged into one or more empty spare LUTs. If so, the LUT-directed ECO process is completed.

[0208] On the other hand, if the generated patch circuit cannot be completely merged into the LUT containing the insertion point or one or more unassigned empty LUTs, at 2310, a disjoint support decomposition (DSD) process can be applied to the patch function corresponding to the patch circuit. Disjoint support decomposition is an inherent operation of Boolean logic synthesis. Given a Boolean function F(x1, x2, ..., x n ), F can often be represented by simpler and decomposed component functions.

[0209] According to some embodiments, a patch function is applied to certain disjoint support decompositions. At least one of the decomposed sub-patch functions has a variable support that is a subset of the variable support of the LUT containing the insertion point. In some embodiments, the subset of variable support can be as large as possible. Then, at 2312, the sub-patch function is merged into the LUT containing the insertion point. The shadow netlist and the LUT mapping circuit representation are updated accordingly at 2314, and the process returns to 2302 to generate a second (i.e., new) patch circuit to be inserted into the LUT mapping circuit representation based on the comparison of the updated shadow netlist with the second GTL netlist until no more ECO patch circuits are needed.

[0210] It should be understood that although the process 2300 is described in a specific order, the operations must not necessarily be performed in the specific order described above. For example, determinations 2306 and 2308 may be performed in a multi-tasking manner or in parallel, or only one of the two may be performed in the process 2300.

[0211] return Fig. 22 , block 2212 indicates that the functionality of the programmable circuit is transformed by merging the ECO patch circuit into the LUT mapped circuit representation. The merged LUT mapped circuit representation is equivalent to the second GTL netlist to perform the same functionality, thereby enabling the programmable circuit to be reprogrammed according to the revised specification by utilizing the free merge cost characteristic of the LUT structure.

[0212] According to some embodiments, the functional transformation of the FPGA also includes performing placement and routing, recompiling the design into a bitstream, and reprogramming the circuit using the bitstream. In one embodiment, incremental placement and routing can be used. Since in most cases, ECO only involves a small portion of logic, this incremental process takes only a small amount of time compared to performing technology mapping on the entire new netlist and redoing the entire placement and routing for LUTK. Specifically, incremental placement and routing is applied, a new bitstream is generated based on the new placement and routing results; and then the programmable circuit is reprogrammed using the new bitstream.

[0213] Other embodiments provide corresponding computer systems for transforming the functionality of programmable circuits to improve circuit functionality.

[0214] Methods according to example embodiments are provided as examples, and examples from one method should not be construed as limiting examples from another method. Figures and other information show example data and example structures; other data and other database structures can be implemented with example embodiments. In addition, methods discussed in different figures can be added to or exchanged with methods in other figures. In addition, specific numerical data values ​​(e.g., specific quantities, amounts, categories, etc.) or other specific information should be construed as illustrations for discussing example embodiments. Such specific information is not provided to limit example embodiments.

[0215] As used herein, the term "hardware Trojan" (HT) refers to an unauthorized or unintended change, modification, insertion, or implantation of a circuit. HT may cause circuit failure, reduce reliability, lead to leakage of confidential information, etc.

[0216] As used herein, the term "arithmetic circuit" refers to a circuit in which one or more portions of a circuit are used to perform operations such as addition, subtraction, multiplication, and any other arithmetic operations.

[0217] As used herein, the term "netlist" refers to logic gates in a circuit and the connection relationships between them.

[0218] As used herein, the term "macro" or "arithmetic macro" refers to a collection of multiple logic cells or standard cells that constitute a specific component in a circuit (e.g., an IC). Specific components include, but are not limited to, adders, multipliers, multiplexers (MUXs), etc.

[0219] As used herein, the term "sub-circuit" refers to the term "macro", and the two terms may be used interchangeably.

[0220] As used herein, the term "2-input exclusive OR (XOR) subcircuit" refers to a subcircuit having 2 input signals and 1 output signal. The function of the output signal is an exclusive OR function of the two input signals.

[0221] As used herein, the term "XOR tree" refers to a subcircuit consisting of one or more 2-input XOR subcircuits and their connections.

[0222] As used herein, the term "1-bit adder" refers to a 1-bit half adder and / or a 1-bit full adder.

[0223] As used herein, the term "1-bit half adder" refers to an arithmetic macro with 2 inputs (e.g., a and b) and 2 outputs (e.g., sum and co). "co" may also be referred to as "carry". The function of sum is the "exclusive or" function of a and b; the function of co is the "sum" function of a and b.

[0224] As used herein, the term "1-bit full adder" refers to an arithmetic macro with 3 inputs (e.g., a, b, and c) and 2 outputs (e.g., sum and co). "co" may also be referred to as "carry". The function of sum is the "exclusive or" function of a, b, and c; the function of co is the "majority vote" function of a, b, and c.

[0225] As used herein, the term "1-bit adder diagram" refers to a subcircuit consisting of one or more 1-bit adders and their connections.

[0226] As used herein, the term "XOR forest" refers to the term "1-bit adder graph", and the two terms may be used interchangeably.

[0227] As used herein, the term "reverse engineering (RE)" refers to the process of extracting arithmetic macros from a circuit. The RE process includes identifying a 2-input exclusive-OR (XOR) subcircuit, an XOR tree, a 1-bit adder, a 1-bit adder graph, and arithmetic macros.

[0228] As used herein, the term "exponential time" refers to the fact that the running time for an algorithm increases exponentially with the number of input signals to the algorithm (e.g., 2 n ), where n is the number of input signals to the algorithm.

[0229] As used herein, the term "polynomial time" means that the running time for an algorithm increases polynomially with the number of input signals to the algorithm.

[0230] As used herein, the term "linear time" means that the running time of an algorithm increases linearly with the number of input signals to the algorithm.

Claims

1. A method for transforming the function of a programmable circuit to improve the function of the circuit, performed by a computer system, the method comprising: providing a lookup table (LUT) mapping circuit representation derived from a programmable circuit implemented using a first register transfer level (RTL) file, the first RTL file having an original specification; Providing a second RTL document of the programmable circuit, the second RTL document having a revised specification, wherein the revised specification is modified from the original specification and has a function transformed from the original specification; converting the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a gate-level GTL netlist representing the LUT mapped circuit representation; generating a second GTL netlist from the second RTL document; generating at least one engineering change ECO patch circuit to be fully merged into the LUT mapped circuit representation based on a comparison of the shadow netlist and the second GTL netlist; as well as The computer system and the ECO engine transform the function of the programmable circuit by merging the at least one ECO patch circuit into the LUT mapping circuit representation, wherein the merged LUT mapping circuit representation is equivalent to the second GTL netlist to perform the same function, thereby enabling the programmable circuit to be reprogrammed according to the revised specification by utilizing the free merge cost characteristics of the LUT structure.

2. The method according to claim 1, wherein the generating step comprises: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be fully incorporated into the LUT containing the insertion point; as well as In response to determining that the ECO patch circuit can be completely merged into the LUT containing the insertion point, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT mapped circuit representation.

3. The method according to claim 2, wherein the generating step further comprises: In response to determining that the ECO patch circuit cannot be completely merged into the LUT containing the insertion point, determining whether the ECO patch circuit can be merged into one or more empty LUTs; and In response to determining that the ECO patch circuit can be merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

4. The method according to claim 2, wherein the generating step further comprises: In response to determining that the ECO patch circuit cannot be fully incorporated into the LUT containing the insertion point, applying disjoint support decomposition to a function of the ECO patch circuit to decompose at least one sub-patch function, wherein the at least one sub-patch function decomposed has a variable support that is a subset of a variable support of a LUT containing the insertion point; Merging the at least one sub-patch function into a LUT containing the insertion point; updating the LUT mapped circuit representation and the shadow netlist; and New ECO patch circuits to be patched into the updated LUT-mapped circuit representation are obtained iteratively by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch circuits are needed.

5. The method of claim 1, wherein the generating step comprises: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be completely incorporated into one or more empty LUTs; as well as In response to determining that the ECO patch circuit can be completely merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

6. The method according to claim 1, wherein the converting step further comprises: Record each possible LUT6 bit mask and the corresponding simplest logical expression; as well as The function of each LUT in the LUT mapping circuit representation is mapped into its equivalent subcircuit to obtain a corresponding shadow netlist.

7. The method according to claim 1, further comprising: Apply incremental placement and routing; Generate a new bitstream based on the new placement and routing results; as well as The programmable circuit is reprogrammed using the new bit stream.

8. A computer system for transforming the function of a programmable circuit to improve the function of the circuit, the computer system comprising: Hardware processor; A non-transitory computer-readable storage medium having stored therein instructions that, when executed, cause the hardware processor to: Obtaining a lookup table (LUT) mapping circuit representation from a programmable circuit implemented using a first register transfer level RTL file, the first RTL file having an original specification; Obtaining a second RTL document of the programmable circuit, wherein the second RTL document is a revised specification, wherein the revised specification is modified from the original specification and has a function transformed from the original specification; converting the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a gate-level GTL netlist representing the LUT mapped circuit representation; generating a second GTL netlist from the second RTL document; generating at least one engineering change ECO patch circuit to be fully merged into the LUT mapped circuit representation based on a comparison of the shadow netlist and the second GTL netlist; as well as The function of the programmable circuit is transformed together with the ECO engine by merging the at least one ECO patch circuit into the LUT mapping circuit representation, wherein the merged LUT mapping circuit representation is equivalent to the second GTL netlist to perform the same function, thereby enabling the programmable circuit to be reprogrammed according to the revised specification by utilizing the free merge cost characteristics of the LUT structure.

9. The system of claim 8, wherein the instructions, when executed, further cause the processor to: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be fully incorporated into the LUT containing the insertion point; as well as In response to determining that the ECO patch circuit can be completely merged into the LUT containing the insertion point, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT mapped circuit representation.

10. The system of claim 9, wherein the instructions, when executed, further cause the processor to: In response to determining that the ECO patch circuit cannot be fully incorporated into the LUT containing the insertion point, determining whether the ECO patch circuit can be incorporated into one or more empty LUTs; and In response to determining that the ECO patch circuit can be merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

11. The system of claim 9, wherein the instructions, when executed, further cause the processor to: In response to determining that the ECO patch circuit cannot be fully incorporated into the LUT containing the insertion point, Applying disjoint support decomposition to the function of the ECO patch circuit to decompose at least one sub-patch function, wherein, The at least one sub-patch function being decomposed has a variable support that is a subset of a variable support of a LUT containing the insertion point; Merging the at least one sub-patch function into a LUT containing the insertion point; updating the LUT mapping circuit representation and the shadow netlist; as well as New ECO patch circuits to be patched into the updated LUT-mapped circuit representation are obtained iteratively by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch circuits are needed.

12. The system of claim 8, wherein the instructions, when executed, further cause the processor to: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be completely incorporated into one or more empty LUTs; as well as In response to determining that the ECO patch circuit can be completely merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

13. The system of claim 8, wherein the instructions, when executed, further cause the processor to: Record each possible LUT6 bit mask and the corresponding simplest logical expression; and The function of each LUT in the LUT mapping circuit representation is mapped into its equivalent subcircuit to obtain a corresponding shadow netlist.

14. The system of claim 8, wherein the instructions, when executed, further cause the processor to: Apply incremental placement and routing; generating a new bitstream based on the new placement and routing results; and The programmable circuit is reprogrammed using the new bit stream.

15. A computer-implemented method for improving circuit function iteration to transform the function of a programmable circuit, the method comprising: receiving a lookup table (LUT) mapping circuit representation originating from a programmable circuit implemented using a first register transfer level (RTL) file, the first RTL file having an original specification; receiving a second RTL document of the programmable circuit, the second RTL document having a revised specification, wherein the revised specification is modified from the original specification and has a function transformed from the original specification; converting the LUT mapped circuit representation into a shadow netlist, the shadow netlist corresponding to a gate-level GTL netlist representing the LUT mapped circuit representation; generating a second GTL netlist from the second RTL document; generating at least one engineering change ECO patch circuit to be fully merged into the LUT mapped circuit representation based on a comparison of the shadow netlist and the second GTL netlist; as well as The computer system and the ECO engine transform the function of the programmable circuit by merging the at least one ECO patch circuit into the LUT mapping circuit representation, wherein the merged LUT mapping circuit representation is equivalent to the second GTL netlist to perform the same function, thereby enabling the programmable circuit to be reprogrammed according to the revised specification by utilizing the free merge cost characteristics of the LUT structure.

16. The method of claim 15, wherein the generating step comprises: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be completely incorporated into one or more empty LUTs; as well as In response to determining that the ECO patch circuit can be completely merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

17. The method of claim 16, wherein the generating step further comprises: In response to determining that the ECO patch circuit cannot be completely merged into the LUT containing the insertion point, determining whether the ECO patch circuit can be merged into one or more empty LUTs; as well as In response to determining that the ECO patch circuit can be merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

18. The method of claim 17, wherein the generating step further comprises: In response to determining that the ECO patch circuit cannot be fully incorporated into the LUT containing the insertion point, applying disjoint support decomposition to a function of the ECO patch circuit to decompose at least one sub-patch function, wherein the at least one sub-patch function decomposed has a variable support that is a subset of a variable support of a LUT containing the insertion point; Merging the at least one sub-patch function into a LUT containing the insertion point; updating the LUT mapped circuit representation and the shadow netlist; and New ECO patch circuits to be patched into the updated LUT-mapped circuit representation are obtained iteratively by comparing the updated shadow netlist with the second GTL netlist until no more ECO patch circuits are needed.

19. The method of claim 15, wherein the generating step comprises: comparing the shadow netlist and the second GTL netlist to obtain an ECO patch circuit for at least one module to be ECOed and an insertion point in a LUT mapping circuit representation corresponding to the ECO patch circuit; locating a LUT containing the insertion point in the LUT-mapped circuit representation to insert the ECO patch circuit; determining whether the ECO patch circuit can be completely incorporated into one or more empty LUTs; as well as In response to determining that the ECO patch circuit can be completely merged into one or more empty LUTs, the ECO patch circuit is identified as an ECO patch circuit to be prepared for merging into the LUT-mapped circuit representation.

20. The method of claim 15, wherein the converting step further comprises: Record each possible LUT6 bit mask and the corresponding simplest logical expression; as well as The function of each LUT in the LUT mapping circuit representation is mapped into its equivalent subcircuit to obtain a corresponding shadow netlist.

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