Multi-bit semiconductor memory cells, memory arrays, and methods of operating the same

Abstract

The application provides a multi-bit semiconductor memory unit, a memory array and an operating method thereof, wherein the multi-bit semiconductor memory unit comprises a pinned diode, a control transistor and a floating diffusion region, and the pinned diode is used for storing charges; wherein the pinned diode is composed of an N-well region and a P-type surface doping region of a photodiode, or composed of a P-well region and an N-type surface doping region of a photodiode. In the application, the N-well region of the photodiode or the P-well region of the photodiode is used as a storage charge unit. In the multi-bit semiconductor memory unit provided by the application, the amount of charges that can be stored by the storage unit is determined by the amount of dopants, and therefore the storage amount is controllable.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and in particular to a multi-bit semiconductor memory cell, a memory array, and a method for operating the same. Background Technology

[0002] Semiconductor memory is a type of storage unit that distinguishes logical states by determining the amount of stored charge. It is characterized by low cost and simple structure, and often occupies a large density in chip design. With the continuous development of semiconductor technology, chip design has become increasingly complex, leading to ever-larger storage spaces. In some practical applications, the area occupied by memory can even reach one-third of the total wafer area.

[0003] Therefore, reducing chip area translates to increased profit, and this is also true for memory technology. Minimizing the footprint of memory cells presents significant profit potential in chip design and has been a long-standing research focus.

[0004] Furthermore, in existing technologies, the storage capacitor of dynamic memory is led out through contact holes, and the interface between the contact holes and the substrate causes significant leakage current. Additionally, the thermal noise (KT / C) of the resistor contributes significantly to the noise, which is inversely proportional to the capacitance. Due to these two constraints, the memory cell capacitor must be made to approximately 20pF.

[0005] However, since the capacitance of a storage cell is positively correlated with its area, this constraint prevents the storage capacitor from being made smaller (i.e., the area cannot be made smaller), and the system also requires continuous signal refresh and writing to prevent the loss of stored charge, making the system more complex.

[0006] Therefore, a method to reduce leakage current and noise is crucial for storage technology. Summary of the Invention

[0007] The purpose of this invention is to provide a multi-bit semiconductor memory cell, a memory array, and its operation method, thereby solving the technical problem that memory occupies a large chip area in the prior art.

[0008] To address the aforementioned technical problems, the present invention provides a multi-bit semiconductor memory cell, comprising:

[0009] Pinned diodes, control transistors, and floating diffusion regions are used to store charge using the pinned diodes;

[0010] The pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, or a P-well region and an N-type surface-doped region of a photodiode.

[0011] Preferably, the P-type surface doped region of the pinned diode is adapted to prevent charges generated by substrate interface defects from entering the N-well region of the photodiode.

[0012] Preferably, the N-type surface doped region is adapted to prevent holes generated by substrate interface defects from entering the P-well region of the photodiode.

[0013] Preferably, a first control gate of the control transistor is further disposed between the pinned diode and the floating diffusion region. The first control gate is located between the photodiode and the floating diffusion region and controls the opening and closing of the path between the pinned diode and the floating diffusion region. The floating diffusion region is suitable as a buffer for signal reading or storage and is connected to the level input terminal.

[0014] Preferably, the pinned diode is further provided with a second control gate of the control transistor, the second control gate being located between the first control gate and the photodiode, and controlling the opening and closing of the passage between the pinned diode and the floating diffusion region.

[0015] Preferably, the second control gate portion is located above the photodiode.

[0016] Preferably, at least two of the multi-bit semiconductor memory cells share a floating diffusion region.

[0017] Preferably, the photodiode is provided with a light shielding structure, which is suitable for shielding the photodiode from light signal sensing when the multi-bit semiconductor memory cell is being read or written.

[0018] Preferably, the amount of charge written into the N-well or P-well region of the photodiode is greater than 100e.

[0019] Preferably, by increasing the depth of the N-well or P-well region of the photodiode, the full-well capacity of the N-well or P-well region of the photodiode is increased, thereby improving the number of resolvable bits of the multi-bit semiconductor memory cell.

[0020] The technical solution provided by the present invention also includes a multi-bit semiconductor memory cell, which includes: a pinned diode, a control transistor and a floating diffusion region, and uses the pinned diode to store charge;

[0021] The pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, or is composed of a P-well region and an N-type surface-doped region of a photodiode.

[0022] A first control gate and a second control gate of the control transistor are also provided between the pinned diode and the floating diffusion region. The first control gate is located between the photodiode and the floating diffusion region and controls the opening and closing of the path between the pinned diode and the floating diffusion region.

[0023] The floating diffusion area is suitable as a buffer for signal reading or storage and is connected to the level input terminal;

[0024] The second control gate is disposed between the first control gate and the photodiode, and controls the opening and closing of the passage between the pinned diode and the floating diffusion region;

[0025] The reading or writing process of the multi-bit semiconductor memory cell is realized by controlling the opening and closing of the first control gate and / or the second control gate in a timing manner.

[0026] The technical solution provided by this invention also includes an operation method for a multi-bit semiconductor memory cell, providing the multi-bit semiconductor memory cell as described above, comprising:

[0027] When the pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, the second control gate is connected to a positive voltage during data storage to passivate surface defects and further reduce leakage current.

[0028] When the pinned diode is composed of the P-well region of a photodiode and the N-type surface-doped region, the second control gate is connected to a negative voltage during data storage to passivate surface defects and further reduce leakage current.

[0029] The technical solution provided by this invention also includes an operation method for a multi-bit semiconductor memory cell, providing the multi-bit semiconductor memory cell as described above.

[0030] During the writing process, the first control gate is turned off first, and then the second control gate is turned off, in order to ensure that the signal is completely written.

[0031] During the readout process, the second control gate is turned off first, and then the first control gate is turned off, in order to prevent electron backflow.

[0032] The technical solution provided by this invention also includes a multi-bit semiconductor memory cell, comprising:

[0033] Read / write circuitry and the multi-bit semiconductor memory cell described above;

[0034] The read / write circuit includes:

[0035] A write transistor is used to connect the control signal and the floating diffusion region, which is suitable for writing the control signal into the floating diffusion region;

[0036] A reset transistor, connected to a reset voltage and the floating diffusion region, is adapted to reset the control of the floating diffusion region;

[0037] The follower transistor is connected to the drain of the row selection transistor and a constant high level potential, and its gate is connected to the floating diffusion region, which is suitable for converting the signal of the floating diffusion region to the output terminal.

[0038] A row selection transistor, connected to the follower transistor and the signal acquisition terminal, is adapted to read the row selection of the control signal.

[0039] The technical solution provided by this invention also includes a multi-bit semiconductor memory cell, comprising: a read / write circuit and the multi-bit semiconductor memory cell as described above;

[0040] The read / write circuit includes:

[0041] A write transistor is used to connect the control signal and the floating diffusion region, which is suitable for writing the control signal into the floating diffusion region;

[0042] A reset transistor, connected to a reset voltage and the floating diffusion region, is adapted to reset the control of the floating diffusion region;

[0043] The follower transistor is connected to the drain of the row selection transistor and a constant high level potential, and its gate is connected to the floating diffusion region, which is suitable for converting the signal of the floating diffusion region to the output terminal.

[0044] A row selection transistor, connected to the follower transistor and the signal acquisition terminal, is adapted to read the row selection of the control signal;

[0045] The signal acquisition terminal is connected to an external ramp circuit, which is suitable for reading signals through a correlated double sampling method to eliminate KT / C noise.

[0046] The technical solution provided by this invention also includes an operation method for a multi-bit semiconductor memory cell: providing the multi-bit semiconductor memory cell as described above, wherein the data writing process of the multi-bit semiconductor memory cell includes:

[0047] The data signal is divided into data packets, and the length of each data packet is equal to the maximum number of bits that a semiconductor memory cell can store.

[0048] The data packets are converted into data packet voltages, where each data packet voltage corresponds to the amount of charge that a multi-bit semiconductor memory cell needs to store;

[0049] Turn on the write transistor to transmit the data packet voltage to the floating diffusion region;

[0050] Turn on the control transistor to transmit the data packet voltage to the N-well or P-well region of the photodiode;

[0051] When the write transistor and control transistor are turned off, the write data is stored in the N-well or P-well region of the photodiode.

[0052] The technical solution provided by this invention also includes a method for operating a multi-bit semiconductor memory cell, comprising:

[0053] The multi-bit semiconductor memory cell described above is provided, and the data readout process of the multi-bit semiconductor memory cell includes:

[0054] A positive reset voltage is provided to turn on the row select transistor, and the reset transistor is turned on. The reset voltage will then be transmitted to the floating diffusion region.

[0055] When the reset transistor is turned off, the voltage across the ramp circuit and the signal acquisition terminal is compared. When the voltages are equal, the first voltage collected at this time is recorded.

[0056] Keep the row selection transistor on, turn on the control transistor, so that the charge stored in the N-well region or P-well region of the photodiode is transferred to the floating diffusion region, thereby changing the voltage of the floating diffusion region;

[0057] Turn off the control transistor, compare the voltage across the ramp circuit and the signal acquisition terminal, and record the second voltage collected at this time when the voltages are equal;

[0058] By comparing the difference between the first voltage and the second voltage, the signal stored in each multi-bit semiconductor memory cell can be obtained.

[0059] Preferably, the data readout process of the multi-bit semiconductor memory cell includes:

[0060] A positive reset voltage is provided to turn on the row select transistor, and the reset transistor is turned on. The reset voltage will then be transmitted to the floating diffusion region.

[0061] Turn off the reset transistor;

[0062] Keep the row selection transistor on, turn on the control transistor, so that the charge stored in the N-well region or P-well region of the photodiode is transferred to the floating diffusion region, thereby changing the voltage of the floating diffusion region;

[0063] Turn off the control transistor and record the voltage collected at this time to obtain the signal stored in each multi-bit semiconductor memory cell.

[0064] The technical solution provided by this invention also includes a multi-bit semiconductor memory array, comprising:

[0065] A multi-row multi-bit semiconductor memory cell, wherein each row of multi-bit semiconductor memory cells includes at least two groups of multi-bit semiconductor memory cells;

[0066] Each group of the multi-bit semiconductor memory cells includes: a read / write circuit and at least two pixel cells. The read / write circuit includes: a write transistor, a reset transistor, a follower transistor, and a row select transistor. Each pixel cell includes: a pinned diode, a control transistor, and a floating diffusion region. The pinned diode is composed of: an N-well region of a photodiode and a P-type surface doped region, or a P-well region of a photodiode and an N-type surface doped region.

[0067] In this configuration, the pixel units in each group of multi-bit semiconductor memory cells share a common drive, while the gate potentials of the control transistors are controlled separately.

[0068] In each row of the multi-bit semiconductor memory cell, the control transistors in the corresponding order of the pixel cells in different groups share a gate potential, and the write transistor, the reset transistor, and the row selection transistor in each row of the multi-bit semiconductor memory cell each share a gate potential.

[0069] Preferably, all rows of multi-bit semiconductor memory cells share the ground potential, reset potential, and drain potential of the follower transistor.

[0070] The technical solution provided by this invention also includes an operation method for a multi-bit semiconductor memory array as described above, wherein non-row data can be read or written simultaneously; row data cannot be read and written simultaneously.

[0071] Preferably, it includes:

[0072] The first cycle performs data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row;

[0073] In the second cycle, data is written to the multi-bit semiconductor memory cell in the (n+1)th row. At this time, the (n+2)th row is split into data segments.

[0074] In the third cycle, the multi-bit semiconductor memory cell in row n+1 is reset by FD voltage. At this time, data is written to row n+2 and data is split in row n+3.

[0075] In the fourth cycle, data is read from the multi-bit semiconductor memory cell in row n+1. At this time, FD voltage is reset in row n+2, data is written in row n+3, and data is segmented in row n+4.

[0076] n is an integer greater than zero.

[0077] Preferably, the step of performing data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row in the first cycle includes: the signal data is segmented into data packets by the circuit and converted into data packet voltages for each column of multi-bit semiconductor memory cells in this row, and each data packet voltage corresponds to the amount of charge to be stored in a multi-bit semiconductor memory cell.

[0078] Preferably, the step of writing data to the multi-bit semiconductor memory cell in the (n+1)th row in the second cycle includes: turning on the write transistor, so that the data packet voltage is transmitted to the floating diffusion region of each column respectively; turning on the control transistor, so that the data packet voltage is transmitted from the floating diffusion region to the N-well region or P-well region of the corresponding photodiode; turning off the write transistor and the control transistor, so that the signal is stored.

[0079] Preferably, the step of resetting the floating diffusion region voltage of the multi-bit semiconductor memory cell in the (n+1)th row in the third cycle includes: the reset voltage is positive, the row selection transistor is turned on, the reset transistor is turned on, the reset voltage is transmitted to the floating diffusion region of each column, the reset transistor is turned off, and the first reference voltage Vref collected at this time is recorded.

[0080] Preferably, the step of reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle includes: keeping the row selection transistor on, turning on the control transistor, so that the charge stored in the N-well region or P-well region of the photodiode will be transferred to its corresponding floating diffusion region to change its voltage, turning off the control transistor, and recording the second reference voltage collected at this time; comparing the difference between the first reference voltage and the second reference voltage can obtain the signal stored in each multi-bit semiconductor memory cell.

[0081] Preferably, the step of reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle includes: keeping the row selection transistor on, turning on the control transistor, so that the charge stored in the N-well or P-well region of the photodiode will be transferred to its corresponding floating diffusion region to change its voltage, turning off the control transistor, and recording the signal stored in the multi-bit semiconductor memory cell corresponding to the voltage collected at this time.

[0082] Compared with the prior art, the multi-bit semiconductor memory cell, memory array, and operation method provided in the technical solution of the present invention have the following beneficial effects:

[0083] 1. In the embodiments provided in the technical solution of the present invention, a pinned diode is used to store charge, which can achieve precise control of the amount of charge. Furthermore, multiple binary bits can be identified based on the amount of electrons stored in the N-well region or the amount of holes stored in the P-well region of the pinned diode (i.e., the charge stored in the N-well region or P-well region of the photodiode) and a pre-defined correspondence, enabling a single memory to store multiple binary bits. When the same number of bits needs to be stored, the number of memory cells is greatly reduced, that is, the area used by the memory cells is also greatly reduced.

[0084] 2. In the embodiments provided in the technical solution of the present invention, the electronic readout accuracy can be controlled with high precision. With the same full-well capacity, the higher the electronic readout accuracy, the more bits can be resolved, and the greater the memory area saved.

[0085] 3. In the embodiments provided in the technical solution of the present invention, pinned diodes are used as storage cells to store charge, reducing the electrons generated at the interface between SiO2 and Si. Measurements show that the leakage current of the storage cell is approximately 1E-15A / µm. 2 The existing storage unit is approximately 1E-12A / um. 2 In the embodiments provided by the present invention, the leakage current of the storage cell is 2-3 orders of magnitude smaller than that of storage cells in the prior art. Because the leakage current of the storage cell is significantly reduced, the capacitance of the storage cell can be reduced to approximately 0.4 WF. Since the capacitance of the storage cell is positively correlated with its area, the technical solution provided by the present invention can further reduce the area occupied by the storage cell.

[0086] 4. In the embodiments provided in the technical solution of the present invention, multiple multi-bit semiconductor memory cells share the same write transistor. Reading uses a ramp circuit with a correlated double sampling method to process the signal, eliminating the influence of KT / C noise and allowing the capacitance of a single multi-bit semiconductor memory cell to be smaller. Simultaneously, using multiple groups (generally more than 32) of photodiodes sharing the FD reduces KT / C noise caused by the write transistor during the writing process and saves area.

[0087] 5. In the embodiments provided in the technical solution of the present invention, the control transistor of the storage unit is provided with a first control gate and a second control gate. The signal readout and write process can be optimized by controlling the timing of the first control gate and the second control gate. Specifically, during the data storage period, the second control gate is partially located on the photodiode. For an n-type photodiode, the second control gate can be connected to a positive voltage to passivate surface defects and further reduce leakage current. During the write process, the first control gate can be turned off first and then the second control gate can be turned off to prevent the signal from not being completely written. During the readout process, the second control gate can be turned off first and then the first control gate can be turned off to prevent electron backflow. Attached Figure Description

[0088] Figure 1 This is a schematic diagram of the storage unit structure provided in one embodiment of the present invention;

[0089] Figure 2 This is a schematic diagram of a storage cell structure provided in one embodiment of the present invention;

[0090] Figure 3 This is a schematic diagram of a storage cell structure provided in one embodiment of the present invention;

[0091] Figure 4 This is a schematic diagram of a storage cell structure provided in another embodiment of the present invention;

[0092] Figures 5 to 6 This is a schematic diagram of the structure of a multi-bit semiconductor memory array provided in one embodiment of the present invention;

[0093] Figure 7 for Figures 5 to 6 A timing diagram illustrating the read / write method of the provided multi-bit semiconductor memory array. Detailed Implementation

[0094] Numerous specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0095] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are merely examples for ease of explanation and should not limit the scope of protection of the present invention.

[0096] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the multi-bit semiconductor memory cell, memory array and its operation method of the present invention will be described in detail below with reference to the accompanying drawings.

[0097] In this invention, a multi-bit semiconductor memory cell is provided, comprising:

[0098] The device comprises a pinned diode, a control transistor, and a floating diffusion region, wherein the pinned diode is used for charge storage; wherein the pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, or a P-well region and an N-type surface-doped region of a photodiode.

[0099] For a specific embodiment, please refer to Figure 1 As shown, Figure 1 The memory cell structure provided in this embodiment includes: a P-type silicon substrate 1; a floating N-well region 3 of the memory; a P-type isolation region 2 of the floating N-well region 3 of the memory; a P-type surface-doped region 4 of the floating N-well region 3 of the memory; a first control gate 5; and a signal floating region 6 (floating diffusion region). The floating N-well region 3 and the P-type silicon substrate 1 constitute a photodiode, and together with the P-type surface-doped region 4, they form a pinned diode. The floating N-well region 3 serves as the charge storage region in the multi-bit semiconductor memory cell provided in this embodiment.

[0100] In a specific embodiment, the P-type surface doped region 4 of the pinned diode is adapted to prevent charges generated by substrate interface defects from entering the floating N-well region 3 of the photodiode.

[0101] In a specific embodiment, a control transistor is further provided between the pinned diode and the floating diffusion region (signal floating region 6). The control transistor includes a first control gate 5, which is located between the photodiode and the floating diffusion region, and controls the opening and closing of the path between the pinned diode and the floating diffusion region (signal floating region 6).

[0102] The floating diffusion area (signal floating area 6) is suitable as a buffer area for signal reading or storage and is connected to the level input terminal.

[0103] In a specific embodiment, a light-shielding structure is provided for the photodiode, which is suitable for shielding the photodiode from light signal sensing when the multi-bit semiconductor memory cell is being read and written.

[0104] In a specific embodiment, the amount of charge written into the N-well region (floating N-well region 3) of the photodiode is greater than 100e.

[0105] In a specific embodiment, by increasing the depth of the N-well region of the photodiode, the full-well capacity of the N-well region of the photodiode is increased, thereby improving the number of resolvable bits of the multi-bit semiconductor memory cell.

[0106] Another specific embodiment is referenced. Figure 2 As shown, Figure 2 The memory cell structure provided in this embodiment includes: a P-type silicon substrate 1; a P-type isolation region 2 of the floating n-well of the memory; a floating n-well region 3 of the memory; a surface-doped region 4 of the floating n-well region of the memory; a first control gate 5; a second control gate 5'; and a signal floating region 6. The floating n-well region 3 and the P-type silicon substrate 1 constitute a photodiode, and the addition of the P-type surface-doped region 4 forms a pinned diode.

[0107] In a specific embodiment, the P-type surface doped region 4 of the pinned diode is adapted to prevent charges generated by substrate interface defects from entering the N-well region of the photodiode.

[0108] In a specific embodiment, a control transistor is further provided between the pinned diode and the floating diffusion region. The control transistor includes a first control gate 5, which controls the opening and closing of the path between the pinned diode and the floating diffusion region.

[0109] The floating diffusion area is suitable as a buffer for signal reading or storage and is connected to the level input terminal.

[0110] In a specific embodiment, the pinned diode is further provided with a second control gate 5' of the control transistor. The second control gate 5' is located between the first control gate 5 and the photodiode, controlling the opening and closing of the path between the pinned diode and the floating diffusion region, and simultaneously affecting the effect of the surface doped region 4. Preferably, the second control gate 5' is partially located above the photodiode.

[0111] In other specific embodiments, the photodiode's doped well region is P-type, and the surface doped region is N-type. That is, the pinned diode consists of a P-well region and an N-type surface doped region of the photodiode. See further details below. Figure 1 and Figure 2 The N-type and P-type doped regions are swapped. (For further reference...) Figure 1 The memory cell structure provided in this embodiment includes: an N-type silicon substrate 1; an N-type isolation region 2 of a floating P-well for the memory; a floating P-well region 3 of the memory; a surface-doped region 4 of the floating P-well region of the memory; a first control transistor 5; and a signal floating region 6. The floating P-well region 3 and the N-type silicon substrate 1 constitute a photodiode, and together with the N-type surface-doped region 4, they form a pinned diode.

[0112] If you continue to refer to Figure 2The memory cell structure provided in this embodiment includes: an N-type silicon substrate 1; an N-type isolation region 2 of a floating P-well; a floating P-well region 3 of the memory; a surface-doped region 4 of the floating P-well region; a first control transistor 5; a second control transistor 5'; and a signal floating region 6. The floating P-well region 3 and the N-type silicon substrate 1 constitute a photodiode, and together with the N-type surface-doped region 4, they form a pinned diode.

[0113] In a specific embodiment, the N-type surface doped region is adapted to prevent holes generated by substrate interface defects from entering the P-well region of the photodiode.

[0114] In a specific embodiment, at least two of the multi-bit semiconductor memory cells share a floating diffusion region. Preferably, more than 32 of the memory cells share a floating diffusion region, thereby saving area.

[0115] In a specific embodiment, a light shielding structure is also provided for the photodiode, which is suitable for shielding the photodiode from light signal sensing when the multi-bit semiconductor memory cell is performing read and write operations.

[0116] In a specific embodiment, the amount of charge written into the N / P well region (floating N / P well region 3) of the photodiode is greater than 100e.

[0117] In a specific embodiment, by increasing the depth of the N / P well region (floating N-well region 3) of the photodiode, the full-well capacity of the N / P well region (floating N / P well region 3) of the photodiode is increased, thereby improving the number of resolvable bits of the multi-bit semiconductor memory cell.

[0118] The design features of this invention are as follows:

[0119] In this invention, the N / P well region of a pinned diode is used as the charge storage unit. The amount of charge stored is determined by the doping dose, and therefore the storage capacity of the storage unit can be controlled by adjusting the doping dose. Furthermore, multiple binary bits can be identified based on the amount of charge in the N / P well region. Specifically, the correspondence between the read charge and the stored information can be predetermined. For example, reading an electron / hole count between 0 and 99 represents 0000, between 100 and 199 represents 0001, between 200 and 299 represents 0010, and so on, with an electron / hole count between 1500 and 1599 representing 1111. Thus, a full-well capacity of 1600 can have 16 positions, storing 4 bits of data, significantly reducing the number of storage units and the area used. Because the leakage current of the storage unit in this invention is very small, each position can even distinguish approximately 10 electron / holes, meaning a storage unit with a full-well capacity of 1200 can have up to 120 positions.

[0120] The characteristic of this method is that, according to the agreed correspondence, a single memory is not limited to storing 3 binary bits: the higher the precision control of electron / hole readout, the more bits can be resolved for the same full-well capacity, and the greater the memory area saved.

[0121] In a preferred embodiment, the full-well capacity can be increased by increasing the depth of a single-layer N / P well or by increasing the number of N / P wells to multiple layers, thereby further increasing the number of bits that the memory cell can resolve.

[0122] In a preferred embodiment, a P / N type surface doped region is added above the floating N / P well region of the memory to prevent charges generated by defects at the Si-SiO2 interface from entering the floating N / P well region, thereby improving the electronic storage accuracy within the floating N / P well region.

[0123] The floating diffusion region FD serves as a buffer for signal reading or storage.

[0124] The control transistor Tx controls the opening and closing of the path between the N-well region or P-well region of the photodiode and the floating diffusion region FD. In a preferred embodiment, the control transistor Tx may have two gates, namely a first control gate and a second control gate.

[0125] The reading or writing process of the multi-bit semiconductor memory cell is realized by controlling the opening and closing of the first control gate and the second control gate in a timing manner.

[0126] The present invention also provides a method for operating a multi-bit semiconductor memory cell, comprising: providing the multi-bit semiconductor memory cell as described above.

[0127] When the pinned diode is composed of the N-well region and the P-type surface-doped region of the photodiode, during data storage, the second control gate is positively voltage-passivated to passivate surface defects, which is suitable for further reducing leakage current.

[0128] Embodiments of the present invention also provide an operation method for a multi-bit semiconductor memory cell, wherein the multi-bit semiconductor memory cell described above is provided.

[0129] During the writing process, the first control gate is turned off first, and then the second control gate is turned off, in order to ensure that the signal is completely written.

[0130] During the readout process, the second control gate is turned off first, and then the first control gate is turned off, in order to prevent electron backflow.

[0131] refer to Figure 3 As shown, the technical solution of the present invention also provides a multi-bit semiconductor memory cell, comprising:

[0132] Read / write circuitry and the multi-bit semiconductor memory cell described above;

[0133] The read / write circuit includes:

[0134] A write transistor Wx is connected to the floating diffusion region FD (the drain terminal of the control transistor Tx) and a control signal Vw. The source terminal of the control transistor Tx is connected to a pixel unit. The write transistor Wx is adapted to write the control signal into the floating diffusion region FD.

[0135] The reset transistor Rx is connected to the reset voltage Vr and the floating diffusion region FD, and is adapted to reset the control of the floating diffusion region FD;

[0136] The follower transistor SF is connected to the drain terminal of the row selection transistor Sx and the constant high level terminal DVDD. The gate of the follower transistor SF is connected to the floating diffusion region FD, which is suitable for converting the signal of the floating diffusion region FD to the output terminal. The constant high level terminal DVDD and the reset voltage Vr can be connected to the same potential.

[0137] The row selection transistor Sx is connected to the follower transistor SF and the signal acquisition terminal, and is adapted to read the row selection of the control signal.

[0138] Preferably, the signal acquisition terminal is externally connected to a ramp circuit, which is suitable for reading the signal through a correlated double sampling method to eliminate KT / C noise.

[0139] refer to Figure 4 ,exist Figure 3 Based on this, the source terminal of the write transistor Wx (i.e., the floating diffusion region FD, the drain terminal of the control transistor Tx) can be connected in parallel with multiple control transistors Tx (TX11…TX1n) and the pixel unit connected to the other end of the control transistor Tx, that is, TX11 to TX1n share the drive of the follower transistor SF. Similarly, the drain terminal DVDD of the follower transistor SF and the reset voltage Vr can be connected to the same potential.

[0140] The technical solution of the present invention also provides Figure 3 The following describes an operation method for a multi-bit semiconductor memory cell:

[0141] The multi-bit semiconductor memory cell described above is provided, wherein the data writing process of the multi-bit semiconductor memory cell includes:

[0142] The data signal is divided into data packets, and the length of each data packet is equal to the maximum number of bits that a semiconductor memory cell can store.

[0143] The data packet is converted into a data packet voltage Vw, where each data packet voltage Vw corresponds to the amount of charge that a multi-bit semiconductor memory cell needs to store;

[0144] Turn on the write transistor Wx to transmit the data packet voltage Vw to the floating diffusion region FD;

[0145] Turn on the control transistor Tx to transmit the data packet voltage Vw to the floating n-well region;

[0146] When the write transistor Wx and the control transistor Tx are turned off, the written data is stored in the floating n-well region.

[0147] In one specific embodiment of the readout process, the data readout process of the multi-bit semiconductor memory cell includes:

[0148] A positive reset voltage is provided to turn on the row selection transistor Sx and the reset transistor Rx. The reset voltage will then be transmitted to the floating diffusion region FD.

[0149] When the reset transistor Rx is turned off, the voltage across the ramp circuit and the signal acquisition terminal is compared. When the voltages are equal, the first voltage collected at this time is recorded.

[0150] Keep the row selection transistor Sx on, turn on the control transistor Tx, so that electrons in the N-well region or holes in the P-well region of the photodiode can be transferred into the floating diffusion region FD, causing the voltage FD of the floating diffusion region to decrease or increase.

[0151] When the control transistor Tx is turned off, the voltage across the ramp circuit and the signal acquisition terminal is compared. If the voltages are equal, the second voltage collected at this time is recorded.

[0152] By comparing the difference between the first voltage and the second voltage, the signal stored in each multi-bit semiconductor memory cell can be obtained.

[0153] In another specific embodiment of the readout process, the data readout process of the multi-bit semiconductor memory cell includes:

[0154] A positive reset voltage is provided to turn on the row selection transistor Sx and the reset transistor Rx. The reset voltage will then be transmitted to the floating diffusion region FD.

[0155] Turn off the reset transistor Rx;

[0156] Keep the row selection transistor Sx on, turn on the control transistor, and allow the charge stored in the floating n-well region to be transferred to the floating diffusion region, thereby reducing the voltage of the floating diffusion region;

[0157] Turn off the control transistor and record the voltage collected at this time to obtain the signal stored in each multi-bit semiconductor memory cell.

[0158] When the data in the storage cell is read out, the charge stored in the N-well or P-well region of the photodiode is cleared, and the stored signal is lost. Therefore, the stored data needs to be rewritten every unit of time.

[0159] The technical solution of the present invention also provides Figures 5 to 6 The multi-bit semiconductor memory array shown includes:

[0160] A multi-row semiconductor memory cell, wherein each row of semiconductor memory cells includes at least two groups of multi-bit semiconductor memory cells;

[0161] Each group of the multi-bit semiconductor memory cells includes: a read / write circuit and at least two pixel cells. The read / write circuit includes: a write transistor Wx, a reset transistor Rx, a follower transistor and a row selection transistor Sx. Each pixel cell includes: a pinned diode, a control transistor Tx and a floating diffusion region. The pinned diode is composed of: an N-well region of a photodiode and a P-type surface-doped region, or a P-well region of a photodiode and an N-type surface-doped region.

[0162] In this configuration, the pixel units in each group of the multi-bit semiconductor memory cells share a common drive, while the gate potential of the control transistor Tx is controlled separately.

[0163] In each row of the multi-bit semiconductor memory cell, the control transistors of the corresponding order in different groups of pixel cells share a gate potential, and the write transistor Wx, the reset transistor Rx and the row selection transistor Sx in each row of the multi-bit semiconductor memory cell each share a gate potential.

[0164] In a specific embodiment, all rows of multi-bit semiconductor memory cells share the ground potential, reset potential, and follower transistor drain potential.

[0165] In a specific embodiment, DVDD and reset voltage Vr can be connected to the same potential or controlled separately.

[0166] The technical solution of the present invention also provides a method for reading and writing a multi-bit semiconductor memory array, such as... Figure 7 As shown, Figure 7 for Figures 5 to 6 The timing diagram of the read / write method for the provided multi-bit semiconductor memory array is shown. For data not in the same row, it can be read or written simultaneously; data in the same row cannot be read and written simultaneously.

[0167] In specific embodiments, the following are included:

[0168] The first cycle performs data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row;

[0169] In the second cycle, data is written to the multi-bit semiconductor memory cell in the (n+1)th row. At this time, the (n+2)th row is split into data segments.

[0170] In the third cycle, the multi-bit semiconductor memory cell in row n+1 is reset by FD voltage. At this time, data is written to row n+2 and data is split in row n+3.

[0171] In the fourth cycle, data is read from the multi-bit semiconductor memory cell in row n+1. At this time, FD voltage is reset in row n+2, data is written in row n+3, and data is segmented in row n+4.

[0172] n is an integer greater than zero.

[0173] In a specific embodiment, the step of performing data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row in the first cycle includes: the signal data is segmented into data packets by the circuit and converted into data packet voltages for each column of multi-bit semiconductor memory cells in this row, with each data packet voltage corresponding to the amount of charge to be stored in a multi-bit semiconductor memory cell.

[0174] In a specific embodiment, the step of writing data to the multi-bit semiconductor memory cell in the (n+1)th row in the second cycle includes: turning on the write transistor, so that the data packet voltage is transmitted to the floating diffusion region of each column respectively; turning on the control transistor, so that the data packet voltage is transmitted from the floating diffusion region to the N-well region or P-well region of the respective photodiode; turning off the write transistor and the control transistor, so that the signal is stored.

[0175] In a specific embodiment, the step of resetting the floating diffusion region voltage of the multi-bit semiconductor memory cell in the (n+1)th row in the third cycle includes: the reset voltage is positive, the row selection transistor is turned on, the reset transistor is turned on, the reset voltage is transmitted to the floating diffusion region of each column, the reset transistor is turned off, and the first reference voltage Vref collected at this time is recorded.

[0176] In a specific embodiment, the step of reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle includes: keeping the row selection transistor on, turning on the control transistor, so that the electrons stored in the N-well region or the holes stored in the P-well region of the photodiode will enter their respective floating diffusion regions, causing their voltage to decrease (N-well region) or increase (P-well region), turning off the control transistor, and recording the second reference voltage collected at this time; comparing the difference between the first reference voltage and the second reference voltage can obtain the signal stored in each multi-bit semiconductor memory cell.

[0177] In a specific embodiment, the step of reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle includes: keeping the row selection transistor on, turning on the control transistor, so that the electrons stored in the N-well region or the holes stored in the P-well region of the photodiode will enter their respective floating diffusion regions to lower (N-well region) or raise (P-well region), turning off the control transistor, and recording the signal stored in the multi-bit semiconductor memory cell corresponding to the voltage collected at this time.

[0178] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A multi-bit semiconductor memory cell, characterized in that, include: Pinned diodes, control transistors, and floating diffusion regions are used to store charge using the pinned diodes; The pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, or a P-well region and an N-type surface-doped region of a photodiode. The photodiode is adapted not to sense light signals when the multi-bit semiconductor memory cell is being read or written. A first control gate and a second control gate of the control transistor are also provided between the pinned diode and the floating diffusion region. The first control gate is located between the photodiode and the floating diffusion region and controls the opening and closing of the path between the pinned diode and the floating diffusion region. The floating diffusion area is suitable as a buffer for signal reading or storage and is connected to the level input terminal; The second control gate is disposed between the first control gate and the photodiode, and controls the opening and closing of the passage between the pinned diode and the floating diffusion region; The reading or writing process of the multi-bit semiconductor memory cell is realized by controlling the opening and closing of the first control gate and / or the second control gate in a timing manner. When the pinned diode is composed of an N-well region and a P-type surface-doped region of a photodiode, the second control gate is connected to a negative voltage during data storage to passivate surface defects, thereby further reducing leakage current. When the pinned diode is composed of a P-well region and an N-type surface-doped region of a photodiode, the second control gate is connected to a positive voltage during data storage to passivate surface defects, thereby further reducing leakage current.

2. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, The P-type surface doped region of the pinned diode is adapted to prevent charges generated by substrate interface defects from entering the N-well region of the photodiode.

3. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, The N-type surface doped region is adapted to prevent holes generated by substrate interface defects from entering the P-well region of the photodiode.

4. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, The second control gate portion is located above the photodiode.

5. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, At least two of the aforementioned multi-bit semiconductor memory cells share a floating diffusion region.

6. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, The photodiode is provided with an optical shielding structure, which is suitable for shielding the photodiode from light signal sensing when the multi-bit semiconductor memory cell is being read or written.

7. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, The amount of charge written into the N-well or P-well region of the photodiode is greater than 100e.

8. The multi-bit semiconductor memory cell as described in claim 1, characterized in that, By increasing the depth of the N-well or P-well region of the photodiode, the full-well capacity of the N-well or P-well region of the photodiode is increased, thereby improving the number of resolvable bits of the multi-bit semiconductor memory cell.

9. A method for operating a multi-bit semiconductor memory cell, characterized in that, include: Provides a multi-bit semiconductor memory cell as described in claim 1. During the writing process, the first control gate is turned off first, and then the second control gate is turned off, in order to ensure that the signal is completely written. During the readout process, the second control gate is turned off first, and then the first control gate is turned off, in order to prevent electron backflow.

10. A multi-bit semiconductor memory cell, characterized in that, include: Read / write circuitry and the multi-bit semiconductor memory cell as described in claim 1; The read / write circuit includes: A write transistor is used to connect the control signal and the floating diffusion region, which is suitable for writing the control signal into the floating diffusion region; A reset transistor, connected to a reset voltage and the floating diffusion region, is adapted to reset the control of the floating diffusion region; The follower transistor connects the drain of the row selection transistor to the constant high level potential, and the gate is connected to the floating diffusion region, which is suitable for converting the signal of the floating diffusion region to the output terminal. A row selection transistor, connected to the follower transistor and the signal acquisition terminal, is adapted to read the row selection of the control signal.

11. A multi-bit semiconductor memory cell, characterized in that, include: Read / write circuitry and the multi-bit semiconductor memory cell as described in claim 1; The read / write circuit includes: A write transistor is used to connect the control signal and the floating diffusion region, which is suitable for writing the control signal into the floating diffusion region; A reset transistor, connected to a reset voltage and the floating diffusion region, is adapted to reset the control of the floating diffusion region; The follower transistor connects the drain of the row selection transistor to the constant high level potential, and the gate is connected to the floating diffusion region, which is suitable for converting the signal of the floating diffusion region to the output terminal. A row selection transistor, connected to the follower transistor and the signal acquisition terminal, is adapted to read the row selection of the control signal; The signal acquisition terminal is connected to an external ramp circuit, which is suitable for reading signals through a correlated double sampling method to eliminate KT / C noise.

12. A method for operating a multi-bit semiconductor memory cell, characterized in that, include: A multi-bit semiconductor memory cell as described in claim 10 is provided, wherein the data writing process of the multi-bit semiconductor memory cell includes: The data signal is divided into data packets, and the length of each data packet is equal to the maximum number of bits that a semiconductor memory cell can store. The data packets are converted into data packet voltages, where each data packet voltage corresponds to the amount of charge that a multi-bit semiconductor memory cell needs to store; Turn on the write transistor to transmit the data packet voltage to the floating diffusion region; Turn on the control transistor to transmit the data packet voltage to the N-well or P-well region of the photodiode; When the write transistor and control transistor are turned off, the write data is stored in the N-well or P-well region of the photodiode.

13. A method for operating a multi-bit semiconductor memory cell, characterized in that, include: A multi-bit semiconductor memory cell as described in claim 11 is provided, wherein the data readout process of the multi-bit semiconductor memory cell includes: A positive reset voltage is provided to turn on the row select transistor, and the reset transistor is turned on. The reset voltage will then be transmitted to the floating diffusion region. When the reset transistor is turned off, the voltage across the ramp circuit and the signal acquisition terminal is compared. When the voltages are equal, the first voltage collected at this time is recorded. Keep the row selection transistor on, turn on the control transistor, so that the charge stored in the N-well region or P-well region of the photodiode is transferred to the floating diffusion region, thereby changing the voltage of the floating diffusion region; Turn off the control transistor, compare the voltage across the ramp circuit and the signal acquisition terminal, and record the second voltage collected at this time when the voltages are equal; By comparing the difference between the first voltage and the second voltage, the signal stored in each multi-bit semiconductor memory cell can be obtained.

14. The method of operating a multi-bit semiconductor memory cell as described in claim 13, characterized in that, The data readout process of the multi-bit semiconductor memory cell includes: A positive reset voltage is provided to turn on the row select transistor, and the reset transistor is turned on. The reset voltage will then be transmitted to the floating diffusion region. Turn off the reset transistor; Keep the row selection transistor on, turn on the control transistor, so that the charge stored in the N-well region or P-well region of the photodiode is transferred to the floating diffusion region, thereby changing the voltage of the floating diffusion region; Turn off the control transistor and record the voltage collected at this time to obtain the signal stored in each multi-bit semiconductor memory cell.

15. A multi-bit semiconductor memory array, characterized in that, include: A multi-row multi-bit semiconductor memory cell, wherein each row of multi-bit semiconductor memory cells includes at least two groups of multi-bit semiconductor memory cells as described in claim 1; Each group of the multi-bit semiconductor memory cells includes: a read / write circuit and at least two pixel cells. The read / write circuit includes: a write transistor, a reset transistor, a follower transistor, and a row select transistor. Each pixel cell includes: a pinned diode, a control transistor, and a floating diffusion region. The pinned diode is composed of: an N-well region of a photodiode and a P-type surface doped region, or a P-well region of a photodiode and an N-type surface doped region. In this configuration, the pixel units in each group of multi-bit semiconductor memory cells share a common drive, while the gate potentials of the control transistors are controlled separately. In each row of the multi-bit semiconductor memory cell, the control transistors in the corresponding order of the pixel cells in different groups share a gate potential, and the write transistor, the reset transistor, and the row selection transistor in each row of the multi-bit semiconductor memory cell each share a gate potential.

16. The multi-bit semiconductor memory cell array as described in claim 15, characterized in that, All rows of multi-bit semiconductor memory cells share the ground potential, reset potential, and follower transistor drain potential.

17. A method of operating a multi-bit semiconductor memory array as described in claim 15, characterized in that, For data that is not in the same row, it can be read or written simultaneously; for data in the same row, it cannot be read and written simultaneously.

18. The method of operating a multi-bit semiconductor memory array as described in claim 17, characterized in that, include: The first cycle performs data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row; In the second cycle, data is written to the multi-bit semiconductor memory cell in the (n+1)th row. At this time, the (n+2)th row is split into data segments. In the third cycle, the multi-bit semiconductor memory cell in row n+1 is reset by FD voltage. At this time, data is written to row n+2 and data is split in row n+3. In the fourth cycle, data is read from the multi-bit semiconductor memory cell in row n+1. At this time, FD voltage is reset in row n+2, data is written in row n+3, and data is segmented in row n+4. n is an integer greater than zero.

19. The method of operating a multi-bit semiconductor memory array as described in claim 18, characterized in that, The first cycle of performing data segmentation on the multi-bit semiconductor memory cell in the (n+1)th row includes: the signal data is segmented into data packets by the circuit and converted into the data packet voltage of each column of multi-bit semiconductor memory cell in this row, and each data packet voltage corresponds to the amount of charge to be stored in a multi-bit semiconductor memory cell.

20. The method of operating a multi-bit semiconductor memory array as described in claim 18, characterized in that, The steps of writing data to the multi-bit semiconductor memory cell in the (n+1)th row in the second cycle include: turning on the write transistor, so that the data packet voltage is transmitted to the floating diffusion region of each column respectively; turning on the control transistor, so that the data packet voltage is transmitted from the floating diffusion region to the N-well region or P-well region of the corresponding photodiode; turning off the write transistor and the control transistor, so that the signal is stored.

21. The method of operating a multi-bit semiconductor memory array as described in claim 18, characterized in that, The steps for resetting the floating diffusion region voltage of the multi-bit semiconductor memory cell in the (n+1)th row in the third cycle include: the reset voltage is positive, the row selection transistor is turned on, the reset transistor is turned on, the reset voltage is transmitted to the floating diffusion region of each column, the reset transistor is turned off, and the first reference voltage Vref collected at this time is recorded.

22. The method of operating a multi-bit semiconductor memory array as described in claim 21, characterized in that, The steps for reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle include: keeping the row selection transistor on, turning on the control transistor, so that the charge stored in the N-well or P-well region of the photodiode will be transferred to its corresponding floating diffusion region to change its voltage, turning off the control transistor, and recording the second reference voltage collected at this time; comparing the difference between the first reference voltage and the second reference voltage can obtain the signal stored in each multi-bit semiconductor memory cell.

23. The method of operating a multi-bit semiconductor memory array as described in claim 21, characterized in that, The steps for reading data from the multi-bit semiconductor memory cell in the (n+1)th row in the fourth cycle include: keeping the row selection transistor on, turning on the control transistor, so that the charge stored in the N-well or P-well region of the photodiode is transferred to its corresponding floating diffusion region to change its voltage, turning off the control transistor, and recording the signal stored in the multi-bit semiconductor memory cell corresponding to the voltage collected at this time.

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