Increased channel boost periodicity and reduced word line bias

Abstract

An apparatus and technique are described for increasing the channel boost of a NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage VpassL is applied to a designated word line to create a periodic low or drop in the channel boost level. A normal pass voltage Vpass is applied to other unselected word lines. The low point creates a barrier to the movement of electrons in the channel toward the selected word line, preventing electrons from pulling down the voltage in the channel region adjacent to the selected word line. VpassL can be applied to the designated word line at the source and / or drain side of the selected word line. Control circuitry can be configured with various parameters to implement this technique.

Description

Technical Field

[0001] This technology relates to the operation of memory devices. Background Technology

[0002] Semiconductor memory devices have become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials, such as floating gates or charge trapping materials, can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is a bit-cost scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0004] Memory devices include, for example, memory cells that can be arranged in series as NAND strings, wherein select gate transistors are provided at the ends of the NAND strings to selectively connect the channels of the NAND strings to source lines or bit lines. However, various challenges exist in operating such memory devices. Summary of the Invention

[0005] Accordingly, in one implementation, a device includes: control circuitry configured to connect to a plurality of word lines, the word lines being connected to NAND string memory cells and including selected word lines and unselected word lines, and the NAND string including a channel; and a memory interface connected to the control circuitry. The control circuitry is configured to issue commands via the memory interface to apply a plurality of voltage signals to the plurality of word lines, thereby boosting the voltage of the channel. The plurality of voltage signals include programming voltage signals applied to the selected word lines, and voltage signals increasing from a corresponding initial voltage to a pass voltage, wherein among the unselected word lines, the pass voltage is lower for specified word lines spaced apart along the NAND string than for word lines between specified word lines.

[0006] In another implementation, a method includes: applying a programming voltage signal to a selected word line during a programming operation, the selected word line and an unselected word line being among multiple word lines connected to the selected NAND string and the unselected NAND string, and the unselected NAND string including a channel; and, during the application of the programming voltage signal, applying a voltage signal to the unselected word line, the voltage signal applied to the unselected word line increasing from a corresponding initial voltage to a corresponding pass voltage, generating a periodic drop on the boost in the channel.

[0007] In another implementation, a device includes: a NAND string including a plurality of memory cells and a channel; and a plurality of word lines connected to the memory cells, each word line being adjacent to a corresponding region of the channel and configured to carry a voltage signal that boosts the voltage of the corresponding region of the channel, the channel having a voltage that periodically decreases along the length of the NAND string. Attached Figure Description

[0008] Figure 1A This is a block diagram of an exemplary memory device.

[0009] Figure 1B yes Figure 1A A block diagram of the arrangement of the memory device 100, wherein the control circuitry 130 on the first die 130a communicates with the memory structure 126 on the separate second die 126b.

[0010] Figure 2 It is a drawing Figure 1A A block diagram of one embodiment of the sensing block 51.

[0011] Figure 3 It is illustrated Figure 1A An exemplary implementation of a power control circuit 115 for providing voltage to a block of memory cells in a plane.

[0012] Figure 4 It is based on Figure 1A A perspective view of an exemplary memory die 400, wherein blocks are provided in corresponding planes P0 and P1.

[0013] Figure 5 It is illustrated Figure 1A An exemplary transistor 520 in the memory structure 126.

[0014] Figure 6 It is illustrated Figure 4 An exemplary cross-sectional view of a portion of frame B0-0, containing NAND strings 700n and 710n.

[0015] Figure 7A The illustration shows the basis Figure 4 and Figure 6 An exemplary view of the NAND string in box B0-0.

[0016] Figure 7B It is illustrated Figure 7A An exemplary top view of block B0-0, having corresponding NAND strings, bit lines, and sensing circuitry.

[0017] Figure 8 The threshold voltage (Vth) distribution of an eight-state memory device is illustrated.

[0018] Figure 9A An example of a memory cell that has undergone programming interference is illustrated.

[0019] Figure 9B The illustration depicts what happened Figure 9A A table showing the voltages used when dealing with different types of programming interference.

[0020] Figure 10A The illustration depicts exemplary voltage signals during the pre-charge phase and programming / boost phase of the programming operation, providing insights into the combination of... Figure 9A The discussion covers countermeasures against programming interference.

[0021] Figure 10B An exemplary curve showing the channel voltage versus location within a NAND string is plotted, using... Figure 10A Different voltage signals.

[0022] Figure 11 The illustration shows the use of techniques such as combination. Figure 10A The programming interference countermeasures discussed are boosting in the channel of the NAND string.

[0023] Figure 12A The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-6, WLn-9... and WLn+3, WLn+6, WLn+9...., such that WL_dVpass_init = 3 and WL_dVpass_period = 3.

[0024] Figure 12B The illustration shows the use of, for example, combinations Figure 12A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn+3, WLn+6, WLn+9..., such that WL_dVpass_init = 3 and WL_dVpass_period = 3.

[0025] Figure 12C The illustration shows the use of, for example, combinations Figure 12A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-6, WLn-9..., such that WL_dVpass_init = 3 and WL_dVpass_period = 3.

[0026] Figure 13 The illustration shows the use of, for example, combinations Figure 10AThe programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-4, WLn-7, WLn-10... and WLn+4, WLn+7, WLn+10..., such that WL_dVpass_init = 4 and WL_dVpass_period = 3.

[0027] Figure 14 The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-7, WLn-11... and WLn+3, WLn+7, WLn+11..., such that WL_dVpass_init = 3 and WL_dVpass_period = 4.

[0028] Figure 15 The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-7, WLn-12... and WLn+3, WLn+7, WLn+12..., such that the specified word lines are spaced apart at progressively larger intervals along the NAND string in a direction moving away from the selected word lines.

[0029] Figure 16 The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boost voltages in the channel of the NAND string, wherein the countermeasures involve applying VpassL-, VpassL and VpassL+ to specified word lines, namely WLn-2, ​​WLn-5, and WLn-9, respectively, and applying them to WLn+2, WLn+5, and WLn+9, respectively, such that the voltage across the specified word lines gradually increases with respect to the specified word lines that are further away from the selected word lines.

[0030] Figure 17A The curve of channel voltage versus time is plotted when WLn is below WL, based on... Figure 10A The voltage signal.

[0031] Figure 17B The curve of channel voltage versus time is plotted when WLn is in the middle to lower WL, based on the voltage signal in Figure 10A.

[0032] Figure 17C The curve of channel voltage versus time is plotted when WLn is in the middle of WL, based on the voltage signal in Figure 10A.

[0033] Figure 17D The curve of channel voltage versus time is plotted when WLn is above WL, according to Figure 10A The voltage signal.

[0034] Figure 18 The curves of channel voltage versus time for different values ​​of dVpass are plotted based on the voltage signal in Figure 10A.

[0035] Figure 19 The graph shows the channel voltage versus time for different values ​​of WL_dVpass_init (the number of word lines between WLn and the nearest word line to receive VpassL), based on... Figure 10A The voltage signal.

[0036] Figure 20 The plot shows the channel voltage versus time curves for different values ​​of WL_dVpass_period (the interval between word lines receiving VpassL), based on... Figure 10A The voltage signal.

[0037] Figure 21A The curve of WL_dVpass_period with respect to the position of WLn is plotted.

[0038] Figure 21B The curves of VpassL and dVpass with respect to the position of WLn are plotted.

[0039] Figure 21C The curves of the NAND string subjected to programming interference countermeasures are plotted against the WLn position.

[0040] Figure 21D The NAND string channel is illustrated, in which 75% of the drain-side word lines are subjected to programming interference countermeasures.

[0041] Figure 21E The diagram illustrates the NAND string channel, where 50% of the drain-side word lines are subjected to programming interference countermeasures.

[0042] Figure 21F The NAND string channel is illustrated, in which 0% of the drain-side word lines are subjected to programming interference countermeasures.

[0043] Figure 22A The process of programming blocks is illustrated.

[0044] Figure 22B It is illustrated for Figure 22A The table of dVpass values ​​for step 2202.

[0045] Figure 22C It is illustrated for Figure 22A The table of WL_dVpass_init values ​​in step 2202.

[0046] Figure 22D It is illustrated for Figure 22A The table of WL_dVpass_period values ​​in step 2202.

[0047] Figure 23 An exemplary voltage signal for performing programming operations according to Figure 22 is illustrated. Detailed Implementation

[0048] Devices and techniques for increasing the channel voltage of a NAND string during programming by applying a periodic low word line bias are described.

[0049] In some memory devices, memory cells are grouped together as NAND strings, such as blocks or sub-blocks. Each NAND string comprises a number of memory cells connected in series between one or more drain-side selected-gate transistors (SGD transistors) and one or more source-side selected-gate transistors (SGS transistors). The one or more drain-side selected-gate transistors are located at the drain terminals of the NAND string's connection to bit lines, and the one or more source-side selected-gate transistors are located at the source terminals of the NAND string or other memory strings or a group of connected memory cells' connection to source lines. The selected-gate transistors are also called selected gates. Additionally, memory cells may be arranged with common control gate lines (e.g., word lines), which act as control gates. A set of word lines extends from the source side of the block to the drain side of the block. See, for example, [example missing]. Figure 7A Memory cells can be connected as other types of strings and in other ways.

[0050] In a 3D memory structure, memory cells can be arranged as vertical NAND strings in a stack within a substrate, where the stack comprises alternating conductive and dielectric layers. The conductive layers act as word lines connecting to the memory cells. Each NAND string can have a pillar shape that intersects the word lines to form a memory cell. Additionally, each NAND string contains various layers extending vertically within the stack. See, for example... Figure 6 The NAND string 700n has a channel 660 and a charge trapping layer 664. The source end 700s of the NAND string is connected to the substrate 611, and the drain end 700d of the NAND string is connected to the bit line BL0.

[0051] In a 2D memory structure, memory cells can be arranged as horizontal NAND strings on a substrate.

[0052] Programming operations on memory cells within a block typically involve applying a series of programming pulses to the selected word line WLn, while a voltage is applied to the unselected word line. The word lines are connected to the selected NAND string where programming will occur, and to the unselected NAND string where programming is suppressed. As the voltage on the word line ramps up, the voltage in the channel of the unselected NAND string increases or rises due to capacitive coupling with the word line. This helps prevent programming interference or accidental programming of memory cells in the unselected NAND string connected to WLn. In particular, a higher voltage boost in the channel region close to WLn can help reduce programming interference. Erasable state memory cells are especially susceptible to programming interference, such as... Figure 8 As shown. One approach to increasing the boost level is to increase the pass voltage. However, if the pass voltage becomes too high, it can itself cause programming interference. Furthermore, programming interference is expected to worsen in 3D memory devices as the channel length of the NAND string increases. This increase in channel length corresponds to an increase in the number of word lines in a block. For example, some blocks have 96 or more word lines.

[0053] The techniques presented in this paper address the aforementioned and other problems. In one aspect, a low pass voltage VpassL is applied to some of the word lines to generate periodic lows or drops in the channel boost level. See Figure 10A and Figure 10B The example voltage signals VpassL and Vpass are shown in the diagram. These word lines are referred to as designated word lines. See [link to diagram]. Figure 12A The exemplary dropouts 1201-1206 and the exemplary specified word lines WLn-9, WLn-6, WLn-3, WLn+3, WLn+6, and WLn+9 are shown in the diagram. The dropout creates a barrier to the movement of electrons in the channel toward the selected word line, preventing electrons from pulling down the voltage in the channel region adjacent to the selected word line. See also... Figure 12A .

[0054] In one approach, VpassL is applied to a specified word line on both the source and drain sides of WLn. See [link to relevant documentation]. Figure 12A In another approach, based on the word line programming order, VpassL is applied to one side of WLn but not to the other. For example, VpassL can be applied to a specified word line on the unprogrammed side of the selected word line, but not to programmed word lines on the programmed side of the selected word line. See [link to relevant documentation]. Figure 12B and Figure 12C , as an example.

[0055] The control circuit can be configured with various parameters for implementing the technology. For example, the parameter WL_dVpass_init specifies the position of the initially specified word line closest to the selected word line. The parameter WL_dVpass_period specifies the period or interval of other specified word lines relative to the initially specified word line. WL_dVpass_init can be equal to (see...) Figure 12A and Figure 12B ) or different from (see Figure 13-16 WL_dVpass_period.

[0056] WL_dVpass_period can be fixed or variable. For example, it can gradually increase in the direction of movement away from the selected word line, such as... Figure 15 and Figure 16 The parameter dVpass specifies the difference between the nominal through voltage Vpass and VpassL. Furthermore, dVpass (and VpassL) can be fixed or varied. For example, dVpass can be gradually decreased (and VpassL can be increased) as the voltage moves away from the selected word line. Figure 16 .

[0057] WL_dVpass_period, dVpass, and VpassL can also be functions of the selected word line position, since the probability of programming interference varies as a function of the selected word line position. See Figure 21A and Figure 21B .

[0058] The periodically decreasing portion of the NAND string can be a function of the WLn position. See Figure 21C to Figure 21E .

[0059] These other features will be discussed further below.

[0060] Figure 1AThis is a block diagram of an exemplary storage device. Memory device 100 (such as a non-volatile storage system) may include one or more memory dies 108. Memory die 108 (or chip) includes a memory structure 126 (such as an array of memory cells), control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable by word lines via row decoder 124 and by bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ... 53 (sensing circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may be located on a die 127 separate from the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120, and between controller and one or more memory dies 108 via line 118.

[0061] Memory structures can be 2D or 3D. A memory structure can include one or more arrays of memory cells, including 3D arrays. A memory structure can include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without an intermediate substrate. A memory structure can include any type of non-volatile memory, monolithically formed in one or more physical stages of an array of memory cells having active regions disposed on a silicon substrate. A memory structure can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0062] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, on-chip address decoder 114, and power control circuitry 115. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is software programmable. In other embodiments, the state machine is not implemented using software and is entirely implemented as hardware (e.g., circuitry).

[0063] The on-chip address decoder 114 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 124 and 132. Power control circuitry 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. It may include word line, SGS, and SGD transistors, as well as drivers for the source lines. See also... Figure 3 In one approach, the sensing block may include a bit line driver.

[0064] In some implementations, certain components can be combined. In various designs, one or more (alone or in combination) of the components other than memory structure 126 can be considered as at least one control circuit configured to perform the techniques described herein (including the steps of the processes described herein). For example, the control circuit may include any one or a combination of the following: control circuit 110, state machine 112, decoders 114 and 132, power control circuit 115, sensing blocks 51, 52, ..., 53, read / write circuit 128, controller 122, etc. A state machine is a circuit that can control the operation of control circuit 110. In some embodiments, the state machine is implemented by or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0065] The off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct several read errors. RAM 122b may be DRAM, which stores uncommitted data, as an example. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, the data is erased from RAM 122b and committed or released to a block of memory cells. RAM 122b may store data for one or more word lines.

[0066] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffering, surge isolation, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0067] The memory in controller 122 (such as ROM 122a and RAM 122b) includes code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or additionally, the processor may access the code from a subset 126a of the memory structure (such as reserved areas of memory cells in one or more word lines).

[0068] For example, code can be used by the controller to access memory structures, such as for programming, reading, and erasing operations. The code may contain boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during the boot or startup process and enables the controller to access memory structures. The code can be used by the controller to control one or more memory structures. Upon startup, processor 122e retrieves the boot code from ROM 122a or a subset 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code contains drivers to perform basic tasks, such as controlling and allocating memory, rationally prioritizing instruction outputs, and controlling input and output ports.

[0069] For example, the controller of RAM 122b and / or control circuit 110 can store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits per cell stored in the memory cell, the portion of the programmed word line in the block or sub-block, the portion of the programmed sub-block in the block, the strength of the ECC process used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as the bit line or word line voltage settling time and the number of sensed passes.

[0070] In general, the control code may contain instructions to perform the functions described herein, steps including the flowcharts discussed further below, and voltage waveforms, including the voltage waveforms discussed further below. The control circuitry may be configured to execute instructions to perform the functions described herein.

[0071] In one embodiment, the host is a computing device (e.g., a laptop, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) to program the one or more processors to perform the methods described herein. The host may also include additional system memory in communication with the one or more processors, one or more input / output interfaces, and / or one or more input / output devices.

[0072] Other types of non-volatile memory besides NAND flash memory can also be used.

[0073] Semiconductor memory devices include volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM), and non-volatile memory devices such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured as NAND or NOR.

[0074] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. As other non-limiting examples, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions (such as floating gates, conductive nanoparticles, or charge storage dielectric materials).

[0075] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) configured with NAND typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, including memory cells and SG transistors.

[0076] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where each string is shared by multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0077] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0078] In 2D memory structures, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer, on which or in which the memory elements are formed, or it may be a carrier substrate attached to the memory elements after their formation. As a non-limiting example, the substrate may contain a semiconductor, such as silicon.

[0079] Memory elements can be arranged as a single memory device level in a sequential array, such as multiple rows and / or columns. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0080] The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface of the substrate).

[0081] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction), each column having multiple memory elements. The columns can be arranged in a 2D configuration, e.g., in the xy-plane, resulting in a 3D arrangement of the memory elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0082] As a non-limiting example, in a 3D NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. 3D memory arrays can also be designed in NOR and ReRAM configurations.

[0083] Typically, in a monolithic 3D memory array, one or more memory device classes are formed on a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers, which are at least partially within the single substrate. As a non-limiting example, the substrate may contain a semiconductor such as silicon. In a monolithic 3D array, the layers constituting the memory device classes of the array are typically formed on the layers of the memory device classes below the array. However, the layers of adjacent memory device classes in a monolithic 3D memory array may be shared or may have intermediate layers between the memory device classes.

[0084] 2D arrays can be formed separately and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages one on top of the other. The substrates can be thinned or removed from the memory device stages before stacking, but because the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Alternatively, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0085] Typically, associated circuitry is required to operate the memory element and to communicate with it. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be on the same substrate as the memory element and / or on a separate substrate. For example, the controller for memory read / write operations may be located on a separate controller chip from the memory element and / or on the same substrate.

[0086] Those skilled in the art will recognize that this technology is not limited to the 2D and 3D exemplary structures described herein, but covers all relevant memory structures within the spirit and scope of this technology as described herein and understood by those skilled in the art.

[0087] Figure 1B yes Figure 1AA block diagram of the arrangement of a memory device 100, wherein control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The control circuitry may communicate with the memory structure and the die 126b via a memory interface 131 (e.g., similar to memory interface 122d). Examples of memory interfaces (I / F) include JEDEC's Common Flash Memory Interface. The techniques described herein can be implemented using a control die 130a incorporated into one or more memory dies 126b, wherein the memory die includes the memory structure 126 and the control die includes control circuitry 130, which represents all or a subset of the peripheral circuitry of the memory structure. The control circuitry may be on the same die as the multiple memory cells or on a different die than the multiple memory cells.

[0088] For example, the memory structure may contain non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a set of circuits that perform memory operations (e.g., write, read, erase, and others) on the memory structure. Control circuitry may include state machine 112, storage area 113, on-chip address decoder 114, and power control circuitry 115. In another embodiment, a portion of read / write circuitry 128 is located on control die 130a, while another portion of read / write circuitry is located on memory die 126b. For example, read / write circuitry may include a sense amplifier. The sense amplifier may be located on the control die and / or the memory die.

[0089] In an exemplary implementation, control circuitry 130 is configured to connect to a plurality of word lines connected to memory cells in a NAND string, and memory interface 131 is connected to the control circuitry. The circuitry is configured to issue commands via the memory interface to apply a plurality of voltage signals to the plurality of word lines, thereby boosting the voltage of the channels of the NAND string.

[0090] The term "memory die" can refer to a semiconductor die containing non-volatile memory cells for storing data. The term "control circuitry die" can refer to a semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0091] Figure 2 It is a drawing Figure 1AA block diagram of one embodiment of the sensing block 51. The individual sensing block 51 is divided into one or more core portions, referred to as sensing circuits 60-63 or sensing amplifiers, and a common portion, referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each of the sensing circuits in the group communicates with its associated management circuitry via a data bus 176. Thus, there are one or more management circuits communicating with the sensing circuitry of a group of storage elements (memory cells).

[0092] As an example, sensing circuit 60 operates during a programming cycle to provide a precharge / programming suppression voltage to an unselected bit line, or to provide a programming enable voltage to a selected bit line. The unselected bit line is connected to an unselected NAND string and to an unselected memory cell within it. The unselected memory cell can be a memory cell within an unselected NAND string, where the memory cell is connected to a selected or unselected word line. The unselected memory cell can also be a memory cell within a selected NAND string, where the memory cell is connected to an unselected word line. The selected bit line is connected to the selected NAND string and to the selected memory cell within it.

[0093] The sensing circuit 60 also operates during the verification test in the programming cycle to sense memory cells, thereby determining whether they have been programmed by reaching an assigned data state (e.g., if their Vth exceeds the verification voltage indicated by the assigned data state). The sensing circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sensing circuit 60 also operates during an erase operation in the verification test to determine whether multiple memory cells have a Vth below the verification voltage. As further described below, verification tests can be performed on memory cells connected to all word lines in a block, or on memory cells connected to odd or even number lines. The sensing circuit senses whether the on-current in the connected bit lines is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is above or below the word line voltage, respectively.

[0094] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a gate-through or bit-line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a gate-through to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming suppression voltage such as 1-2V may be used to precharge and suppress unselected NAND strings. Alternatively, a programming enable voltage such as 0V may be used to allow programming in selected NAND strings. Selector 56 may be operated as a gate-through by supplying a power voltage Vdd, for example, 3-4V, to the control gate of transistor 55.

[0095] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage between Vcg and Vth, where Vcg is the voltage at the control gate 58 and Vth, for example, 1V, is the threshold voltage of transistor 55. This assumes the source line is at 0V. This mode can be used during sensing operations such as read and verify operations. Thus, the bit line voltage is set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass, for example, 1.5V Vbl_sense + Vth to transistor 55 to provide, for example, 0.5V Vbl_sense on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57, which is higher than the control gate voltage on transistor 55, to provide source follower mode during sensing operations. Vbl refers to the bit line voltage.

[0096] Vbl selector 173 can be controlled by one of several voltage signals. For example, the Vbl selector can be controlled by a programmable suppression voltage signal, which increases from an initial voltage of, for example, 0V to a programmable suppression voltage of, for example, Vbl_inh for the corresponding bit line of an unselected NAND string during a programming cycle. Vbl selector 173 can be controlled by a programmable enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during a programming cycle. As an example, the Vbl selector can select from... Figure 3 The voltage signal of the BL voltage driver 340 in the middle.

[0097] In one embodiment, the selector 56 of each sensing circuit can be controlled independently of the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled independently of the Vbl selectors of other sensing circuits.

[0098] During sensing, sensing node 171 is charged to an initial voltage Vsense_init, such as 3V. The sensing node is then passed through a bit line via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in an on or off state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during the sensing time. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in an on state, and its Vth is at or below the verification voltage. If the sensing node voltage does not decay below Vtrip, the memory cell is in an off state, and its Vth is above the verification voltage. Sensing node latch 172 is set to 0 or 1, for example, based on whether the memory cell is in an on or off state, via comparator circuit 175. Data in the sensing node latch can be bits read by processor 192 and used to update trip latch 174. Subsequently, for the next programming cycle, the bits in the jump latch, along with the allocated data states in latches 194-197, can be used by the processor to determine whether the memory cell and NAND string are selected or not for programming in the programming cycle, and thereby pass the appropriate enable or suppress bit line voltages through the bit lines respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0099] The management circuitry 190 includes a processor 192, four sets of exemplary data latches 194-197 for sensing circuits 60-63, and an I / O interface 196 coupled between the sets of data latches and the data bus 120. Each sensing circuit may be provided with, for example, a set of three data latches including individual latches LDL, MDL, and UDL. In some cases, a different number of data latches may be used. In the three-bit embodiment per unit, the LDL stores bits of the lower page of data, the MDL stores bits of the middle page of data, and the UDL stores bits of the upper page of data.

[0100] Processor 192 performs calculations, such as determining data stored in the sensed memory cells, and stores the determined data in a set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits representing write data to be programmed into memory, introduced from data bus 120 during a programming operation. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0101] During the read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As the memory is progressively passed through various predetermined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to processor 192 via data bus 176. At this time, processor 192 determines the resulting memory state by considering the trip events(s) of the sensing circuit and the information from the state machine via input line 193 regarding the applied control gate voltage. The binary code of the memory state is then calculated, and the resulting data bits are stored in data latches 194-197.

[0102] Some implementations may include multiple processors 192. In one embodiment, each processor 192 will include output lines (not shown) such that each of the output lines is wired-ORed together. In some embodiments, the output lines are inverted before being connected to the wired-OR line. This configuration allows for rapid determination of when the programming process has been completed during programming verification testing, as the state machine receiving the wired-OR signal can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit is sent to the wired-OR line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wired-OR line eight times, or logic is added to the processor 192 to accumulate the results of the associated bit lines, so that the state machine only needs to read the wired-OR line once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0103] During the programming or verification operation of a memory cell, the data to be programmed (write data) is stored from the data bus 120 in the set of data latches 194-197. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell is allowed to be reprogrammed, based on the amplitude of the programming pulse.

[0104] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. In a process called incremental step-pulse programming, each voltage pulse can increase in amplitude from the previous programming pulse by a step size. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming suppression mode, such as by updating its latches. This prevents the memory cell coupled to the bit line from being further programmed, even if additional programming pulses are applied to its control gate.

[0105] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some implementations, the data latches are implemented as shift registers, such that parallel data stored therein is converted into serial data on the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be combined to form a block shift register, allowing blocks of data to be input or output serially. In particular, the banks of read / write circuits are adapted such that each of its sets of data latches shifts data sequentially onto or off the data bus, as if they were part of a shift register used for the entire read / write block.

[0106] Data latches identify when an associated memory cell has reached a certain milepost in the programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. A data latch indicates whether a memory cell is currently storing one or more bits of a page of data. For example, an LDL latch might be used to store the lower page of data. The LDL latch is toggled (e.g., from 0 to 1) when the lower page bit is stored in the associated memory cell. For three bits per cell, an MDL or UDL latch is toggled when the middle or upper page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0107] Figure 3 It is illustrated Figure 1A An exemplary implementation of the power control circuit 115 is provided to provide voltage to blocks of memory cells in a plane. In one embodiment, the circuitry shown can be repeated for each plane of the bare die. In this example, the memory structure 126 includes a set of four associated blocks B0-0 to B0-3, and another set of four associated blocks B0-4 to B0-7. See also Figure 4 A block can lie in one or more planes. Figure 1A The line decoder 124 provides voltage to the word line and select gate control line of each block via transistor 322. In one embodiment, a separate line decoder is provided for each block. The line decoder provides control signals to the pass transistors that connect the block to the line decoder. In one embodiment, the pass transistors of each group of blocks are controlled by a common control gate voltage. Thus, all pass transistors of a group of blocks are either turned on or off at a given time. If a pass transistor is turned on, voltage from the line decoder is provided to the corresponding control gate line or word line. If a pass transistor is turned off, the line decoder is disconnected from the corresponding control gate line or word line, causing the voltage to float on the corresponding control gate line or word line.

[0108] For example, control gate line 312 is connected to the group of transistors 313-316, which in turn are connected to control gate lines B0-4 to B0-7 respectively. Control gate line 317 is connected to the group of transistors 318-321, which in turn are connected to control gate lines B0-0 to B0-3 respectively.

[0109] Typically, programming or reading operations are performed one at a time on a selected sub-block within a block. Erasing operations can be performed on either a selected block or a sub-block. A line decoder can connect global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is supplied to the global control line from several voltage drivers. Some of these voltage drivers can provide voltage to switch 350, which is connected to the global control line. Control is achieved via transistor 324 to pass the voltage from the voltage drivers to switch 350.

[0110] The voltage driver may include a selected data word line (WL) driver 347, which provides voltage on the selected data word line during programming or read operations. The driver 347 may provide a pre-charge voltage and a programming voltage on WLn during the programming cycle of a programming operation. Figure 6 In this context, driver 348 can be used for unselected data word lines, and dummy word line drivers 349 and 349a can be used to provide voltage on dummy word lines WLDD and WLDS, respectively.

[0111] The voltage driver may also include separate SGD drivers for each sub-block. For example, such as Figure 7A In this configuration, SGD drivers 346, 346a, 346b, and 346c can be provided for SB0, SB1, SB2, and SB3, respectively. The SGD drivers provide control lines with voltages connected to the control gate of the SGD transistor (drain-side selected gate transistor). In one option, the SGS driver 345 is common to different sub-blocks within the block and provides control lines with voltages connected to the control gate of the SGS transistor (source-side selected gate transistor).

[0112] Various components including the line decoder can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0113] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b, for example, via a conductive path 682. See Figure 6 In one scheme, the p-well region 611b is common to the block. The Vp-well can be connected to Figure 12 and... Figure 13 The Verase in the block is the same. A set of bit lines 342 is also shared by the block. The source line (SL) voltage driver 331 provides voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via local interconnect 651.

[0114] Bit line voltage driver 340 includes a voltage source that provides voltage to bit line 342. As an example, the bit line voltage used for sensing erase verification tests can be 0.5V.

[0115] In such Figures 4 to 7B In the stacked memory device illustrated, groups of connected memory cells can be arranged as NAND strings that extend vertically upward from the substrate. In one embodiment, the bottom (or source end) of each NAND string contacts the substrate (e.g., the well region), and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0116] Figure 4 This is a perspective view of an exemplary memory die 400, wherein blocks are provided in corresponding planes P0 and P1, and... Figure 1A Consistent. The memory die includes a substrate 611, an intermediate region 402 in which blocks of memory cells are formed, and an upper region 403 in which one or more upper metal layers, such as those forming bit lines, are patterned. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 611. Additionally, a first block sequence 405 (labeled B0-0 to B0-n-1) of n blocks is formed in P0, and a second block sequence 415 (labeled B1-0 to B1-n-1) of n blocks is formed in P1. Each plane may have associated row and column control circuitry, such as... Figure 1A The row decoder 124, the read / write circuit 128, and the column decoder 132.

[0117] In one embodiment, the control circuitry 110, which may be located in the peripheral region of the bare die, can be shared between planes. Each plane may have a separate set of bit lines.

[0118] By providing blocks of memory cells in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0119] The substrate 611 may also carry the circuitry beneath the block, as well as one or more underlying metal layers patterned in the conductive path, to carry the circuitry's signals.

[0120] In this example, memory cells are formed in vertical NAND strings within a block. Each block comprises a region of stacked memory cells, where alternating levels of the stack represent word lines. In one possible configuration, each block has opposing layered sides from which vertical contact bodies extend upwards to an upper metal layer to form connections with conductive paths. Although two planes are illustrated as an example, other examples may use four or more planes. One plane per bare die is also possible.

[0121] While the examples above relate to 3D memory devices with vertically extending NAND strings, the techniques presented herein can also be applied to 2D memory devices where the NAND strings extend horizontally on a substrate.

[0122] Figure 5 It is illustrated Figure 1A An exemplary transistor 520 in the memory structure 126. As an example, the transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may represent a memory cell or a select gate transistor. The drain end of the transistor is optionally connected to the bit line BL via one or more other transistors in the NAND string, and the source end of the transistor is optionally connected to the source line SL via one or more other transistors in the NAND string.

[0123] Figure 6 It is illustrated Figure 4 An exemplary cross-sectional view of a portion of frame B0-0 includes NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. A block comprises a stack 610 of alternating conductive layers (word line layers) and dielectric layers. A layer may be a rectangular plate having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0124] A stack is illustrated as comprising one level, but may optionally include one or more levels of alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers, wherein memory vias are formed during fabrication.

[0125] The conductive layer includes SGS, WLDS, WL0-WL95, WLDD, and SGD(0). In this example, there are 96 data word lines, although the number of data word lines can be greater or less than 96. In another exemplary implementation, there are 160 data word lines.

[0126] The conductive layer connected to the control gate of the memory cell is called a word line, and the conductive layers connected to the control gates of the source-side select-gate transistor and the drain-side select-gate transistor are called source-side and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells, which are not eligible to store user data. Dummy memory cells may have the same construction as data memory cells, but are considered by the controller to be ineligible to store any type of data, including user data. One or more dummy memory cells may be provided at the drain and / or source terminals of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cell, which are eligible to store user data. DL is an exemplary dielectric layer.

[0127] The top 610t and bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0128] NAND strings are formed by etching memory holes in a stack and then depositing multiple thin layers of material along the sidewalls of the memory holes. Memory cells are formed in regions where word lines intersect with the multiple thin layers, and select gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers. For example, drain-side select gate transistor 716 is formed at the intersection of SGD control lines and multiple thin layers, source-side select gate transistor 701 is formed at the intersection of SGS control lines and multiple thin layers, topmost data memory cell 714 is formed at the intersection of WL95 word line and multiple thin layers, and bottommost data memory cell 703 is formed at the intersection of WL0 word line and multiple thin layers.

[0129] Multiple thin layers can be formed into a ring layer and can be deposited, for example, using atomic layer deposition. For example, the layer may include a barrier oxide layer 663, a charge trapping layer 664 or a film of silicon nitride (Si3N4) or other nitrides, a tunneling layer 665 (e.g., gate oxide), and a channel 660 (e.g., comprising polysilicon). A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. Word lines or control lines may include a metal, such as tungsten. In this example, all layers are provided within memory vias. In other embodiments, some layers may be provided within word line or control line layers. Multiple thin layers form columnar active regions (AA) of the NAND string.

[0130] The stack is formed on substrate 611. In one embodiment, the substrate includes a p-well region 611a connected to the source end of the NAND string (see also...). Figure 3 The p-well region may include an epitaxial region 612 extending upward adjacent to the source-side selected gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 to receive the source line voltage, and a p+ contact 612b connected to a conductive path 682 to receive the p-well voltage. The local interconnect 651 may include a conductive material 651b, such as a metal surrounded by an insulating material 651a, to prevent metal conduction with adjacent word lines. In one possible implementation, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0131] The NAND string 700n has a source end 700s at the bottom 610b of the stack body 610, which is connected to the p-well. The NAND string 700n also has a drain end 700d at the top 610t of the stack body, which is connected to the bit line BL0 via a bit line contact 680 comprising an n-type material.

[0132] NAND strings can be viewed as having floating body channels because the length of the channels is not formed in the substrate.

[0133] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are drawn from the channel into the charge trapping layer and then through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the channels of the NAND string are charged, for example by applying a positive erase pulse to the substrate via local interconnect 651, causing electrons to return from the charge trapping layer to the channel.

[0134] Figure 7A The illustration shows the basis Figure 4 and Figure 6 An exemplary illustration of a NAND string in box B0-0. The NAND strings are arranged as sub-blocks of a block in a 3D configuration. Each sub-block contains multiple NAND strings, with one exemplary NAND string depicted here. For example, SB0, SB1, SB2, and SB3 include exemplary NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have [specific features / conditions] according to [the provided text]. Figure 6The subblock comprises data word lines, dummy word lines, and select gate lines. Each subblock includes a set of NAND strings extending in the x-direction and having a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n are in subblocks SB0, SB1, SB2, and SB3, respectively. Block programming can occur based on the word line programming sequence. One option is to program memory cells in different portions of different subblocks of a word line before programming the memory cells of the next word line, one subblock at a time. For example, this could involve programming WL0 in SB0, SB1, SB2, and then SB3, then programming WL1 in SB0, SB1, SB2, and then SB3, and so on. As an example, the word line programming sequence could begin with WL0 (source extreme word line) and end with WL95 (drain extreme word line). In another example, in a reverse programming sequence, the word line programming sequence begins with the drain extreme word line and ends with the source extreme word line.

[0135] In an erase operation, typically the entire block is erased, although partial block erasure is also possible.

[0136] Multiple memory cells of B0-0 are arranged in NAND strings, wherein each NAND string includes a continuous charge trapping layer along the length of the NAND string. NAND strings 700n, 710n, 720n, and 730n have channels 700a, 710a, 720a, and 730a, respectively. Furthermore, NAND string 700n includes an SGS transistor 701, dummy memory cells 702, data memory cells 703-714, dummy memory cells 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, dummy memory cells 722, data memory cells 723-734, dummy memory cells 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, dummy memory cells 742, data memory cells 743-754, dummy memory cells 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-774, a dummy memory cell 775, and an SGD transistor 776.

[0137] This example illustrates one SGD transistor at the drain end of each NAND string and one SGS transistor at the source end of each NAND string. In one embodiment, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another embodiment, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0138] Figure 7B It is illustrated Figure 7A An exemplary top view of block B0-0, showing the corresponding NAND strings, bit lines, and sensing circuitry. The view is in the xy-plane. Each circle represents a NAND string. In this example, sixteen NAND strings are depicted in each sub-block. SB0 contains... Figure 7A The NAND string 700n and the additional NAND strings 700n1-700n15. SB1 contains Figure 7A The NAND string 710n and the additional NAND strings 710n1-710n15. SB2 contains... Figure 7A The NAND string 720n and the additional NAND strings 720n1-720n15. SB3 contains... Figure 7A The NAND string 730n and the additional NAND strings 730n1-730n15.

[0139] A set of bit lines BL0-BL15 are connected to NAND strings. Each bit line is connected to a corresponding group of NAND strings, containing one NAND string in each sub-block. For example, BL0 is connected to NAND strings 700n, 710n, 720n, and 730n in a group of NAND strings 799, BL1 is connected to NAND strings 700n1, 710n1, 720n1, and 730n1, and so on. Each bit line is also connected to a corresponding sensing circuit. Figure 2 The sensing circuits 60-63 are identical. For example, BL0-BL15 are connected to sensing circuits SC0-SC15 respectively.

[0140] Figure 8 The threshold voltage (Vth) distribution of an eight-state memory device is illustrated. Eight data states, or three bits per cell, are shown as an example. The techniques described herein can be applied to other modes, involving one or more bits per cell. The vertical axis plots the number of memory cells on a logarithmic scale, and the horizontal axis plots the threshold voltage on a linear scale. The Vth distribution can represent memory cells connected to word lines or all memory cells in a block. After erasing the block, the Vth distribution 800 is obtained, indicating the erase state. The erase operation is complete when all or nearly all memory cell Vths are below the verification voltage VvEr.

[0141] The memory cells then undergo programming operations. Each of the memory cells will have an assigned data state. Some memory cells are assigned to an erase state and are not programmed. Most memory cells are programmed to higher states, such as AF, which in this example are represented as Vth distributions 801-807, respectively. These memory cells undergo verification testing using verification voltages VvA-VvG. Programming higher-state memory cells may interfere with erase-state memory cells connected to WLn, as mentioned in the overview, resulting in a widened and upward-shifted Vth distribution 800a. Interference known as Vpass interference may also occur in erase-state memory cells connected to unselected word lines by applying a pass voltage.

[0142] Figure 9A An example of a memory cell subjected to programming interference is illustrated. The memory cell is arranged according to... Figure 7A and Figure 7B The NAND strings are 700n, 710n, 700n1, and 710n1. Word lines include WL0, WL1, WL2, ..., WLn-1, WLn, WLn+1, ..., WL94 and WL95. In this example, memory cell MCP is selected for programming, making NAND string 710n the selected NAND string. Memory cells MCX, MCY, and MCXY are not selected for programming, making NAND strings 700n, 700n1, and 710n1 unselected NAND strings. Referring to the x, y, and z coordinate system, MCX is in the x-direction, MCY is in the y-direction, and MCXY is relative to MCP in both the x and y directions. Each of these exemplary memory cells is connected to WLn (the selected word line). BL0 is the selected bit line because it is connected to the selected NAND string, and BL1 is the unselected bit line because it is not connected to the selected NAND string. NAND strings can have a common source voltage and an SGS voltage.

[0143] Based on the architecture of 3D memory devices, programming interference can be classified into three modes: X-mode, Y-mode, and XY-mode. These modes are experienced by MCX, MCY, and MCXY, respectively.

[0144] In the selected NAND string 710n, the SGD transistors are turned on (conducted) by setting a positive Vsgd, which is common to all SGD transistors in SB1. The dummy word lines WLDD and WLDS can be biased with corresponding voltages, typically lower than the voltages of the data word lines. The data word lines receive a nominal pass voltage Vpass, such as 9V. The bit line BL0 is connected to ground to supply electrons for programming. Therefore, during MXP programming, the channel voltage is 0V. The MXP is programmed using a high programming voltage Vpgm, such as 20V, applied to WLn.

[0145] In a suppressed NAND string, using NAND string 700n1 subjected to XY mode programming interference as an example, the SGD transistor is turned off (non-conducting) by setting Vsgd = 0V and BL1 = Vddsa (positive power supply voltage). This Vsgd is common to the SGD transistor in SB0. The SGS transistor is turned off by biasing it with 0V. Therefore, the channel voltage floats along the length of the NAND string.

[0146] When the voltage of an unselected word line ramps up from an initial level such as 0V to a final level Vpass (see...) Figure 10A When Vpgm is applied to WLn, the channel potential in the NAND string 700n1 is coupled from 0V to Vboost, for example. This upcoupling is due to the capacitance of the materials forming the NAND string and word lines. For example, these materials may include a MONOS stack containing a metal layer as word lines, a barrier oxide layer, a nitride charge trapping layer, an oxide tunneling layer, and a polysilicon channel layer. When Vpgm is applied to WLn, the effective programming voltage will occur as Vpgm-Vboost in the suppressed NAND string. This results in relatively high stress on the suppressed memory cell MCXY, which may lead to programming interference, or an upward shift of Vth in the memory cell. The stress is even higher when Vboost is lower.

[0147] Vboost can be reduced by electron leakage from the grain boundaries of the polysilicon channel. This leakage is expected to worsen in future memory devices with increasing channel lengths. Such electrons may move toward higher-voltage regions of the channel adjacent to the selected word lines. See Figure 11 Vboost can vary for different channel regions based on the Vth of the corresponding memory cell. Vboost is proportional to Vpass - Vth. Therefore, the actual boost potential is lower than the ideal potential.

[0148] Figure 9B The illustration shows Figure 9ATable of voltages used when different types of programming interference occur. The first row indicates that for a NAND string in the programming mode (e.g., NAND string 710n), a positive voltage Vsgd is applied to the SGD transistor while Vbl = 0V to provide an SGD transistor in the on state. The second row indicates that for a NAND string in the x mode (e.g., NAND string 710n1), Vsgd is applied to the SGD transistor while a positive voltage Vddsa is applied to the bitline voltage to provide an SGD transistor in the non - on state. The third row indicates that for a NAND string in the y mode (e.g., NAND string 700n), 0V is applied to the SGD transistor and Vbl = 0V to provide an SGD transistor in the non - on state. The fourth row indicates that for a NAND string in the xy mode (e.g., NAND string 700n1), 0V is applied to the SGD transistor and Vbl = Vddsa to provide an SGD transistor in the non - on state.

[0149] Figure 10A Illustrates exemplary voltage signals during the pre - charge phase and the programming / boost phase of a programming operation, which provide countermeasures against programming interference as discussed Figure 9A herein. The vertical axis plots voltage and the horizontal axis plots time. The pre - charge phase and the programming / boost phase occur in a programming cycle, where the programming operation includes multiple successive programming cycles. A verification phase is also used in the programming cycle, as Figure 23 illustrated. Curve 1000 plots the voltage signal applied to both the selected and unselected wordlines from time t0 - t1. A positive voltage such as 2V can be used to allow the bitline voltage to pre - charge the channel.

[0150] For the selected wordline, curve 1001 from t2 - t6 plots the voltage increase from an initial level such as 0V to the programming voltage Vpgm and remains at Vpgm. The voltage can first increase from 0V to Vpass and then from Vpass to Vpgm. From an unspecified unselected wordline (e.g., an unselected wordline that is not the specified wordline), curve 1002 from t2 - t6 plots the voltage increase from an initial level such as 0V to Vpass and remains at Vpass. For the specified unselected wordline, curve 1003 from t2 - t6 plots the voltage increase from an initial level such as 0V to VpassL and remains at VpassL, where VpassL < Vpass. VpassL can be applied to wordlines spaced apart in a group of wordlines to create a drop in the boost level of the channel.

[0151] Figure 10BAn exemplary curve showing the channel voltage (Vch) versus location within a NAND string is plotted, using... Figure 10A Different voltage signals. The position in the NAND string extends from the first programmed (pgm.) WL at one end of the NAND string to the last programmed WL at the other end of the NAND string. For example, in the case of source-to-drain WL programming order and 96 word lines, the first programmed WL is WL0 at the source end, and the last programmed WL is WL95 at the drain end. WLn refers to the exemplary selected word line. On one side of WLn (e.g., below WLn in a block, such as in Figure 6 (Or 7A) word lines, which were programmed before the time WLn was programmed. This is indicated by "programmed" in the diagram. Therefore, Vch will be a function of Vth of the memory cell and the voltage across it. A higher Vth will result in a lower Vch, as mentioned. Vch varies significantly for these word lines due to the random data state programmed into the memory cells connected to them.

[0152] The word line on the other side of WLn (e.g., above WLn) is unprogrammed, meaning it wasn't programmed when WLn was programmed. This is indicated by "unprogrammed" in the diagram. Therefore, Vch will primarily be a function of voltage. When no programming interference countermeasures are used (curve 1013), Vch is consistent, and when programming interference countermeasures are used (curve 1020), it exhibits a periodic decrease.

[0153] The word lines below WLn (WL0-WLn-1) and above WLn (WLn+1 to the last word line) are, for example, Figure 6 and Figure 7A WL95 in the middle.

[0154] A programmed word line is a word line for which programming has occurred for the memory cells connected to it, according to the word line programming order of the block. Memory cells connected to a programmed word line can include both programmed and erased memory cells, typically in a random distribution of data states. An unprogrammed word line is a word line for which programming has not yet occurred for the memory cells connected to it, and therefore the memory cells are in an erased state. Furthermore, a programmed word line is a memory cell connected to it that has been programmed.

[0155] Curve 1010 represents the case where a nominal voltage Vpass is applied to all unselected word lines. This curve includes portion 1011 of the unselected word lines below WLn, portion 1012 of the selected word lines, and portion 1013 of the unselected word lines above WLn. Curve 1020 represents the case with programming interference countermeasures. VpassL is applied to the specified unselected word lines, and a nominal voltage Vpass is applied to the remaining unselected word lines between the specified unselected word lines. This curve includes portion 1021 of the unselected word lines below WLn, portion 1022 of the selected word lines, portion 1023 of the exemplary specified unselected word lines above WLn, and portion 1024 of the exemplary unspecified unselected word lines above WLn receiving Vpass. When using VpassL, a small decrease in overall Vch may occur.

[0156] For WLn, Vch is higher when using programmed interference countermeasures (curve 1022). Programmed interference can therefore be reduced.

[0157] Figure 11 The illustration shows the use of techniques such as combination. Figure 10A The boost in the NAND string channel during the programming interference countermeasures discussed. Figures 11 to 16 The figure includes a curve illustrating Vch relative to the NAND string location, ranging from the source side to the drain side, during programming when Vpgm is applied to the selected word line WLn. The figure also illustrates the layers of the NAND string, including a barrier oxide layer 663, a charge trapping layer 664, a tunneling layer 665, and a channel 660. Electron movement within the channel is also depicted, with electrons represented by linesd circles. Arrows indicate the direction of movement. The control gate line, including the word line and the select gate line, is adjacent to the layers of the NAND string. The voltage applied to the control gate line is also plotted. Additionally, Figure 11 Figure 16 provides a simplified example where all memory cells are assumed to be in an erased data state. This simplified example helps to illustrate the theory of programming interference countermeasures. Figure 10B The actual situation is shown, in which the memory cell connected to the source-side word line is programmed.

[0158] For example, the control gate lines and their voltages include: SGS (0V), WLDS (Vdummy), ..., WLn-11 to WLn-1 (Vpass), WLn (Vpgm), WLn+1 to WLn+11 (Vpass), ..., WLDD (Vdummy) and SGD (0) (0V). In one configuration, 0V <Vdummy<Vpass。

[0159] In this unselected NAND string, programming is suppressed and boost is encouraged by disconnecting the SGD and SGS transistors to float Vch. The voltage of WLn ramps up from 0V to Vpgm, resulting in a peak Vch of Vch in the channel region adjacent to WLn, which is Vch_max1 with programming interference countermeasures or Vch_max2 without them. The voltage of the unselected word lines ramps up from 0V to Vpass, resulting in Vch_nom in the adjacent channel regions, including the source-side channel region (curve 1101) and the drain-side channel region (curve 1102). Arrow 1103 illustrates an exemplary range of Vch in the source-side channel when the associated memory cell is programmed. Vch_nom is equal to Vpass multiplied by the word line-to-channel coupling ratio, for example, 0.8-0.9. The lower peak of Vch_max2 represents the case where all unselected word lines ramp up from 0V to the common pass voltage Vpass. The higher peaks in Vch_max1 indicate that some unselected word lines rise from 0V to VpassL while other word lines rise from 0V to Vpass. This can be combined with... Figures 12A to 16 The subject of discussion.

[0160] As mentioned, the channel experiences a boost through capacitive coupling due to the increased word line voltage. Furthermore, electrons in the grain boundaries of the polysilicon channel can move towards the high-voltage region of the channel adjacent to WLn. Electrons can also leak from SGS and SGD transistors into the channel and move towards WLn. As an example, an increase in electrons or negative charge at WLn will decrease the peak Vch from Vch_max1 to Vch_max2.

[0161] By applying VpassL to a specified word line, a periodic decrease in Vch can be generated, making it more difficult for electrons to reach the channel region adjacent to WLn. Advantageously, this programming interference countermeasure is performed without increasing Vpass. Increasing Vpass can lead to interference with memory cells connected to unselected word lines, as well as increased power consumption. Programming interference can thus be reduced, particularly for memory cells in 3D NAND strings. In the following combination Figures 12A to 16 The discussion provides various examples of periodic declines in Vch.

[0162] Figure 12A The illustration shows the use of, for example, combinations Figure 10AThe programming interference countermeasures discussed are boosting in the channel of a NAND string, where the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-6, WLn-9... and WLn+3, WLn+6, WLn+9...., such that WL_dVpass_init = 3 and WL_dVpass_period = 3. Recall that the parameter WL_dVpass_init specifies the position of the initially specified word line closest to the selected word line (e.g., a word line specified to receive a lower pass voltage to create a drop in the channel voltage that inhibits electron movement toward WLn). The parameter WL_dVpass_period specifies the period or interval of the other specified word lines relative to the initially specified word line.

[0163] By applying VpassL to a specified word line, a corresponding drop in the channel voltage is generated. For example, drops 1201, 1202, and 1203 are generated in channel regions 1211, 1213, and 1215, respectively, adjacent to WLn-9, WLn-6, and WLn-3. Similarly, drops 1204, 1205, and 1206 are generated in channel regions 1219, 1221, and 1223, respectively, adjacent to WLn+3, WLn+6, and WLn+9.

[0164] The "X" in these channel regions indicates a barrier to electron movement caused by a drop in voltage. Higher nominal channel voltages are generated in the channel regions between the specified word lines. For example, nominal channel voltages are generated in channel regions 1210 adjacent to WL0 to WLn-10, in channel regions 1212 adjacent to WLn-8 and WLn-7, in channel regions 1214 adjacent to WLn-5 and WLn-4, and in channel regions 1216 adjacent to WLn-2 and WLn-1. Similarly, as an example, nominal channel voltages are generated in channel regions 1218 adjacent to WLn-1 and WLn-2, ​​in channel regions 1220 adjacent to WLn+4 and WLn+5, in channel regions 1222 adjacent to WLn+7 and WLn+8, and in channel regions 1224 adjacent to WLn+10 to the last word line WL95 or WL159.

[0165] Electrons will tend to be trapped in the channel with a higher Vch region, between the decreases in Vch, and remain close to the interface between the polysilicon channel and the tunneling oxide. Due to the potential barrier created by the decrease in the channel, electron movement towards the channel region 1217 adjacent to WLn will be blocked. Therefore, the decrease in the boost potential at WLn is reduced, and the peak voltage Vch_max1 is achieved to minimize programming interference. In general, the decrease can be generated by applying VpassL to a word line surrounded by multiple word lines receiving Vpass. The decrease can be generated by applying VpassL to multiple word lines surrounded by word lines receiving Vpass.

[0166] In one option, the word line voltage pattern can be extended across the entire NAND string. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL1, WL4, WL7, WL10, WL13, WL16, WL19, WL22, WL25, WL28, WL31, WL34, WL37, WL43, WL46, WL49, WL52, WL55, WL58, WL61, WL64, WL67, WL70, WL73, WL76, WL79, WL82, WL85, WL88, WL91, and WL94.

[0167] In another option, the word line voltage mode can extend on unprogrammed word lines but not on programmed word lines. For example, see... Figure 12B and Figure 12C .

[0168] on the whole, Figures 12A to 16 The pattern shown is for simplicity and represents a portion of the NAND string, but it can be applied to the entire NAND string.

[0169] The word line voltage pattern can extend over most of the NAND string length, on both the source and drain sides, or only on the source or drain side without extending on both sides. Similarly, the periodic drop in the channel can extend over most of the NAND string length. Other options are also possible.

[0170] Arrows 1232 and 1233 represent WL_dVpass_init, which consists of three word lines. That is, on the source and drain sides, the unselected word line of the receive VpassL closest to WLn is three word lines away from WLn. Furthermore, the unselected word line of the receive VpassL closest to WLn is separated from WLn by two intermediate word lines. Arrows 1230, 1231, 1234, and 1235 represent WL_dVpass_period, which also consists of three word lines. Thus, in this example, WL_dVpass_period = WL_dVpass_init. Arrows 1230 and 1231 indicate that WLn-9 is three word lines away from WLn-6, and WLn-6 is three word lines away from WLn-3. In other words, regarding WLn-3, the closest unselected word line to the received VpassL for WLn is the word line to receive VpassL every three word lines after WLn-3. Thus, VpassL is applied at intervals or periods of three word lines.

[0171] `WL_dVpass_init` can be the same or different for the source and drain sides. `WL_dVpass_period` can also be the same or different for the source and drain sides. `WL_dVpass_period` can also be fixed or varied on the source and / or drain sides. For example, Figure 15 and Figure 16 The variation of WL_dVpass_period is shown.

[0172] The word line receiving VpassL can be expressed as follows: WLn+ / -(WL_dVpass_init+α* WL_dVpass_period), where α=0,1,2,3,4…. Other examples are provided below.

[0173] In one option, WLn-1 and / or WLn+1 receive a specific pass voltage because they are adjacent to WLn. For example, WLn-1 and / or WLn+1 may receive a reduced pass voltage, which is less than Vpass and may be greater than VpassL. The lower pass voltage can be used on these word lines because of the high Vpgm edge field on WLn.

[0174] In this example, among the unselected word lines on the drain side of the selected word lines (WLn to WL95), the voltage is lower for the specified word lines (WLn+3, WLn+6, WLn+9...) separated by intervals (as shown by arrows 1234 and 1235) along the NAND string than for the word lines (WLn+4, WLn+5, WLn+7, WLn+8) between the specified word lines.

[0175] Furthermore, the specified word lines are separated along the NAND string at equal intervals (either three word lines separated or two word lines in between). Additionally, among the specified word lines, the nearest word line (WLn-3, WLn+3) of the selected word line is N (=3) word lines away from the selected word line, with each interval comprising N word lines.

[0176] Among the unselected word lines on the source and / or drain sides of the selected word lines, the voltage for the specified word lines spaced apart along the NAND string is lower than that for the word lines between the specified word lines.

[0177] Figure 12B The illustration shows the use of, for example, combinations Figure 12A The programming interference countermeasures discussed are boosting in the channel of a NAND string, where the countermeasures involve applying VpassL to specified word lines, including WLn+3, WLn+6, WLn+9..., such that WL_dVpass_init = 3 and WL_dVpass_period = 3. This scheme is similar to... Figure 12A The scheme differs in that the drop in Vch occurs on the drain side of WLn but not on the source side. In this example, the drain-side word line is unprogrammed, resulting in a consistent drop in Vch. In contrast, Vch fluctuates randomly based on the programmed data state on the source side of WLn, such as... Figure 10B As shown, this makes the effect of the decrease less predictable. Random variations in Vch on the source side can produce a decrease in Vch, which suppresses electron movement without applying VpassL on the source side.

[0178] This assumes that the word line programming order begins on the source side of the NAND string and ends on the drain side. Other programming orders are possible, such as starting on the drain side of the NAND string and ending on the source side. In any case, a decrease in Vch can occur on the unprogrammed side of WLn but not on the programmed side.

[0179] Arrow 1241 represents WL0 to WLn-1, which receive Vpass. This creates a corresponding channel region 1240, where electrons can move toward WLn. Recall, arrow 1103 illustrates an exemplary range of Vch in the source-side channel when the associated memory cell is programmed.

[0180] In another option, VpassL is applied to both the programmed and unprogrammed specified word lines, but based on the theory that providing a shorter distance between Vch drops on the unprogrammed side of WLn is more important than on the programmed side of WLn, the spacing between the unprogrammed specified word lines is smaller than the spacing between the programmed specified word lines.

[0181] In one option, the word line voltage pattern can extend across the entire drain side of WLn. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL43, WL46, WL49, WL52, WL55, WL58, WL61, WL64, WL67, WL70, WL73, WL76, WL79, WL82, WL85, WL88, WL91, and WL94.

[0182] Figure 12C The illustration shows the use of, for example, combinations Figure 12A The programming interference countermeasures discussed are boosting in the channel of the NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-6, WLn-9..., such that WL_dVpass_init = 3 and WL_dVpass_period = 3.

[0183] This scheme is similar to Figure 12A The scheme differs from the one where the drop in Vch occurs on the source side of WLn and not on the drain side. In this example, the source-side word line is unprogrammed.

[0184] This assumes that the word line programming sequence begins on the drain side of the NAND string and ends on the source side.

[0185] Arrow 1241a represents WLn+1 to WL95, which receive Vpass. This creates the corresponding channel region 1240a, where electrons can move toward WLn. Arrow 1103 illustrates an exemplary range of Vch in the drain-side channel when the associated memory cell has been programmed. Arrows 1233a, 1234a, and 1235a represent WL_dVpass_init, which consists of three word lines.

[0186] In one option, the word line voltage pattern can extend across the entire source side of WLn. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL1, WL4, WL7, WL10, WL13, WL16, WL19, WL22, WL25, WL28, WL31, WL34, and WL37.

[0187] By applying VpassL to a specified word line, a corresponding drop in the channel voltage is generated. For example, drops 1204a, 1205a, and 1206a are generated in the channel regions 1219a, 1221a, and 1223a adjacent to WLn-3, WLn-6, and WLn-9, respectively.

[0188] A nominal channel voltage is generated in the channel regions 1218a adjacent to WLn-1 and WLn-2, ​​1220a adjacent to WLn-4 and WLn-5, 1222a adjacent to WLn-7 and WLn-8, and 1224a adjacent to WL0 to WLn-10.

[0189] Figure 13 The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boosting in the channel of a NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-4, WLn-7, WLn-10... and WLn+4, WLn+7, WLn+10..., such that WL_dVpass_init = 4 and WL_dVpass_period = 3. VpassL is applied to WLn-10, WLn-7, WLn-4, WLn+4, WLn+7, and WLn+10 to produce drops of 1301, 1302, 1303, 1304, 1305, and 1306 in Vch at channel regions 1311, 1313, 1315, 1319, 1321, and 1323, respectively. Vpass is applied to the remaining unselected word lines so that channel regions 1310, 1312, 1314, 1316, 1318, 1320, 1322, and 1324 are in Vch_nom.

[0190] Arrows 1332 and 1333 represent WL_dVpass_init, which has four word lines, and arrows 1330, 1331, 1334, and 1335 represent WL_dVpass_period, which has three word lines.

[0191] In this example, the specified word lines are separated by intervals that each include at least three word lines.

[0192] Furthermore, among the specified word lines, the closest word line (WLn-4, WLn4) of the selected word line is N (=4) word lines away from the selected word line, and each is spaced by M (=3) word lines, where N≠M.

[0193] In one option, the word line voltage pattern can be extended across the entire NAND string. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL0, WL3, WL6, WL9, WL12, WL15, WL18, WL21, WL24, WL27, WL30, WL33, WL36, WL44, WL47, WL50, WL53, WL56, WL59, WL62, WL65, WL68, WL71, WL74, WL77, WL80, WL83, WL86, WL89, and WL92.

[0194] Figure 14 The illustration shows the use of, for example, combinations Figure 10A The programming interference countermeasures discussed are boosting in the channel of a NAND string, wherein the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-7, WLn-11... and WLn+3, WLn+7, WLn+11..., such that WL_dVpass_init = 3 and WL_dVpass_period = 4. VpassL is applied to WLn-11, WLn-7, WLn-3, WLn+3, WLn+7, and WLn+11 to produce drops 1401, 1402, 1403, 1404, 1405, and 1406 in Vch of channel regions 1411, 1413, 1215, 1219, 1421, and 1423, respectively. Vpass is applied to the remaining unselected word lines so that channel regions 1410, 1412, 1414, 1216, 1218, 1420, 1422, and 1424 are in Vch_nom.

[0195] Arrows 1232 and 1233 represent WL_dVpass_init, which has three word lines, and arrows 1430, 1431, 1434, and 1435 represent WL_dVpass_period, which has four word lines.

[0196] In one option, the word line voltage pattern can be extended across the entire NAND string. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL1, WL5, WL9, WL13, WL17, WL21, WL25, WL29, WL33, WL37, WL43, WL47, WL51, WL55, WL59, WL63, WL67, WL71, WL75, WL79, WL83, WL87, and WL91.

[0197] Figure 15 The illustration shows the use of, for example, combinations Figure 10AThe programming interference countermeasures discussed are boosting in the channel of a NAND string, where the countermeasures involve applying VpassL to specified word lines, including WLn-3, WLn-7, WLn-12... and WLn+3, WLn+7, WLn+12..., such that the specified word lines are spaced apart along the NAND string with gradually increasing intervals in the direction of movement away from the selected word lines. This scheme is based on the theory that smaller intervals between specified word lines closer to WLn are more important than those further away from WLn, and its implementation can be simplified by reducing the number of word lines receiving VpassL. VpassL is applied to WLn-12, WLn-7, WLn-3, WLn+3, WLn+7, and WLn+12 to produce drops in Vch to 1501, 1502, 1503, 1504, 1505, and 1506, respectively, in channel regions 1511, 1513, 1515, 1519, 1521, and 1523. Vpass is applied to the remaining unselected word lines to bring channel regions 1510, 1512, 1514, 1516, 1518, 1520, 1522, and 1524 to a higher voltage Vch_nom.

[0198] Arrows 1532 and 1533 indicate WL_dVpass_init = 3, arrows 1531 and 1534 indicate WL_dVpass_period = 4, and arrows 1530 and 1535 indicate WL_dVpass_period = 5. The specified word lines are therefore separated by word lines 3, 4, 5, ... with increasing distances from WLn on the source and drain sides of WLn.

[0199] In another option, on the drain or source side, but not on both, the specified word lines are spaced with gradually increasing intervals along the NAND string in the direction of movement away from the selected word lines.

[0200] In one option, the word line voltage pattern can be extended across the entire NAND string. For example, with word lines WL0 to WL95 and WLn = 40, the word lines receiving VpassL can be: WL7, WL15, WL22, WL28, WL33, WL37, WL43, WL47, WL52, WL58, WL65, WL73, WL82, and WL92.

[0201] Figure 16 The illustration shows the use of, for example, combinations Figure 10AThe programming interference countermeasure under discussion is the boosting in the channel of the NAND string, where the countermeasure involves applying VpassL-, VpassL, and VpassL+ to specified word lines, which respectively include WLn-2, WLn-5, WLn-9, and are respectively applied to WLn+2, WLn+5, WLn+9, such that the reduced pass voltages of the specified word lines gradually increase for the specified word lines that are gradually farther from the selected word line. VpassL-, VpassL, and VpassL+ (where VpassL- < VpassL < VpassL+) are exemplary pass voltages, which are less than Vpass. Three exemplary reduced pass voltages (<Vpass) are illustrated, but there can be two or more of them.

[0202] VpassL+ is applied to WLn-9 and WLn+9 to respectively produce drops 1601 and 1606 in Vch of channel regions 1511 and 1523. VpassL is applied to WLn-5 and WLn+5 to respectively produce drops 1502 and 1505 in Vch of channel regions 1513 and 1521. VpassL- is applied to WLn-2 and WLn+2 to respectively produce drops 1603 and 1604 in Vch of channel regions 1515 and 1519.

[0203] Vpass is applied to the remaining unselected word lines to make channel regions 1510, 1512, 1514, 1516, 1518, 1520, 1522, and 1524 at Vch_nom.

[0204] Arrows 1532 and 1533 represent WL_dVpass_init, which are two word lines, arrows 1531 and 1534 represent WL_dVpass_period = three word lines, and arrows 1530 and 1535 represent WL_dVpass_period = four word lines.

[0205] In one option, the pattern of the word line voltages can extend across the entire NAND string. For example, in the case of word lines WL0 to WL95 and WLn = 40, the word lines that receive VpassL can be: WL7, WL15, WL22, WL28, WL33, WL37, WL43, WL47, WL52, WL58, WL65, WL73, WL82, and WLn92.

[0206] The control circuit can be configured with parameters such as dVpass, WL_dVpass_init, and WLn+_dVpass_period to achieve the periodic word line biasing of the techniques described herein. Also see Figures 22B to Figure 22DThe parameter table is provided. These parameters can be optimized based on testing. Generally, if dVpass is too high (VpassL too low), gate-induced drain leakage may occur, generating many electron-hole pairs in the channel, leading to a high probability of a peak Vch at WLn. If dVpass is too low (VpassL too high), the potential barrier created by the periodic decrease in Vch may not be large enough to suppress electron movement in the channel. See also... Figure 18 If WL_dVpass_init is too low, such as one or two word lines, the initially specified word line may be too close to WLn, causing Vch at WLn to be pulled down. See also Figure 19 If WL_dVpass_period is too low, the number of word lines in the specified receive VpassL will be too large, potentially pulling down the overall Vch. See also Figure 20 .

[0207] exist Figures 17A to 17D In this context, the WL programming order is from the source side of the block to the drain side. Furthermore, the lower word line is WL0 or within a few word lines from the source end of the block, the lower-middle WL is approximately 25% between the source and drain ends, the upper-middle WL is approximately 75% between the source and drain ends, and the upper WL is at the drain end of the block or within a few word lines from the drain end. Additionally, data is based on the block, including the interface between the top and bottom halves of the block. The plotted time range corresponds to... Figure 10A It includes a pre-charge phase and a programming / boost phase. Additionally, dVpass = 0.8V, WL_dVpass_init = 4 word lines, and WL_dVpass_init = 4 word lines.

[0208] Figure 17A The diagram illustrates the situation when WLn is the lower WL, according to... Figure 10A The curves represent the channel voltage versus time for the voltage signal. Curves 1700 and 1701 show Vch with and without programmed interference countermeasures, respectively. When programmed interference countermeasures are used, the peak Vch increases significantly.

[0209] Figure 17B The diagram illustrates the situation when WLn is a lower-middle WL, based on... Figure 10A The voltage signal is plotted as channel voltage versus time. Curves 1710 and 1711 show Vch with and without programmed interference countermeasures, respectively. As before, the peak Vch increases significantly when programmed interference countermeasures are used.

[0210] Figure 17C The diagram illustrates the situation when WLn is a mid-to-high WL, based on... Figure 10AThe voltage signal is plotted as a channel voltage versus time. Curves 1720 and 1721 show Vch with and without programmed interference countermeasures, respectively. As before, the peak Vch increases significantly when programmed interference countermeasures are used.

[0211] Figure 17D The diagram illustrates the situation when WLn is above WL, according to... Figure 10A The voltage signal is plotted as channel voltage versus time. Curves 1730 and 1731 plot Vch with and without programming interference countermeasures, respectively. In this case, the peak Vch does not increase when programming interference countermeasures are used. This indicates that the countermeasures are not advantageous when WLn is relatively close to the drain endpoint of the NAND string (e.g., within a subset of word lines adjacent to the drain endpoint), where the subset comprises no more than 5-10% of a set of word lines connected to the NAND string.

[0212] Figures 21A to 21C The paper illustrates the basis for the analysis described herein. Figures 17A to 17D This section describes exemplary implementations of known programming interference countermeasures. In one approach, for the WLn position near the drain endpoint of the NAND string, the programming interference countermeasure can be gradually eliminated or not used. In another approach, the portion of the NAND string subjected to programming interference countermeasures is a function of WLn.t.

[0213] Figure 18 The channel voltage versus time curves for different values ​​of dVpass are plotted based on the voltage signal in Figure 10A. The curves include "nom." to indicate the nominal or comparative case where no programming interference countermeasures are used. The lowest peak Vch is for this case. The next relatively high peak Vch corresponds to dVpass = 0.4V. The next relatively high peak Vch corresponds to dVpass = 0.8V. The highest peak Vch corresponds to dVpass = 1.2-2.0V. The data is based on WLn = 40, WL_dVpass_init = 4 word lines. The boost potential increases with increasing dVpass, but saturates as dVpass reaches 1.2V, thus not improving the obstruction of electron movement in the channel. dVpass is set such that VpassL is a positive voltage. In one implementation, the voltage (VpassL) applied to the word line adjacent to the channel region with a periodic decrease is a positive voltage and is no more than 2V lower than the voltage (Vpass) applied to the word lines of the remaining regions adjacent to the channel.

[0214] Figure 19 It is illustrated, according to Figure 10AThe voltage signal is plotted as a channel voltage versus time for different values ​​of WL_dVpass_init, WLn, and the number of word lines between the nearest word line to the received VpassL. In this example, WLn = 90 out of 160 word lines. The curve includes "40WL or nom.", indicating WL_dVpass_init = 40 or no programming interference countermeasures are used. Peak Vch is lowest in this case. The next higher peak Vch corresponds to WL_dVpass_init = 15 word lines. The next higher peak Vch corresponds to WL_dVpass_init = 2 word lines. The highest peak Vch corresponds to WL_dVpass_init = 3-5 word lines. WL_dVpass_init = 2 word lines may be less than optimal. The boost level increases with increasing WL_dVpass_init until WL_dVpass_init reaches 3-5 word lines. The boost level then decreases with further increases in WL_dVpass_init.

[0215] Figure 20 It is illustrated, according to Figure 10A The voltage signal is plotted as channel voltage versus time for different values ​​of WL_dVpass_period, the interval between word lines receiving VpassL, and the channel voltage versus time. In this example, there are 160 word lines, WLn = 40, dVpass = 0.8V, and WL_dVpass_init = 4 in this example. The curve includes "nom.", indicating the nominal case where no programming interference countermeasures are used. The peak Vch is the lowest for this case. The next relatively high peak Vch corresponds to WL_dVpass_period = 3 word lines. The next relatively high peak Vch corresponds to WL_dVpass_period = 5 word lines. The next relatively high peak Vch corresponds to WL_dVpass_period = 8 word lines. The highest peak Vch corresponds to WL_dVpass_period = 20 word lines, although it is roughly the same for 5, 8, and 20 word lines. The boost potential increases with larger periods and almost saturates when the period exceeds 8 word lines. This indicates that having fewer word lines with a bias of VpassL can be advantageous for optimizing the peak Vch. However, having a smaller period and thus applying VpassL to more word lines can reduce Vpass interference, where Vpass is high enough to interfere with memory cells connected to unselected word lines.

[0216] Figure 21A The curve of WL_dVpass_period relative to the WLn position is plotted. The WLn position refers to the position of WLn among the multiple word lines of the NAND string connected to the block. The WL position extends from the first WL programmed to the last WL programmed.

[0217] Figures 17A to 17D As shown, when WLn is on the drain side of the NAND string, programming interference countermeasures may lose their effectiveness. Accordingly, one approach is to set the parameters of the programming interference countermeasures based on the position of the selected word line WLn among the multiple word lines of the block and based on the WL programming order.

[0218] In this case, WL_dVpass_period is the number N1 when WLn is between the first programmed word line and the transition word line WLx, and the number N2>N1 when WLn is between WLx or between WLx and the last programmed word line. WLx can be within a subset of word lines adjacent to the last programmed word line, where the subset includes no more than 5-10% of a set of word lines connected to the NAND string. For example, in the case of 96 word lines, and assuming a source-to-drain programming order, WLx could be WL85-WL90. Increasing WL_dVpass_period reduces the number of word lines receiving VpassL to minimize the reduction in overall Vch when using VpassL, such as... Figure 10B What I saw.

[0219] In this example, the interval or period is an increasing function of the distance from the first programmed WL to the selected word line.

[0220] Figure 21B The curves of VpassL and dVpass versus the position of WLn are plotted. Since programming interference countermeasures are less effective when WLn is closer to the last programmed word line, VpassL can be increased (and dVpass can be decreased) when WLn is closer to the last programmed word line. Therefore, VpassL and dVpass can be set based on the position of WLn. In this case, VpassL = VpassL- when WLn is between the first programmed WL and the transition word line WLx, and VpassL = VpassL+ when WLn is between WLx or between WLx and the last programmed word line, where VpassL- <VpassL+。

[0221] In this example, the through voltage of the specified word line is an increasing function of the distance of the selected word line from the first programmed WL.

[0222] Alternatively, nominal techniques can be used when WLn is close to the last programmed WL.

[0223] Figure 21CIllustrates a curve of the portion of a NAND string experiencing programming interference countermeasures versus the WLn position. As mentioned, as the WLn position becomes closer to the last programmed WL, the programming interference countermeasures can be phased out. In one scenario, the portion of the NAND string experiencing programming interference countermeasures on the drain side of WLn (and adjacent to WLn) is a function of the WLn position. For example, the portion of the NAND string experiencing programming interference countermeasures on the drain side of WLn can be a decreasing function of the distance between WLn and the first programmed WL. That is, as the distance becomes smaller, this portion becomes smaller. Various options are possible.

[0224] In one scenario, this portion is 100% when WLn < WLx (curve 2110), this portion is 0% when WLn ≥ WLx (curve 2114), or this portion is a non - zero portion such as 50% when WLn ≥ WLx (curve 2113). In another scenario, this portion is less than 100% when WLn < WLx, such as 75% (curve 2111). In another option, as WLn moves closer to the drain end, this portion gradually decreases (curve 2112).

[0225] On one side of the unselected NAND string, the programming interference countermeasures can create a periodic decrease in a portion of the unselected NAND string, for example where this portion is a decreasing function of the distance between the selected word line and the first programmed WL.

[0226] Figures 21D to 21F Illustrates different portions of a NAND string experiencing programming interference countermeasures as a function of different WLn positions, which is consistent with Figure 21C As previously discussed, for the portion of the NAND string experiencing programming interference countermeasures, a periodic decrease is created in the corresponding channel region. In these examples, the WL programming order is from the source side to the drain side. "Distance" refers to, for example, the distance in terms of the number of word lines or the physical distance between WLn and the first programmed WL.

[0227] Figure 21D Illustrates a NAND string channel where seventy - five percent of the drain - side word lines experience programming interference countermeasures. The NAND string channel includes a source - side region 2120 of WLn that may not experience programming interference countermeasures, a drain - side region 2121 of WLn that experiences programming interference countermeasures (including 75% of all drain - side word lines), and a drain - side region 2122 of WLn that does not experience programming interference countermeasures (including 25% of all drain - side word lines). The dashed lines refer to the channel voltage in different regions. The periodic decrease in the channel voltage is in region 2121 but not in regions 2120 and 2122. Conversely, a fixed channel voltage can exist in regions 2120 and 2122.

[0228] Figure 21E The diagram illustrates a NAND string channel where 50% of the drain-side word lines are subject to programming interference countermeasures. The NAND string channel includes a source-side region 2130 of the WLn (WLn) not subject to programming interference countermeasures, an adjacent drain-side region 2131 of the WLn subject to programming interference countermeasures (comprising 50% of all drain-side word lines), and a non-adjacent drain-side region 2132 of the WLn not subject to programming interference countermeasures (comprising 50% of all drain-side word lines). Dashed lines represent channel voltages in the different regions. Periodic drops in channel voltage occur in region 2131 but not in regions 2130 and 2132. Conversely, a fixed channel voltage can exist in regions 2130 and 2132.

[0229] Figure 21F The diagram illustrates a NAND string channel where 0% of the drain-side word lines are subject to programming interference countermeasures. The NAND string channel includes source-side region 2140 and drain-side region 2141 of the WLn, which are not subject to programming interference countermeasures. Dashed lines indicate the channel voltage in the different regions. Periodic drops are absent. Conversely, a fixed channel voltage may exist in regions 2140 and 2141.

[0230] Figure 22A The process of programming a block is illustrated. Step 2200 initiates the programming loop in the programming operation. Programming operations can result in different Vth levels for memory cells, such as... Figure 8 As illustrated in the diagram. Step 2201 includes performing a pre-charge phase. Step 2202 includes setting parameters for the programming / boost phase, including dVpass, WL_dVpass_init, and WL_dVpass_period. Step 2202a includes taking into account the WLn position. As discussed, these parameters can be optimized based on factors such as the WLn position. See also the diagram showing the parameter table. Figures 22B to 22D This cross-references to codewords accessed by control circuitry. For example, parameters can also be optimized at the block or chip level. Step 2203 includes a programming / boost phase, which involves ramping up the voltages of selected and unselected word lines to provide periodic drops in the boost along the NAND string channel, as discussed. Step 2204 includes a verification phase. Decision step 2205 determines whether to proceed to the next programming cycle. If decision step 2205 is true, then proceed to step 2200 again. If decision step 2205 is false, the programming operation is completed in step 2206. Figure 23 Exemplary details of the voltage signals in the precharge phase 2307, programming / boost phase 2308, and verification phase 2309 are provided.

[0231] Figure 22B It is illustrated for Figure 22AThe table of dVpass values ​​in step 2202. The control circuit can access one of eight different values ​​using a 3-bit codeword. For example, codewords 000, 001, 010, 011, 100, 101, 110, and 111 correspond to dVpass = 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, 1.8, and 2.0V, respectively.

[0232] Figure 22C It is illustrated for Figure 22A Step 2202 involves a table of values ​​for WL_dVpass_init. As before, the control circuitry can access one of eight distinct values ​​using a 3-bit codeword. For example, codewords 000, 001, 010, 011, 100, 101, 110, and 111 correspond to word lines WL_dVpass_init = 3, 4, 5, 6, 7, 8, 9, and 10, respectively.

[0233] Figure 22D It is illustrated for Figure 22A Step 2202 refers to the table of WL_dVpass_period values. As before, the control circuit can use a 3-bit codeword to access one of eight different values. For example, codewords 000, 001, 010, 011, 100, 101, 110, and 111 correspond to word lines WL_dVpass_period = 3, 4, 5, 6, 7, 8, 9, and 10, respectively.

[0234] Figure 23 Exemplary voltage signals used for programming operations according to Figure 22 are illustrated. The vertical dimension represents voltage and the horizontal dimension represents time, from time point t0 to t12. The voltages illustrated are examples. The illustrated time period corresponds to a programming cycle and includes a precharge phase 2307 (t0-t2), a programming / boost phase 2308 (t2-t8), and a verification phase 2309 (t9-t12). Voltage signals 2300, 2310, 2320, 2330, 2340, and 2350 illustrate VWLn (voltage of the selected word line), VWL_unsel (voltage of the unselected word line), Vsgd (voltage of the SGD transistor), Vsgs (voltage of the SGS transistor), Vbl (bit line voltage), and Vsl (source line voltage), respectively.

[0235] The precharge phase is used to charge the channels of the NAND string. During the precharge phase, curve 2301 illustrates a positive voltage, such as 1-2V, for VWLn. During the programming / boost phase, VWLn increases from 0V at t3 (curve 2302) to the pass voltage Vpass (curve 2304), and then to the peak level Vpgm at t5 (curve 2305). VWLn then decreases back to 0V at t6 before the verification phase 2309. During the verification phase, a verification signal 2306 is applied to the selected word line, and the selected memory cell is sensed during different verification voltages of the verification signal. In this example, the verification voltages are VvE, VvF, and VvG.

[0236] For VWL_unsel, curve 2311 illustrates a positive voltage such as 1-2V during the precharge phase. During the programming / boost phase, VWL_unsel increases from 0V (curve 2312) to Vpass (curve 2314) or VpassL (curve 2315) and remains at that level during Vpgm application. As mentioned, VpassL is applied to the specified word line, and Vpass is applied to the remaining word lines between the specified word lines. VWL_unsel is set to Vread during the verification phase 2309, which can be equal to Vpass.

[0237] For Vsgd, curve 2321 plots a positive voltage, such as 4-6V, for all SGD transistors in the block. This allows Vbl to be passed through the channel. For the SGD transistors of the selected sub-block, curve 2322 plots Vsgd_sel, for example, 2.5V during the programming / boost phase. Vsgd_sel is high enough that the selected NAND string receiving the programming enable voltage Vbl_en = 0V will provide the associated SGD transistor with an on state. For the SGD transistors of the unselected sub-block, curve 2323 plots Vsgd_unsel, for example, 0V during the programming / boost phase. This provides the SGD transistor with an off state for the unselected NAND string receiving the programming suppressor voltage Vbl_inh. This allows the associated channel to be boosted via capacitive coupling as VWLn and VWL_unsel ramp up from 0V to Vpass or VpassL. This is in addition to the boost from the precharge phase. Curve 2324 shows Vsgd_sel at an elevated level, such as 4-6V, during the verification phase to allow sensing to occur in the associated NAND string. Curve 2325 shows Vsgd_unsel at 0V during the verification phase because no sensing occurs in the associated NAND string.

[0238] For Vsgs, in one configuration, all SGS transistors in the block are connected and receive the same voltage. During the pre-charge phase, curve 2331 illustrates a positive voltage, such as 4-6V, for all SGS transistors in the block. This allows voltage to pass from the substrate to the channel.

[0239] Curve 2334 illustrates Vsgs = 0V during the programming / boost phase. Curve 2335 shows Vsgd at a raised level, such as 4-6V, during the verification phase to allow sensing to occur in the selected NAND string.

[0240] Vbl represents the bit line voltage, which can be set separately for selected and unselected NAND strings. During the precharge phase, curve 2341 illustrates the positive precharge voltage Vbl_pc, such as 2V for the selected NAND string. Curve 2343 illustrates 0V for the bit line connected to an unselected NAND string. During the programming / boost phase, curve 2342 illustrates, for example, a programming suppression voltage Vbl_inh = 1.5V for an unselected NAND string, and curve 2343 illustrates, for example, a programming enable voltage Vbl_en = 0V for the selected NAND string. Curve 2344 shows, for example, Vbl = 0.5V during the verification phase.

[0241] For Vsl, during the precharge phase, in the first time period from t0 to t1, curve 2351 illustrates a positive precharge voltage, such as 2V. During the programming / boost phase, curve 2354 illustrates a positive Vsl voltage to help keep the SGS transistor in a non-conducting state. Vsl can be a small positive voltage during the verification phase, as illustrated by curve 2355.

[0242] For purposes of illustration and description, the foregoing detailed description of the invention has been provided. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in accordance with the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments with various modifications suited to the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory device, comprising: A control circuit is configured to be connected to a plurality of word lines, the plurality of word lines being connected to memory cells in a NAND string and including selected word lines and unselected word lines, the NAND string including a channel; and A memory interface is connected to the control circuit, which is configured to issue commands via the memory interface to apply a plurality of voltage signals to the plurality of word lines, thereby boosting the voltage of the channel. The plurality of voltage signals include a programming voltage signal applied to selected word lines and a voltage signal that increases from a corresponding initial voltage to a pass voltage, wherein, among the unselected word lines, the pass voltage is lower for specified word lines spaced apart along the NAND string than for word lines between specified word lines. and The voltage across the specified word line is an increasing function of the distance between the selected word line and the first programmed word line among the plurality of word lines.

2. The memory device of claim 1, wherein: The specified word lines are spaced equally along the NAND string; and Each of the equal intervals includes at least three word lines.

3. The memory device of claim 1, wherein: Among the specified word lines, the word line closest to the selected word line is N word lines away from the selected word line, and each of the intervals includes M word lines, where N≠M.

4. The memory device of claim 1, wherein: Among the specified word lines, the word line closest to the selected word line is N word lines away from the selected word line, and each of the intervals includes N word lines.

5. The memory device of claim 1, wherein: The specified word lines include unprogrammed word lines.

6. The memory device of claim 1, wherein: The interval is an increasing function of the distance between the selected word line and the first programmed word line among the plurality of word lines.

7. The memory device of claim 1, wherein: The pass voltage applied to the word lines between the specified word lines is no more than 2V higher than the pass voltage applied to the specified word lines.

8. The memory device of claim 1, wherein: The specified word lines are spaced apart by gradually increasing intervals along the NAND string in the direction of moving away from the selected word line.

9. The memory device of claim 1, wherein: The voltage across the specified word line gradually increases as the specified word line moves further away from it.

10. A method for operating a memory device, comprising: In the programming operation, a programming voltage signal is applied to a selected word line, the selected word line and an unselected word line being among a plurality of word lines connected to the selected NAND string and the unselected NAND string, wherein the unselected NAND string includes a channel; and During the application of the programming voltage signal, a voltage signal is applied to the unselected word line, and the voltage signal applied to the unselected word line increases from a corresponding initial voltage to a corresponding pass voltage, resulting in a periodic drop in the boost in the channel; and Among the unselected word lines, the voltage across the specified word lines spaced apart along the NAND string is lower than that across the word lines between the specified word lines. and The voltage across the specified word line is an increasing function of the distance between the selected word line and the first programmed word line among the plurality of word lines.

11. The method of claim 10, wherein: The periodic descent is adjacent to unselected word lines separated along the unselected NAND string; and The unselected word lines adjacent to the periodically decreasing number are separated from each other by at least two word lines in between.

12. The method of claim 10, wherein: The periodic decline occurs in the unprogrammed portion of the unselected NAND string.

13. The method of claim 12, wherein: The portion is a decreasing function of the distance between the selected word line and the first programmed word line among the plurality of word lines.

14. The method of claim 12, wherein: The portion is on the drain side of the selected word line.

15. A memory device, comprising: NAND strings consist of multiple memory cells and channels; as well as Multiple word lines are connected to the memory cells, each word line being adjacent to a corresponding region of the channel and configured to carry a voltage signal that boosts the voltage of the corresponding region of the channel, the channel having a voltage that periodically decreases along the length of the NAND string; and When a programming voltage is applied to a selected word line among the plurality of word lines, the periodic drop occurs in the corresponding region of the channel adjacent to an unselected word line among the plurality of word lines; and During the application of the programming voltage signal, a voltage signal is applied to the unselected word line, and the voltage signal applied to the unselected word line increases from a corresponding initial voltage to a corresponding pass voltage, resulting in a periodic drop in the boost in the channel; and Among the unselected word lines, the voltage across the specified word lines spaced apart along the NAND string is lower than that across the word lines between the specified word lines. and The voltage across the specified word line is an increasing function of the distance between the selected word line and the first programmed word line among the plurality of word lines.

16. The memory device of claim 15, wherein: The periodic decrease occurs over most of the length of the NAND string.

17. The memory device of claim 15, wherein: The voltage of the word line adjacent to the region of the channel with the periodic drop is a positive voltage and is no more than 2V lower than the voltage of the word line adjacent to the rest of the channel.

18. The memory device of claim 15, wherein: The voltage of a word line adjacent to the region of the channel with the periodic drop is a function of the position of the selected word line among the plurality of word lines.

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