Row Erase Feature, Associated Methods, and Systems for Memory Devices

Abstract

This application relates to a row clear feature for a memory device and associated methods and systems. In some embodiments, the memory device may receive a command from a host device for a row of a memory array included in the memory device. The memory device may determine that the command is for two or more columns associated with the row, where each column is coupled to a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate a word line based on writing the set of predetermined data to the two or more columns.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to row clear features and associated methods and systems for memory devices. Background Art

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices within computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), requires an external power source to maintain its data. In contrast, non-volatile memory can retain its stored data even without external power. Non-volatile memory can be used in a variety of technologies, including flash memory (such as NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improvements to memory devices generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, improving reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. Summary of the Invention

[0003] In one aspect, the present application relates to a method comprising: receiving, at a memory device, a command for a row of a memory array of the memory device, wherein the row is associated with a group of columns; activating the row in response to the command; writing data from a register of the memory device to two or more columns in the group; and deactivating the row based at least in part on writing the data to the two or more columns in the group.

[0004] On the other hand, the present application provides a device comprising: a memory array comprising a row and a set of columns associated with the row; and peripheral circuitry coupled to the memory array, the peripheral circuitry configured to: receive a command for the row; activate the row in response to receiving the command; write data from a register of the device to two or more columns in the set; and deactivate the row based at least in part on writing the data to the two or more columns in the set.

[0005] On the other hand, the present application provides a system comprising: a host device; and a memory device coupled to the host device, the memory device comprising: a memory array having a row and a set of columns associated with the row; and peripheral circuitry coupled to the memory array, the peripheral circuitry configured to: receive a command for the row from the host device; activate the row in response to receiving the command; write data from a register of the memory device to two or more columns in the set; and deactivate the row based at least in part on writing the data to the two or more columns in the set. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. The components in the drawings are not necessarily drawn to scale. Instead, emphasis should be placed on clearly illustrating the principles of the present technology.

[0007] Figure 1 is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0008] Figure 2 is a block diagram schematically illustrating a memory array of a memory device according to an embodiment of the present technology.

[0009] Figure 3 is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0010] Figure 4 is a block diagram of a system having a memory device configured according to an embodiment of the present technology.

[0011] Figure 5 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0012] Disclosed are methods, systems, and apparatus for memory devices (e.g., DRAMs) that provide a row clear feature. When a host device (e.g., a memory controller) allocates memory space (e.g., a portion of a memory array) of the memory device, the memory controller can place individual memory cells of the memory space into a known state (e.g., a logic state of 1 or a logic state of 0 for binary data) by writing a set of predetermined data. This operation may be referred to as "clearing" (or "pre-clearing"), as it removes the existing, previous data stored in the memory cells. The sequence of 1s and 0s in the binary data may be referred to as a data pattern or bit pattern.

[0013] In some embodiments, to clear memory space, a memory controller may issue a write command along with a set of predetermined data to a memory device, for example, by providing the data on a data bus coupled to the memory device. The memory device may then receive the data via the data bus to write the data to a memory location specified by an address (e.g., a column address) included in the write command. For example, the memory location corresponding to the column address may be cleared by "overwriting" the memory cells coupled to the column with the set of predetermined data. In some cases, writing data to a group of memory cells coupled to a column (bit line) of a memory array identified by the corresponding column address may be referred to as writing data to the column. If the memory controller needs to allocate more memory space than a single write command can clear at once (e.g., 4 bytes, 8 bytes, 16 bytes, etc.), the memory controller may repeatedly issue the write command (each time with a different column address) while providing data on the data bus for each of the multiple write commands. Such repetition can occupy the command / address bus and the data bus for extended periods of time during memory operations (e.g., when clearing 256 bytes, 512 bytes, 1,024 bytes, etc.) and consume significant power.

[0014] Several embodiments of the present technology are directed to clearing a portion of a memory array with a single command, eliminating the need to repeatedly execute external write commands issued to a memory device comprising the memory array. In some embodiments, a single command can clear all memory cells coupled to a word line (row) and can be referred to as a row clear command. Alternatively, a single command can clear a subset of a row of memory cells, such as memory cells corresponding to two or more column addresses associated with the row. In addition, a set of predetermined data for the row clear command can be internally used in the memory device (e.g., stored in a register of the memory device), eliminating the need for a host device to provide data on a data bus during a row clear operation. In this way, the present technology facilitates clearing a portion of a memory array without occupying the command / address and data buses for an extended period of time.

[0015] This technique can provide additional advantages over repeatedly executing external write commands, such as consuming less power during the clear operation, clearing a row (or portion of a row) in less time, and the like. For example, because the data pattern of the memory device to be used can be used internally (e.g., stored in a register), the host device does not need to drive the data terminals (DQ) of the memory device with the data pattern, thereby reducing power consumption. In addition, because the data pattern written to a column is the same from one column address to another (e.g., the bit pattern is repeated for two or more columns), the memory device can maintain the write driver with the data pattern established for writing the first column of the row while writing all subsequent columns (or a subset of columns), thereby avoiding the power consumption associated with triggering the write driver. Furthermore, the timing parameters required to maintain between writing from one column to another can be tightened, for example by avoiding the duration required to stabilize the memory device's data input buffer with external data, by quickly moving to the next column, and because the memory device "knows" the next column selected for writing data without needing to decode the next column address or the like.

[0016] Memory device reference supporting embodiments of the present technology Figure 1 A more detailed description of the memory array supporting embodiments of the present technology is provided in Figure 2 A schematic depiction of a memory device configured to support a row clear feature according to an embodiment of the present technology is provided. Figure 3 A memory system including a memory device according to an embodiment of the present technology is described. Figure 4 A method of operating a memory device for row clearing feature according to an embodiment of the present technology is described. Figure 5 describe.

[0017] Figure 1 1 is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present technology. The memory device 100 may include a memory cell array, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., Figure 1 In some embodiments, each memory bank may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells (e.g., m×n memory cells) arranged at the intersection of the word lines (e.g., m word lines, which may also be referred to as rows) and bit lines (e.g., n bit lines, which may also be referred to as columns). In some embodiments, each bit line address (each column address) associated with a particular row may include multiple bit lines (columns) coupled to multiple memory cells, for example, across multiple memory banks via a hierarchical bit line architecture with local and master / global bit lines. Each word line in the plurality may be coupled to a corresponding word line driver (WL driver) configured to control the voltage of the word line during memory operation.

[0018] Memory cells may include any of several different memory media types, including capacitive, phase change, magnetoresistive, ferroelectric, or the like. In some embodiments, a portion of memory array 150 may be configured to store ECC bits. Selection of word lines WL may be performed by row decoder 140, and selection of bit lines BL may be performed by column decoder 145. Sense amplifiers (SAMPs) may be provided for corresponding bit lines BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via transfer gates (TGs) (which may function as switches). Memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0019] The memory device 100 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus, respectively, to receive a command signal CMD and an address signal ADDR. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for a data bus inversion function), and DMI (for a data mask inversion function), and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0020] The command terminals and address terminals can be supplied with address signals and bank address signals from the outside. The address signals and bank address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140 (which can be referred to as a row driver) and a decoded column address signal (YADD) to the column decoder 145 (which can be referred to as a column driver). The address decoder 110 can also receive the bank address portion of the ADDR input and supply a decoded bank address signal (BADD) and a bank address signal to both the row decoder 140 and the column decoder 145.

[0021] The command and address terminals may be supplied with a command signal CMD, an address signal ADDR, and a chip select signal CS from a memory controller. The command signals may represent various memory commands from the memory controller, such as a refresh command, an activate command, a precharge command, and an access command (which may include a read command and a write command). The select signal CS may be used to select the memory device 100 to respond to the command and address provided to the command and address terminals. When a valid CS signal is provided to the memory device 100, the command and address may be decoded and a memory operation may be performed. The command signal CMD may be provided as an internal command signal ICMD to the command decoder 115 via the command / address input circuit 105.

[0022] The command decoder 115 may include circuitry to decode the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as a row command signal that selects a word line and a column command signal that selects a bit line. Other examples of memory operations that the memory device 100 may perform based on the decoded internal command signal ICMD include a refresh command (e.g., to rebuild the full charge stored in individual memory cells of the memory array 150), an activate command (e.g., to activate a row in a particular memory bank, in some cases for subsequent access operations), or a precharge command (e.g., to deactivate an activated row in a particular memory bank). The internal command signals may also include output and input activation commands, such as the clocked command CMDCK ( Figure 1 not shown).

[0023] In some embodiments, command decoder 115 may further include one or more registers 118 for tracking various counts and / or values (e.g., a count of refresh commands received by memory device 100 or self-refresh operations performed by memory device 100) and / or for storing various operating conditions for memory device 100 to perform specific functions, features, and modes (or test modes). Thus, in some embodiments, registers 118 (or a subset of registers 118) may be referred to as mode registers. Additionally or alternatively, memory device 100 may include registers 118 as a separate component from command decoder 115. In some embodiments, registers 118 may include multi-purpose registers (MPRs) configured to write and / or read specialized data to and from memory device 100.

[0024] When a read command is issued to a memory bank with an open row and a column address is provided in time as part of the read command, read data can be read from a memory cell in memory array 150 specified by the row address (which may have been provided as part of an activate command identifying the open row) and the column address. The read command can be received by command decoder 115, which can provide an internal command to input / output circuit 160 so that the read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by read delay information RL that can be programmed in memory device 100 (e.g., in a mode register (e.g., register 118)). The read delay information RL can be defined in terms of clock cycles of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the read command is received by memory device 100 when the associated read data is provided.

[0025] When a write command is issued to a memory bank with an open row and a column address is provided in time as part of the write command, write data may be supplied to data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by command decoder 115, which may provide an internal command to input / output circuit 160, so that the write data may be received by a data receiver in input / output circuit 160 and supplied to memory array 150 via input / output circuit 160 and read / write amplifier 155. The write data may be written to the memory cells specified by the row and column addresses. The write data may be supplied to the data terminals at a time defined by write delay information (WL). The write delay information (WL) may be programmed in memory device 100 (e.g., in a mode register (e.g., register 118)). The write delay information (WL) may be defined based on clock cycles of the CK clock signal. For example, the write delay information (WL) may be the number of clock cycles of the CK signal after the write command is received by memory device 100 when the associated write data is received.

[0026] The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to an internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potentials VOD and VARY may be used in sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0027] The power supply terminal may also be supplied with a power supply potential VDDQ. Power supply potential VDDQ may be supplied to input / output circuit 160 along with power supply potential VSS. In an embodiment of the present technology, power supply potential VDDQ may be the same potential as power supply potential VDD. In another embodiment of the present technology, power supply potential VDDQ may be a different potential from power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for input / output circuit 160 to prevent power supply noise generated by input / output circuit 160 from propagating to other circuit blocks.

[0028] The clock terminal and the data clock terminal may be supplied with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, and WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have opposite clock levels and transition between opposite clock levels simultaneously. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high clock level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0029] An input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive the CK and CKF signals and the WCK and WCKF signals. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase- and frequency-controlled internal clock signals based on the internal clock signal ICLK and the clock enable signal CKE received from the command decoder 115.

[0030] For example, the internal clock circuit 130 may include a clock path ( ) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1(not shown). Internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies, allowing data to be output from and input to memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. Internal clock signal ICLK may also be supplied to timing generator 135, and thus various internal clock signals may be generated.

[0031] Memory device 100 can be connected to any of a number of electronic devices, or components thereof, that are capable of utilizing memory for temporary or persistent storage of information. For example, the host device of memory device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, a router, etc.) or a digital image (audio and / or video) recorder, a vehicle, an appliance, a toy, or any of many other products. In one embodiment, the host device can be directly connected to memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a networking connection or through an intermediary device).

[0032] In some embodiments, memory device 100 may receive a command from a host device (e.g., a memory controller) directed to one of the word lines (rows) of memory array 150. Memory device 100 may determine that the command is directed to two or more columns (bit lines) associated with the row, where each column is coupled to a group of memory cells. In some embodiments, memory device 100 makes this determination based on one or more bits of the command (e.g., in conjunction with command decoder 115) and / or an indication stored in a register of memory device 100 (e.g., register 118). In response to receiving the command, memory device 100 may activate the word line (e.g., open the row) so that memory device 100 can write to the two or more columns of the row with a predetermined set of data. In this regard, the host device may have already assumed (determined) the predetermined set of data and stored the data in a register of memory device 100 (e.g., register 118 or a different register) so that the data pattern is available internally to memory device 100 before executing the command. In some embodiments, memory device 100 may utilize a counter (or portion of register 118) to track which columns have been selected for writing data and which columns remain to be written. Subsequently, the memory device 100 may deactivate the word lines (eg, turn off the rows) based at least in part on writing a predetermined set of data to two or more columns of the memory array 150 .

[0033] Figure 2 is a schematic diagram illustrating a memory device according to an embodiment of the present technology (for example, referring to Figure 1 1. The diagram 200 includes a memory array 205 having m word lines 225 (also individually identified as R0 to Rm-1) and n bit lines (also individually identified as C0 to Cn-1), which may be referenced. Figure 1 1. An example of a memory array 150 is depicted, or includes aspects of the memory array 150. For example, each of the m word lines is associated with n bit lines. Furthermore, diagram 200 includes a word line decoder 210 (which may be an example of, or include aspects of, row decoder 140) and a bit line decoder 230 (which may be an example of, or include aspects of, column decoder 145).

[0034] The word line decoder 210 may receive a row address signal 215 (eg, Figure 1) and select one of the m word lines. In addition, the word line decoder 210 can drive a word line driver 220 coupled to the selected word line (which can be considered part of the word line decoder 210 in some embodiments) to control the voltage of the selected word line during memory operations. For example, the memory device can activate the selected word line (e.g., via an activate command) to "turn on" the row so that the memory cells coupled to the row can be accessed (e.g., read, modified) through the columns associated with the row. Similarly, the memory device can deactivate the selected word line (e.g., via a precharge command) to "turn off" the row so that the memory cells coupled to the row can no longer be accessed.

[0035] Similarly, the bit line decoder 230 may receive a column address signal 235 (eg, reference Figure 1 2) and selects one of the n bit lines depicted in diagram 200. Furthermore, bit line decoder 230 can drive column drivers 240 (which, in some embodiments, can be considered part of bit line decoder 230) coupled to the selected bit line to access (e.g., read, write) the memory cells of the open row. Thus, column address signal 235 can include a column select signal that identifies a particular column of n bit lines to access the memory cells of the selected column (e.g., each of columns C0 to Cn-1 corresponding to the column address). Furthermore, each column depicted in diagram 200 (e.g., C0, C1, etc.) can include multiple columns (e.g., sub-columns; not shown), each coupled to a group of memory cells.

[0036] By way of example, each of rows R0 through Rm-1 may be coupled to a total of 1,024 bytes of memory cells, respectively. Furthermore, each of rows R0 through Rm-1 may be associated with sixty-four (64) columns (or column addresses). Thus, each of columns C0 through Cn-1 includes 16 bytes (i.e., 128 bits) of memory cells, which in some embodiments may be organized using a hierarchical bitline architecture including local and master (or global) bitlines, such as a bitline architecture including a local I / O line (LIOT), a master I / O line (MIOT), and a transfer gate (TG) coupling the local and master I / O lines, as described with reference to FIG. Figure 1 In some cases, the memory cells coupled to all columns (or column addresses) associated with a single row (eg, 64 column addresses) can be referred to as a page of memory array 205 .

[0037] Aspects of the present technology facilitate clearing a row (e.g., clearing all or a subset of memory cells coupled to a row having multiple columns associated with the row) with a single command, such as a row clear command, a command with an indication to clear two or more columns (column addresses) of the row. This command can provide a row clear feature in a manner that is energy efficient compared to executing multiple externally issued write commands to achieve the same result. Furthermore, the command can clear the row in an accelerated manner, as described in more detail herein. In some embodiments, the command includes aspects of an activate (ACT) command, such as a modified ACT command. For example, the ACT command can be altered and / or appended to include one or more bits indicating the clearing of two or more columns.

[0038] For example, after a row to be erased (e.g., a target row) is activated in response to receiving a row erase command, the memory device may identify a first column (a first column address) to be written with a predetermined set of data that may be used internally in the memory device. Once the first column (e.g., C1) is written with the predetermined set of data (e.g., all memory cells associated with the first column address are overwritten with the predetermined set of data), the memory device may move to the next column by updating the column select signal to identify the next column (e.g., C2) to be written with the predetermined set of data.

[0039] If a row clear command instructs the clearing of all columns associated with a target row, the memory device may iterate through all columns (i.e., all column addresses) of the target row (e.g., C0 to Cn-1) by updating the column select signals to identify all columns one at a time (column address). If a row clear command instructs the clearing of a subset of columns associated with the target row (e.g., by identifying an initial column Ci and a final column Cf that define a range of columns to be cleared), the memory device may clear the subset of columns by iterating through the range of columns (e.g., column addresses) using the column select signals that identify the range of columns (e.g., Ci to Cf). In some embodiments, the memory device may utilize a counter that is configured to identify a column address among the column addresses associated with the target row and to keep track of which columns (and which columns) are written with a predetermined data set. This counter (or logic circuitry to execute it) may be used in an error checking and scrubbing (ECS) operation that the memory device may perform, during which the memory device may read data from the columns of the target row and perform an error checking and correction (ECC) operation to detect and / or correct errors in the data.

[0040] In some embodiments, such an indication (or flag) regarding the scope of the row clear command may be included in one or more bits of the row clear command, in a register (e.g., register 118, a multi-purpose register), or both. In some embodiments, the memory device may be preconfigured to clear a specific portion of the target row based on the flag (or indication) associated with the row clear command. For example, the memory device may include a command state table for the row clear command to specify such preconfigured portions, such as clearing half of a page, clearing a quarter of a page, clearing columns Ci through Cf, etc.

[0041] A set of predetermined data (which may be referred to as a data pattern or bit pattern, given the specific sequence of 1s and 0s in the predetermined data set) may be assumed by a host device (e.g., a memory controller) and stored in a register (e.g., register 118) of the memory device so that the data pattern can be used internally by the memory device when a row clear command is executed. For example, the set of predetermined data may include all 1s, all 0s, or any combination of 1s and 0s. In some embodiments, the host device may determine (e.g., assume) the set of predetermined data based on the primary application and / or operating environment in which the memory device may be deployed, such as a graphics application that tends to exhibit a specific pattern in a group of memory cells, a power-sensitive mobile application, an autonomous driving application with a degraded operating temperature range, a data center application for highly reliable data integrity, or the like. In some embodiments, the memory device may utilize logic circuitry that writes data stored in the register of the memory device to the memory array in response to an external command specifying a single column (column address) to write data from the register to the column.

[0042] Figure 3 is a schematic diagram illustrating a memory device according to an embodiment of the present technology (for example, referring to Figure 1 and 2 3. A block diagram 300 of a memory device described herein is provided. Diagram 300 includes a memory array 305 (which may be an example of or include aspects of memory array 150 and / or memory array 205). Memory array 305 may include a plurality of word lines (e.g., reference Figure 2300 illustrates one of the depicted bits (R0 through Rm-1) and a plurality of wordline drivers 220, and diagram 300 illustrates one of each depicted as a wordline 225 and a wordline driver 220 coupled thereto. Furthermore, a memory array 305 includes a plurality of bitlines (also individually identified as C0 through Cn-1) coupled to the wordlines (e.g., wordline 225). The memory device also includes peripheral circuitry 310 coupled to the memory array 305. Diagram 300 depicts that the peripheral circuitry 310 may also be coupled to a command decoder 315 (which may be an example of command decoder 115 or include aspects of command decoder 115), first and second registers 325 and 330 (which may be examples of register 118 or include aspects of register 118, respectively), and a counter 345. Furthermore, the memory device may include an I / O data buffer 335, a write driver 340, and a bitline decoder 230.

[0043] Peripheral circuitry 310 can be configured to receive commands from a host device (e.g., a memory controller) coupled to the memory device via a command / address bus 320. For example, peripheral circuitry 310 can receive a command from the host device, wherein the command is directed to one of the rows of memory array 305 (e.g., row 225). Peripheral circuitry 310 can activate row 225 in conjunction with wordline driver 220 in response to receiving the command. Furthermore, the command can instruct the memory device to write data to two or more columns associated with row 225 of memory array 305, such as writing data to memory cells coupled to columns (column addresses) of memory array 305 for at least two columns (two column addresses). In this regard, the host device may have already written (stored) the data in a register (e.g., register 325) of the memory device to make the data available internally when the command is executed.

[0044] In some cases, the command may instruct the memory device to write data from register 325 to all columns associated with row 225 of memory array 305. In other words, the command may clear (overwrite) all memory cells coupled to each individual column C0 to Cn-1, such as a page clear mode (or feature). Because the command is executed in page clear mode, all columns associated with row 225 (e.g., columns C0 to Cn-1) may contain the same data pattern, such as a repeating bit pattern written for all columns C0 to Cn-1. In other cases, the command may instruct the memory device to write data to a subset of columns associated with row 225, such as a subpage clear mode (or feature). In such cases, the memory device may write data to two or more columns associated with row 225, which may be indicated by a range of column addresses to be cleared, such as by identifying an initial column Ci and a final column Cf that define the range of columns to be cleared.

[0045] In this regard, the host device may be configured to program a register of the memory device (e.g., register 330) to indicate whether the command is for all columns associated with row 225 (e.g., page clear mode) or a subset of columns associated with row 225 (e.g., subpage clear mode). Additionally or alternatively, the host device may be configured to program one or more bits of the command to indicate the same, such as whether the command is implemented in page clear mode or subpage clear mode. Although diagram 300 depicts registers 325 and 330 as two separate components, in some embodiments, a single register (e.g., register 118) may be configured to perform the functions of register 325 (e.g., storing data from the host device) and register 330 (e.g., storing an indication of the command mode). Thus, command decoder 315 may be configured to determine whether the command is for all columns associated with row 225 (e.g., page clear mode) or a subset of columns associated with row 225 (e.g., subpage clear mode) based on an indication that may be stored in one or more bits of the command, a register of the memory device, or both.

[0046] Because the data to be written to individual columns associated with row 225 can be internally retrieved from register 325, the memory device may not need to access I / O data buffer 335 when executing commands to store data to individual columns. In this regard, the memory device can load a data pattern from register 325 to write driver 340 without receiving data from the host device via I / O data buffer 335. Write driver 340 can be configured to provide a data pattern for each individual column, the data pattern corresponding to the data in register 325. Furthermore, because the data pattern remains the same when data is written to different columns, once the memory device loads (e.g., activates) write driver 340 with the data pattern to write to the first column of memory array 305, the memory device does not need to change the data pattern of write driver 340 when writing to subsequent columns. In this way, the memory device can save power and time executing row clear commands compared to executing multiple external write commands, for example, by saving time for the external data in I / O data buffer 335 to stabilize, saving time and power consumption for triggering write driver 340 for different columns, etc.

[0047] Counter 345 can be configured to identify the column address to which data is written, for example, one column address at a time. In some embodiments, counter 345 can provide the column address to bitline decoder 230 via column address signal 235, so that the memory device can identify the column to which the data is written based on the counter. In such embodiments, bitline decoder 230 can identify the column selected based on the column address provided to bitline decoder 230 from counter 345, instead of decoding a column address signal (e.g., column address signal 235). Furthermore, counter 345 can be configured to generate (iterate through) all column addresses corresponding to all columns associated with row 225. In this manner, the memory device can write data to all columns (all column addresses) associated with row 225 by writing data to individual columns identified by counter 345 as counter 345 iterates through all columns (column addresses), for example, by performing a full row erase operation (i.e., page erase mode).

[0048] Similarly, the memory device can implement commands in subpage clear mode in conjunction with counter 345, such as commands that identify an initial column Ci and a last column Cf defining a range of columns to be cleared. For example, the memory device can write data to a first column (e.g., Ci) associated with row 225, where counter 345 identifies a first address for the first column. Subsequently, the memory device can update counter 345 to identify a second address for a second column to which the data is to be written. After writing the data to the second column, the memory device can determine that the second address corresponds to the address of the last column (e.g., Cf) of the range and can stop updating counter 345. If the second address does not correspond to the address of the last column of the range (or it is otherwise determined that there are more columns to be written in the range), the memory device can update counter 345 to continue writing data to the immediately following columns until all columns in the range have been written with data.

[0049] The memory device can complete writing a single column with internally available data within a duration tCCDclear, which can be less than another duration tCCD_L corresponding to the duration for the memory device to complete an external write command to write a single column with data provided externally from a host device. tCCDclear can be less than tCCD_L because the memory device can omit accessing the I / O data buffer 335, changing the data pattern loaded in the write driver 340, performing error checking and correction (ECC) operations on the external data, etc. Furthermore, the memory device "knows" which column to write data next, for example by utilizing a counter that iterates (loops) through each individual column associated with a row, so that the memory device can reduce the time between writing from one column to another.

[0050] When the memory device completes writing data to the columns associated with row 225 (either all columns C0 to Cn-1 (e.g., a full row clear operation, page clear mode) or a subset of columns specified by a command (e.g., a partial row clear operation, subpage clear mode)), the memory device may wait for a predetermined duration before deactivating row 225 (e.g., by executing a precharge command on row 225). For example, the predetermined duration may correspond to the time tWR required to elapse from the last write command executed on the last column before deactivating row 225. In some embodiments, tWR may ensure the fidelity of the data written to the memory cells coupled to the last column. After waiting the predetermined duration (e.g., tWR), the memory device may perform a precharge operation to deactivate (e.g., turn off) row 225.

[0051] In some embodiments, a memory device may receive a precharge command from a host device to deactivate a row. In some embodiments, a memory device may deactivate a row without receiving a precharge command from a host device, which may be referred to as an auto-precharge mode. In this regard, a memory device operating in auto-precharge mode may be configured to deactivate a row in response to receiving a command to activate a row, e.g., deactivate a row without receiving one or more additional commands from a host device.

[0052] In some embodiments, a full row clear command (eg, a command in page clear mode) may be associated with a timing parameter tRowClear, which may be expressed as:

[0053] tRowClear=tCCDclear×N+tWR

[0054] The parameter N corresponds to the number of columns (column addresses) associated with the row to be cleared. In such embodiments, the host device may transmit a precharge command to the memory device to deactivate the row after a time tRowClear has elapsed from transmitting the full row clear command.

[0055] Figure 4 is a block diagram of a system 401 having a memory device 400 configured according to an embodiment of the present technology. The memory device 400 may be a reference Figures 1 to 3 As shown, the memory device 400 includes a main memory 402 (e.g., DRAM, NAND flash, NOR flash, FeRAM, PCM, etc.) and a control circuit system 406 operatively coupled to a host device 408 (e.g., an upstream central processing unit (CPU), a memory controller). The control circuit system 406 may include reference Figures 1 to 3For example, control circuitry 406 may include aspects of command / address input circuitry 105, address decoder 110, command decoders 115 and / or 315, word line decoder 210, peripheral circuitry 310, and the like.

[0056] Main memory 402 includes a plurality of memory units 420, each of which includes a plurality of memory cells. Memory units 420 may be individual memory dies, memory planes within a single memory die, a stack of memory dies connected vertically with through-silicon vias (TSVs), or the like. For example, in one embodiment, each of memory units 420 may be formed from a semiconductor die and arranged with other memory unit dies into a single device package. In other embodiments, multiple memory units 420 may be co-located on a single die and / or distributed across multiple device packages. In some embodiments, memory units 420 may also be subdivided into memory regions 428 (e.g., banks, ranks, channels, blocks, pages, etc.).

[0057] Memory cells may include, for example, floating gates, charge trapping, phase change, capacitors, ferroelectrics, magnetoresistive, and / or other suitable storage elements configured to store data persistently or semi-persistently. Main memory 402 and / or individual memory cells 420 may also include other circuit components for accessing and / or programming (e.g., writing to) memory cells and other functions, such as for processing information and / or communicating with control circuitry 406 or host device 408, such as multiplexers, decoders, buffers, read / write drivers, address registers, data-out / data-in registers, etc. Although shown in the illustrated embodiment as having a specific number of memory cells, rows, columns, regions, and memory cells for illustrative purposes, the number of memory cells, rows, columns, regions, and memory cells may vary, and in other embodiments, the proportions may be greater or less than shown in the illustrated example. For example, in some embodiments, memory device 400 may include only one memory cell 420. Alternatively, the memory device 400 may include 2, 3, 4, 8, 10, or more than 10 (eg, 16, 32, 64, or more than 64) memory cells 420. Although Figure 4 Memory cells 420 are shown as each including four memory regions 428, but in other embodiments, each memory cell 420 may include one, two, three, eight, or more than eight (e.g., 16, 32, 64, 100, 128, 256, or more) memory regions.

[0058] In one embodiment, control circuitry 406 may be provided on the same die as main memory 402 (e.g., including command / address / clock input circuitry, decoders, voltage and timing generators, input / output circuitry, etc.). In another embodiment, control circuitry 406 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), control circuitry on a memory die, etc.), or other suitable processor. In one embodiment, control circuitry 406 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines to control the operation of memory device 400, including managing main memory 402 and handling communications between memory device 400 and host device 408. In some embodiments, control circuitry 406 may include embedded memory with memory registers for storing, for example, memory addresses, row counters, bank counters, memory pointers, fetched data, etc. In another embodiment of the present technology, memory device 400 may not include control circuitry, but may rely on external control (e.g., provided by host device 408 or by a processor or controller separate from memory device 400).

[0059] Host device 408 can be any of a number of electronic devices, or components thereof, that are capable of utilizing memory for temporary or persistent storage of information. For example, host device 408 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). Host device 408 can be any of a networked device (e.g., a switch, a router, etc.) or a digital image (audio and / or video) recorder, a vehicle, an appliance, a toy, or any of many other products. In one embodiment, host device 408 can be directly connected to memory device 400, but in other embodiments, host device 408 can be indirectly connected to the memory device (e.g., via a networked connection or through an intermediary device).

[0060] In operation, control circuitry 406 can directly write to or otherwise program (e.g., erase) various memory regions of main memory 402. Control circuitry 406 communicates with host device 408 via a host device bus or interface 410. In some embodiments, host device 408 and control circuitry 406 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, host device 408 and control circuitry 406 can communicate via a serial interface (e.g., a Serial Attached SCSI (SAS), a Serial AT Attached (SATA) interface, a Peripheral Component Interconnect Express (PCIe)), or other suitable interface (e.g., a parallel interface). Host device 408 can send various requests (e.g., in the form of packets or packet streams) to control circuitry 406. Requests can include commands to read, write, erase, return information, and / or perform specific operations (e.g., refresh operations, TRIM operations, precharge operations, activate operations, wear-leveling operations, garbage collection operations, etc.).

[0061] In some embodiments, memory device 400 may receive a command from host device 408 via interface 410. The command may be directed to a row of a memory array (e.g., main memory 402), where a row is associated with a group of columns. Memory device 400 may activate the row in response to receiving the command and write data from a register (e.g., register 415) to two or more columns in the group. In some embodiments, host device 408 may have already predetermined the data and stored it in a register of memory device 400. Subsequently, memory device 400 may deactivate the row based at least in part on writing the data to two or more columns in the group.

[0062] In some embodiments, the host device 408 may store data in the register 415 of the memory device to make the data available internally to the memory device 400 before transmitting the command to the memory device 400. Furthermore, the host device 408 may be configured to program a second register (not shown) of the memory device 400 to indicate that the command is directed to each individual column or subset of columns in the group. Additionally or alternatively, the host device 408 may be configured to program one or more bits of the command to indicate that the command is directed to all columns or subsets of columns in the group.

[0063] Figure 5 5 is a flowchart 500 illustrating a method of operating a memory device according to an embodiment of the present technology. Flowchart 500 may be an example of a method that may be performed by a memory device (e.g., peripheral circuitry 310, control circuitry 406) or include aspects of the method, as described with reference to FIG. Figures 1 to 4 describe.

[0064] The method includes receiving, at a memory device, a command for a row of a memory array of the memory device, wherein the row is associated with a set of columns (block 510). According to one aspect of the present technique, the receiving feature of block 510 may be performed by the peripheral circuitry 310 (or the control circuitry 406), as described with reference to FIG. Figures 1 to 5 describe.

[0065] The method further includes activating the row in response to the command (block 515). According to one aspect of the present technology, the activation feature of block 515 may be performed by the peripheral circuitry 310 (or the control circuitry 406), as described with reference to FIG. Figures 1 to 5 describe.

[0066] The method further includes writing data from a register of the memory device to two or more columns in the group (block 520). According to one aspect of the present technique, the write feature of block 520 may be performed by the peripheral circuitry 310 (or the control circuitry 406), as described with reference to FIG. Figures 1 to 5 describe.

[0067] The method further includes deactivating a row based at least in part on writing data to two or more columns in the group (block 525). According to one aspect of the present technology, the deactivation feature of block 525 may be performed by the peripheral circuitry 310 (or the control circuitry 406), as described with reference to FIG. Figures 1 to 5 describe.

[0068] In some embodiments, each column in the group is coupled to a plurality of memory cells. In some embodiments, the command is an activate (ACT) command. In some embodiments, writing data from a register of the memory device to two or more columns in the group includes writing a repeating bit pattern based on the data from the register. In some embodiments, the method may further include: activating a write driver of the memory device according to a data pattern of data stored in the register before writing the data, the write driver being configured to be coupled to the columns in the group; and maintaining the write driver activated with the data pattern while writing the data to the two or more columns in the group.

[0069] In some embodiments, writing data to two or more columns in the group is performed without accessing a data input buffer of the memory device. In some embodiments, deactivating a row is performed in response to a command for an activated row. In some embodiments, the method may further include determining that the command is for each individual column in the group based on an indication stored in one or more bits of the command, a second register of the memory device, or both. In some embodiments, the method may further include writing data to the individual columns in the group based on a counter of the memory device configured to identify the column address, wherein the counter is further configured to iterate through all column addresses corresponding to the individual columns in the group.

[0070] In some embodiments, the method may further include waiting a predetermined duration after writing data to an individual column in the group before deactivating the row. In some embodiments, the method may further include receiving an additional command for a row of the memory array, the additional command received after a predetermined duration from receiving the command, wherein deactivating the row is performed in response to receiving the additional command. In some embodiments, the method may further include: determining that the command is for a subset of columns comprising two or more columns, wherein the determination is based on an indication stored in one or more bits of the command, a second register of the memory device, or both; writing data to a first column of the subset, wherein a counter of the memory device identifies a first address of the first column of the subset; updating the counter to identify a second address of a second column of the subset to which the data is written; and writing data to a second column of the subset based on the counter identifying the second address. In some embodiments, the method may further include: determining that the second address corresponds to an address of a last column of the subset; and waiting a predetermined duration before deactivating the row.

[0071] It should be noted that the above methods describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, two or more embodiments from the methods may be combined.

[0072] The information and signals described herein may be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0073] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate or die, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping method.

[0074] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0075] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of ..." or "one or more of ...") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on ..." should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on ..." should be interpreted in the same manner as the phrase "based at least in part on ..."

[0076] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Specifically, in the foregoing description, numerous specific details are discussed to provide a thorough and advantageous description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A method for a memory device, comprising: receiving, at the memory device, a command for a row of a memory array of the memory device, wherein the row is associated with a set of columns; activating the row in response to the command; writing data from a single register of the memory device to two or more columns in the group; and deactivating the row based at least in part on writing the data to the two or more columns in the group, Wherein writing the data from the single register of the memory device to the two or more columns in the group comprises writing a repeating bit pattern based on the data from the single register. The method according to claim 1 , wherein the command is an activate (ACT) command.

3. The method according to claim 1, further comprising: activating a write driver of the memory device according to a data pattern of the data stored in the single register before writing the data, the write driver being configured to be coupled to a column in the group; and The write driver is maintained activated with the data pattern while writing the data to the two or more columns in the group. 4 . The method of claim 1 , wherein writing the data to the two or more columns in the group is performed without accessing a data input buffer of the memory device. The method of claim 1 , wherein deactivating the row is performed in response to the command having activated the row.

6. The method according to claim 1, further comprising: The command is determined to be for each individual column in the set based on an indication stored in one or more bits of the command, a second register of the memory device, or both.

7. The method according to claim 6, further comprising: The data is written to an individual column in the group based on a counter of the memory device configured to identify a column address, wherein the counter is further configured to iterate through all column addresses corresponding to the individual column in the group.

8. The method according to claim 7, further comprising: A predetermined duration is waited after writing the data to the individual columns in the group before deactivating the row.

9. The method according to claim 6, further comprising: An additional command is received for the row of the memory array, the additional command being received after a predetermined duration from receiving the command, wherein deactivating the row is performed in response to receiving the additional command.

10. The method of claim 1, further comprising: determining that the command is for a subset of the columns including the two or more columns, wherein the determination is based on an indication stored in one or more bits of the command, a second register of the memory device, or both; writing the data to a first column of the subset, wherein a counter of the memory device identifies a first address of the first column of the subset; updating the counter to identify a second address where a second column of the subset of the data is written; and The data is written to the second column of the subset based on identifying the second address by the counter.

11. The method according to claim 10, further comprising: determining that the second address corresponds to an address of a last column of the subset; and Wait for a predetermined duration before deactivating the row.

12. A memory device comprising: a memory array comprising a row and a set of columns associated with the row; and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to: receiving a command for the row; activating the row in response to receiving the command; writing data from a single register of the memory device to two or more columns in the group; and deactivating the row based at least in part on writing the data to the two or more columns in the group, Wherein the peripheral circuitry is configured to write the data from the single register of the memory device to the two or more columns in the group by writing a repeating bit pattern based on the data from the single register.

13. The memory device of claim 12, further comprising: A write driver is coupled to the single register and configured to provide a data pattern for columns in the group, the data pattern corresponding to the data stored in the single register.

14. The memory device of claim 12, further comprising: A second register is configured to store an indication that the command is for each individual column or subset of the columns in the group.

15. The memory device of claim 12, further comprising: A command decoder is configured to determine that the command is for each individual column or subset of the columns in the group based on an indication stored in one or more bits of the command.

16. The memory device of claim 12, further comprising: A counter is configured to identify a column address, wherein the counter is further configured to iterate through all column addresses corresponding to individual columns in the set.

17. A memory system comprising: host device; and a memory device coupled to the host device, the memory device comprising: a memory array having a row and a set of columns associated with the row; and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to: receiving a command for the row from the host device; activating the row in response to receiving the command; writing data from a single register of the memory device to two or more columns in the group; and deactivating the row based at least in part on writing the data to the two or more columns in the group, Wherein the peripheral circuitry is configured to write the data from the single register of the memory device to the two or more columns in the group by writing a repeating bit pattern based on the data from the single register.

18. The memory system of claim 17, wherein the host device is configured to store the data in the single register of the memory device such that the memory device writes the data to the two or more columns in the group.

19. The memory system of claim 17, wherein the host device is configured to perform at least one of: programming a second register of the memory device to indicate that the command is directed to each individual column or subset of the columns in the group; or One or more bits of the command are programmed to indicate that the command is for each individual column in the group or the subset of the columns.

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