A method for quickly determining the read reference voltage of 3D TLC NAND flash memory

Abstract

The invention discloses a method for determining a reference voltage for reading a 3D TLC NAND flash memory, and relates to the technical field of NAND flash memory. The method comprises the following steps: S1. obtaining an initial default reference voltage group in a 3D TLC NAND flash memory, and starting to read stored data; S2. determining whether the storage cell type of the 3D TLC NAND flash memory is an FG type or a CT type, and if it is an FG type, executing step S3, and if it is a CT type, executing step S4; S3. sequentially reading the stored data stored in the FG type 3D TLC NAND flash memory, and correspondingly adjusting the corresponding FG type reference voltage by a voltage adjustment method, and executing step S5; S4. sequentially reading the stored data stored in the CT type 3D TLC NAND flash memory, and correspondingly adjusting the corresponding CT type reference voltage by a voltage adjustment method, and executing step S5; S5. arranging the optimized reference voltage to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and terminating the program, thereby solving the problem that the prior art for determining the reference voltage of the 3D TLC NAND flash memory is not suitable for 3D stacked flash, and is not specific and efficient enough.

Description

Technical Field

[0001] The present invention relates to the technical field of NAND flash memory, and more specifically, to a method for quickly determining a read reference voltage of a 3D TLC NAND flash memory. Background Art

[0002] The principle of the existing NAND flash memory threshold voltage distribution scanning scheme is that when data reading fails, the controller continuously adjusts the reference voltage until a suitable reference voltage is found, and the adjustment is performed using different reference standards.

[0003] There are two methods to adjust the flash read reference voltage:

[0004] The first is based on the parallax scheme. Find a read reference voltage with a bit error rate lower than the ECC error correction capability. This scheme is mainly adjusted by using the ratio of the number of 0s and 1s in the storage page. In order to reduce the data dependence of the error rate, the SSD controller scrambles the stored data to ensure that there are the same number of 0s and 1s in the flash memory cells, and the number of cells in each state is almost the same. The key idea based on the parallax scheme is to find a read reference voltage with approximately 50% of the cell bits being 1 and 50% of the cell bits being 0. To this end, the SSD controller uses a binary search algorithm to gradually narrow the optimization range of the read reference voltage until the desired ratio is reached.

[0005] For SLC NAND flash memory, the controller only needs to search for the read voltage once. For MLC NAND flash memory, there are three searches, using V b Read the MSB page, using V a and V c Read the LSB page. The search process of MLC flash memory is mainly divided into three steps. In the first step, the controller searches for V b , search for the appropriate voltage V b , the threshold voltage is less than V b The cells occupy 50% and the MSB page data is read as 1, which is greater than V b The cells occupy 50% and the MSB page data is read as 0. The subsequent steps require V b The second step is to search for V a , 25% of the cells are in the ER state, by finding V b The voltage V of the left 50% voltage unit a . The threshold voltage is less than V a The unit reads the LSB page data as 1; in the third step, similarly, the controller searches for V c , 25% of the cells are in P3 state, by finding V b The voltage V of the right 50% voltage unit c . The threshold voltage is greater than V cThe cell reads the LSB page data as 1 at V a and V c The LSB page data is read as 0.

[0006] The second is based on ROR technology. Based on the lowest raw bit error rate (RBER), the Retention Optimized Reading (ROR) online technology overcomes persistent noise. This technology reduces the raw bit error rate by adaptively learning and adjusting the optimized read reference voltage. Persistent noise causes the threshold voltage to shift to the left, and as the persistence time V opt Gradually decreasing.

[0007] The ROR read voltage optimization technology is divided into three steps: the first is initialization, that is, optimizing the initial read reference voltage; then the read reference voltage is shifted to the left at equal intervals of ΔV to search for the optimal read reference voltage V opt ; Finally, record the V of the last programming page opt .

[0008] The prior patent discloses a technology for improving performance at least related to reading data from a memory based on a parallax scheme; the data is stored as a codeword in a block of the memory. The data reading includes determining whether each bit in a portion of the block is zero or one based on a voltage measurement value. Before performing a decoding process by an ECC decoder of the memory to decode the codeword, a first number of errors "coder performs" and a second number of errors "second number" are estimated, wherein the first number of errors "wherein the first is associated with each bit that is true zero but is incorrectly determined to be one, and wherein the second number of errors "wherein each is true is associated with each bit that is true one but is incorrectly determined to be zero. Thereafter, decoding is performed on the codeword based on the decoding process.

[0009] However, most of the existing methods for reading reference voltages of NAND flash memory chips are for previous 2D planar flash memory. The current 3D stacked flash memory has become the mainstream of the market and cannot fully adapt to the error characteristics of 3D flash memory and the threshold voltage distribution offset characteristics. In addition, the existing solutions cannot achieve fast and effective adjustments, and no specific adjustment process for reading reference voltage is given. For flash memory devices with different usage levels, the degree of electron loss is also different. Different degrees of adjustment processes should be set for different degrees of loss in order to achieve more efficient adjustment. The two existing technologies mentioned above are both based on threshold sampling technology, and their disadvantages are that they require time and storage loss.

[0010] Therefore, how to invent a specific and efficient method for reading reference voltage that can adapt to 3D stacked flash memory is a problem that urgently needs to be solved in this technical field. Summary of the invention

[0011] Aiming at the problem that the prior art of determining the reference voltage of 3D TLC NAND flash memory is not suitable for 3D stacked flash and cannot achieve high-efficiency adjustment, the present invention proposes a method for quickly determining the read reference voltage of 3D TLC NAND flash memory, which has the characteristics of high-efficiency adjustment and convenient calculation.

[0012] In order to achieve the above-mentioned purpose of the present invention, the technical scheme adopted is as follows:

[0013] A method for determining a read reference voltage of a 3D TLC NAND flash memory comprises the following steps:

[0014] S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data;

[0015] S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4;

[0016] S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by a voltage adjustment method, and executes step S5;

[0017] S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method accordingly, and execute step S5;

[0018] S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

[0019] Preferably, the stored data in the TLC NAND flash memory is divided into the most significant bit, the middle significant bit, and the least significant bit.

[0020] Furthermore, in order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, namely V 1 、V 2 、V 3 、V 4 、V 5 、V b 、V 7 .

[0021] Furthermore, the step S3 is specifically as follows:

[0022] S301. Read the least significant bit data stored in the 3D TLC NAND flash memory;

[0023] S302. Set V 4 V base , V 2 V adjust , substituting into the voltage adjustment method, V base Indicates adjustment of V adjust The reference voltage required in the process, V adjust Indicates the reference voltage that needs to be adjusted;

[0024] S303. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory;

[0025] S304. Set the adjusted V 2 and V 4 Corresponding to V base1 and V base2 , let V 3 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 3 .

[0026] Furthermore, the step S4 is specifically as follows:

[0027] S401. Read the most significant bit data stored in the 3D TLC NAND flash memory;

[0028] S402. Set V 1 V base , V 5 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0029] S403. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory;

[0030] S404. Set V 4 V adjust , V base is the default value, and the voltage adjustment method is substituted to obtain the optimized reference voltage V 4 ;

[0031] S405. Set the optimized reference voltage V 4 V base , V 2 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 2 ;

[0032] S406. Set the optimized reference voltage V 4 Vbase , V 6 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 6 ;

[0033] S407. Read the least significant bit data stored in the 3D TLC NAND flash memory;

[0034] S408. Set V 1 and the optimized reference voltage V 5 V base1 and V base2 , V 3 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0035] S409. Set the optimized reference voltage V 6 V base , V 7 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 7 .

[0036] Furthermore, the voltage adjustment method comprises the following specific steps:

[0037] M1. Initialize V adjust , V base , and Δ p The value of V adjust Indicates the reference voltage that needs to be adjusted, V base Indicates adjustment of V adjust The reference voltage required in the process, Δ p Indicates the minimum step voltage for each left adjustment;

[0038] M2.Through V base Get the number of units N in the ideal state base and through V adjust and V base Get the actual number of units N intial ;

[0039] M3. Calculate the number of units N in the ideal state base and the actual number of units N intial The difference Δ;

[0040] M4. Determine the number of steps p for each adjustment based on the value of Δ and adjust V adjust The size of the new reference voltage V that needs to be adjusted adjust1; The calculation formula is as follows:

[0041] M5. According to the adjusted V adjust1 Calculate the actual number of units N again initial1 , and calculate the new difference Δ 1 ;

[0042] M6. According to Δ 1 The value of determines the number of steps p1 for each adjustment, and adjusts V adjust1 The size of the new reference voltage V adjust2 ;

[0043] M7. According to the adjusted V adjust2 Calculate the actual number of units N again initial2 , and calculate the new difference Δ 2 ;

[0044] M8. Calculate Δ a1 =0.5*(Δ+Δ 1 ), Δ a2 =0.5*(Δ 1 +Δ 2 ); if Δ a1 >Δ a2 , total Δ = Δ 1 , Δ 1 =Δ 2 , repeat steps M5 to M7; if Δ a1 <Δ a2 , the adjustment process stops and the optimal read reference voltage is obtained Where Δ a1 is Δ 1 and the average value of Δ, Δ a2 is Δ 1 With Δ 2 The average value of .

[0045] Furthermore, in step M2, by V base Get the number of units N in the ideal state base The specific method is: draw the threshold voltage distribution corresponding to the 3DTLC NAND flash memory, the number of cells in the ideal state N base That is V base The number of flash memory cells on the left.

[0046] Furthermore, in step M3, Δ is obtained by:

[0047] Δ=|N intial -N base *0.5|.

[0048] Furthermore, in step M4, the number of steps p for each adjustment is determined, and the specific method is as follows:

[0049] When Δ>0.5*N base * At 5%, p = 4;

[0050] When 0.5*N base *1%<Δ≤0.5*N base * At 5%, p = 2;

[0051] When Δ<0.5*N base *When 1%, p=1.

[0052] Furthermore, in step M4, adjust V adjust The specific formula is as follows:

[0053] V adjust1 =V adjust -p*Δ p .

[0054] The beneficial effects of the present invention are as follows:

[0055] Based on actual tests, the present invention divides 3D TLC NAND flash memory into FG type and CT type 3D stacked flash memory, reduces adjustment redundancy, proposes a corresponding adjustment algorithm, solves the problem that the prior art of determining the reference voltage of 3D TLC NAND flash memory is not suitable for 3D stacked flash and is not specific and efficient enough, and proposes a method for quickly determining the read reference voltage of 3D TLC NAND flash memory, which has the characteristics of being specific, efficient and easy to calculate. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A flowchart of a method for quickly determining a read reference voltage of a 3D TLC NAND flash memory is shown.

[0057] Figure 2 This is a schematic diagram of the threshold voltage distribution corresponding to TLC flash memory.

[0058] Figure 3 Schematic diagram of two electron loss mechanisms in the storage cell of 3D TLC NAND flash memory.

[0059] Figure 4 It is a schematic diagram of the cell structure of FG-type 3D TLC NAND flash memory.

[0060] Figure 5 It is a schematic diagram of the cell structure of CT-type 3D TLC NAND flash memory.

[0061] Figure 6 FIG. 4 is a reference voltage distribution offset diagram of the threshold voltage of the FG-type 3D TLC NAND flash memory.

[0062] Figure 7FIG. 4 is a reference voltage distribution offset diagram of the threshold voltage of a CT-type 3D TLC NAND flash memory.

[0063] Figure 8 is the reference voltage V in step S302 2 Reference voltage distribution diagram before adjustment.

[0064] Fig. 9 is the reference voltage V in step S302 2 Reference voltage distribution diagram before adjustment

[0065] Fig.10 is the reference voltage V in step S304 3 Adjusted reference voltage distribution diagram.

[0066] Fig.11 is the reference voltage V in step S402 5 Adjusted reference voltage distribution diagram.

[0067] Fig.12 is the reference voltage V in steps S404 and S406 2 、V 4 、V 6 Adjusted reference voltage distribution diagram.

[0068] Fig.13 is the reference voltage V in steps S408 and S409 3 、V 7 Adjusted reference voltage distribution diagram. DETAILED DESCRIPTION

[0069] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] Example 1

[0071] like Figure 1 , Figure 3 , Figure 4 , Figure 5 As shown, a method for determining a read reference voltage of a 3D TLC NAND flash memory comprises the following steps:

[0072] S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data;

[0073] S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4;

[0074] S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by a voltage adjustment method, and executes step S5;

[0075] S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method accordingly, and execute step S5;

[0076] S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

[0077] like Figure 2 As shown, the stored data in the TLC NAND flash memory is divided into the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB). In this embodiment, the reading process is divided into the MSB page reading process, the CSB page reading process, and the LSB page reading process:

[0078] (1)MSB read operation. In state P 0 and state P 1 Apply a read reference voltage V 1 , in state P 4 and state P 5 Apply a read reference voltage V 5 , if the cell threshold voltage V<V 1 or V>V 5 , the bit read is 1, otherwise it is 0.

[0079] (2) CSB read operation. In state P 1 and state P 2 Between, state P 3 and state P 4 Between, state P 5 and state P 6 The read reference voltage V 2 、V 4 and V 6 If the cell threshold voltage V 4 >VCT>V 2 or V>V 6 , the bit read is 0, otherwise it is 1.

[0080] (3) LSB read operation. In state P 2 and state P 3 Between, state P 6 and state P 7 Apply a read reference voltage V 3 and V 7, if the cell threshold voltage V 7 >V>V 3 , the bit read is 0, otherwise it is 1.

[0081] In order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, namely V 1 、V 2 、V 3 、V 4 、V 5 、V 6 、V 7 .

[0082] Example 2

[0083] like Figure 1 , Figure 3 , Figure 4 , Figure 5 As shown, a method for determining a read reference voltage of a 3D TLC NAND flash memory comprises the following steps:

[0084] S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data;

[0085] S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4;

[0086] S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by a voltage adjustment method, and executes step S5;

[0087] S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method accordingly, and execute step S5;

[0088] S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

[0089] like Figure 2 As shown, the stored data in the TLC NAND flash memory is divided into the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB). In this embodiment, the reading process is divided into the MSB page reading process, the CSB page reading process, and the LSB page reading process:

[0090] (1)MSB read operation. In state P 0 and state P 1Apply a read reference voltage V 1 , in state P 4 and state P 5 Apply a read reference voltage V 5 , if the cell threshold voltage V<V 1 or V>V 5 , the bit read is 1, otherwise it is 0.

[0091] (2) CSB read operation. In state P 1 and state P 2 Between, state P 3 and state P 4 Between, state P 5 and state P 6 The read reference voltage V 2 、V 4 and V 6 If the cell threshold voltage V 4 >VCT>V 2 or V>V 6 , the bit read is 0, otherwise it is 1.

[0092] (3) LSB read operation. In state P 2 and state P 3 Between, state P 6 and state P 7 Apply a read reference voltage V 3 and V 7 , if the cell threshold voltage V 7 >V>V 3 , then the read bit is 0, otherwise it is 1. In order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, namely V 1 、V 2 、V 3 、V 4 、V 5 、V 6 、V 7 .

[0093] like Figure 6 , Figure 7As shown in the figure, there are two main mechanisms for electron loss in flash memory cells, namely lateral charge migration (LCM) and vertical charge de-trap (VCT). The LCM mechanism only exists in CT-type 3D flash memory, which is caused by the two types of flash memory structures. The stability of the CT type is more easily affected by P / E cycles and data retention time. The VCT effect exists in both FG and CT flash memories. The VCT effect is mainly caused by the wear of the oxide layer (Tunnel Oxide) that prevents electron loss in the storage cell after the number of erases increases. When the oxide layer is worn to a certain extent, electrons can easily escape from the storage cell, resulting in data damage. It can be seen that the threshold voltage distribution is shifted to the left in both types of flash memory, but the specific characteristics of the shift are different. The low state shift is more in the FG-type 3D flash memory, while the high state shift is more in the CT-type 3D flash memory. After the threshold voltage shifts, using a fixed reference voltage will obviously cause data reading errors. Rapidly adjusting the reference voltage is very important in flash memory because the storage system must not only consider data stability but also latency. Too many adjustments will result in excessive time delays. Figure 6 and Figure 7 It can be seen that the threshold voltage distribution shifts to the left as a whole with the increase of P / E Cycles and data retention time, which also means that the read reference voltage should also be adjusted to the left.

[0094] The step S3 is specifically:

[0095] S301. Read the least significant bit data stored in the 3D TLC NAND flash memory;

[0096] S302. Set V 4 V base , V 2 V adjust , substituting into the voltage adjustment method, V base Indicates adjustment of V adjust The reference voltage required in the process, V adjust Indicates the reference voltage that needs to be adjusted;

[0097] S303. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory;

[0098] S304. Set the adjusted V 2 and V 4 Corresponding to V base1 and V base2 , let V 3 V adjust, substitute into the voltage adjustment method, and get the optimized reference voltage V 3 .

[0099] Example 3

[0100] A method for determining a read reference voltage of a 3D TLC NAND flash memory comprises the following steps:

[0101] S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data;

[0102] S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4;

[0103] S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by a voltage adjustment method, and executes step S5;

[0104] S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method accordingly, and execute step S5;

[0105] S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

[0106] The stored data in the TLC NAND flash memory is divided into the most significant bit, the middle significant bit and the least significant bit.

[0107] In order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, namely V 1 、V 2 、V 3 、V 4 、V 5 、V 6 、V 7 .

[0108] Furthermore, the step S3 is specifically as follows:

[0109] S301. Read the least significant bit data stored in the 3D TLC NAND flash memory;

[0110] S302. Set V 4 V base , V 2 V adjust , substituting into the voltage adjustment method, Vbase Indicates adjustment of V adjust The reference voltage required in the process, V adjust Indicates the reference voltage that needs to be adjusted;

[0111] S303. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory;

[0112] S304. Set the adjusted V 2 and V 4 Corresponding to V base1 and V base2 , let V 3 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 3 .

[0113] like Figure 6 , Figure 7 As shown in the figure, there are two main mechanisms for electron loss in flash memory cells, namely lateral charge migration (LCM) and vertical charge de-trap (VCT). The LCM mechanism only exists in CT-type 3D flash memory, which is caused by the two types of flash memory structures. The stability of the CT type is more easily affected by P / E cycles and data retention time. The VCT effect exists in both FG and CT flash memories. The VCT effect is mainly caused by the wear of the oxide layer (Tunnel Oxide) that prevents electron loss in the storage cell after the number of erases increases. When the oxide layer is worn to a certain extent, electrons can easily escape from the storage cell, resulting in data damage. It can be seen that the threshold voltage distribution is shifted to the left in both types of flash memory, but the specific characteristics of the shift are different. The low state shift is more in the FG-type 3D flash memory, while the high state shift is more in the CT-type 3D flash memory. After the threshold voltage shifts, using a fixed reference voltage will obviously cause data reading errors. Rapidly adjusting the reference voltage is very important in flash memory because the storage system must not only consider data stability but also latency. Too many adjustments will result in excessive time delays. Figure 6 and Figure 7 It can be seen that the threshold voltage distribution shifts to the left as a whole with the increase of P / E Cycles and data retention time, which also means that the read reference voltage should also be adjusted to the left.

[0114] like Figure 8 , Fig. 9 , Fig.10 As shown, the step S3 is specifically as follows:

[0115] S301. Read the least significant bit (LSB) data stored in the 3D TLC NAND flash memory;

[0116] S302. Set V 4 V base , V 2 V adjust , substituting into the voltage adjustment method, V base Indicates adjustment of V adjust The reference voltage required in the process, V adjust Indicates the reference voltage that needs to be adjusted;

[0117] S303. Read the intermediate valid bit (CSB) data stored in the 3D TLC NAND flash memory;

[0118] S304. Set the adjusted V 2 and V 4 Corresponding to V base1 and V base2 , let V 3 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 3 .

[0119] like Fig.10 , Fig.11 , Fig.12 As shown, the step S4 is specifically as follows:

[0120] S401. Read the most significant bit (MSB) data stored in the 3D TLC NAND flash memory;

[0121] S402. Set V 1 V base , V 5 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0122] S403. Read the intermediate valid bit (CSB) data stored in the 3D TLC NAND flash memory;

[0123] S404. Set V 4 V adjust , V base is the default value, and the voltage adjustment method is substituted to obtain the optimized reference voltage V 4 ;

[0124] S405. Set the optimized reference voltage V 4 V base , V 2 V adjust, substitute into the voltage adjustment method, and get the optimized reference voltage V 2 ;

[0125] S406. Set the optimized reference voltage V 4 V base , V 6 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 6 ;

[0126] S407. Read the least significant bit (LSB) data stored in the 3D TLC NAND flash memory;

[0127] S408. Set V 1 and the optimized reference voltage V 5 V base1 and V base2 , V 3 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0128] S409. Set the optimized reference voltage V 6 V base , V 7 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 7 .

[0129] Example 4

[0130] A method for determining a read reference voltage of a 3D TLC NAND flash memory comprises the following steps:

[0131] S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data;

[0132] S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4;

[0133] S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by a voltage adjustment method, and executes step S5;

[0134] S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method accordingly, and execute step S5;

[0135] S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

[0136] like Figure 2 As shown, the stored data in the TLC NAND flash memory is divided into the most significant bit (MSB), the middle significant bit (CSB), and the least significant bit (LSB). In this embodiment, the reading process is divided into the MSB page reading process, the CSB page reading process, and the LSB page reading process:

[0137] (1)MSB read operation. In state P 0 and state P 1 Apply a read reference voltage V 1 , in state P 4 and state P 5 Apply a read reference voltage V 5 , if the cell threshold voltage V<V 1 or V>V 5 , the bit read is 1, otherwise it is 0.

[0138] (2) CSB read operation. In state P 1 and state P 2 Between, state P 3 and state P 4 Between, state P 5 and state P 6 The read reference voltage V 2 、V 4 and V 6 If the cell threshold voltage V 4 >VCT>V 2 or V>V 6 , the bit read is 0, otherwise it is 1.

[0139] (3) LSB read operation. In state P 2 and state P 3 Between, state P 6 and state P 7 Apply a read reference voltage V 3 and V 7 , if the cell threshold voltage V 7 >V>V 3 , then the read bit is 0, otherwise it is 1. In order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, namely V 1 、V 2 、V 3 、V 4 、V 5 、V6 、V 7 .

[0140] like Figure 6 , Figure 7 As shown in the figure, there are two main mechanisms for electron loss in flash memory cells, namely lateral charge migration (LCM) and vertical charge de-trap (VCT). The LCM mechanism only exists in CT-type 3D flash memory, which is caused by the two types of flash memory structures. The stability of the CT type is more easily affected by P / E cycles and data retention time. The VCT effect exists in both FG and CT flash memories. The VCT effect is mainly caused by the wear of the oxide layer (Tunnel Oxide) that prevents electron loss in the storage cell after the number of erases increases. When the oxide layer is worn to a certain extent, electrons can easily escape from the storage cell, resulting in data damage. It can be seen that the threshold voltage distribution is shifted to the left in both types of flash memory, but the specific characteristics of the shift are different. The low state shift is more in the FG-type 3D flash memory, while the high state shift is more in the CT-type 3D flash memory. After the threshold voltage shifts, using a fixed reference voltage will obviously cause data reading errors. Rapidly adjusting the reference voltage is very important in flash memory because the storage system must not only consider data stability but also latency. Too many adjustments will result in excessive time delays. Figure 6 and Figure 7 It can be seen that the threshold voltage distribution shifts to the left as a whole with the increase of P / E Cycles and data retention time, which also means that the read reference voltage should also be adjusted to the left.

[0141] like Figure 8 , Fig. 9 , Fig.10 As shown, the threshold voltage distribution of FG type has more shift in low state (P 0 , P 1 , P 2 , P 3 ), which means that only the reference voltages that distinguish these four low states need to be adjusted (V 1 , V 2 , V 3 ), while V 1 The default reference voltage is 0V and cannot be adjusted to the left. In the actual process, the voltage that needs to be adjusted is only V 2 , V 3 Therefore, the step S3 is specifically as follows:

[0142] S301. Read the least significant bit (LSB) data stored in the 3D TLC NAND flash memory;

[0143] S302. Set V 4 V base , V 2 V adjust , substituting into the voltage adjustment method, V base Indicates adjustment of V adjust The reference voltage required in the process, V adjust Indicates the reference voltage that needs to be adjusted;

[0144] S303. Read the intermediate valid bit (CSB) data stored in the 3D TLC NAND flash memory;

[0145] S304. Set the adjusted V 2 and V 4 Corresponding to V base1 and V base2 , let V 3 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 3 .

[0146] like Fig.10 , Fig.11 , Fig.12 As shown, unlike the FG type, the stability of the CT type 3D TLC flash memory is poor. Although the stability of the MSB page is also higher than that of other pages, the raw bit error rate (RBER) of different pages is relatively high. Therefore, the read reference voltages in the reading process of different pages need to be adjusted. The entire adjustment process is more complicated than that of the FG type. The step S4 is specifically as follows:

[0147] S401. Read the most significant bit (MSB) data stored in the 3D TLC NAND flash memory; the read reference voltage required for the MSB page read process is V 1 and V 5 In actual systems, P 0 is the erase state, V 1 Set to 0V, and you cannot adjust it to the left to lower the voltage. Therefore, the only voltage that needs to be adjusted is V 5 During this adjustment process, V 5 is set to V adjust , V 1 Set to V base We adjust V to the left 5 Until V 1 and V 5 The number of cells between the two is closest to 50% of the total number of MSB pages, and the corresponding V 5 , considering it as the optimal reference voltage.

[0148] S402. Set V 1 V base , V 5 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0149] S403. Read the intermediate valid bit (CSB) data stored in the 3D TLC NAND flash memory;

[0150] S404. Set V 4 V adjust , V base is the default value, and the voltage adjustment method is substituted to obtain the optimized reference voltage V 4 ;

[0151] S405. Set the optimized reference voltage V 4 V base , V 2 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 2 ;

[0152] S406. Set the optimized reference voltage V 4 V base , V 6 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 6 ;

[0153] S407. Read the least significant bit (LSB) data stored in the 3D TLC NAND flash memory;

[0154] S408. Set V 1 and the optimized reference voltage V 5 V base1 and V base2 , V 3 V adjust , substituting into the voltage adjustment method, we can get the optimized reference voltage V 5 ;

[0155] S409. Set the optimized reference voltage V 6 V base , V 7 V adjust , substitute into the voltage adjustment method, and get the optimized reference voltage V 7 .

[0156] As the P / E cycles and data retention time increase, the threshold voltage distribution will shift to the left. If a fixed reference voltage is used for judgment, a large number of data read errors will occur, which is not allowed in our storage system. Therefore, the corresponding read reference voltage should also move to the left. To adjust the reference voltage to the left, a reference standard is required to determine when the adjustment should stop. When the number of cells in each state is close to equal, it is used as the standard for stopping the adjustment. Therefore, the voltage adjustment method has the following specific steps:

[0157] M1. Initialize V adjust , V base , and Δ p The value of V adjust Indicates the reference voltage that needs to be adjusted, V base Indicates adjustment of V adjust The reference voltage required in the process, Δ p Indicates the minimum step voltage for each leftward adjustment; in this embodiment, Δ p is set to 7.5mv.

[0158] M2.Through V base Get the number of units N in the ideal state base and through V adjust and V base Get the actual number of units N intial ;

[0159] M3. Calculate the number of units N in the ideal state base and the actual number of units N intial The difference Δ;

[0160] M4. Determine the number of steps p for each adjustment based on the value of Δ and adjust V adjust The size of the new reference voltage V that needs to be adjusted adjust1 ; The calculation formula is as follows:

[0161] M5. According to the adjusted V adjust1 Calculate the actual number of units N again initial1 , and calculate the new difference Δ 1 ;

[0162] M6. According to Δ 1 The value of determines the number of steps p1 for each adjustment, and adjusts V adjust1 The size of the new reference voltage V adjust2 ;

[0163] M7. According to the adjusted V adjust2 Calculate the actual number of units N again initial2, and calculate the new difference Δ 2 ;

[0164] M8. Calculate Δ a1 =0.5*(Δ+Δ 1 ), Δ a2 =0.5*(Δ 1 +Δ 2 ); if Δ a1 >Δ a2 , let Δ=Δ 1 , Δ 1 =Δ 2 , repeat steps M5 to M7; if Δ a1 <Δ a2 , the adjustment process stops and the optimal read reference voltage is obtained Where Δ a1 is Δ 1 and the average value of Δ, Δ a2 is Δ 1 With Δ 2 The average value of .

[0165] Step M2, through V base Get the number of units N in the ideal state base The specific method is: draw the threshold voltage distribution corresponding to the 3D TLC NAND flash memory, the number of cells in the ideal state N base That is V base The number of flash memory cells on the left.

[0166] Step M3, obtaining Δ, the specific method is:

[0167] Δ=|N intial -N base *0.5|.

[0168] Step M4, determining the number of steps p for each adjustment, the specific method is:

[0169] When Δ>0.5*N base * At 5%, p = 4;

[0170] When 0.5*N base *1%<Δ≤0.5*N base * At 5%, p = 2;

[0171] When Δ<0.5*N base *When 1%, p=1.

[0172] Step M4, adjust V adjust The specific formula is as follows:

[0173] V adjust1 =V adjust -p*Δp .

[0174] Based on actual tests, the present invention divides 3D TLC NAND flash memory into FG type and CT type 3D stacked flash memory, reduces adjustment redundancy, proposes a corresponding adjustment algorithm, solves the problem that the prior art of determining the reference voltage of 3D TLC NAND flash memory is not suitable for 3D stacked flash and is not specific and efficient enough, and proposes a method for quickly determining the read reference voltage of 3D TLC NAND flash memory, which has the characteristics of being specific, efficient and easy to calculate.

[0175] Based on actual tests, the present invention divides 3D TLC NAND flash memory into FG type and CT type 3D stacked flash memory, reduces adjustment redundancy, proposes a corresponding adjustment algorithm, solves the problem that the prior art of determining the reference voltage of 3D TLC NAND flash memory is not suitable for 3D stacked flash and is not specific and efficient enough, and proposes a method for quickly determining the read reference voltage of 3D TLC NAND flash memory, which has the characteristics of being specific, efficient and easy to calculate.

[0176] Obviously, the above embodiments of the present invention are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A method for quickly determining a read reference voltage of a 3D TLC NAND flash memory, characterized in that: The following steps are involved: S1. Get the initial default reference voltage group in the 3D TLC NAND flash memory and start reading the stored data; In order to distinguish the storage state of the flash memory cell of the 3D TLC NAND flash memory, the reference voltage group is divided into 7 reference voltages, which are ; S2. Determine whether the storage cell type of the 3D TLC NAND flash memory is FG type or CT type. If it is FG type, execute step S3; if it is CT type, execute step S4; S3 sequentially reads the storage data stored in the FG-type 3D TLC NAND flash memory, and accordingly adjusts the corresponding FG-type reference voltage by the voltage adjustment method, and executes step S5; The stored data in the TLC NAND flash memory is divided into the most significant bit, the middle significant bit, and the least significant bit; The step S3 is specifically: S301 reads the least significant bit data stored in the 3D TLC NAND flash memory; S302. Set for , for , substituting into the voltage adjustment method, Indicates adjustment The reference voltage required in the process, Indicates the reference voltage that needs to be adjusted; S303. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory; S304. Set the adjusted and Corresponding to and ,set up for , substitute into the voltage adjustment method, and get the optimized reference voltage ; S4. Sequentially read the storage data stored in the CT-type 3D TLC NAND flash memory, and adjust the corresponding CT-type reference voltage by the voltage adjustment method, and execute step S5; The step S4 is specifically as follows: S401 reads the most significant bit data stored in the 3D TLC NAND flash memory; S402. Set for , for , substituting into the voltage adjustment method, we get the optimized reference voltage ; S403. Reading the intermediate valid bit data stored in the 3D TLC NAND flash memory; S404. Set for , As the default value, substitute the voltage adjustment method to get the optimized reference voltage ; S405. Set the optimized reference voltage for , for , substitute into the voltage adjustment method, and get the optimized reference voltage ; S406. Set the optimized reference voltage for , for , substitute into the voltage adjustment method, and get the optimized reference voltage ; S407. Reading the least significant bit data stored in the 3D TLC NAND flash memory; S408. Set and the optimized reference voltage for and , for , substituting into the voltage adjustment method, we get the optimized reference voltage ; S409. Assume the optimized reference voltage for , for , substitute into the voltage adjustment method, and get the optimized reference voltage ; S5. Arrange the optimized reference voltages to obtain an optimized reference voltage group for reading the 3D TLC NAND flash memory, and end the program.

2. The method for quickly determining a read reference voltage of a 3D TLC NAND flash memory according to claim 1, characterized in that: The voltage adjustment method comprises the following specific steps: M1. Initialization , , as well as The value of Indicates the reference voltage that needs to be adjusted. Indicates adjustment The reference voltage required in the process, Indicates the minimum step voltage for each left adjustment; M2. Pass The number of units required to obtain the ideal state and through and Get the actual number of units ; M3. Calculate the number of units in the ideal state and the actual number of units The difference ; M4. According to The value of determines the number of steps for each adjustment , and adjust The size of ; M5. According to the adjusted Calculate the actual number of units again , and calculate the new difference ; M6. According to The value of determines the number of steps for each adjustment , and adjust The size of the new reference voltage that needs to be adjusted is obtained ; M7. According to the adjusted Calculate the actual number of units again , and calculate the new difference ; M8. Calculation , ; like ,make , , repeat steps M5 to M7; if , the adjustment process stops and the optimal read reference voltage is obtained ,in and the average value of ∆, for and The average value of .

3. The method for quickly determining a read reference voltage of a 3D TLC NAND flash memory according to claim 2, wherein: Step M2, by The number of units required to obtain the ideal state The specific method is: draw the threshold voltage distribution corresponding to the 3D TLC NAND flash memory; the number of cells in the ideal state ,Right now The number of flash memory cells on the left.

4. The method for quickly determining a read reference voltage of a 3D TLC NAND flash memory according to claim 3, characterized in that: Step M3, get the difference , the specific method is: 。 5. The method for quickly determining a read reference voltage of a 3D TLC NAND flash memory according to claim 4, characterized in that: Step M4, determine the number of steps for each adjustment , the specific method is: when hour, = 4; when hour, = 2; when hour, = 1.

6. The method for quickly determining a read reference voltage of a 3D TLC NAND flash memory according to claim 5, characterized in that: Step M4, Adjust The specific formula is as follows: 。

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