Memory device and operating method thereof

Abstract

The present application relates to a memory device and an operating method thereof. According to an embodiment, a memory device includes: a plurality of cell strings, each cell string including memory cells and selection transistors connected in series; a peripheral circuit configured to apply a verification voltage to the selection transistor and perform internal operations on the memory cells; and a control logic configured to control the peripheral circuit to apply an operating voltage for internal operations. The control logic includes a bad string management component configured to: verify the threshold voltage of the selection transistor; and control the peripheral circuit to perform internal operations on the cell string including the selection transistor that passed the verification based on the verification result of the selection transistor.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores data and a storage controller for controlling the memory device. Memory devices can be classified as either volatile memory devices or non-volatile memory devices.

[0003] A volatile memory device is a device that stores data only when power is supplied and loses the stored data when power is interrupted. For example, a volatile memory device includes a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] Non-volatile memory devices are devices that do not lose data without power. For example, non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc.

[0005] To improve the integration density of memory devices, research is underway into three-dimensional structures. Three-dimensional memory devices have structural characteristics that differ from existing two-dimensional memory devices. Due to these structural differences, various driving methods for three-dimensional memory devices are also under investigation. Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory device and an operating method thereof that can process only a corresponding string as a defective string when distribution of selection transistors is abnormally formed.

[0007] A memory device according to an embodiment of the present disclosure may include: a plurality of cell strings, each including a memory cell and a select transistor connected in series; a peripheral circuit configured to apply a verification voltage to the select transistor and perform an internal operation on the memory cell; and control logic configured to control the peripheral circuit to apply an operating voltage for the internal operation. The control logic may include a bad string management component configured to verify the threshold voltage of the select transistor and, based on the verification result of the select transistor, control the peripheral circuit to perform an internal operation on the cell string including the select transistor that passed the verification.

[0008] A method for operating a memory device according to an embodiment of the present disclosure may include the following steps: verifying a threshold voltage of a selection transistor; storing status information based on a verification result of the threshold voltage of the selection transistor; outputting a status signal based on the status information, the status signal including a first status signal indicating a pass state of the selection transistor and a second status signal indicating a fail state of the selection transistor; and performing an internal operation in response to the status signal.

[0009] According to an embodiment of the present teachings, when distribution abnormality of a selection transistor is formed, a memory device capable of treating only a corresponding string as a defective string and an operating method thereof can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 3 is a diagram illustrating a memory cell array according to an embodiment of the present disclosure.

[0013] Figure 4 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0014] Figure 5 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0015] Figure 6 is a graph illustrating reliability degradation due to a change in the threshold voltage of a selection transistor according to an embodiment of the present disclosure.

[0016] Figure 7 is a graph showing a change in the threshold voltage of a selection transistor according to an embodiment of the present disclosure.

[0017] Figure 8 is a block diagram illustrating bad string management components according to an embodiment of the present disclosure.

[0018] Figure 9 is a diagram showing a configuration of a row decoder according to an embodiment of the present disclosure.

[0019] Figure 10 is a diagram showing a configuration of a row decoder according to an embodiment of the present disclosure.

[0020] Figure 11 is a diagram illustrating a bad block processing method according to an embodiment of the present disclosure.

[0021] Figure 12is a diagram illustrating an erase operation according to an embodiment of the present disclosure.

[0022] Figure 13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0023] Figure 14 is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0024] Figure 15 is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure.

[0025] Figure 16 is a diagram illustrating a user system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions disclosed in this specification or application are used to describe the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms and are not limited to the specific embodiments described in this specification or application.

[0027] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can realize the technical spirit of the present disclosure.

[0028] Figure 1 is a block diagram illustrating a storage device 1000 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the storage device 1000 may include a memory device 100 and a storage controller 200 .

[0030] The storage device 1000 may be a device that stores data under the control of a host 2000 (eg, a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a display device, a tablet PC, or an in-vehicle infotainment system).

[0031] The storage device 1000 may be implemented as one of various types of storage devices according to a host interface used as a communication method for communicating with the host 2000. For example, the storage device 1000 may be implemented as any of various types of storage devices, such as multimedia cards in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital cards in the form of SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI-Express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

[0032] The memory device 1000 may be implemented as any of various types of packages. For example, the memory device 1000 may be implemented as any of various types of packages such as package on package (POP), system on package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0033] The memory device 100 may store data or use stored data. Specifically, the memory device 100 may operate in response to the control of the memory controller 200. In addition, the memory device 100 may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array including a plurality of memory cells storing data.

[0034] Each memory cell may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0035] The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and a memory block may include a plurality of pages. Here, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100.

[0036] The memory device 100 may be implemented using double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, perpendicular NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In this specification, for convenience of description, it is assumed that the memory device 100 uses NAND flash memory.

[0037] The memory device 100 may receive a command and an address from the memory controller 200. The memory device 100 may be configured to access an area selected by the received address in the memory cell array. Accessing the selected area may mean performing an operation corresponding to the received command on the selected area. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. Here, a programming operation may be an operation in which the memory device 100 writes data to an area selected by an address. A read operation may mean an operation in which the memory device 100 reads data from an area selected by an address. An erase operation may mean an operation in which the memory device 100 erases data stored in an area selected by an address.

[0038] Each of the plurality of memory dies included in the memory device 100 may include at least one memory cell array. In addition, the plurality of memory dies may be controlled by a die interleaving operation, a channel interleaving operation, a path interleaving operation, or a plane interleaving operation.

[0039] In an embodiment of the present disclosure, the memory device 100 may include a bad string management component 140. The bad string management component 140 may store state information of the selection transistor as a result of a verification operation on the selection transistor, and may output a state signal based on the state information of the selection transistor. In addition, based on the verification result of the selection transistor, the bad string management component 140 may control the peripheral circuit to perform internal operations on the cell string including the selection transistor that passed the verification, and not perform internal operations on the cell string including the selection transistor that failed the verification. The internal operation performed by the peripheral circuit may be a read operation, an erase operation, or a program operation.

[0040] When power is applied to the memory device 1000, the memory controller 200 may execute firmware (FW). The firmware (FW) may include: a host interface layer (HIL) that receives a request input from the host 2000 or outputs a response to the host 2000; a flash translation layer (FTL) that manages operations between an interface of the host 2000 and an interface of the memory device 100; and a flash interface layer (FIL) that provides a command to the memory device 100 or receives a response from the memory device 100.

[0041] The memory controller 200 may receive data and a logical address (LA) from the host 2000, and convert the LA into a physical address (PA) indicating an address of a memory cell where data included in the memory device 100 is to be stored. The LA may be a logical block address (LBA), and the PA may be a physical block address (PBA).

[0042] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. according to a request from the host 2000. During a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0043] The memory controller 200 may independently control the memory device 100 to perform a program operation, a read operation, or an erase operation, independent of a request from the host 2000. For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation for performing background operations such as wear leveling, garbage collection, and read reclamation.

[0044] The host 2000 may communicate with the storage device 1000 using at least one of various communication protocols such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual Inline Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0045] Figure 2 is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0046] Reference Figure 2, the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0047] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. As an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include a plurality of pages. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0048] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0049] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. That is, the peripheral circuit 120 may drive the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0050] Specifically, the peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , and an input / output circuit 125 .

[0051] The row decoder 121 may be connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In addition, the row lines RL may also include a tube select line.

[0052] The row decoder 121 may be configured to operate in response to the control of the control logic 130. The row decoder 121 may receive a row address RADD from the control logic 130. Specifically, the row decoder 121 may be configured to decode the row address RADD. The row decoder 121 may select at least one of the memory blocks BLK1 to BLKz based on the decoded address. In addition, the row decoder 121 may select at least one word line of the memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0053] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a level higher than the read voltage to unselected word lines.

[0054] In an embodiment, an erase operation of the memory cell array 110 may be performed in memory block units. During the erase operation, the row decoder 121 may select a memory block according to a decoded address and apply a ground voltage to a word line connected to the selected memory block.

[0055] The voltage generator 122 may operate in response to the control of the control logic 130. The voltage generator 122 may be configured to generate a plurality of voltages using an external power supply voltage supplied to the memory device 100. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. in response to the control of the control logic 130. That is, the voltage generator 122 may generate various operation voltages Vop for program operations, read operations, and erase operations in response to the operation signal OPSIG.

[0056] As an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory cell array 110.

[0057] As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal power supply voltage, and may selectively enable the plurality of pumping capacitors to generate a plurality of voltages in response to control by the control logic 130. Furthermore, the generated voltages may be supplied to the memory cell array 110 via the row decoder 121.

[0058] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be connected to the memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. Furthermore, the first to nth page buffers PB1 to PBn may operate in response to control by the control logic 130. Specifically, the first to nth page buffers PB1 to PBn may operate in response to a page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn may temporarily store data received via the first to nth bit lines BL1 to BLn, or may sense the voltage or current of the bit lines BL1 to BLn during a read operation or a verify operation.

[0059] Specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first to nth page buffers PB1 to PBn may transmit data DATA received through the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. The memory cells of the selected page may be programmed according to the transmitted data DATA. The memory cells of the page selected according to the transmitted data DATA may be programmed. The memory cells connected to the bit lines to which a program enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a program inhibit voltage (e.g., a power supply voltage) is applied may be maintained.

[0060] During a program verification operation, the first through nth page buffers PB1 through PBn may read page data from selected memory cells through the first through nth bit lines BL1 through BLn.

[0061] During a read operation, under the control of the column decoder 124 , the first to nth page buffers PB1 to PBn may read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 .

[0062] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0063] As an embodiment, the page buffer group 123 may store the results of the erase operation. Specifically, the control logic 130 may control the peripheral circuit 120 to sequentially perform a verification operation for the erase operation on the cell strings included in the memory block. In addition, the control logic 130 may store the verification results of the erase operation in the page buffers connected to the respective bit lines in the page buffer group 123.

[0064] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0065] The input / output circuit 125 may transfer a command CMD and an address ADDR received from the memory controller 200 to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0066] The sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT during a read operation or a verification operation, and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0067] The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code. The control logic 130 may output an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. In addition, the control logic 130 may determine whether a verification operation for an internal operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0068] As an embodiment of the present disclosure, the control logic 130 may store verification information for an erase operation, including a pass signal PASS or a fail signal FAIL, in the page buffer group 123. Specifically, the memory device may sequentially perform erase verification on all cell strings included in a memory block for each cell string, and store the results of the erase verification in the page buffers connected to each bit line. As an embodiment, the control logic 130 may count the number of failed memory cells based on the verification information regarding the erase operation, and may output a trigger signal to apply an additional erase voltage when the number of failed memory cells exceeds a preset number.

[0069] As an embodiment, the control logic 130 may control the peripheral circuit 120 to verify the threshold voltage of the select transistor and perform internal operations on the cell strings including the selected transistors that passed the verification according to the verification results of the select transistors. Specifically, during an erase operation, the control logic 130 may control the peripheral circuit 120 to generate a block word line voltage even if the memory block to be erased includes a failed select transistor. In addition, during the erase voltage application period of the erase operation, the peripheral circuit 120 may be controlled to generate a select line selection signal for all cell strings included in the memory block and apply the same voltage to the select lines corresponding to all cell strings.

[0070] The bad string management component 140 can store state information of the selection transistor as a result of the verification operation on the selection transistor, and can output a state signal according to the state information of the selection transistor. In addition, the bad string management component 140 can control the peripheral circuit to perform internal operations on the cell string including the selection transistor that passed the verification and not perform internal operations on the cell string including the selection transistor that failed the verification according to the verification result of the selection transistor.

[0071] Figure 3 is a diagram illustrating a memory cell array 110 according to an embodiment of the present disclosure.

[0072] Reference Figure 3 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may be formed in a three-dimensional structure, and each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along the +X direction, the +Y direction, and the +Z direction. Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0073] Figure 4 is a diagram illustrating a memory block BLKa according to an embodiment of the present disclosure.

[0074] Reference Figure 4 , the storage block BLKa can be Figure 3 Any memory block among the memory blocks BLK1 to BLKz shown. The memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (i.e., +X direction).

[0075] In addition, Figure 4 In the embodiment, two cell strings are arranged in the column direction (ie, +Y direction), but this is for convenience of description, and in other embodiments, three or more cell strings may be arranged in the column direction.

[0076] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0077] Each of the select transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. As an embodiment, a pillar for providing a channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the blocking insulating layer may be provided in each cell string.

[0078] Source select transistors SST of respective cell strings may be connected between a common source line CSL and memory cells MC1 to MCp.

[0079] As an embodiment, source selection transistors of cell strings arranged in the same row may be connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows may be connected to different source selection lines. Figure 4 , the source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1 , and the source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2 .

[0080] As another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0081] The first to nth memory cells MC1 to MCn of each cell string may be connected between a source select transistor SST and a drain select transistor DST.

[0082] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MCp and (p+1)th memory cells MCp+1 to nth memory cells MCn. The first to pth memory cells MCp can be arranged sequentially in the -Z direction and can be connected in series between the source select transistor SST and the tube transistor PT. The (p+1)th memory cells MCp+1 to nth memory cells MCn can be arranged sequentially in the +Z direction and can be connected in series between the tube transistor PT and the drain select transistor DST. The first to pth memory cells MCp and (p+1)th memory cells MCp+1 to nth memory cells MCn can be connected via the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string can be connected to the first to nth word lines WL1 to WLn, respectively.

[0083] The gate of the tube transistor PT of each cell string may be connected to the pipe line PL.

[0084] The drain select transistors DST of each cell string are connected between the corresponding bit line and the memory cells MCp+1 to MCn. Cell strings arranged in a row direction can be connected to drain select lines extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row can be connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row can be connected to a second drain select line DSL2.

[0085] The cell strings arranged in the column direction may be connected to the bit lines extending in the column direction. Figure 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column may be connected to the m-th bit line BLm.

[0086] Memory cells connected to the same word line within cell strings arranged in a row direction can be configured as a page. For example, the memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m in the first row can represent one page. The memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m in the second row can represent another page. The cell strings arranged in a row direction can be selected by selecting one of the drain select lines DSL1 and DSL2. In addition, a page within the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0087] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to the even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to the odd bit lines, respectively.

[0088] As an embodiment, at least one or more of the first to nth memory cells MC1 to MCn may be used as dummy memory cells. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When more dummy memory cells are provided, the reliability of the operation of the memory block BLKa may be improved, but the size of the memory block BLKa may be increased. When fewer memory cells are provided, the size of the memory block BLKa may be reduced, but the reliability of the operation of the memory block BLKa may be reduced.

[0089] To efficiently control at least one or more dummy memory cells, each dummy memory cell may have a desired threshold voltage. Before or after an erase operation on the memory block BLKa, a program operation may be performed on all or some of the dummy memory cells. When an erase operation is performed after the program operation, the dummy memory cells may have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0090] Figure 5 is a diagram illustrating a memory block BLKb according to an embodiment of the present disclosure.

[0091] Reference Figure 5 , storage block BLKb represents Figure 3 Another embodiment of a memory block among the memory blocks BLK1 to BLKz shown. The memory block BLKb may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' may extend along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLK1'.

[0092] The source select transistors SST of each cell string may be connected between a common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row may be connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row may be connected to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row may be connected to a second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly connected to one source select line.

[0093] First to nth memory cells MC1 to MCn of each cell string may be connected in series between source select transistors SST and drain select transistors DST, and gates of first to nth memory cells MC1 to MCn may be connected to first to nth word lines WL1 to WLn, respectively.

[0094] The drain select transistors DST of each cell string can be connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction can be connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row can be connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row can be connected to the second drain select line DSL2.

[0095] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 5 The memory block BLKb may have Figure 4 The storage block BLKa has a similar circuit.

[0096] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the even bit lines, respectively, and odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to the odd bit lines, respectively.

[0097] As an embodiment, at least one or more of the first to nth memory cells MC1 to MCn may be used as dummy memory cells. For example, at least one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the reliability of the operation of the memory block BLKb may be improved, but the size of the memory block BLKb may be increased. When fewer memory cells are provided, the size of the memory block BLKb may be reduced, but the reliability of the operation of the memory block BLKb may be reduced.

[0098] To efficiently control at least one or more dummy memory cells, each dummy memory cell may have a desired threshold voltage. A programming operation may be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLKb. When an erase operation is performed after the program operation, the dummy memory cells may have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0099] Figure 6 is a graph illustrating reliability degradation due to a change in the threshold voltage of a selection transistor according to an embodiment of the present disclosure.

[0100] Reference Figure 6 , shows a cell string including a drain select transistor DST connected to a bit line BL, memory cells MC connected in series, and a source select transistor SST connected to a source line SL. The drain select transistor DST can control the amount of current I between the bit line BL and the memory cell MC. BL , and the source select transistor SST can control the current amount I between the source line SL and the memory cell MC SL For example, when the threshold voltage of the drain select transistor DST or the source select transistor SST is lower than the normal threshold voltage, since the amount of current sensed from the memory cell during the sensing operation may be lower than the normal current amount, a level higher than the actual threshold voltage of the memory cell may be sensed. Conversely, when the threshold voltage of the drain select transistor DST or the source select transistor SST is higher than the normal threshold voltage, since the amount of current sensed from the memory cell during the sensing operation may be higher than the normal current amount, a level lower than the actual threshold voltage of the memory cell may be sensed.

[0101] Figure 7 is a graph showing a change in the threshold voltage of a selection transistor according to an embodiment of the present disclosure.

[0102] Reference Figure 7, shows the threshold voltages of select transistors, including drain select transistors and source select transistors. Select transistors such as the drain select transistor and the source select transistor can perform a switching function, connecting or disconnecting a bit line or source line to a cell string. Specifically, in a memory device in which a memory block is implemented in a three-dimensional structure, the select transistors can be formed in the same structure as the memory cells. Therefore, in order for the select transistors to perform the switching function, they can have a normal threshold voltage 71 of a constant level.

[0103] However, the threshold voltage of the selection transistor may change due to various reasons. Specifically, as internal operations (e.g., read operations, erase operations, or program operations) of the memory block are repeated, leakage current may be generated in the selection transistor, and the threshold voltage of the selection transistor may decrease due to the generated leakage current. In addition, when internal operations are performed on a memory cell or cell string close to the selection transistor, the threshold voltage of the selection transistor may increase due to interference with the operating voltage driving the internal operation.

[0104] During internal operations (e.g., a read operation, an erase operation, or a program operation), the data of the memory cell is not sensed normally due to a left shift or a right shift that respectively reduces or increases the threshold voltage of the selection transistor relative to the previously formed normal threshold voltage 71, and thus the reliability of the memory device may be reduced.

[0105] In an embodiment of the present disclosure, the threshold voltage of the selection transistor (e.g., DST or SST) can be verified, and internal operations can be performed based on the verification results. Specifically, in order to determine whether the normal threshold voltage 71 of the selection transistor has changed, each of the first threshold voltage Vc1 and the second threshold voltage Vc2 can be set as a reference voltage. The first threshold voltage Vc1 can be a voltage for checking whether the threshold voltage has decreased, and can be set to the same level as the verification target voltage of the programming operation that increases the threshold voltage of the selection transistor. Alternatively, the first threshold voltage Vc1 can be set to the average voltage of the lowest voltage of the normal threshold voltage distribution of the selection transistor. The second threshold voltage Vc2 can be a voltage for checking whether the threshold voltage has increased, and can be set to the average voltage of the highest voltage of the normal threshold voltage distribution of the selection transistor.

[0106] In addition, the memory device can perform a verification operation regarding whether the threshold voltage of the selection transistor has changed by comparing the threshold voltage of the selection transistor with a preset reference voltage. Specifically, when the threshold voltage Vth of the selection transistor is measured to be lower than the first threshold voltage Vc1, the change value indicating the change in the threshold voltage may be a value of "1", and when the threshold voltage Vth of the selection transistor is measured to be higher than the first threshold voltage Vc1, the change value may be a value of "0". In addition, when the threshold voltage Vth of the selection transistor is measured to be higher than the second threshold voltage Vc2, the change value indicating the change in the threshold voltage may be a value of "1", and when the threshold voltage Vth of the selection transistor is measured to be lower than the second threshold voltage Vc2, the change value may be a value of "0". That is, when the threshold voltage Vth of the selection transistor decreases or increases, the change value may be "1", and the memory device can verify the threshold voltage of the selection transistor based on the change value. For example, as a result of verifying a particular select transistor, when the change value of the first threshold voltage Vc1 is "1" and the change value of the second threshold voltage Vc2 is "0," the memory device may determine that the threshold voltage Vth of the corresponding select transistor has decreased. Alternatively, as a result of verifying a particular select transistor, when the change value of the first threshold voltage Vc1 is "0" and the change value of the second threshold voltage Vc2 is "1," the memory device may determine that the threshold voltage Vth of the corresponding select transistor has increased. For example, as a result of verifying a particular select transistor, when the change value of the first threshold voltage Vc1 is "1" and the change value of the second threshold voltage Vc2 is "1," the memory device may determine that the distribution of the threshold voltage Vth of the corresponding select transistor has broadened as a whole. For example, as a result of verifying a particular select transistor, when the change value of the first threshold voltage Vc1 is "0" and the change value of the second threshold voltage Vc2 is "0," the memory device may determine that the corresponding select transistor maintains the initial distribution of the normal threshold voltage 71.

[0107] Figure 8 is a block diagram illustrating the bad string management component 140 according to an embodiment of the present disclosure.

[0108] Reference Figure 8 The bad string management component 140 may include a register 141 and a status signal output circuit 142. The register 141 may receive a verification result ST_vf of the threshold voltage of the selection transistor and store status information of the selection transistor according to the received verification result. In addition, the status signal output circuit 142 may output a status signal Status_SIG indicating a pass or fail based on the status information stored in the register 141.

[0109] The row decoder 121 may receive a row address RADD from the control logic 130 and a status signal Status_SIG from the bad string management component 140. Furthermore, the row decoder 121 may be controlled to perform internal operations only on cell strings including select transistors that have passed verification based on the row address and status signal. The internal operations may include programming, reading, and erasing operations.

[0110] Specifically, the row decoder 121 may perform a switching operation in response to a state signal so that a block word line voltage is not applied to a cell string including a selection transistor that has failed verification. For example, a program operation and a read operation may be performed in units of pages, and the row decoder 121 may perform a switching operation in response to a state signal so as not to generate a block word line BLKWL voltage.

[0111] Figure 9 and Figure 10 is a diagram showing a configuration of the row decoder 121 according to an embodiment of the present disclosure. Figure 11 is a diagram illustrating a bad block processing method according to an embodiment of the present disclosure.

[0112] Reference Figure 9 and Figure 10 , respectively, show the first circuit 121-1 and the second circuit 121-2 of the row decoder 121. The memory device can perform defect processing on a failed cell string including a failed selection transistor in units of one string based on the first circuit 121-1 and the second circuit 121-2.

[0113] When the memory device is powered on, the DSL_OK<0:n> signal may be first set to "1," and after a verification operation of the selection transistor, when the corresponding selection line is processed as defective, the DSL_OK<0:n> signal may be set to "0." That is, the DSL_OK<0:n> signal may be a signal indicating whether the drain selection line can operate normally. Specifically, when the BADBLK_LOAD signal, the XA signal, the XB signal, the XC signal, and the XD signal are all applied as "1," a signal "1" may be generated as the CON_N signal, the SEL_DSL signal, and the DSL_OK<0:n> signal. <x>The DSL_OK<0:n> signals are updated when the CAM_BAD_WRITE signal is received. Here, the XA, XB, XC, and XD signals may be signals applied in response to a specific address. The SEL_DSL signal may be a signal indicating that the drain select line DSL is selected in response to a specific address. The CON_N signal may be a signal indicating that a memory block is selected in response to a specific address.

[0114] As an embodiment, when an internal operation is performed on a cell string in which the DSL_OK<0:n> signal is set to "0", the row decoder 121 may perform a switching operation differently depending on whether the internal operation is performed in units of one string or in units of multiple strings. Specifically, when the internal operation is performed in units of one string (for example, when the internal operation is a program operation or a read operation), the row decoder 121 may receive "1" as the SEL_DSL corresponding to the drain select line according to a specific address. <x>However, when the specific address is a cell string including a failed selection transistor, DSL_OK <x>The signal can be set to "0" and "1" can be generated as SEL_DSL <x>signal, and thus the block word line BLKWL voltage may not be generated. In this case, the voltage of the global word line Global WL may not be transferred to the local word line Local WL, and a program operation or a read operation may not be performed. Figure 11 , even when one block among the memory blocks is not decoded, “1” may be transmitted to the control logic as a BADBLK signal, and thus an internal operation status may be generated as a fail.

[0115] On the other hand, when the internal operation is performed in units of multiple strings (for example, when the internal operation is an erase operation in which a memory block is used as one operation unit), the row decoder 121 can perform the internal operation regardless of whether a defective cell string including a failed select transistor exists. Specifically, the erase operation may include an erase pulse period and an erase verification period. During the erase pulse period, the row decoder 121 can apply the same voltage to all drain select lines DSL included in the memory block. Specifically, the row decoder 121 can be controlled so that all SEL_DSL<0:n> signals are generated as "1" so that all drain select lines can be selected. Even when one of the DSL_OK<0:n> signals is "1" (i.e., even when one of the drain select lines is operating normally), the row decoder 121 can perform a switching operation to generate a block word line BLKWL voltage. During the erase verification period, the row decoder 121 can be controlled for each cell string to perform erase verification on all cell strings in sequence. When erasure verification is performed for each cell string, when a specific string is processed as a bad string, a sensing operation may be performed while the block word line BLKWL is disabled (CON_N="0").

[0116] Figure 12 is a diagram illustrating an erase operation according to an embodiment of the present disclosure.

[0117] Reference Figure 12 , an erase cycle may include an erase pulse period and an erase verification period.

[0118] The erase pulse period may be a period during which an erase voltage is applied to a memory block. Specifically, when the erase voltage is applied to a memory cell included in the memory block, charges trapped in a floating gate may move and the threshold voltage of the memory cell may change. In other words, the erase pulse period may be a period for causing the memory cell included in the memory block to enter an erased state in which the memory cell is not programmed.

[0119] The erase verification period may be a period for verifying whether the threshold voltages of the memory cells included in the memory block have reached the erased state, which is the target state, after the erase pulse period. The erase verification period may include a period for sensing the bit lines. During the erase verification period, the sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT and compare the sensing voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0120] Conventionally, when the distribution of the threshold voltages of the select transistors included in a memory block is abnormally formed, the memory block including the corresponding select transistors may be identified as a bad block. In addition, when an internal operation (e.g., an erase operation) is performed on the bad block, a block word line voltage for the bad block is not generated, and thus an erase voltage is not applied to the cell strings including normal select transistors.

[0121] According to an embodiment of the present disclosure, even if a plurality of select transistors with abnormally formed threshold voltage distributions are present in a memory block, a block wordline voltage can be generated when at least one normal select transistor is present, thereby applying an erase voltage to the memory block. Furthermore, during the erase verification period, the memory device can sequentially perform erase verification on a plurality of cell strings and determine whether a pass or fail is performed for each cell string.

[0122] Figure 13 is a flowchart illustrating a method of operating a memory device, such as memory device 100 , according to an embodiment of the present disclosure.

[0123] The memory device may verify the threshold voltage of the selection transistor (S1310). When the internal operation of the memory block is repeated a plurality of times, a leakage current may be generated in the selection transistor, and the threshold voltage of the selection transistor may decrease due to the generated leakage current. Alternatively, the threshold voltage of the selection transistor may increase due to interference with the operating voltage of the internal operation. The memory device may verify whether the threshold voltage of the selection transistor is shifted to the left (left shift) (wherein the threshold voltage of the selection transistor is lower than the normal threshold voltage previously formed) or shifted to the right (right shift) (wherein the threshold voltage of the selection transistor is higher than the normal threshold voltage) (see Figure 7 ). The memory device may use the first threshold voltage Vc1 and the second threshold voltage Vc2 as reference voltages to determine whether the threshold voltage of the selection transistor is changed.

[0124] In addition, the memory device may store state information according to the verification result (S1320). Specifically, when the threshold voltage of the selection transistor changes, the memory device may store the state information of the selection transistor as fail, and when the threshold voltage of the selection transistor does not change, the memory device may store the state information of the selection transistor as pass.

[0125] In addition, the memory device may output a status signal according to the status information (S1330). Specifically, the memory device may output a status signal indicating whether verification of the threshold voltage has passed or failed based on the stored status information.

[0126] In addition, the memory device may perform an internal operation (S1340) in response to the state signal. Here, the internal operation may include a programming operation, a read operation, or an erase operation. As an embodiment, during a programming operation or a read operation, the memory device may perform a switching operation so that a block word line voltage is not applied to a cell string including a failed selection transistor. As an embodiment, even in the case where a failed selection transistor is included in a memory block, the memory device may apply an erase voltage to a cell string including a remaining pass selection transistor. Specifically, the memory device may generate a selection line selection signal for all cell strings included in the memory block and apply the same erase voltage to the selection lines corresponding to all cell strings. In addition, the memory device may perform erase verification on all cell strings included in the memory block in sequence for each cell string, and store the result of the erase verification in a page buffer connected to the bit line.

[0127] Figure 14 is a diagram illustrating a memory card system 3000 according to an embodiment of the present disclosure.

[0128] Reference Figure 14 , the memory card system 3000 may include a memory controller 3100 , a memory device 3200 , and a connector 3300 .

[0129] The memory controller 3100 may be electrically connected to the memory device 3200 and may be configured to access the memory device 3200. For example, the memory controller 3100 may be configured to control read operations, write operations, erase operations, and background operations on the memory device 3200. The memory controller 3100 may be configured to provide an interface between the memory device 3200 and a host. In addition, the memory controller 3100 may drive firmware for controlling the memory device 3200.

[0130] For example, the memory controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0131] The storage controller 3100 can communicate with an external device through the connector 3300. The storage controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the storage controller 3100 can be configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Minidisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 may be defined by at least one of the various communication standards mentioned above.

[0132] For example, the memory device 3200 may be implemented using various nonvolatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM).

[0133] The memory controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage (UFS).

[0134] Figure 15 is a diagram illustrating a solid-state drive (SSD) system 4000 according to an embodiment of the present disclosure.

[0135] Reference Figure 15 , an SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals SIG with the host 4100 through a signal connector 4001 and receive power PWR through a power connector 4002. The SSD 4200 may include an SSD controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply device 4230, and a buffer memory 4240.

[0136] In an embodiment, the SSD controller 4210 may perform a reference Figure 1 The functions of the storage controller 200 described above are described. The SSD controller 4210 may control the plurality of flash memories 4221 to 422n in response to a signal SIG received from the host 4100. For example, the signal SIG may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal SIG may be a signal defined by at least one interface such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0137] The auxiliary power supply device 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply device 4230 can receive power PWR from the host 4100 and be charged with the power. When the power supply from the host 4100 is unstable, the auxiliary power supply device 4230 can provide power to the SSD 4200. For example, the auxiliary power supply device 4230 can be provided in the SSD 4200 or can be provided outside the SSD 4200. For example, the auxiliary power supply device 4230 can be provided on the motherboard and can provide auxiliary power to the SSD 4200.

[0138] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0139] Figure 16 is a diagram illustrating a user system 5000 according to an embodiment of the present disclosure.

[0140] Reference Figure 16 , the user system 5000 may include an application processor 5100 , a memory module 5200 , a network module 5300 , a storage module 5400 , and a user interface 5500 .

[0141] The application processor 5100 may drive components, an operating system (OS), user programs, and the like included in the user system 5000. For example, the application processor 5100 may include a controller, an interface, a graphic engine, and the like that control components included in the user system 5000. The application processor 5100 may be provided as a system on chip (SoC).

[0142] The memory module 5200 can operate as a main memory, a working memory, a buffer memory, or a cache memory of the user system 5000. The memory module 5200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 5100 and the memory module 5200 may be packaged based on a package-on-package (POP) and provided as one semiconductor package.

[0143] The network module 5300 can communicate with external devices. For example, the network module 5300 can support wireless communication protocols such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. For example, the network module 5300 can be included in the application processor 5100.

[0144] The storage module 5400 can store data. For example, the storage module 5400 can store data received from the application processor 5100. Alternatively, the storage module 5400 can transmit the data stored in the storage module 5400 to the application processor 5100. For example, the storage module 5400 can be implemented as a non-volatile semiconductor memory element using a memory such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, the storage module 5400 can be provided as a removable storage device (removable drive) such as a memory card and an external drive of the user system 5000.

[0145] For example, the storage module 5400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with a reference Figures 1 to 13 The memory module 5400 can be used in conjunction with the memory device described in the reference Figure 1 The described memory device 1000 operates identically.

[0146] The user interface 5500 may include an interface for inputting data or instructions to the application processor 5100 or for outputting data to an external device. For example, the user interface 5500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 5500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0147] Although the detailed description of the present disclosure describes specific embodiments, various changes and modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present disclosure and the following claims.

[0148] CROSS-REFERENCE TO RELATED APPLICATIONS

[0149] This application claims the benefit of Korean Patent Application No. 10-2020-0107379, filed on August 25, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.< / x> < / x> < / x> < / x>

Claims

1. A memory device, comprising: a plurality of cell strings, each cell string including a memory cell and a selection transistor connected in series; a peripheral circuit configured to apply a verification voltage to the selection transistor and perform an internal operation on the memory cell; as well as a control logic configured to control the peripheral circuit to apply an operating voltage for the internal operation, wherein the control logic includes a bad string management component configured to: verifying a threshold voltage of the select transistor; controlling the peripheral circuit to perform the internal operation on the cell string including the selection transistor that passed the verification according to the verification result of the selection transistor; and The peripheral circuit is controlled to perform a switching operation on a cell string including a selection transistor that has failed verification according to the verification result of the selection transistor.

2. The memory device according to claim 1, wherein The bad string management component includes: a register configured to store state information of the selection transistor according to the verification result; and A state signal output circuit is configured to output a state signal according to the state information, the state signal including a first state signal indicating a pass state of the selection transistor and a second state signal indicating a fail state of the selection transistor.

3. The memory device according to claim 2, wherein The peripheral circuit is configured to perform the switching operation in response to the state signal during a program operation or a read operation so that a block word line voltage is not applied to a cell string corresponding to the second state signal.

4. The memory device according to claim 1 , further comprising: a memory block including one or more cell strings including a selection transistor that has failed verification, When an erase operation is performed using the memory block as an operation unit, the control logic is configured to control the peripheral circuit to perform an erase operation on remaining cell strings of the plurality of cell strings except for the one or more cell strings.

5. The memory device according to claim 4, wherein When there is at least one selection transistor that has passed verification among the selection transistors included in the memory block, the control logic is configured to control the peripheral circuit to generate a block word line voltage corresponding to the memory block.

6. The memory device according to claim 4, wherein The erasing operation includes an erasing voltage application period and an erasing verification period; and The control logic is configured to: controlling the peripheral circuit to generate a selection line selection signal for all cell strings included in the memory block during the erase voltage application period; and The same voltage is applied to the selection lines corresponding to all the cell strings.

7. The memory device according to claim 6, wherein: The control logic is configured to control the peripheral circuit to sequentially perform erase verification on all the cell strings included in the memory block for each cell string in the erase verification period and store a result of the erase verification in a page buffer connected to a bit line.

8. The memory device according to claim 7, wherein The control logic is configured to: Counting the number of memory cells that fail the erase verification; and When the number of failed memory cells exceeds a preset number, a trigger signal is output to additionally apply an erase voltage.

9. The memory device according to claim 1, wherein The control logic is configured to compare the threshold voltage of the selection transistor with a preset reference voltage to verify whether the threshold voltage of the selection transistor is changed.

10. A method of operating a memory device, the method comprising the steps of: verifying a threshold voltage of a select transistor; storing state information according to a verification result of the threshold voltage of the selection transistor; outputting a state signal according to the state information, the state signal including a first state signal indicating a pass state of the selection transistor and a second state signal indicating a fail state of the selection transistor; performing an internal operation in response to the status signal; and A switching operation is performed on a cell string including a selection transistor that has failed verification according to the verification result of the selection transistor.

11. The method according to claim 10, wherein: The step of performing the internal operation includes performing the switching operation so that a block word line voltage is not applied to a cell string corresponding to the second state signal during a program operation or a read operation.

12. The method according to claim 10, wherein: The step of performing the internal operation includes the following steps: when an erase operation is performed on a memory block including a plurality of cell strings and the plurality of cell strings include one or more cell strings including selection transistors that have failed verification, applying an erase voltage to the remaining cell strings of the plurality of cell strings except for the one or more cell strings.

13. The method according to claim 12, wherein: The steps of performing the internal operation include the following steps: generating a selection line selection signal for the plurality of cell strings included in the memory block; and The same erase voltage is applied to selection lines corresponding to the plurality of cell strings.

14. The method according to claim 12, further comprising the steps of: sequentially performing erasure verification on the plurality of cell strings included in the memory block for each cell string; and A result of the erase verification is stored in a page buffer connected to the bit lines.

15. The method according to claim 14, further comprising the steps of: Counting the number of memory cells that fail the erasure verification; as well as When the number of failed memory cells exceeds a preset number, a trigger signal is output to additionally apply the erase voltage.

16. The method according to claim 10, wherein The step of verifying the threshold voltage includes comparing the threshold voltage of the selection transistor with a preset reference voltage to verify whether the threshold voltage of the selection transistor is changed.

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