Electronic component, circuit board device and method for manufacturing electronic component

Abstract

The present invention discloses an electronic component, which includes a component body and an external electrode. The component body includes a dielectric and an internal electrode. The external electrodes each include a base layer formed on multiple surfaces of the component body and a conductive material layer formed on the base layer, the base layer is connected to the internal electrode, and the base layer includes a metal and common material particles dispersed in the metal. The base layer includes common material particles on the interface between the base layer and the conductive material layer, and the common material particles on the interface have edges covered by metal. The conductive material layer contacts the common material particles on the interface and the metal covering the edges of the common material particles on the interface.

Description

Technical Field

[0001] The present invention relates to an electronic component, a circuit board arrangement and a method for manufacturing an electronic component. Background Art

[0002] Due to the need to reduce the size of electronic devices, in order to reduce the mounting area of ​​electronic components, external electrodes are generally formed integrally on the component body in which the internal electrodes are arranged. The external electrode may include a base layer that contains not only metal but also co-material particles and other materials to control the sintering temperature of the external electrode and ensure adhesion of the external electrode to the component body.

[0003] If the amount of the common material particles in the base layer of the external electrode is too small, the thermal stress generated between the external electrode and the element body during sintering cannot be sufficiently alleviated, and cracks may occur in the element body and / or the base layer. On the other hand, if the amount of the common material particles in the base layer of the external electrode is too large, the uniformity of the plating layer formed on the base layer may be reduced.

[0004] Patent document 1 discloses a method of soldering external electrodes in which the amount of common material particles in the inner portion of the base layer of the external electrode is smaller than the amount of common material particles near the base layer surface to reduce cracks and ensure adhesion of solder to the external electrode.

[0005] Patent Document 1: JP-A-2000-277371 Summary of the invention

[0006] However, if the amount of common material particles near the surface of the external electrode base layer is too small, when sintering is performed to solidify the base layers and integrate the base layers with the element body while the base layers of adjacent electronic components are in contact with each other, poor fusion may occur: the base layers of adjacent different electronic components stick to each other.

[0007] On the other hand, if the amount of common material particles near the surface of the external electrode base layer is increased to prevent poor fusion during sintering, and if the common material particles on the surface of the external electrode base layer are removed by physical or chemical polishing after sintering to improve the uniformity of the plating on the base layer, damage to the component body is greater.

[0008] An object of the present invention is to provide an electronic component, a circuit board device, and a method of manufacturing an electronic component, which can minimize poor fusion and damage to a component body while preventing a decrease in plating uniformity.

[0009] According to one aspect of the present invention, an electronic component is provided, which includes a component body and an external electrode. The component body includes a dielectric and an internal electrode. The external electrodes each include a base layer formed on multiple surfaces of the component body and a conductive material layer formed on the base layer, the base layer is connected to the internal electrode, and the base layer includes a metal and common material particles dispersed in the metal. The base layer includes common material particles at the interface between the base layer and the conductive material layer, and the common material particles at the interface have edges covered by metal. The conductive material layer is in contact with the common material particles at the interface and the metal covering the edges of the common material particles at the interface.

[0010] The metal near the interface in the base layer can surround the common material particles.

[0011] The metal at the interface may cover the edges of the common material particles at the interface.

[0012] The length of the cross section of each common material particle on the interface in contact with the conductive material layer may be in the range of 0.1 μm to 12 μm.

[0013] The thickness of the metal sheet covering the edge of the co-material particle may be in the range of 0.1 μm to 0.7 μm in cross section, and the length of the metal sheet may be in the range of 0.2 μm to 2.5 μm.

[0014] The thickness of the metal sheet covering the edge of the co-material particle may be in the range of 0.2 μm to 0.6 μm in cross section, and the length of the metal sheet may be in the range of 0.5 μm to 2.0 μm.

[0015] The amount of the co-material particles in the base layer may be in the range of 10 wt % to 45 wt %.

[0016] The main component of the dielectric and the main component of the co-material particles may have the same composition.

[0017] The main component of the co-material particles may be oxide ceramics.

[0018] In the base layer, the ratio of the common material particles to the metal on the element body side may be equal to that on the conductive material layer side.

[0019] The main component of the co-material particles may be at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate and titanium dioxide.

[0020] The metal may include at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy thereof.

[0021] The element body may include a laminate, the laminate includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer and the second internal electrode layer are alternately arranged with a dielectric therebetween. The external electrode may include a first external electrode and a second external electrode, the first external electrode is located on a first side surface of the laminate and connected to the first internal electrode layer, and the second external electrode is spaced from the first external electrode, is located on a second side surface of the laminate opposite to the first side surface, and is connected to the second internal electrode layer.

[0022] According to another aspect of the present invention, there is provided a circuit board device including a circuit board and an electronic component mounted on the circuit board. The electronic component is connected to the circuit board via a solder layer attached to a conductive material layer of the electronic component.

[0023] According to another aspect of the present invention, a method for manufacturing an electronic component is provided. The method includes the following steps: forming a component body including a dielectric and an internal electrode; applying a mixed material obtained by dispersing common material particles in an electrode material containing a metal to the opposite side surfaces of the component body and the surrounding surface of the component body adjacent to the side surface; sintering the mixed material to form a base layer in which the common material particles are dispersed in the metal on the opposite side surfaces and the surrounding surface of the component body; oxidizing the metal of the base layer to form an oxide film of the metal on the exposed surface of the base layer; and sandblasting and polishing the exposed surface of the base layer from a direction oblique to each exposed surface of the base layer to remove the oxide film and make the metal rise above the edge of the common material particles; and forming conductive material layers on the base layer in such a way that each conductive material layer is in contact with the common material particles and the metal rising above the edge of the common material particles.

[0024] The bevel angle relative to each exposed surface of the base layer may be in the range of 15 degrees to 35 degrees.

[0025] According to an aspect of the present invention, it is possible to prevent adhesion degradation of the plating layer while minimizing poor fusion and damage to the component body.

[0026] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view showing a laminated ceramic capacitor according to a first embodiment of the present invention;

[0028] Figure 2 yes Figure 1 A cross-sectional view of a stacked ceramic capacitor taken along its longitudinal direction;

[0029] Figure 3 yes Figure 1 An enlarged cross-sectional view of the EC portion in FIG.

[0030] Figure 4 is a flowchart showing a method of manufacturing a laminated ceramic capacitor according to a first embodiment;

[0031] Figure 5A is a cross-sectional view for explaining a method of manufacturing a laminated ceramic capacitor according to a first embodiment;

[0032] Figure 5B is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0033] Figure 5C is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0034] Figure 5D is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0035] Figure 5E is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0036] Fig. 5F is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0037] Figure 5G is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0038] Figure 5H is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0039] Fig.5I is another cross-sectional view for explaining the method of manufacturing the laminated ceramic capacitor according to the first embodiment;

[0040] Fig. 6A yes Figure 5G An enlarged cross-sectional view of the EA portion;

[0041] Figure 6B yes Figure 5H An enlarged cross-sectional view of the EB portion;

[0042] Figure 7 is a cross-sectional view showing a circuit board device according to a second embodiment, in which a laminated ceramic capacitor is mounted to a circuit board;

[0043] Figure 8 is a perspective view showing an electronic component according to a third embodiment;

[0044] Fig. 9 is a graph showing the relationship between the amount of common material, the fusion failure rate, and the poor plating rate in the multilayer ceramic capacitor of the embodiment, wherein the poor plating rate is examined for the embodiment with and without sandblasting the base layer; and

[0045] Fig.10 Prepared from Fig. 9 of table. DETAILED DESCRIPTION

[0046] Embodiments of the present invention will now be described with reference to the accompanying drawings. The following embodiments are not intended to limit the present invention. The combination of all features described in the various embodiments is not absolutely necessary for the present invention. The configuration of each embodiment may be modified and / or changed according to the design, specifications and various conditions (conditions of use, use environment, etc.) of the devices and equipment to which the present invention is applied. The technical scope of the present invention is defined by the appended claims and is not limited by the following embodiments. In addition, the parts, components and elements shown in the drawings used in conjunction with the following description may be different from the actual parts, components and elements in structure, proportion and shape, so that the parts, components and elements are more easily understood.

[0047] First embodiment

[0048] Figure 1 : is a perspective view showing a laminated ceramic capacitor 1 according to a first embodiment of the present invention. Figure 2 yes Figure 1 1 is a cross-sectional view of a laminated ceramic capacitor 1 taken along its longitudinal direction.

[0049] exist Figure 1 and Figure 2 In the embodiment, a laminated ceramic capacitor 1 includes an element body (component) 2, an external electrode (external electrode) 6A and another external electrode (external electrode) 6B. The element body 2 has a laminate (or stack) 2A, a lower cover layer 5A and an upper cover layer 5B. The laminate 2A has an internal electrode layer (internal electrode layer) 3A, another internal electrode layer 3B, and a dielectric layer 4 interposed between adjacent internal electrode layers 3A and 3B.

[0050] The lowermost layer of the stack 2A is covered by the lower cover layer 5A, and the uppermost layer of the stack 2A is covered by the upper cover layer 5B. The internal electrode layers 3A and 3B are alternately stacked in such a manner that the dielectric layer 4 is interposed therebetween. The shape of the element body 2 can be a roughly rectangular parallelepiped shape, and the shape of the stack 2A can also be a roughly rectangular parallelepiped shape. The element body 2 can be chamfered along the corresponding edges (end edges) of the element body 2. In the following description, the direction perpendicular to the two side surfaces of the element body 2 may be referred to as the longitudinal direction DL, the direction perpendicular to the front and rear surfaces of the element body 2 may be referred to as the width direction DW, and the direction perpendicular to the upper and lower surfaces of the element body 2 may be referred to as the stacking direction DS.

[0051] External electrodes 6A and 6B are located at opposite sides of element body 2 so as to be spaced apart from each other. Each of external electrodes 6A and 6B continuously extends from the side surface of element body 2 to both front and rear surfaces and both upper and lower surfaces.

[0052] In the longitudinal direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions in the stacked body 2A. The internal electrode layer 3A may be closer to the left side surface of the element body 2 than the internal electrode layer 3B, and the internal electrode layer 3B may be closer to the right side surface of the element body 2 than the internal electrode layer 3A. The left end of the internal electrode layer 3A is exposed from the left end of the dielectric layer 4 along the longitudinal direction DL of the element body 2 at the left side surface and is connected to the external electrode 6A. The right end of the internal electrode layer 3B is exposed from the right end of the dielectric layer 4 along the longitudinal direction DL of the element body 2 at the right side surface and is connected to the external electrode 6B.

[0053] On the other hand, in the width direction DW perpendicular to the longitudinal direction DL perpendicularly passing through both side surfaces of the element body 2, the ends of the internal electrode layers 3A and 3B are covered with the dielectric material forming the dielectric layer 4. In the width direction DW, the end of the internal electrode layer 3A can be aligned with the end of the internal electrode layer 3B.

[0054] The outer dimensions of the laminated ceramic capacitor 1 are as follows, for example: the length may be 1.0 mm, the width may be 0.5 mm, and the height may be 0.5 mm. The thickness of each of the internal electrode layer 3A, the internal electrode layer 3B, and the dielectric layer 4 in the stacking direction DS may be in the range of 0.05 μm to 5 μm, for example, 0.3 μm. The thickness of each of the external electrodes 6A and 6B may be in the range of 10 μm to 40 μm, for example.

[0055] The material of the internal electrode layers 3A and 3B may be a metal such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum) or W (tungsten), or may be an alloy containing these metals.

[0056] The main component of the material of the dielectric layer 4 may be, for example, a ceramic material having a perovskite structure. The main component may be contained at a ratio of 50 at % or more. The ceramic material of the dielectric layer 4 may be, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate, or titanium oxide.

[0057] The main component of the material of the lower cover layer 5A and the upper cover layer 5B may be, for example, a ceramic material. The main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as the main component of the ceramic material of the dielectric layer 4 .

[0058] The external electrodes 6A and 6B each include a base layer 7 and a plated layer 9 as a conductive material layer. The external electrodes 6A and 6B are spaced apart from each other in the length direction DL and are formed on a plurality of surfaces of the element body 2. More specifically, the external electrodes 6A and 6B each have five outer surfaces arranged around the element body 2, including an outer surface whose opposite surface is in contact with the end surface of the element body 2 in the longitudinal direction DL. One of the five outer surfaces of each of the external electrodes 6A and 6B serves as a mounting surface that faces and is mounted to a circuit board on which the laminated ceramic capacitor 1 is mounted. The mounting surface is the bottom surface of each of the external electrodes 6A and 6B on the bottom side of the element body 2.

[0059] The base layer 7 is located between the element body 2 and the plating layer 9. The base layer 7 electrically connects the plurality of internal electrode layers 3A or 3B to the plating layer 9. The base layer 7 includes a metal as a conductive material. For example, the metal of the base layer 7 may be mainly composed of a metal containing at least one of Cu, Fe (iron), Zn (zinc), Al (aluminum), Ni, Pt, Pd, Ag, Au, and Sn (tin), or an alloy thereof.

[0060] The base layer 7 also includes a common material in the form of particles. The common material reduces the difference in thermal expansion coefficients between the component body 2 and the base layer 7 to relieve the stress applied to the base layer 7, and can improve the adhesion of the base layer 7 to the component body 2. The common material may have the same composition as the dielectric layer 4. For example, it may contain a ceramic component that is the same as the main component of the ceramic material of the dielectric layer 4. The common material may contain the same main component as the main component of the dielectric layer 4, or a ceramic material that is different from the material of the dielectric layer 4. In the case where the common material contains a ceramic material that is different from the material of the dielectric layer 4, it is preferred that the difference between the thermal expansion coefficients of the common material and the dielectric layer 4 is within ±30% of the thermal expansion coefficient of the dielectric layer 4.

[0061] The common material is mixed with the metal material of the base layer 7, and the edges of the common material particles at the interface between the base layer 7 and the plating layer 9 are covered by the metal material of the base layer 7. The metal material in the base layer 7 near the interface between the base layer 7 and the plating layer 9 surrounds the common material particles. The metal material at the interface between the base layer 7 and the plating layer 9 covers the edges of the common material particles at the interface between the base layer 7 and the plating layer 9. In the base layer 7, the ratio of the common material particles to the metal material on the element body 2 side can be equal to the ratio on the plating layer 9 side.

[0062] The base layer 7 may contain a glass component. The glass component is used for densification of the base layer 7, etc. The glass component may be, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), B (boron), etc. The base layer 7 is electrically connected to the plurality of internal electrode layers 3A and 3B exposed on the side surface of the element body 2.

[0063] The base layer 7 may include the same metal component as the metal component included in the element body 2. The metal component included in the element body 2 may include at least one of Mg, Ni, Cr, Sr, Al, Na, and Fe, and may be, for example, Mg. If the metal component included in the element body 2 is Mg, the base layer 7 may include a compound of the metal in the base layer 7, the metal included in the element body 2, and oxygen. For example, the compound included in the base layer 7 includes Ni, Mg, and O.

[0064] The plating layer 9 is formed on the base layer 7. The plating layer 9 contacts the co-material particles of the base layer 7 and the metal material covering the edges of the co-material particles. For example, the main component of the material of the plating layer 9 is a metal such as Cu, Ni, Al, Zn and Sn, or an alloy containing at least two of Cu, Ni, Al, Zn and Sn. The plating layer 9 may be a plating layer of a single metal component, or may include a plurality of plating layers of different metal components.

[0065] For example, the plating layer 9 may have a three-layer structure, that is, the plating layer 9 may include a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A can improve the adhesion of the plating layer 9 to the base layer 7. The Ni plating layer 9B can improve the heat resistance of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C can improve the wettability of the solder of the plating layer 9. In each of the external electrodes 6A and 6B, the plating layer 9 is electrically connected to the internal electrode layer 3A or 3B through the base layer 7. In addition, the plating layer 9 is electrically connected to the terminal of the circuit board through the solder.

[0066] When the metal component of the base layer 7 is Cu, the Cu plating layer 9A may be omitted. If the Cu plating layer 9A is not formed, the plating layer 9 may have a two-layer structure, that is, the plating layer 9 may include a Ni plating layer 9B and a Sn plating layer 9C formed on the Ni plating layer 9B.

[0067] Figure 3 yes Figure 1 Magnified cross-sectional view of the EC portion.

[0068] exist Figure 3 , the base layer 7 includes a metal layer 7A, common material particles 7B and a coating metal sheet 7C. The common material is mixed in the metal layer 7A and dispersed in the metal layer 7A as the common material particles 7B. Here, the term "particle" means not only including individual small particles, but also including a mass formed by a combination of multiple small particles after a sintering process, which will be described later. The coating metal sheet 7C covers the edge of the common material particle 7B located at the interface between the base layer 7 and the plating layer 9.

[0069] The coated metal sheet 7C can be formed by causing the material of the metal layer 7A to rise above the common material particles 7B located at the interface between the base layer 7 and the plating layer 9. By causing the material of the metal layer 7A around the common material particles 7B to extend to the exposed surface of the common material particles 7B, individual coated metal sheets 7C can be continuously manufactured around the exposed common material particles 7B on the surface (which forms the interface). The coated metal sheet 7C can be arranged on at least a portion of the periphery of the surface of the common material particles 7B on the interface. The coated metal sheet 7C does not have to be arranged on the surface of all the common material particles 7B on the interface, but can be arranged on the surface of some of the common material particles 7B on the interface. In order to form the coated metal sheet 7C on the common material particles 7B on the surface of the base layer 7, the surface of the base layer 7 can be sandblasted and polished from a direction that is inclined to the surface of the base layer. The Cu plating layer 9A is formed on the base layer 7. The Cu plating layer 9A can be in contact with the metal layer 7A, the common material particles 7B and the coated metal sheet 7C.

[0070] By providing the coating metal sheet 7C at the interface between the base layer 7 and the plating layer 9 to cover the edge of the common material particles 7B, the area ratio of the common material particles 7B exposed at the interface between the base layer 7 and the Cu plating layer 9A can be reduced while avoiding a reduction in the ratio of the common material particles 7B in the base layer 7. Therefore, the uniformity of the Cu plating layer 9A on the base layer 7 can be improved while minimizing the difference in thermal expansion coefficients between the element body 2 and the base layer 7.

[0071] Therefore, the wettability of each of the external electrodes 6A and 6B to solder can be improved while minimizing damage to the element body 2 due to the difference in thermal expansion coefficient during the sintering process of forming the base layer 7 on the element body 2 .

[0072] In addition, it is no longer necessary to remove the common material particles 7B on the exposed surface of the base layer 7 to improve the uniformity of the Cu plating layer 9A on the base layer 7. Therefore, it is no longer necessary to physically and chemically polish the base layer 7 before plating to remove the common material particles 7B on the exposed surface of the base layer 7, thereby reducing damage to the component body 2 in the plating pretreatment.

[0073] After the sintering process of forming the base layer 7 on the element body 2, before forming the Cu plating layer 9A on the base layer 7, the coating metal sheet 7C can be formed on the surface of the base layer 7. Therefore, even when the sintering is performed in a state where the base layers 7 of adjacent electronic components are in contact with each other, the contact area between the common material particles 7B of the base layers 7 of different electronic components can be increased, so that poor fusion in which the base layers 7 of adjacent electronic components stick together can be reduced.

[0074] The length L1 of each common material particle 7B on the cross section in contact with the Cu plating layer 9A at the interface between the base layer 7 and the Cu plating layer 9A is preferably in the range of 0.1 μm to 12 μm. By setting the length L1 to be 0.1 μm or more, poor fusion can be prevented, and the polishing amount used to raise the coated metal sheet 7C beyond the edge of the common material particle 7B in the sandblasting polishing can be minimized, thereby reducing damage to the element body 2. In addition, by setting the length L1 to be 12 μm or less, the Cu plating layer 9A can be prevented from being pierced by the common material particle 7B and the continuity of the Cu plating layer 9A on the base layer 7 can be ensured.

[0075] The thickness T1 of the coated metal sheet 7C in the cross section is preferably in the range of 0.1 μm to 0.7 μm, and the length L2 of the coated metal sheet 7C is preferably in the range of 0.2 μm to 2.5 μm. By setting the thickness T1 to be greater than 0.1 μm and the length L2 to be greater than 0.2 μm, the adhesion of the Cu plating layer 9A to the base layer 7 can be improved. By setting the thickness T1 to be less than 0.7 μm and the length L2 to be less than 2.5 μm, the polishing amount used to raise the coated metal sheet 7C beyond the edge of the common material particle 7B during sandblasting can be reduced, thereby reducing damage to the element body 2.

[0076] More preferably, the thickness T1 of the coated metal sheet 7C on the cross section is in the range of 0.2 μm to 0.6 μm, and the length L2 is in the range of 0.5 μm to 2.0 μm. By setting the thickness T1 to be 0.2 μm or more and the length L2 to be 0.5 μm or more, the adhesion of the Cu plating layer 9A to the base layer 7 can be further improved. By setting the thickness T1 to be 0.6 μm or less and the length L2 to be 2.0 μm or less, the polishing amount used to raise the coated metal sheet 7C beyond the edge of the common material particle 7B in the sandblasting polishing can be further reduced, thereby further reducing the damage to the element body 2.

[0077] The amount of the common material particles in the base layer 7 is preferably in the range of 10wt% to 45wt%. If the amount of the common material in the base layer 7 is less than 10wt%, the adhesion of the base layer 7 to the element body 2 is weakened and the above-mentioned poor fusion increases. If the amount of the common material in the base layer 7 is 45% or more, the poor adhesion of the plating increases. Therefore, by setting the amount of the common material in the base layer 7 in the range of 10wt% to 45wt%, it is possible to limit defective fusion and poor adhesion of the plating, and the poor fusion rate and the poor plating rate can be made close to 0%. It is more preferred that the amount of the common material in the base layer 7 is in the range of 15wt% to 35wt%, so that the poor fusion rate and the poor plating rate can be close to 0%.

[0078] Figure 4 is a flowchart showing a method of manufacturing the laminated ceramic capacitor according to the first embodiment. Figures 5A to 5I is a cross-sectional view illustrating an exemplary method of manufacturing the stacked ceramic capacitor according to the first embodiment. Fig. 6A yes Figure 5G An enlarged cross-sectional view of the EA portion. Figure 6B yes Figure 5H For illustration purposes, FIG. 5C to FIG. 5I Only two internal electrode layers 3A and two internal electrode layers 3B that are alternately stacked with dielectric layers 4 interposed therebetween are shown.

[0079] exist Figure 4 In step S1 (mixing step), an organic binder and an organic solvent as a dispersant and a forming aid are added to the dielectric material powder, which are crushed and mixed to produce a muddy slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may include one or more additives. The additive may be, for example, Mg, Mn, V, Cr, Y, Sm, Eu, Gd, TB, Dy, Ho, Er, Tm, YB, Co, Ni, Li, B, Na, K or Si oxide, or glass. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0080] Next, in Figure 4 In step S2 (slurry application step), as Figure 5A As shown, a green sheet 24 is manufactured. Specifically, a slurry containing ceramic powder is applied to a carrier film in a sheet shape and dried to manufacture the green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry is applied by using, for example, a doctor blade method, a die coater method, or a gravure coater method. Step S2 is repeated to prepare a plurality of green sheets 24.

[0081] Next, in Figure 4 In step S3 (printing step), Figure 5BAs shown, a conductive paste (which will become an internal electrode layer) is applied in a predetermined pattern to each of the green sheets 24 (on which the inner electrode layer will be placed) in the green sheets prepared in step S1. Figure 1 The internal electrode layers 3A or 3B shown in the figure are formed on the green sheets 24 to form internal electrode patterns 23. In step S3, a plurality of internal electrode patterns 23 may be formed on each single green sheet 24 so that the internal electrode patterns 23 are spaced apart from each other in the longitudinal direction of the green sheets 24.

[0082] The conductive paste for the internal electrode layer includes a powder of a metal used as a material for the internal electrode layers 3A and 3B. For example, if the metal used as a material for the internal electrode layers 3A and 3B is Ni, the conductive paste for the internal electrode layer includes a powder of Ni. The conductive paste for the internal electrode layer also includes a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for the internal electrode layer may include a ceramic material as a co-material, the ceramic material having a main component having the same composition as the main component of the dielectric layer 4.

[0083] The application of the conductive paste for the internal electrode layer can be performed by using a screen printing method, an inkjet printing method, or a gravure printing method. Therefore, step S3 can be referred to as a printing step. In this way, a plurality of green sheets 24 having internal electrode patterns 23 thereon are prepared.

[0084] Next, in Figure 4 In step S4 (stacking step), Figure 5C As shown, the green sheets 24 on which the internal electrode patterns 23 are formed and the green sheets 24A on which the internal electrode patterns 23 are not formed are stacked in a predetermined order to generate the green sheet block 25. The green sheets 24A on which the internal electrode patterns 23 are not formed are used as the outer layers (lower cover layer 5A and upper cover layer 5B). In step S4, the green sheets 24 having the internal electrode patterns 23A or 23B thereon are divided into two groups, namely, the green sheets 24 having the internal electrode patterns 23A thereon (which will form the internal electrode layer 3A) and the green sheets 24 having the internal electrode patterns 23B thereon (which will form the internal electrode layer 3B). The green sheets 24 having the internal electrode patterns 23A thereon and the green sheets 24 having the internal electrode patterns 23B thereon are alternately stacked in the stacking direction so that the internal electrode patterns 23A on the green sheets 24 are alternately shifted with the internal electrode patterns 23B on the next or adjacent green sheets 24 in the longitudinal direction of the green sheets 24. Furthermore, three types of portions are defined in the green sheet block 25. Specifically, the green sheet block 25 includes a portion in which only the internal electrode pattern 23A is stacked in the stacking direction, a portion in which the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction, and a portion in which only the internal electrode pattern 23B is stacked in the stacking direction.

[0085] Next, in Figure 4 In step S5 (crimping step), Figure 5D As shown, the laminated body block 25 obtained in the lamination step of step S4 of Fig. 4 is pressed so that the green sheets 24 are press-bonded. Pressing the laminated body block 25 can be performed by, for example, sandwiching the laminated body block 25 between resin films and pressing the laminated body block 25 by hydrostatic pressure.

[0086] exist Figure 4 In step S6 (cutting step), as Figure 5E As shown in FIG. 2 , the pressed laminated body block 25 is cut so that the laminated body block 25 is divided into a plurality of element bodies, each of which has a rectangular parallelepiped shape. Each element body has six surfaces. The cutting of the laminated body block 25 is performed at the following parts: a part where only the internal electrode pattern 23A is stacked in the stacking direction, and a part where only the internal electrode pattern 23B is stacked in the stacking direction, as indicated by a plurality of vertical dotted lines 27. The cutting of the laminated body block 25 is performed, for example, by blade cutting or a similar method. Fig. 5F The resulting element body 2 is shown in FIG.

[0087] like Fig. 5F As shown, in each individual element body 2, internal electrode layers 3A and 3B are alternately stacked with dielectric layers 4 interposed therebetween. Internal electrode layer 3A is exposed on one side of each element body 2, and internal electrode layer 3B is exposed on the other side of each element body 2.

[0088] Next, in Figure 4 In step S7 (adhesive removal step), Figure 4 The adhesive contained in each element body 2 obtained in step S6 is removed. The removal of the adhesive is performed by heating the element body 2 at about 350 degrees Celsius in an N2 atmosphere, for example.

[0089] Then, in Figure 4 In step S8 (step of applying a paste for a base layer), a conductive paste for a base layer (bottom layer) 7 is applied to the conductive layer 11 of the substrate. Figure 4The two sides of each component body 2 from which the adhesive is removed in step S7, and those edges of the remaining four surfaces of the component body 2 that are in contact with the corresponding sides. Then, the conductive paste is dried. The conductive paste for the base layer 7 contains a powder or filler of a metal used as a conductive material of the base layer 7. For example, when the metal used as the conductive material of the base layer 7 is Ni, the conductive paste for the base layer contains a powder or filler of Ni. The conductive paste for the base layer also contains, for example, a ceramic component as a main component of the dielectric layer 4 as a co-material. For example, particles of oxide ceramics mainly composed of barium titanate (D50 particle size of 0.8μm to 4μm) are mixed in the conductive paste for the base layer as a co-material, and the range is 10wt% to 40wt%. The conductive paste for the base layer also contains an adhesive and a solvent.

[0090] Next, in Figure 4 In step S9 (sintering and reoxidation step), Figure 5G As shown, in Figure 4 The element body 2 on which the conductive paste for the base layer is applied in step S8 is subjected to a sintering process, so that the internal electrode layers 3A and 3B in each element body 2 are integrated with the dielectric layer 4, and the base layer 7 is cured and integrated with the element body 2. The sintering of the element body 2 is performed, for example, in a sintering furnace at a temperature range of 1000 degrees Celsius to 1350 degrees Celsius for ten minutes to two hours.

[0091] If a base metal such as Ni or Cu is used as the material of internal electrode layers 3A and 3B, the sintering process may be performed in a sintering furnace while keeping the interior of the sintering furnace in a reducing atmosphere to prevent oxidation of internal electrode layers 3A and 3B.

[0092] Then, the ceramic material in the element body 2 and the base layer 7 which are reduced in the sintering process is reoxidized in an oxidizing atmosphere. At the same time, the metal exposed on the surface of each base layer 7' is oxidized to form a metal oxide film on the exposed surface of the base layer 7'. For example, the reoxidation treatment can be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0093] Base layer 7' corresponds to Figure 3 The base layer before the coated metal sheet 7C is formed, such as Fig. 6A As shown. In the base layer 7', the common material particles 7B close to the surface of the base layer 7' protrude from the surface of the base layer 7'. Therefore, the surface flatness of the base layer 7' is not as good as the surface flatness of the base layer 7. An oxide film 7D of the metal layer 7A is formed on the metal layer 7A exposed from the surface of the base layer 7'.

[0094] Then, in Figure 4 In S10 (sandblasting and polishing step), Figure 5HAs shown, in the sandblasting process, the oxide film 7D on the base layer 7' is removed by sandblasting BP from a direction oblique to the exposed surface of the base layer 7', and the material of the metal layer 7A is raised above the common material particles 7B on the exposed surface of the base layer 7' to form a coated metal sheet 7C.

[0095] In sandblasting BP, such as Figure 6B As shown, the element body 2 is arranged in the sandblasting device so that the base layer 7' is exposed, and the sandblasting medium BM is projected from a direction at an oblique angle to each surface of the base layer 7'. The oblique angle θ relative to the projected surface of the base layer 7' is preferably in the range of 15 degrees to 35 degrees. When the sandblasting medium BM obliquely collides with the metal layer 7A around the common material particles 7B on the surface of the base layer 7, the material of the metal layer 7A rises above the common material particles 7B to produce a coated metal sheet 7C on the common material particles 7B.

[0096] For example, the centers of the two surfaces of the element body 2 exposed from the base layer 7' are fixed by a flat jig, and the sandblasting medium BM is projected from various directions through a nozzle that is freely movable relative to the base layer 7', so that the surfaces of the base layer 7' exposed in various directions are polished. Figure 1 The coating metal sheet 7C is formed once on the common material particles 7B on the different exposed surfaces of the external electrodes 6A and 6B. The blasting medium BM is particles made of, for example, zircon or alumina.

[0097] The adjustable projection conditions include projection speed, projection amount, projection area and projection angle. The projection speed is adjusted by adjusting the pressure and path of the sandblasting medium BM. The projection volume is adjusted by adjusting the medium circulation path and the projection time. The projection area is adjusted by adjusting the nozzle shape and the distance between the element body 2 and the nozzle. The projection angle is adjusted by adjusting the nozzle angle so that it is within the range of 15 degrees to 35 degrees relative to each projection surface.

[0098] Next, in Figure 4 In S11 (plating step), Fig.5I As shown, a plating layer 9 is formed on the base layer 7, wherein a coating metal sheet 7C is formed over the common material particles 7B. When forming the plating layer 9, for example, Cu plating, Ni plating, and Sn plating may be performed sequentially. The plating layer 9 may be formed by housing the element body 2 on which the base layer 7 is formed in a drum and immersing the drum in a plating solution, and rotating the drum and energizing the drum.

[0099] The material of the plating layer 9 is evenly arranged on the entire exposed surface of each exposed common material particle 7B via the coated metal sheet 7C on the exposed common material particle 7B. Therefore, the plating layer 9 can be prevented from being pierced by the exposed common material particles 7B on the surface of the base layer 7, and the continuity of the plating layer 9 formed on the base layer 7 can be ensured. Therefore, the plating layer 9 can be in contact with the metal layer 7A, the exposed common material particles 7B and the coated metal sheet 7C.

[0100] As described above, according to the first embodiment, by performing sandblasting BP from a direction oblique to the projection surface of the base layer 7', the metal layer 7A can rise above the exposed common material particles 7B on the surface of the base layer 7', while removing the oxide film 7D on the metal layer 7A. Therefore, it is possible to make the plating layer 9 contact with the metal layer 7A and reduce the contact area between the plating layer 9 and the exposed common material particles 7B without removing the common material particles 7B present on the surface of the base layer 7'. As a result, it is possible to improve the adhesion of the plating layer 9 to the base layer 7 while preventing a decrease in production volume, and at the same time, the above-mentioned poor fusion when sintering the base layer 7', that is, the base layers 7' of the adjacent laminated ceramic capacitors 1 stick together, can be reduced, and damage to the element can be reduced.

[0101] Second embodiment

[0102] Figure 7 1 is a cross-sectional view showing a circuit board device according to a second embodiment of the present invention, on which a laminated ceramic capacitor is mounted. The circuit board device includes a circuit board 11 and a laminated ceramic capacitor 1 mounted on the circuit board 11 .

[0103] like Figure 7 As shown, land electrodes 12A and 12B are formed on a circuit board 11. The circuit board 11 may be a printed circuit board or a semiconductor board formed of Si, for example. The laminated ceramic capacitor 1 is connected to the land electrodes 12A and 12B via solder layers 13A and 13B attached to the Sn plating layer 9C of the external electrodes 6A and 6B, respectively.

[0104] Since the plating layer 9 is in contact not only with the metal layer 7A of the base layer 7 but also with the covering metal sheet 7C, it is possible to improve the continuity of the plating layer 9 on the base layer 7. Therefore, it is possible to improve the wettability of each of the solder layers 13A and 13B to the plating layer 9, and the reliability of the multilayer ceramic capacitor 1 can be maintained even after being mounted on the circuit board 11.

[0105] In the base layer 7, since the ratio of the common material particles to the metal material on the element body 2 side is substantially equal to that on the plating layer 9 side, the resistance of the base layer 7 to thermal processes can be improved.

[0106] As described above, according to the second embodiment, the plating layer 9 is in contact not only with the metal layer 7A of the base layer 7 but also with the coating metal sheet 7C. Therefore, the continuity of the plating layer 9 on the base layer 7 can be improved without removing the common material present on the surface of the base layer 7, and the reliability of the circuit board device including the stacked ceramic capacitor 1 can be improved.

[0107] Third embodiment

[0108] Figure 8 is a perspective view showing an electronic component according to a third embodiment. Figure 8 In the example, a chip inductor is taken as an electronic component.

[0109] The chip inductor 21 includes an element body 22 and two external electrodes 26A and 26B. The element body 22 includes a coil pattern 123 including two terminal segments 123A and 123B formed at both ends thereof and a magnetic material 124. The shape of the element body 22 may be a substantially rectangular parallelepiped shape.

[0110] External electrodes 26A and 26B are located on opposite sides of element body 22 so as to be spaced apart from each other. Each of external electrodes 26A and 26B continuously extends from the side surface of element body 22 to both front and rear surfaces and both upper and lower surfaces.

[0111] The coil pattern 123 is covered with a magnetic material 124. However, the terminal segment 123A is exposed from the magnetic material 124 on one side of the element body 22 and connected to the external electrode 26A, while the terminal segment 123B is exposed from the magnetic material 124 on the other side of the element body 22 and connected to the external electrode 26B.

[0112] For example, the material of the coil pattern 123 and the terminal segments 123A and 123B may be a metal such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or an alloy containing at least one of these metals. The magnetic material 124 is, for example, ferrite.

[0113] The external electrodes 26A and 26B may each be connected to Figure 1 The external electrodes 26A and 26B are configured in the same manner as in the external electrodes 6A and 6B in FIG. In other words, each of the external electrodes 26A and 26B has a base layer and a plating layer. The base layer contains a metal material and common material particles. The common material particles are mixed with the metal of the base layer and dispersed in the metal of the base layer, and the edges of the common material particles existing on the surface of the base layer are covered by the metal of the base layer.

[0114] As described above, according to the third embodiment, the contact area between the plating layers of the external electrodes 26A and 26B and the common material particles can be reduced without removing the common material on the surface of the base layer of each of the external electrodes 26A and 26B. Therefore, it is possible to prevent the uniformity of the plating layers of the external electrodes 26A and 26B from being reduced. In addition, the above-mentioned poor fusion, that is, the base layers of adjacent chip inductors 21 sticking together when the base layer is sintered, can be reduced, and damage to the element body 22 can be reduced.

[0115] In the above embodiment, the laminated ceramic capacitor 1 and the chip inductor are exemplified as the electronic components, but the electronic components may include chip resistors or sensor chips. In the above embodiment, each electronic component includes two external electrodes, but the electronic component may include three or more external electrodes.

[0116] Example

[0117] Fig. 9 1 is a graph showing the relationship between the amount of common material, the fusion failure rate, and the defective plating rate in the multilayer ceramic capacitor of the embodiment, wherein the defective plating rate is examined for the embodiment with and without sandblasting the base layer 7 . Fig.10 It is prepared from Fig. 9 of table.

[0118] In the case where the base layer 7 is not sandblasted, the surface of the base layer is processed by chemical polishing. Fig. 9 and Fig.10 In the experiment, the metal of the base layer 7 is Ni. The amount of common material particles in the base layer 7 is Fig. 9 and Fig.10 The content is expressed in wt%.

[0119] Fig.10 The ratio of the total length of the common material particles 7B in contact with the plating layer 9 to the length of the interface between the base layer 7 and the plating layer 9 is also shown. The total length of the common material particles 7B in contact with the plating layer 9 is the interface between the external electrodes 6A and 6B in one cross section shown in FIG. Figure 3 ) is the sum of the lengths L1 of all the common material particles 7B on the substrate 7. The length of the interface between the substrate 7 and the plating layer 9 is the sum of the lengths of the interface between the substrate 7 and the plating layer 9 in the external electrodes 6A and 6B in the cross section. This ratio is calculated based on five samples of the laminated ceramic capacitor 1. Fig.10 The average value is used in .

[0120] like Figure 5G As shown in FIG. 1 , the fusion failure is that the base layers 7 of the adjacent multilayer ceramic capacitors 1 stick together after sintering is performed in a state where the base layers 7 of the plurality of multilayer ceramic capacitors 1 are in contact with each other. Figure 5G The cross sections shown are used to detect poor fusion in a series of component bodies 2, and the poor fusion rate is calculated based on the observation results.

[0121] Poor plating is poor adhesion between base layer 7 and plating layer 9. Figure 2 The cross section shown was observed to detect defective plating, and the defective plating rate was calculated based on the observation as an average value of five samples of the laminated ceramic capacitor 1 .

[0122] The experiment was conducted on samples with a common material amount in the range of 10%-70% in the base layer 7. When the base layer 7 was sandblasted, the Ni layer was coated on the edges of the common material particles at the interface between the base layer 7 and the plating layer 9, while when the base layer 7 was not sandblasted, the Ni layer was not coated on the edges of the material particles. Therefore, the sandblasting treatment effectively coated the Ni-coated metal sheet 7C to the edges of the common material particles at the interface between the base layer 7 and the plating layer 9.

[0123] Regardless of whether sandblasting is performed or not, the total length of the common material particles 7B in contact with the coating 9 increases as the amount of common material in the base layer 7 increases, resulting in an increase in the ratio of the total length of the common material particles 7B in contact with the coating 9 to the length of the interface between the base layer 7 and the coating 9. However, the increase in the total length of the common material particles 7B in contact with the coating 9 when sandblasting is performed is less than the increase when sandblasting is not performed, so that the ratio of the total length of the common material particles 7B in contact with the coating 9 to the length of the interface between the base layer 7 and the coating 9 when sandblasting is performed is less than the ratio when sandblasting is not performed.

[0124] Therefore, if Fig. 9 and Fig.10 As shown in the figure, whether sandblasting is performed or not, the contact area between the metal in the base layer 7 and the plating layer 9 decreases as the amount of common material in the base layer 7 increases, thereby increasing the defective plating rate. However, the contact area between the metal in the base layer 7 and the plating layer 9 is larger when sandblasting is performed than when sandblasting is not performed, so that the defective plating rate is significantly lower when sandblasting is performed than when sandblasting is not performed.

[0125] In addition, if Fig. 9 and Fig.10 As shown in FIG. 1 , as the amount of the common material in the base layer 7 increases, the poor fusion rate after sintering decreases. Therefore, increasing the amount of the common material in the base layer 7 can effectively reduce the poor fusion rate. Since sintering is performed before sandblasting, the poor fusion rate in the case of sandblasting is equal to the poor fusion rate in the case of not performing sandblasting.

[0126] According to the above results, in the case of performing sandblasting, by setting the amount of common material in the base layer 7 within the range of 10% to 45%, the fusion failure rate and the plating failure rate can be restricted to almost 0%. However, it is considered that the plating failure rate may vary depending on the sandblasting conditions. Therefore, it is preferable to set the amount of common material in the base layer 7 as low as possible so that the fusion failure rate is 0%, and then set the sandblasting conditions so that the plating failure rate is 0%.

Claims

1. An electronic component, comprising: a component body, the component body comprising a dielectric and internal electrodes; and external electrodes, each of the external electrodes includes a base layer formed on multiple surfaces of the element body and a conductive material layer formed on the base layer, the base layer is connected to the internal electrode, the base layer includes a metal and common material particles dispersed in the metal, the base layer includes common material particles at the interface between the base layer and the conductive material layer, the common material particles at the interface have edges covered by the metal, the conductive material layer is in contact with the common material particles at the interface and the metal covering the edges of the common material particles at the interface, The common material contains a main component that is the same as that of the dielectric layer, or a ceramic material that is different from the material of the dielectric layer, wherein the difference between the thermal expansion coefficients of the common material and the dielectric layer is within ±30% of the thermal expansion coefficient of the dielectric layer. 2 . The electronic component according to claim 1 , wherein the metal near the interface in the base layer surrounds the common material particles. 3 . The electronic component according to claim 1 , wherein the metal on the interface covers edges of common material particles on the interface. 4 . The electronic component according to claim 1 , wherein a length of each common material particle on the interface in a cross section in contact with the conductive material layer is in a range of 0.1 μm to 12 μm. 5 . The electronic component according to claim 1 , wherein the thickness of the metal piece covering the edge of the co-material particle in cross section is in the range of 0.1 μm to 0.7 μm, and wherein the length of the metal piece is in the range of 0.2 μm to 2.5 μm. 6 . The electronic component according to claim 1 , wherein the thickness of the metal piece covering the edge of the co-material particle in cross section is in the range of 0.2 μm to 0.6 μm, and wherein the length of the metal piece is in the range of 0.5 μm to 2.0 μm. 7 . The electronic component according to claim 1 , wherein the amount of the co-material particles in the base layer is in the range of 10 wt % to 45 wt %. 8 . The electronic component according to claim 1 , wherein a main component of the dielectric and a main component of the co-material particles have the same composition.

9. The electronic component according to claim 1 or 2, wherein a main component of the co-material particles is oxide ceramic.

10. The electronic component according to claim 1 or 2, wherein in the base layer, a ratio of the common material particles to the metal on the element body side is equal to a ratio on the conductive material layer side.

11. The electronic component according to claim 1 or 2, wherein a main component of the co-material particles is at least one of barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, calcium barium titanate, calcium zirconate, barium zirconate, calcium zirconate titanate and titanium dioxide.

12. The electronic component according to claim 1 or 2, wherein the metal comprises at least one of Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, or an alloy thereof.

13. The electronic component according to claim 1 or 2, wherein the element body includes a laminated body including first internal electrode layers and second internal electrode layers, the first internal electrode layers and the second internal electrode layers are alternately arranged with the dielectric interposed therebetween, and wherein The external electrode comprises: a first external electrode located on a first side surface of the stacked body and connected to the first internal electrode layer, and A second external electrode is spaced apart from the first external electrode, is located on a second side surface of the stacked body opposite to the first side surface, and is connected to the second internal electrode layer.

14. A circuit board device, comprising: Circuit boards; and The electronic component according to any one of claims 1 to 13, which is mounted on the circuit board, the electronic component being connected to the circuit board via a solder layer attached to a conductive material layer of the electronic component.

15. A method for manufacturing an electronic component, the method comprising the steps of: forming a component body including a dielectric and internal electrodes; applying a mixed material obtained by dispersing common material particles in an electrode material containing a metal to opposite side surfaces of the element body and peripheral surfaces of the element body adjacent to the side surfaces; sintering the mixed material to form a base layer on the opposite side surfaces and the peripheral surface of the element body in which the co-material particles are dispersed in the metal; oxidizing the metal of the base layer to form an oxide film of the metal on an exposed surface of the base layer; and sandblasting the exposed surfaces of the base layer from a direction oblique to each exposed surface of the base layer to remove the oxide film and raise the metal beyond the edge of the common material particles; as well as Conductive material layers are formed on the base layer in such a manner that each conductive material layer is in contact with the common material particles and the metal rising above the edge of the common material particles, The common material contains a main component that is the same as that of the dielectric layer, or a ceramic material that is different from the material of the dielectric layer, wherein the difference between the thermal expansion coefficients of the common material and the dielectric layer is within ±30% of the thermal expansion coefficient of the dielectric layer. 16 . The method of manufacturing an electronic component according to claim 15 , wherein the oblique angle relative to each exposed surface of the base layer is in the range of 15 degrees to 35 degrees.

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