Semiconductor devices and manufacturing methods thereof

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. According to one embodiment, the semiconductor device includes: a first substrate; a first insulating film disposed on the first substrate; and a first plug disposed within the first insulating film. The device further includes: a first layer disposed on the first insulating film; and a first metal layer disposed within the first layer on the first plug and electrically connected to the first plug. The device also includes a second metal layer comprising a first portion disposed within the first layer and a second portion disposed on the first layer, and electrically connected to the first metal layer.

Description

[0001] Citation of relevant applications

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2020-146057 filed on August 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] When an opening is formed within a layer on the plug, and a metal layer is formed on the plug exposed within the opening, there is a problem that the plug may be etched due to the etching used to form the opening. Summary of the Invention

[0005] The present invention provides a semiconductor device capable of suitably forming a metal layer on a plug and a method thereof.

[0006] According to one embodiment, a semiconductor device includes: a first substrate; a first insulating film disposed on the first substrate; and a first plug disposed within the first insulating film. The device further includes: a first layer disposed on the first insulating film; and a first metal layer disposed within the first layer on the first plug and electrically connected to the first plug. The device also includes a second metal layer comprising a first portion disposed within the first layer and a second portion disposed on the first layer, and electrically connected to the first metal layer.

[0007] Based on the aforementioned configuration, a semiconductor device capable of suitably forming a metal layer on a plug and a method for manufacturing the same can be provided. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a cross-sectional view showing the structure of the columnar portion in the first embodiment.

[0011] Figure 4 (a) and (b) are cross-sectional views (1 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 5(a) and (b) are cross-sectional views (2 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 6 (a) and (b) are cross-sectional views (3 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0014] Figure 7 This is a cross-sectional view (4 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0015] Figure 8 This is a cross-sectional view (5 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0016] Figure 9 (a) to (c) are cross-sectional views (6 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0017] Figure 10 (a) to (c) are cross-sectional views (7 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0018] Figure 11 (a) to (c) are cross-sectional views (8 / 8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0019] Figure 12 This is another cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figure 13 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0021] Figure 14 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0022] Figure 15 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to the second embodiment.

[0023] Figure 16 This is another cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 16 In Chinese, identical components are marked with the same symbol, and repeated explanations are omitted.

[0025] (First Embodiment) Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1The semiconductor device is a three-dimensional memory formed by bonding array region 1 and circuit region 2.

[0026] Figure 1 The X, Y, and Z directions are shown as mutually perpendicular. In this specification, the +Z direction is treated as the upward direction, and the -Z direction as the downward direction. The -Z direction may or may not be aligned with the direction of gravity.

[0027] Array region 1 includes: a memory cell array 11 containing multiple memory cells, a substrate 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The substrate 12 is, for example, a semiconductor substrate such as a silicon substrate. The interlayer insulating film 13 is, for example, a silicon oxide film, or a multilayer film containing a silicon oxide film and other insulating films. The substrate 12 is an example of a first or second substrate. The interlayer insulating film 13 is an example of a first insulating film.

[0028] Circuit region 2 is disposed below array region 1. The symbol S denotes the mating surface between array region 1 and circuit region 2. Circuit region 2 includes an interlayer insulating film 14 and a substrate 15 beneath the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a multilayer film comprising a silicon oxide film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 15 is an example of a first substrate. Interlayer insulating film 14 and interlayer insulating film 13 are both examples of first insulating films.

[0029] Array region 1 has multiple word lines WL as multiple electrode layers within the memory cell array 11. Figure 1 The stepped structure 21 represents the memory cell array 11. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar portion CL passing through the plurality of word lines WL is electrically connected to the bit line BL via a hole plug 24.

[0030] Circuit region 2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 disposed on a substrate 15 with a gate insulating film as a dielectric, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. In addition, circuit region 2 includes: a plurality of contact plugs 33 disposed on the gate electrode 32, source diffusion layer or drain diffusion layer of these transistors 31; a wiring layer 34 disposed on these contact plugs 33 and including a plurality of wirings; and a wiring layer 35 disposed on the wiring layer 34 and including a plurality of wirings.

[0031] Circuit region 2 also includes: a wiring layer 36 disposed on wiring layer 35 and containing multiple wirings; multiple via plugs 37 disposed on wiring layer 36; and multiple metal pads 38 disposed on these via plugs 37. The metal pads 38 are, for example, metal layers containing a Cu (copper) layer or an Al (aluminum) layer. Circuit region 2 functions as a control circuit (logic circuit) for controlling the operation of array region 1. This control circuit includes transistors 31, etc., and is electrically connected to the metal pads 38.

[0032] Array region 1 includes a plurality of metal pads 41 disposed on metal pads 38 and a plurality of via plugs 42 disposed on the metal pads 41. Additionally, array region 1 includes: a wiring layer 43 disposed on the via plugs 42 and including a plurality of wirings; and a wiring layer 44 disposed on the wiring layer 43 and including a plurality of wirings. The metal pads 41 are, for example, metal layers including Cu or Al layers. The bit lines BL are contained in the wiring layer 44. Furthermore, the control circuit is electrically connected to the memory cell array 11 via the metal pads 41 and 38, and controls the operation of the memory cell array 11 via the metal pads 41 and 38.

[0033] Array region 1 also includes: a plurality of via plugs 45 disposed on wiring layer 44; a plurality of via plugs 46 disposed on these via plugs 45; and a plurality of metal layers 47 disposed on these via plugs 46. The via plugs 46 are disposed within the interlayer insulating film 13, and the metal layers 47 are disposed within the substrate 12. Each metal layer 47 is disposed on a corresponding via plug 46 and is electrically connected to that via plug 46. The via plug 46 is an example of a first plug, and the metal layer 47 is an example of a first metal layer. Further details regarding the via plugs 46 and the metal layers 47 will be described below.

[0034] The array region 1 also includes an insulating film 51, an insulating film 52, a metal layer 53, and a passivation film 54 disposed on the substrate 12.

[0035] An insulating film 51 is formed on a substrate 12. The insulating film 51 is, for example, a silicon oxide film. The insulating film 52 includes a side portion 52a formed on the side of the substrate 12 and the insulating film 51, and an upper portion 52b formed on the upper surface of the insulating film 51. The side portion 52a functions as a sidewall insulating film for the substrate 12 and the insulating film 51. The insulating film 52 is, for example, a silicon oxide film. The insulating film 51 and the insulating film 52 are examples of a first layer, and further examples of a second insulating film, together with the substrate 12.

[0036] The substrate 12 and the insulating film 51 have openings that extend to the interlayer insulating film 13. The insulating film 52 is formed within these openings on the sides of the substrate 12 and the insulating film 51. A metal layer 47 is disposed within these openings. As described below, the metal layer 47 of this embodiment functions as an etching stop layer when the openings are formed within the substrate 12 and the insulating film 51 by etching. This suppresses the etching of the hole plug 46 caused by the etching used to form the openings.

[0037] The metal layer 53 includes: an upper portion 53a formed on the upper surface of the interlayer insulating film 13 and the metal layer 47; a side portion 53b formed on the side surface of the insulating film 52; and an upper portion 53c formed on the upper surface of the insulating film 52. The upper portion 53a and the side portion 53b are disposed within the opening, and the upper portion 53c is disposed outside the opening. The metal layer 53 is electrically connected to each of the metal layers 47. The metal layer 53 may include, for example, an Al layer. The metal layer 53 is an example of a second metal layer. Furthermore, the upper portion 53a and the side portion 53b are examples of a first part, and the upper portion 53c of the metal layer 53 is an example of a second part.

[0038] The passivation film 54 includes insulating films 54a, 54b, and 54c sequentially formed on the insulating film 52 and the metal layer 53. Insulating film 54a is, for example, a silicon oxide film. Insulating film 54b is, for example, a silicon nitride film. Insulating film 54c is, for example, a polyimide film.

[0039] The passivation film 54, for example, has an opening P that exposes the upper surface of the upper portion 53c of the metal layer 53. The upper portion 53c exposed within the opening P serves as... Figure 1 The external bonding pads (bonding pads) of the semiconductor device function as bonding pads. The upper part 53c can be connected to the mounting substrate and other devices via the opening P using bonding wires, solder balls, metal bumps, etc.

[0040] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 2 The hole plug 46, metal layer 47, metal layer 53, etc. are shown.

[0041] In this embodiment, the hole plugs 46 and metal layers 47 contain different metal elements. Each hole plug 46, for example, contains a single-element metal layer or a compound metal layer containing W (tungsten). Each metal layer 47, for example, contains a single-element metal layer or a compound metal layer containing Al (aluminum), Hf (hafnium), or Zr (zirconium). In this embodiment, each hole plug 46 contains a W layer, and each metal layer 47 contains an Al layer. An example of a first metal element is found in the hole plug 46. An example of a second metal element is found in the metal layer 47. Furthermore, when the metal layer 47 is formed by implanting metal atoms into the substrate 12 as described below, each metal layer 47 also contains elements contained in the substrate 12 (e.g., silicon).

[0042] When the metal layer 47 forms an opening in the substrate 12 and the insulating film 51 through etching, it functions as an etch stop layer. This suppresses the etching of the hole plug 46 caused by the etching used to form the opening. In this embodiment, the hole plug 46 and the metal layer 47 have different metal elements; therefore, the metal layer 47 can function as an etch stop layer to suppress the etching of the hole plug 46.

[0043] Furthermore, the metal layer 47 can be completely removed by etching used to form the opening or by subsequent etching. In this case, the metal layer 53 is directly electrically connected to each hole plug 46 by being formed in contact with the upper surface of each hole plug 46. On the other hand, Figure 2 The metal layer 53 shown is formed on each of the orifice plugs 46 through a spacer metal layer 47 and is electrically connected to each orifice plug 46 via the metal layer 47.

[0044] The semiconductor device of this embodiment includes N (N is an integer greater than or equal to 2) vias 46, and N metal layers 47 are provided on these vias 46. Thus, in this embodiment, the vias 46 and the metal layers 47 correspond one-to-one. Figure 2 This diagram shows two of the hole plugs 46 and two of the metal layers 47. In this embodiment, the value of N is, for example, 100 to 10000. The metal layers 47 in this embodiment can be configured in any shape, for example, arranged in a two-dimensional array in the form of a square lattice in the XY plane. The planar shape of each metal layer 47 in this embodiment is, for example, circular.

[0045] Figure 3 This is a cross-sectional view showing the structure of the columnar portion CL in the first embodiment.

[0046] like Figure 3 As shown, the memory cell array 11 has alternating layers of interlayer insulating film 13 (reference). Figure 1 The image contains multiple word lines WL and multiple insulating layers 61. The word lines WL are, for example, a metal layer containing a W (tungsten) layer. The insulating layers 61 are, for example, a silicon oxide film.

[0047] The columnar portion CL sequentially comprises a barrier insulating film 62, a charge storage layer 63, a tunnel insulating film 64, a channel semiconductor layer 65, and a core insulating film 66. The charge storage layer 63 is, for example, a silicon nitride film, and the barrier insulating film 62 is formed on the sides of the word line WL and the insulating layer 61. The charge storage layer 63 may also be a semiconductor layer such as a polysilicon layer. The channel semiconductor layer 65 is, for example, a polysilicon layer, and the tunnel insulating film 64 is formed on the sides of the charge storage layer 63. The barrier insulating film 62, the tunnel insulating film 64, and the core insulating film 66 are, for example, silicon oxide films or metal insulating films.

[0048] Figures 4 to 11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. As described below, the semiconductor device of this embodiment is manufactured by bonding an array wafer W1 containing a plurality of array regions 1 to a circuit wafer W2 containing a plurality of circuit regions 2.

[0049] First, a substrate 12 is prepared, and a memory cell array 11 and an insulating film 13a, which is part of an interlayer insulating film 13, are formed on the substrate 12. Figure 4 (a)). Figure 4 (a) also shows the word line WL, columnar portion CL, and stepped structure portion 21 included in the memory cell array 11. The insulating film 13a is an example of the first insulating film.

[0050] Next, a hard mask layer 71 is formed on the insulating film 13a, and openings H1, H2, and H3 are formed within the insulating film 13a by using the hard mask layer 71 as a mask for RIE (Reactive Ion Etching). Figure 4 (b) Opening H1 is formed to reach the substrate 12. Opening H2 is formed to reach the word line WL. Opening H3 is formed to reach the columnar portion CL. The hard masking layer 71 is, for example, a carbon layer. The hard masking layer 71 is subsequently removed by ashing. Opening H1 is an example of the second opening.

[0051] Next, a resist layer 72 is formed on the insulating film 13a. Figure 5 (a)). The resist layer 72 is formed such that the opening H1 is not covered by the resist layer 72. Next, metal atoms are implanted into the substrate 12 exposed in the opening H1 by ion implantation using the resist layer 72 as a mask. Figure 5 (a)). As a result, a metal layer 47 is formed in the substrate 12 exposed in the opening H1. Figure 5(a) An example is illustrated by two metal layers 47 formed within a substrate 12 exposed within two openings H1. The metal atoms are, for example, Al atoms, and in this case, the metal layers 47 become layers containing Al atoms. The areal concentration of Al atoms within the metal layers 47 is, for example, approximately 1.0 × 10⁻⁶. 16 pcs / cm 2 The metal atoms may also be Hf atoms or Zr atoms. The resist layer 72 is subsequently removed by ashing.

[0052] Next, a metal material layer is formed on the entire surface of the substrate 12, and the surface of the metal material layer is planarized by CMP (Chemical Mechanical Polishing). Figure 5 (b) As a result, a hole plug 46, a contact plug 22, and a hole plug 24 are formed in the openings H1, H2, and H3 respectively from the metal material layer. For example, in each opening H1, a hole plug 46 is formed on a metal layer 47. The metal material layer is, for example, a laminated film comprising a barrier metal layer and a plug material layer. The barrier metal layer, for example, comprises Ti (titanium) or Ta (tantalum). The plug material layer, for example, comprises W, here being a W layer.

[0053] Next, on the substrate 12, an insulating film 13b, a word wiring layer 23, a bit line BL, a via plug 45, a wiring layer 44, wiring 43, a via plug 42, and a metal pad 41 are formed as part of the interlayer insulating film 13, such as a dielectric insulating film 13a. Figure 6 (a)). The array wafer W1 is manufactured in this manner. Figure 6 (a) shows the upper surface S1 of the array wafer W1.

[0054] Next, a substrate 15 is prepared, and on the substrate 15, an interlayer insulating film 14, a transistor 31, a gate electrode 32, a contact plug 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, a metal pad 38, etc., are formed. Figure 6 (b) The circuit wafer W2 is manufactured in this manner. Figure 6 (b) shows the upper surface S2 of the circuit wafer W2.

[0055] Next, the array wafer W1 is bonded to the circuit wafer W2. Figure 7 Specifically, the substrate 12 and substrate 15 are bonded together by separating the memory cell array 11, interlayer insulating film 13, interlayer insulating film 14, transistor 31, hole plug 46, metal layer 47, etc. Figure 7In this process, the vertical orientation of the array wafer W1 is reversed, and the array wafer W1 is bonded to the circuit wafer W2. As a result, the substrate 12 is positioned above the substrate 15. In this bonding step, the interlayer insulating film 13 and the interlayer insulating film 14 are bonded by mechanical pressure, and the metal pads 41 and 38 are bonded by annealing.

[0056] Next, the substrate 12 is thinned by back-side grinding and wet etching. Figure 8 As a result, the thickness of substrate 12 becomes thinner.

[0057] Figure 9 (a) to Figure 11 (c) is an enlarged cross-sectional view showing the substrate 12, the hole plug 46, the metal layer 47, etc.

[0058] Next, an insulating film 51 is formed on the substrate 12. Figure 9 (a)). Next, the insulating film 51 above the metal layer 47 is etched using RIE ( Figure 9 (b) As a result, an opening H4 is formed within the insulating film 51, exposing the substrate 12 within the opening H4. Next, the substrate 12 exposed within the opening H4 is etched using RIE (Reaching Image Etching). Figure 9 (c)). As a result, an opening H4 is also formed in the substrate 12, exposing the interlayer insulating film 13 and the metal layer 47 within the opening H4. The opening H4 is an example of the first opening.

[0059] Metal layer 47 is being processed Figure 9 (c) The RIE functions as an etch stop layer. Therefore, etching of the hole plug 46 due to the RIE can be suppressed. In this embodiment, the hole plug 46 and the metal layer 47 contain different metal elements; therefore, the metal layer 47 can function as an etch stop layer to suppress etching of the hole plug 46.

[0060] Figure 9 (c) The RIE is performed, for example, using an etching gas containing the element F (fluorine). Examples of such etching gases are SF6 or CF4 (S represents sulfur, C represents carbon). The etching gas may also contain SF6 and / or CF4, as well as O2 (O represents oxygen).

[0061] Etching gas containing element F can etch the substrate 12 at high speed. In this case, if a metal layer 47 is not formed on the hole plug 46, then the hole plug 46 will also be etched at high speed along with the substrate 12. According to this embodiment, by performing... Figure 9 (c) A metal layer 47 is formed on the hole plug 46 before the RIE, which can suppress the etching of the hole plug 46.

[0062] Therefore, ideally, the metal layer 47 has high resistance to etching gases containing fluorine (F). Examples of such a metal layer 47 are elemental or compound metal layers containing Al, Hf, or Zr. This allows for both high-speed etching of the substrate 12 using fluorine-containing etching gases and suppression of etching of the via plug 46.

[0063] Next, an insulating film 52 is formed on the entire surface of the substrate 12. Figure 10 (a)). As a result, an insulating film 52 is formed on the surface of the metal layer 47, the interlayer insulating film 13, the substrate 12, and the insulating film 51.

[0064] Next, remove the insulating film 52 on the metal layer 47 and the interlayer insulating film 13. Figure 10 (b)). As a result, the surfaces of the metal layer 47 and the interlayer insulating film 13 are exposed within the opening H4. In addition, the insulating film 52 is processed into a shape including a side portion 52a and a top portion 52b. Figure 10 (b) is performed, for example, by covering a portion of the insulating film 52 (corresponding to the portion of the side portion 52a and the top portion 52b) with a resist layer and removing the other portions of the insulating film 52 by etching.

[0065] Next, a metal layer 53 is formed on the entire surface of the substrate 12. Figure 10 (c)). As a result, a metal layer 53 is formed on the surface of the metal layer 47, the interlayer insulating film 13, and the insulating film 52.

[0066] Next, a portion of the metal layer 53 on the upper surface of the insulating film 52 is removed. Figure 11 (a)). As a result, the metal layer 53 is processed into a shape including a top portion 53a, a side portion 53b and a top portion 53c.

[0067] In addition, metal layer 47 can be used for... Figure 10 (c) is completely removed before this step. In this case, the metal layer 53 is directly electrically connected to each of the orifice plugs 46 by being formed in contact with the upper surface of each orifice plug 46. On the other hand, Figure 11 (a) The metal layer 53 shown is formed on each of the plugs 46 through a spacer metal layer 47 and is electrically connected to each of the plugs 46 via the metal layer 47.

[0068] Next, insulating films 54a, 54b, and 54c of passivation film 54 are sequentially formed on the entire surface of substrate 12. Figure 11 (b)). As a result, a passivation film 54 is formed on the surfaces of the insulating film 52 and the metal layer 53.

[0069] Next, a portion of the passivation film 54 on the upper surface of the upper part 53c is removed. Figure 11(c) As a result, an opening P is formed within the passivation film 54, exposing the upper surface of the upper portion 53c within the opening P. The upper portion 53c exposed within the opening P functions as a bonding pad.

[0070] Then, the array wafer W1 and the circuit wafer W2 are diced into multiple chips. These chips are diced such that each chip contains one array region 1 and one circuit region 2. This process is used to manufacture the chips. Figure 1 Semiconductor devices.

[0071] Figure 12 This is another cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0072] Figure 12 Is with Figure 9 (c) The corresponding cross-sectional view shows the step of forming the opening H4 in the substrate 12. In this embodiment, a metal layer 47 is formed on the hole plug 46.

[0073] Figure 12 The process involves using an etching gas containing SF6 and O2 gases. Figure 12 SF5 produced by SF6 gas is shown. + and F ＊ The etching gas etches the substrate 12 at a relatively fast rate. Therefore, in this embodiment, even when the substrate 12 is relatively thick, the opening H4 can be formed on the substrate 12 in a short time.

[0074] Figure 12 The next step is performed while a metal layer 47 is formed on the hole plug 46. In this embodiment, the metal layer 47 comprises a single-element metal layer or a compound metal layer containing Al, Hf, or Zr elements, and has high resistance to etching gases containing F. Therefore, in this embodiment, even when the substrate 12 is relatively thin, etching of the hole plug 46 can be suppressed.

[0075] Thus, according to this embodiment, it is easy to simultaneously achieve the etching of the opening H4 and the suppression plug 46 on the substrate 12 in a short time.

[0076] In addition, such as Figure 12 As shown, the opening H4 in this embodiment can also be made such that the side surfaces of the substrate 12 and the insulating film 51 are inclined surfaces.

[0077] As described above, the opening H4 of the substrate 12 in this embodiment is formed with a metal layer 47 pre-formed on the hole plug 46. Therefore, according to this embodiment, a metal layer 53 can be suitably formed on the hole plug 46. For example, the metal layer 53 can be formed on the hole plug 46 without the RIE etching used to form the opening H4, while still containing the metal layer 47. Furthermore, the RIE can be performed in a short time.

[0078] (Second Implementation) Figure 13 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0079] The semiconductor device in this embodiment includes and Figure 1 The semiconductor device of this embodiment has the same constituent elements as the semiconductor device of the first embodiment. However, the semiconductor device of the first embodiment has multiple metal layers 47 on multiple hole plugs 46, while the semiconductor device of this embodiment has one metal layer 47 on multiple hole plugs 46. The metal layer 53 of this embodiment is formed on this metal layer 47.

[0080] Figure 14 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment. Figure 14 The hole plug 46, metal layer 47, metal layer 53, etc. are shown.

[0081] In this embodiment, the hole plug 46 and metal layer 47, like in the first embodiment, contain different metal elements. For example, each hole plug 46 contains a W layer, and each metal layer 47 contains an Al layer. In this embodiment, since the hole plug 46 and metal layer 47 contain different metal elements, the metal layer 47 can function as an etch stop layer to suppress the etching of the hole plug 46.

[0082] The semiconductor device of this embodiment includes N (N is an integer greater than or equal to 2) vias 46, and each via 46 has a metal layer 47. The value of N in this embodiment is the same as in the first embodiment, for example, 100 to 10000. The vias 46 of this embodiment can be configured in any shape, for example, arranged in a two-dimensional array in the form of a square lattice within an XY cross section. The planar shape of each metal layer 47 in this embodiment is, for example, a square or a rectangle, or a quadrilateral.

[0083] Furthermore, the semiconductor device of this embodiment may also have fewer than N metal layers 47 on N hole plugs 46. For example, the semiconductor device of this embodiment may also have n metal layers 47 on k×n hole plugs 46 (k and n are integers of 2 or more). In this case, it is ideal to arrange each metal layer 47 on the corresponding k hole plugs 46.

[0084] Figure 15This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. The semiconductor device of this embodiment, like that of the first embodiment, is manufactured by bonding an array wafer W1 containing multiple array regions 1 to a circuit wafer W2 containing multiple circuit regions 2.

[0085] First, prepare substrate 12, and form metal layer 47 within substrate 12. Figure 15 (a)). The metal layer 47 is formed within the substrate 12, for example, by forming a recess within the substrate 12 using photolithography and RIE, and embedding the metal layer 47 within the recess. The metal layer 47 can be formed by, for example, plasma CVD (Chemical Vapor Deposition) or sputtering. In this case, the metal layer 47 is formed, for example, by forming the metal layer 47 inside and outside the recess of the substrate 12 using CVD or sputtering, and removing the metal layer 47 outside the recess of the substrate 12 using etch-back. The metal layer 47 is, for example, an Al layer, an Hf layer, or a Zr layer.

[0086] Next, a memory cell array 11 and an insulating film 13a, which is part of the interlayer insulating film 13, are formed on the substrate 12 and the metal layer 47. Figure 15 (b)). Figure 15 (b) also shows the word line WL, columnar section CL, and stepped structure section 21 included in the memory cell array 11.

[0087] Next, a rigid masking layer 71 is formed on the insulating film 13a, and openings H1 to H3 are formed in the insulating film 13a by using the rigid masking layer 71 as a mask for the RIE. Figure 15 (b) Opening H1 is formed to reach metal layer 47. Opening H2 is formed to reach word line WL. Opening H3 is formed to reach columnar portion CL. In this embodiment, multiple openings H1 are formed to reach one metal layer 47, and metal layer 47 is exposed in each opening H1.

[0088] In this embodiment, the following is omitted. Figure 5 Step (a) is implemented. Figure 5 (b) to Figure 11 Step (b) is followed. Figure 5 In step (b), a plug 46 is formed on the metal layer 47 exposed within each opening H1. Figure 9 In step (c), a metal layer 47 is exposed within the opening H4. Figure 10 In step (c), a metal layer 53 is formed on the metal layer 47. This is how it is manufactured. Figure 13 Semiconductor devices.

[0089] Figure 16This is another cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment.

[0090] Figure 16 Is with Figure 9 (c) The corresponding cross-sectional view shows the step of forming the opening H4 in the substrate 12. In this embodiment, a metal layer 47 is formed on the plurality of hole plugs 46.

[0091] Figure 16 The process involves using an etching gas containing SF6 and O2. Therefore, in this embodiment, even when the substrate 12 is relatively thick, the opening H4 can be formed on the substrate 12 in a short time.

[0092] Figure 16 The process is then performed with a metal layer 47 formed on the hole plug 46. Therefore, in this embodiment, even when the substrate 12 is relatively thin, etching of the hole plug 46 can be suppressed.

[0093] Thus, according to this embodiment, similar to the first embodiment, it is easy to simultaneously achieve the etching of the opening H4 and the suppression plug 46 on the substrate 12 in a short time.

[0094] As described above, the opening H4 of the substrate 12 in this embodiment is formed in a state where a metal layer 47 is pre-formed on a plurality of hole plugs 46. Therefore, according to this embodiment, similarly to the first embodiment, a metal layer 53 can be suitably formed on the hole plugs 46. For example, the metal layer 53 can be formed on the hole plugs 46 that have not undergone RIE etching to form the opening H4, while still containing the metal layer 47. Furthermore, the RIE can be performed in a short time.

[0095] Furthermore, in this embodiment, in Figure 15 In step (a), a plurality of metal layers 47 are formed within the substrate 12. Figure 15 In step (b), a corresponding opening H1 can be formed on each metal layer 47. Therefore, multiple metal layers 47, as in the first embodiment, can be formed using plasma CVD or sputtering instead of ion implantation. Conversely, in this embodiment, in... Figure 15 In step (a), an ion implantation layer 47 can be formed using ion implantation instead of plasma CVD or sputtering.

[0096] The foregoing has described several embodiments, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to include such embodiments and variations as those contained within the scope or spirit of the invention.

Claims

1. A semiconductor device comprising: a first substrate; a first insulating film disposed on the first substrate; a first plug disposed within the first insulating film; a first layer disposed on the first insulating film and including a semiconductor layer; a first metal layer disposed within the first layer on the first plug and electrically connected to the first plug; and a second metal layer including a first portion disposed within the first layer and a second portion disposed on the first layer and electrically connected to the first metal layer.

2. The semiconductor device according to claim 1, wherein the first layer further comprises a second insulating film disposed on the upper surface and side surface of the semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein the first plug comprises a first metal element, and the first metal layer comprises a second metal element different from the first metal element.

4. The semiconductor device according to claim 3, wherein the first metal element is tungsten, and the second metal element is aluminum, hafnium, or zirconium.

5. The semiconductor device according to claim 1 or 2, comprising N plugs as the first plugs, and N metal layers disposed on the N plugs as the first metal layers, wherein, N is an integer greater than or equal to 2.

6. The semiconductor device according to claim 1 or 2, comprising N plugs as the first plugs, and a metal layer disposed on the N plugs as the first metal layer, wherein, N is an integer greater than or equal to 2.

7. The semiconductor device of claim 1 or 2, wherein the second portion of the second metal layer comprises a bonding pad.

8. A semiconductor device comprising: a first insulating film; a first plug disposed within the first insulating film; a semiconductor layer disposed on the first insulating film; a first metal layer disposed within the semiconductor layer on the first plug and electrically connected to the first plug; and a second metal layer comprising a first portion disposed within the semiconductor layer and a second portion disposed on the semiconductor layer and electrically connected to the first metal layer.

9. The semiconductor device according to claim 8, further comprising a second insulating film disposed on the upper surface and side surface of the semiconductor layer, wherein the first portion is disposed within the semiconductor layer and the second insulating film, and the second portion is disposed on the semiconductor layer and the second insulating film.

10. A method for manufacturing a semiconductor device, comprising: Prepare a first substrate and a second substrate, form a first metal layer in the second substrate, form a first plug on the first metal layer, and bond the first substrate and the second substrate together by means of the first plug and the first metal layer. Place the second substrate above the first substrate, form a first opening in the second substrate, expose the first metal layer in the first opening, and form a second metal layer in the first opening, so that the second metal layer is electrically connected to the first plug.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the first opening is formed using a gas containing fluorine.

12. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the first plug comprises a first metal element, and the first metal layer comprises a second metal element different from the first metal element.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the first metal element is tungsten, and the second metal element is aluminum, hafnium, or zirconium.

14. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the first metal layer is formed in the first substrate by implanting metal atoms into the first substrate.

15. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the first metal layer is formed in the first substrate by forming a recess in the first substrate and embedding the first metal layer in the recess.

16. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the first metal layer and the first plug are formed by: forming a first insulating film on the second substrate, forming a second opening in the first insulating film and exposing the second substrate in the second opening, forming the first metal layer in the second substrate exposed in the second opening, and forming the first plug in the second opening.

17. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the first metal layer and the first plug are formed by: forming the first metal layer in the second substrate, forming a first insulating film on the second substrate and the first metal layer, forming a second opening in the first insulating film and exposing the first metal layer in the second opening, and forming the first plug on the first metal layer exposed in the second opening.

18. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein the second metal layer is directly electrically connected to the first plug, or electrically connected to the first plug via the first metal layer.

Images