Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate including a target layer, the substrate including a target region for forming a target pattern and a cutting region corresponding to a cutting position; forming a discrete core layer on the substrate; forming dummy sidewalls on the sidewalls of the core layer; forming a filling layer on the target layer where the dummy sidewalls and the core layer are exposed; etching the dummy sidewalls located in the target region to form a trench between the filling layer and the core layer; forming a mask sidewall in the trench; removing the core layer and the filling layer; using the mask sidewall as a mask to remove the dummy sidewalls located in the cutting region; and patterning the target layer using the mask sidewall as a mask to form a target pattern. Embodiments of the present invention facilitate increasing the process window for removing the dummy sidewalls located in the cutting region.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to decrease. To accommodate these smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has also been shortened. However, as the device channel length shortens, the distance between the source and drain of the device also decreases. As a result, the gate structure's ability to control the channel deteriorates, making it increasingly difficult for the gate structure to pinch off the channel with voltage. This makes subthreshold leakage (SCL), also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually begun to transition from planar MOSFETs to more efficient three-dimensional transistors, such as fin field-effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. In addition, FinFETs are more compatible with existing integrated circuit manufacturing than other devices.

[0004] In the semiconductor field, depending on process requirements, it is usually necessary to form fins with different pitches, or remove dummy fins at unnecessary locations to ensure that the fin pattern layer meets the design requirements. Currently, one approach is to achieve the above goals through a fin cutting process. Among them, the fin cutting process generally includes a fin cutting first process and a fin cutting last process. However, the current process window of the cutting process is small. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which avoids the use of a cutting process and is conducive to increasing the process window for removing the dummy sidewalls located in the cutting area.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate including a target layer, the substrate including a target area for forming a target pattern and a cutting area corresponding to a cutting position; forming a discrete core layer on the substrate; forming a dummy sidewall on the sidewall of the core layer; forming a filling layer on the target layer exposed by the dummy sidewall and the core layer; etching the dummy sidewall located in the target area to form a groove between the filling layer and the core layer; forming a mask sidewall in the groove; removing the core layer and the filling layer; using the mask sidewall as a mask, removing the dummy sidewall located in the cutting area; using the mask sidewall as a mask, patterning the target layer to form a target pattern.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate including a target layer, the substrate including a target area for forming a target pattern and a cutting area corresponding to a cutting position; a core layer, separate from the target layer; a sidewall structure layer, located on the sidewall of the core layer, the sidewall structure layer including a dummy sidewall located in the cutting area and a mask sidewall located in the target area, the mask sidewall being used as a mask for patterning the target layer; a filling layer, located on the target layer exposed by the core layer and the sidewall structure layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a method for forming a semiconductor structure, in which a pseudo sidewall located in the target area is etched to form a groove between the filling layer and the core layer, and a mask sidewall is formed in the groove. In this embodiment, the pseudo sidewall located in the target area is etched. Compared with removing the pseudo sidewall located in the cutting area by using a cutting process (Cut), the process window for etching the pseudo sidewall located in the target area is larger. Moreover, the embodiment of the present invention can use the mask sidewall as a mask to remove the pseudo sidewall located in the cutting area, and use the mask sidewall as a mask to pattern the target layer. Accordingly, the embodiment of the present invention avoids using a cutting process to remove the pseudo sidewall in the cutting area, and accordingly does not need to form a graphic transfer mask (Transfer Mask) for the cutting process in the cutting area, which is beneficial to increasing the process window for removing the pseudo sidewall located in the cutting area, avoiding defects in the cutting process (for example, residual pseudo sidewalls in the cutting area), and other problems, thereby improving the process yield and the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 6 to 191 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] As known from the background technology, it is usually necessary to use a cutting process to remove unnecessary patterns to achieve different spacings between target patterns or meet other design requirements. For example, in the semiconductor field, a fin cutting process is usually used to form fins with different spacings.

[0013] However, the current process window of the cutting process is getting smaller and smaller, and it is difficult to adapt to the demand for the gradual reduction of the critical size of the device. Taking the cut-first process as an example, the reasons why the process window of the cutting process is getting smaller and smaller are analyzed. Figures 1 to 5 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 , providing a substrate, including a target layer 1 for forming a target pattern, the substrate including a target area i for forming a target pattern and a cutting area ii corresponding to a cutting position; forming a discrete sidewall 2 on the target layer 1.

[0015] refer to Figures 2 to 4 , removing the side wall 2 located in the cutting area ii; the step of removing the side wall 2 located in the cutting area ii includes: forming a mask layer 3 on the substrate 1, the mask layer 3 having a mask opening 4 exposing the side wall 2 located in the cutting area ii; using the mask layer 3 as a mask, etching the side wall 2 along the mask opening 4; removing the mask layer 3.

[0016] refer to Figure 5 , using the sidewall 2 as a mask, the substrate 1 is patterned to form a fin 5 .

[0017] In the formation method, the process window for removing the sidewall 2 located in the cutting area ii is small, and as the critical dimension of the device is further reduced, the process window for removing the sidewall 2 located in the cutting area ii is also getting smaller and smaller.

[0018] Specifically, as the critical dimensions of the device continue to shrink, the opening size of the mask opening 4 becomes smaller and smaller, which makes it more difficult to form the mask opening 4. The process of forming the mask opening 4 includes a photolithography process. The opening size of the mask opening 4 becomes smaller and smaller, and the requirements for the overlay offset accuracy of the photolithography process become higher and higher. The process window of the photolithography process is smaller; moreover, in order to ensure that the mask layer 3 has sufficient protection capability for the side wall 2 located in the target area i, the mask layer 3 usually needs to have a larger thickness. The process of forming the mask opening 4 also includes an etching process. The thickness of the mask layer 3 is relatively large. At the same time, the size of the mask opening 4 is small, which easily leads to a larger height-to-width ratio of the etching process, and the process window of the etching process is also getting smaller and smaller.

[0019] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein a pseudo sidewall located in the target area is etched, a groove is formed between the filling layer and the core layer, and a mask sidewall is formed in the groove; in this embodiment, the pseudo sidewall located in the target area is etched, and compared with using a cutting process (Cut) to remove the pseudo sidewall located in the cutting area, the process window for etching the pseudo sidewall located in the target area is larger. Moreover, the embodiment of the present invention can use the mask sidewall as a mask to remove the pseudo sidewall located in the cutting area, and use the mask sidewall as a mask to pattern the target layer. Accordingly, the embodiment of the present invention avoids using a cutting process to remove the pseudo sidewall in the cutting area, and accordingly does not need to form a graphic transfer mask (Transfer Mask) for the cutting process in the cutting area, which is beneficial to increasing the process window for removing the pseudo sidewall located in the cutting area and preventing defects in the cutting process (for example, residual pseudo sidewalls in the cutting area), thereby improving the process yield and the performance of the semiconductor structure.

[0020] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figures 6 to 19 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0022] refer to Figure 6 , providing a substrate including a target layer 100, wherein the substrate includes a target area I for forming a target pattern and a cutting area II corresponding to a cutting position. The substrate is used to provide a platform for the process.

[0023] The target layer 100 is a film layer to be patterned to form a target pattern. In this embodiment, the target layer 100 is an initial substrate. The initial substrate is subsequently patterned to form a substrate and a fin protruding from the substrate. Accordingly, the target pattern is a fin. The fin is used to form a fin field-effect transistor (FinFET).

[0024] The target area I is the area where the subsequent target pattern layer is located, and the area on the substrate other than the target area I is the cutting area II. Accordingly, in this embodiment, the target area I is the active area (AA), and the cutting area II is the isolation area.

[0025] In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The initial substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, the initial substrate may include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer. The second semiconductor layer is subsequently patterned to form fins, and the first semiconductor layer remains as the substrate.

[0026] In other embodiments, the target pattern may also be a gate structure, an interconnect trench in a back-end-of-line process, a channel stack in a gate-all-around (GAA) transistor, or a hard mask (HM) layer. Depending on the actual target pattern to be formed, the material of the target layer may also be other corresponding materials.

[0027] In this embodiment, the substrate further includes an adhesion layer 101 and a hard mask material layer 102 stacked sequentially on the target layer 100. The adhesion layer 101 is used to improve the adhesion between the hard mask material layer 102 and the target layer 100 and reduce the stress generated between the film layers. In this embodiment, the material of the adhesion layer 101 is silicon oxide.

[0028] After the mask sidewalls are subsequently formed, the hard mask material layer 102 is first patterned using the mask sidewalls as a mask to form a hard mask layer. Even if the mask sidewalls are damaged during the process of patterning the target layer 100, the target layer 100 can continue to be patterned using the hard mask layer as a mask, which is beneficial for improving the process stability of patterning the target layer 100 and correspondingly improving the accuracy of pattern transfer. In addition, the subsequent processes of forming a core layer on the target layer 100, removing the core layer and filler layer, and etching the dummy sidewalls using the mask sidewalls as a mask all include etching processes. The hard mask material layer 102 can also define the etching stop position in these etching processes to avoid etching damage to the film layer below it, thereby reducing the probability of height inconsistency on the top surface of the film layer to be etched below it, and correspondingly improving the etching uniformity of the subsequent patterning of the target layer 100.

[0029] The material of the hard mask material layer 102 includes at least one of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 102 is silicon nitride.

[0030] It should be noted that, in this embodiment, the forming method further includes: forming an etching buffer layer 110 on the target layer 100. Specifically, the etching buffer layer 110 is formed on the hard mask material layer 102.

[0031] In this embodiment, subsequent steps also include: forming a discrete core layer on the target layer 100; forming a sidewall film that conformally covers the core layer and the target layer 100, and the sidewall film located on the sidewall of the core layer is used as a pseudo sidewall; forming a filling layer on the sidewall film exposed by the core layer and the pseudo sidewall; removing part of the height of the pseudo sidewall to form a groove; filling the groove with a mask sidewall; removing the core layer and the filling layer; and using the mask sidewall as a mask to pattern the target layer 100 to form a target pattern.

[0032] By forming the etching buffer layer 110, the sidewall film is formed on the etching buffer layer 110, so that before the subsequent patterning of the target layer 100, the sidewall film, the etching buffer layer 110 and the dummy sidewall can be etched using the mask sidewall as a mask; after removing the filling layer and the core layer, one side of the mask sidewall exposes the sidewall film, and the other side exposes the substrate surface. The etching buffer layer 110 is used to reduce the effect of the film height difference on both sides of the mask sidewall on the etching of the sidewall film and the dummy sidewall, so as to avoid the problem of inconsistent etching depth, thereby facilitating In order to prevent damage to the film layer located below the etching buffer layer 110, the process effect of the subsequent patterned target layer 100 is correspondingly improved. Moreover, the pattern of the mask side wall can be transferred to the pseudo side wall, the side wall film and the etching buffer layer 110. When there is a bottom defect at the bottom of the pseudo side wall or the side wall verticality is low, it is beneficial to etch away the bottom defect of the pseudo side wall, prevent the pattern defect of the pseudo side wall from causing adverse effects on the patterned target layer 100, and make the side wall verticality of the etched pseudo side wall, side wall film and etching buffer layer 110 higher, thereby improving the accuracy of pattern transfer.

[0033] In this embodiment, the etching selectivity ratio between the etching buffer layer 110 and the dummy side wall is 1:2 to 2:1, and the etching properties of the etching buffer layer 110 are similar to those of the dummy side wall, thereby ensuring that the side wall film, the dummy side wall and the etching buffer layer 110 can be etched in the same step later using the mask side wall as a mask, which is beneficial to reducing the difficulty of etching the side wall film, the dummy side wall and the etching buffer layer 110 using the mask side wall as a mask, and correspondingly improving the verticality of the side wall at the bottom of the dummy side wall.

[0034] As an example, the etching selectivity ratio between the etching buffer layer 110 and the dummy sidewall spacer is 1:1.1.

[0035] According to the material of the subsequent dummy sidewall spacer, the material of the etching buffer layer 110 includes silicon oxide, silicon, silicon carbide, silicon oxynitride, silicon oxycarbide or silicon carbon oxynitride. In this embodiment, the material of the etching buffer layer 110 is silicon oxide.

[0036] The thickness of the etching buffer layer 110 should not be too small or too large. If the thickness of the etching buffer layer 110 is too small, it is easy to cause the etching buffer layer 110 to be used to reduce the effect of the height difference of the film layer on both sides of the mask side wall on the etching of the side wall film and the pseudo side wall. If the thickness of the etching buffer layer 110 is too large, the time required for the subsequent etching of the pseudo side wall, the side wall film and the etching buffer layer 110 using the mask side wall as a mask is too long, which is easy to increase the additional process time. For this reason, in the present embodiment, the thickness of the side wall film in the direction perpendicular to the substrate surface is the reference thickness, and the thickness of the etching buffer layer 110 is 3 to 8 times the reference thickness.

[0037] In this embodiment, a deposition process is used to form the etching buffer layer 110. The deposition process may be an atomic layer deposition process or a chemical vapor deposition process.

[0038] Continue to refer Figure 6 A separate core layer 120 is formed on the target layer 100. The core layer 120 is used to provide support for the subsequent formation of dummy sidewalls. Specifically, the core layer 120 is separated on the etching buffer layer 110.

[0039] The core layer 120 will be removed later. Therefore, the core layer 120 is made of a material that is easily removable. The material of the core layer 120 has etch selectivity with the etch buffer layer 110 and the subsequently formed dummy sidewalls and mask sidewalls. This helps minimize damage to other film layers during the core layer 120 removal process and reduces the difficulty of removing the core layer 120. The material of the core layer 120 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the core layer 120 is amorphous silicon.

[0040] The core layer 120 may be formed by a process combining deposition and etching, or may be formed by a patterning process such as SAQP or SADP, so that the core layer 120 has a smaller pitch and size.

[0041] refer to Figure 7 , forming a dummy sidewall spacer 130 on the sidewall of the core layer 120 .

[0042] The dummy sidewall spacer 130 located in the target area I is used to occupy a space for the subsequent formation of a mask sidewall spacer.

[0043] Specifically, the dummy sidewall spacer 130 is formed on the etching buffer layer 110 .

[0044] In this embodiment, the dummy sidewall spacer 130 is made of a material having similar etching properties to the etch buffer layer 110. Specifically, the etching selectivity ratio between the etch buffer layer 110 and the dummy sidewall spacer 130 is 1:2 to 2:1. Furthermore, the material of the dummy sidewall spacer 130 also has etching selectivity with the material of the core layer 120. The material of the dummy sidewall spacer 130 includes silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride, or titanium oxide.

[0045] In this embodiment, the material of the dummy sidewall 130 is the same as that of the etching buffer layer 110, which is beneficial to further reduce the process difficulty of etching the dummy sidewall 130 and the etching buffer layer 110 using the mask sidewall as a mask in the same step, thereby improving process compatibility.

[0046] In this embodiment, the step of forming the dummy sidewall spacer 130 includes forming a sidewall spacer film 125 conformally covering the core layer 120 and the target layer 100 . The sidewall spacer film 125 on the sidewall of the core layer 120 serves as the dummy sidewall spacer 130 .

[0047] In this embodiment, an atomic layer deposition process is used to form the sidewall film 125. The atomic layer deposition process has a high step coverage capability, thereby improving the coverage capability of the sidewall film 125 on the top surface and sidewalls of the core layer 120 and the etching buffer layer 110, which in turn helps to improve the thickness uniformity of the sidewall film 125 and also helps to improve the verticality of the sidewalls of the dummy sidewalls 130.

[0048] In this embodiment, the formation method also includes: removing the side wall film 125 located on the top surface of the core layer 120, thereby exposing the top of the core layer 120 to facilitate the subsequent removal of the core layer 120, and also exposing the top surface of the pseudo side wall 130 located on the side wall of the core layer 120, so that the pseudo side wall 130 located in the target area I can be etched through the exposed top surface of the pseudo side wall 130.

[0049] refer to Figures 8 to 10 A filling layer 140 is formed on the target layer 100 exposed by the core layer 120 and the dummy sidewalls 130. Subsequently, a portion of the dummy sidewalls 130 is removed to form a trench surrounded by the filling layer 140, the core layer 120, and the remaining dummy sidewalls 130. The filling layer 140 is used to provide support for the subsequent formation of mask sidewalls in the trench.

[0050] The filling layer 140 will be removed later, so the filling layer 140 is selected from a material that is easily removable. The material of the filling layer 140 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the filling layer 140 is the same as that of the core layer 120. The material of the filling layer 140 is amorphous silicon. This not only helps avoid the introduction of new material types, thereby improving process compatibility and reducing process risks, but also, after the mask sidewalls are formed, the core layer 120 and the filling layer 140 can be removed in the same step, which helps simplify the process steps.

[0051] The formation method further includes removing the spacer film 125 located on the top surface of the core layer 120, thereby exposing the top of the core layer 120 to facilitate subsequent removal of the core layer 120. In this embodiment, during the step of forming the filling layer 140, the spacer film 125 located on the top surface of the core layer 120 is removed, which facilitates integrating the formation of the filling layer 140 with the removal of the spacer film 125 located on the top surface of the core layer 120, thereby simplifying the process and improving process compatibility.

[0052] In this embodiment, the steps of forming the filling layer 140 include: Figure 8 As shown, a filling material layer 135 is formed to cover the sidewall film 125; Figure 9 As shown, the sidewall film 125 located on the top surface of the core layer 120 is used as a stop position to planarize the filling material layer 135; Figure 10 As shown, after planarizing the filling material layer 135, the filling material layer 135 above the top surface of the core layer 120 is removed to form the filling layer 140. In the step of removing the filling material layer 135 above the top surface of the core layer 120, the spacer film 125 located on the top surface of the core layer 120 is removed.

[0053] In this embodiment, the process for forming the filling material layer 135 includes one or more of a spin coating process, a chemical vapor deposition process, and an atomic layer deposition process. As an example, a chemical vapor deposition (CVD) process is used to form the filling material layer 135. The CVD process has a high filling capacity, which helps improve the filling quality of the filling material layer 135 between the sidewalls 130 and reduces the probability of defects in the filling material layer 135. The CVD process is also low-cost.

[0054] In this embodiment, the filler material layer 135 is planarized with the spacer film 125 located on the top surface of the core layer 120 as the stop point, which helps reduce the difficulty of planarizing the filler material layer 135 and further helps improve the flatness of the top surface of the planarized filler material layer 135. Specifically, the process of planarizing the filler material layer 135 includes a chemical mechanical polishing process.

[0055] In this embodiment, an etching process is used to remove the filling material layer 135 above the top surface of the core layer 120 and the spacer film 125 located on the top surface of the core layer 120. Specifically, the etching process can be a dry etching process. The dry etching process has high etching precision and etching efficiency.

[0056] In other embodiments, the sidewall film located on the top surface of the core layer and the target layer can be removed after the dummy sidewall is formed and before the filling layer is formed. Accordingly, an anisotropic etching process is used to remove the sidewall film located on the top surface of the core layer and the target layer. Specifically, the anisotropic etching process can be an anisotropic dry etching process. The steps of forming the filling layer accordingly include: forming a filling material layer covering the core layer and the dummy sidewall on the substrate; and flattening the filling material layer with the top surface of the dummy sidewall as the stopping position to form the filling layer.

[0057] refer to Figures 11 to 14 The dummy sidewall spacer 130 located in the target area I is etched to form a trench 300 between the filling layer 140 and the core layer 120. The trench 300 is used to provide a space for the subsequent formation of the mask sidewall spacer.

[0058] In this embodiment, only the dummy sidewall 130 located in the target area I is etched. Therefore, the trench 200 is only located in the target area I, so that the subsequent mask sidewall will not be formed in the cutting area II. The mask sidewall is only formed in the target area I, and accordingly, there is no need to perform the step of cutting the mask sidewall located in the cutting area II, thereby avoiding the cutting process.

[0059] Moreover, the process of etching the pseudo sidewall 130 located in the target area I includes forming a protective layer covering the pseudo sidewall 130 of the cutting area II. In this embodiment, the pseudo sidewall 130 located in the target area I is etched. Compared with using a cutting process (Cut) to remove the pseudo sidewall located in the cutting area, the protective layer in this embodiment can be formed on the filling layer 140 and the core layer 120. The thickness of the protective layer is relatively small. At the same time, the protective layer can be located on the filling layer 140 and the core layer 120, which has a greater tolerance for the overlay offset and critical dimension deviation of the photolithography process for forming the protective layer. Therefore, the difficulty of the patterning process of the protective layer is lower, which is conducive to increasing the process window for forming the protective layer. In addition, compared with only etching the pseudo sidewall 130 in the cutting area II, the pseudo sidewall 130 located in the target area I is etched in this embodiment. The number of etched pseudo sidewalls 130 is greater, which correspondingly makes the process window for etching the pseudo sidewall 130 located in the target area I larger.

[0060] In this embodiment, a portion of the dummy sidewall spacer 130 located in the target area I is etched away. In the step of forming the dummy sidewall spacer 130, the sidewall of the dummy sidewall spacer 130 has a certain inclination, and the bottom of the dummy sidewall spacer 130 is prone to a bottom footing problem. The closer to the bottom of the dummy sidewall spacer 130, the larger the lateral dimension of the dummy sidewall spacer 130, and the greater the deviation between the lateral dimension of the dummy sidewall spacer 130 and the designed dimension. By removing a portion of the dummy sidewall spacer 130, a mask sidewall is formed in the trench 300, so that the lateral dimension of the mask sidewall is smaller than the lateral dimension of the dummy sidewall 130, thereby reducing the deviation between the lateral dimension of the mask sidewall and the designed dimension.

[0061] In other embodiments, according to the actual process, in the step of etching the dummy sidewall spacers located in the target area, the dummy sidewall spacers with the entire height located in the target area may be removed by etching.

[0062] In this embodiment, etching the dummy sidewall spacer 130 located in the target area I includes the following steps.

[0063] like Figures 11 to 12 As shown, a protection layer 230 is formed on the core layer 120 and the filling layer 140 to cover the top surface of the dummy sidewall spacer 130 in the cutting area II. The protection layer 230 exposes the dummy sidewall spacer 130 in the target area I. The protection layer 230 is used as a mask for etching the dummy sidewall spacer 130.

[0064] The protective layer 230 is made of a material having etching selectivity with the dummy sidewall spacer 130, thereby ensuring that the protective layer 230 can be used as a mask for etching the dummy sidewall spacer 130. In this embodiment, the protective layer 230 is an inorganic hard mask material, and the material of the protective layer 230 includes silicon oxide, silicon nitride, or titanium nitride.

[0065] In this embodiment, the material of the protection layer 230 is silicon nitride.

[0066] In other embodiments, the material of the protection layer may also be an organic mask material.

[0067] In this embodiment, the steps of forming the protective layer 230 include: Figure 11 As shown, a protective material layer 210 is formed on the protective layer 230; a mask layer 220 is formed on the protective material layer 210; Figure 12 As shown, the protective material layer 210 is etched using the mask layer 220 as a mask; and the mask layer 220 is removed.

[0068] In this embodiment, the material of the mask layer 220 is photoresist.

[0069] In this embodiment, the process of etching the protective material layer 210 using the mask layer 220 as a mask includes one or both of a dry etching process and a wet etching process. In this embodiment, the process of removing the mask layer 220 includes one or both of an ashing process and a wet stripping process.

[0070] like Figure 13 As shown, the dummy sidewall spacer 130 of the target area I is etched using the protection layer 230 as a mask.

[0071] In this embodiment, during the process of etching the pseudo side wall 130 of the target area I, since there is an etching selectivity ratio between the pseudo side wall 130 and the core layer 120 or the filling layer 140, the core layer 120 and the filling layer 140 can define the stopping position of etching in the direction parallel to the substrate and perpendicular to the side wall of the pseudo side wall 130, thereby helping to reduce the process difficulty of etching the pseudo side wall 130 located in the target area I, so that this embodiment can flexibly select the process of etching the pseudo side wall 130.

[0072] Specifically, in this embodiment, in the step of etching the pseudo side wall 130 of the target area I, the etching selectivity ratio between the pseudo side wall 130 and the core layer 120 or the filling layer 140 is at least 50:1, so that the process of etching the pseudo side wall 130 is not likely to cause mis-etching of the core layer 120 or the filling layer 140, thereby preventing the expansion of the opening size of the groove 300, and correspondingly ensuring that the deviation between the critical size of the subsequent mask side wall and the design size is small, which is also beneficial to ensuring the cross-sectional morphology quality of the groove 300.

[0073] In this embodiment, the process for removing a portion of the height of the dummy sidewall 130 is an isotropic etching process. Along a direction perpendicular to the sidewalls of the core layer 120, the thickness of the dummy sidewall 130 is highly consistent, and the top area of ​​the dummy sidewall 130 exposed in each region is highly consistent. Therefore, when etching the dummy sidewall 130 using the isotropic etching process, the removal height of the dummy sidewall 130 is also highly consistent. Furthermore, the use of an isotropic etching process is beneficial in reducing damage to other film layers. For example, it reduces the probability of mis-etching the core layer 120 or the filling layer 140, thereby preventing the opening size of the trench 300 from being enlarged, thereby ensuring that the deviation between the opening size of the trench 300 and the designed size is small.

[0074] In this embodiment, one or both of a dry etching process and a wet etching process are used to etch the dummy sidewall spacer 130 of the target area I. As an example, the material of the dummy sidewall spacer 130 is silicon oxide, and a wet etching process is used to etch the dummy sidewall spacer 130 of the target area I, wherein the etching solution of the wet etching process is a hydrofluoric acid solution.

[0075] like Figure 14As shown, the protection layer 230 is removed.

[0076] Specifically, an etching process for removing the protective layer 230 is selected based on the material of the protective layer 230. In this embodiment, the material of the protective layer 230 is silicon nitride, and a wet etching process is used to remove the protective layer 230.

[0077] refer to Figures 15 and 16 , a mask sidewall 150 is formed in the trench 300. The mask sidewall 150 is used as a mask for subsequently etching the dummy sidewall 130 of the cutting region II and patterning the target layer 100.

[0078] In this embodiment, the mask side wall 150 is only located on the target area I. Subsequently, the mask side wall 150 can be used as a mask to remove the dummy side wall 130 located in the cutting area II, and the mask side wall 150 can be used as a mask to pattern the target layer 100. Accordingly, this embodiment avoids using a cutting process to remove the dummy side wall 130 in the cutting area II.

[0079] Moreover, as can be seen from the above, the deviation between the opening size of the trench 300 and the design size is small. Accordingly, after the mask sidewall 150 is formed in the trench 300, the deviation between the lateral size of the mask sidewall 150 and the design size is smaller than the lateral size of the dummy sidewall 130. Therefore, in the process of patterning the target layer 100 using the mask sidewall 150 as a mask, it is beneficial to improve the accuracy of the pattern transfer, reduce the deviation between the critical size of the target pattern and the design size, and thus improve the pattern accuracy (for example: critical size accuracy) and morphology quality of the target pattern, and also help to improve the pitch walking problem, which is correspondingly beneficial to increase the process window of the subsequent process, improve the process yield and the performance of the semiconductor structure.

[0080] In this embodiment, the material of the mask side wall 150 is different from the material of any one of the pseudo side wall 130, the filling layer 140 and the core layer 120, thereby ensuring that the mask side wall 150 and any one of the pseudo side wall 130, the filling layer 140 and the core layer 120 have etching selectivity, thereby ensuring that the subsequent process of removing the filling layer 140 and the core layer 120 has a low probability of causing mis-etching of the mask side wall 150, and ensuring that the mask side wall 150 is used as a mask for etching the pseudo side wall 130 and the patterned target layer 100.

[0081] In this embodiment, the etching selectivity ratio between the dummy spacer 130 and the mask spacer 150 is at least 10:1. The etching selectivity between the dummy spacer 130 and the mask spacer 150 is relatively large, thereby ensuring that the mask spacer 150 can be used as an etching mask for removing the dummy spacer 130 in the cutting area II.

[0082] The material of the mask spacer 150 includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide and titanium. As an example, the material of the mask spacer 150 is silicon nitride.

[0083] In this embodiment, the steps of forming the mask sidewall 150 include: Figure 15 As shown, the mask spacer material 145 is filled in the trench 300, and the mask spacer material 145 also covers the top surface of the filling layer 140 and the core layer 120, as well as the dummy spacer 130 of the cutting area II; Figure 16 As shown, the mask spacer material 145 above the top surfaces of the filling layer 140 and the core layer 120 is removed to form a mask spacer 150 .

[0084] In this embodiment, the process for forming the mask spacer material 145 includes an atomic layer deposition process. The atomic layer deposition process has a high gap-filling capability, making it easy to completely fill the trench 300 with the mask spacer material 145. In addition, the film layer formed by the atomic layer deposition process has a high density, which is beneficial for improving the density of the mask spacer and correspondingly improving the pattern transfer effect when subsequently etching the dummy spacer 130 and the patterned target layer 100 using the mask spacer as a mask.

[0085] In this embodiment, an etching process is used to remove the mask spacer material 145 above the top surfaces of the filling layer 140 and the core layer 120 ; the etching process includes a dry etching process, which has high etching precision and etching efficiency.

[0086] In this embodiment, the dummy sidewall spacer 130 located in the cutting area II and the mask sidewall spacer 150 in the target area I constitute a sidewall structure layer 200 . The sidewall structure layer 200 is located on the sidewall of the core layer 120 .

[0087] Specifically, in this embodiment, the target area I still retains some of the remaining dummy sidewalls 130 , and the sidewall structure layer 200 located in the target area I includes the dummy sidewalls 130 and the mask sidewalls 150 located on the dummy sidewalls 130 .

[0088] refer to Figure 17 , removing the core layer 120 and the filling layer 140 to facilitate subsequent patterning of the target layer 100 using the mask sidewalls 150 as a mask. In this embodiment, the process of removing the core layer 120 and the filling layer 140 includes one or both of dry etching and wet etching. In this embodiment, after removing the core layer 120 and the filling layer 140, the sidewall film 125 located on the substrate is exposed.

[0089] refer to Figure 18, using the mask sidewall 150 as a mask, remove the dummy sidewall 130 located in the cutting area II.

[0090] The dummy spacer 130 located in the cutting area II is removed, thereby preventing the dummy spacer 130 located in the cutting area II from having adverse effects on the subsequent patterning target layer 100 .

[0091] In this embodiment, the mask side wall 150 is only located on the target area I, so the mask side wall 150 can be used as a mask to remove the dummy side wall 130 located in the cutting area II. Accordingly, this embodiment avoids using a cutting process to remove the dummy side wall in the cutting area, and there is no need to form a graphic transfer mask (Transfer Mask) for the cutting process in the cutting area, which is beneficial to increasing the process window for removing the dummy side wall 130 located in the cutting area II, avoiding defects in the cutting process (for example, residual dummy side wall in the cutting area), and thereby improving the process yield and the performance of the semiconductor structure.

[0092] In this embodiment, the mask sidewall 150 is used as a mask and an anisotropic etching process is adopted to remove the dummy sidewalls 130 located in the cutting area II. The anisotropic etching process has the characteristic of anisotropic etching. Specifically, the longitudinal etching rate of the etching process is greater than the lateral etching rate. By adopting the anisotropic etching process, while removing the dummy sidewalls 130 located in the cutting area II, the probability of causing lateral mis-etching of the dummy sidewalls 130 located below the mask sidewall 150 is reduced. The dummy sidewalls 130 located in the target area I can be retained under the shielding of the mask sidewall 150. In addition, the dummy sidewalls 130 located in the target area I can support the mask sidewalls 150, ensuring that the mask sidewalls 150 are not easily tilted or collapsed.

[0093] In this embodiment, in the step of removing the dummy sidewall 130 located in the cutting area II using the mask sidewall 150 as a mask, the mask sidewall 150 is also used as a mask to etch the sidewall film 125 and the etching buffer layer 110 and the dummy sidewall 130 of the target area I.

[0094] The etching buffer layer 110 can reduce the influence of the film height difference on both sides of the mask side wall 150 on the etching of the side wall film 125 and the pseudo side wall 130, so as to avoid the problem of inconsistent etching depth, thereby helping to prevent damage to the film layer located below the etching buffer layer 110, and correspondingly improving the process effect of the subsequent graphic target layer 100. Moreover, it can also transfer the pattern of the mask side wall 150 to the pseudo side wall 130, the side wall film 125 and the etching buffer layer 110, which is helpful to etch and remove the bottom defects of the pseudo side wall 130, so as to prevent the graphic defects of the pseudo side wall 130 from having an adverse effect on the graphic target layer 100.

[0095] Specifically, in this embodiment, the anisotropic etching process is an anisotropic dry etching process. The dry etching process is easy to achieve anisotropic etching and has high process controllability and good etching profile controllability.

[0096] refer to Figure 19 , using the mask sidewall 150 as a mask, the target layer 100 is patterned to form a target pattern.

[0097] As can be seen from the foregoing, this embodiment avoids using a cutting process to remove the pseudo side wall in the cutting area, which is beneficial to increasing the process window for removing the pseudo side wall 130 located in the cutting area II and preventing defects in the cutting process (for example, residual pseudo side wall in the cutting area). This is not only beneficial to improving the process yield and the performance of the semiconductor structure, but also improves the graphical process effect and graphic transfer accuracy of the graphical target layer 100, and correspondingly improves the graphic accuracy and morphology quality of the target graphic.

[0098] Moreover, compared with the lateral dimensions of the pseudo sidewall, the deviation between the lateral dimensions of the mask sidewall 150 and the design dimensions is smaller, and the graphic accuracy of the mask sidewall 150 is high. Therefore, in the process of patterning the target layer 100 using the mask sidewall 150 as a mask, it is beneficial to improve the accuracy of graphic transfer, reduce the deviation between the critical dimension of the target graphic and the design dimension, and correspondingly improve the graphic effect of the patterned target layer 100, thereby improving the graphic accuracy (for example: critical dimension accuracy) and morphology quality of the target graphic, and also helping to improve the problem of spacing swing, which is correspondingly beneficial to increasing the process window of subsequent processes, improving the process yield and the performance of the semiconductor structure.

[0099] In this embodiment, the target layer 100 is the initial substrate. Therefore, the initial substrate is patterned using the mask spacers 150 as a mask to form a substrate 180 and a fin 170 protruding from the substrate 180. Accordingly, the target pattern is the fin 170. The fin 170 is used to form a fin field-effect transistor (FinFET). The fin 170 formed in this embodiment has high pattern quality and dimensional accuracy, which helps improve the performance of the FinFET.

[0100] In other implementations, the target pattern may also be a gate structure, an interconnect trench in a back-end-of-line process, a channel stack or a hard mask layer in a gate-all-around transistor, or other patterns. When the target pattern is other patterns, this embodiment also helps improve the pattern quality and dimensional accuracy of the target pattern, thereby correspondingly improving device performance.

[0101] In this embodiment, before patterning the target layer 100, the hard mask material layer 102 and the adhesion layer 101 are patterned in sequence using the mask spacers 150 as a mask, and the remaining hard mask material layer 102 is used as the hard mask layer 160. Therefore, even if the mask spacers 150 are worn out during the process of patterning the target layer 100, the hard mask layer 160 can continue to serve as a mask for patterning the target layer 100, thereby improving the accuracy and stability of pattern transfer.

[0102] Accordingly, the present invention also provides a semiconductor structure. Figure 16 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0103] The semiconductor structure includes: a substrate, including a target layer 100, the substrate including a target area I for forming a target pattern and a cutting area II corresponding to a cutting position; a core layer 120, separated on the target layer 100; a sidewall structure layer 200, located on the sidewall of the core layer 120, the sidewall structure layer 200 including a pseudo sidewall 130 located in the cutting area II and a mask sidewall 150 located in the target area I, the mask sidewall 150 being used as a mask for patterning the target layer 100; a filling layer 140, located on the target layer 100 exposed by the core layer 120 and the sidewall structure layer 200.

[0104] In this embodiment, by making the sidewall structure layer 200 include a dummy sidewall 130 located in the cutting area II and a mask sidewall 150 located in the target area I, this embodiment can subsequently use the mask sidewall 150 as a mask to remove the dummy sidewall 130 located in the cutting area II. Compared with using a cutting process (Cut) to remove the dummy sidewall located in the cutting area, this embodiment avoids the step of using a cutting process to remove the dummy sidewall in the cutting area, and accordingly does not need to form a graphic transfer mask (Transfer Mask) for the cutting process in the cutting area, which is beneficial to increasing the process window for removing the dummy sidewall 130 located in the cutting area II and preventing defects in the cutting process (for example, residual dummy sidewalls in the cutting area), thereby improving the process yield and the performance of the semiconductor structure.

[0105] The substrate is used to provide a platform for the process.

[0106] The target layer 100 is a film layer to be patterned to form a target pattern. In this embodiment, the target layer 100 is an initial substrate. The initial substrate is subsequently patterned to form a substrate and a fin protruding from the substrate. Accordingly, the target pattern is a fin. The fin is used to form a fin field-effect transistor (FinFET).

[0107] Target Area I is the area where the subsequent target pattern layer will be located. The area on the substrate other than Target Area I is the dicing area II. Accordingly, in this embodiment, Target Area I is the active area (AA), and dicing area II is the isolation area. In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate can also be made of other materials, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0108] In other embodiments, the target pattern may also be a gate structure, an interconnect trench in a back-end process, a channel stack or a hard mask layer in a gate-all-around transistor, etc. Depending on the actual target pattern to be formed, the material of the target layer may also be other corresponding materials.

[0109] In this embodiment, the substrate further includes an adhesion layer 101 and a hard mask material layer 102 stacked sequentially on the target layer 100. The adhesion layer 101 is used to improve the adhesion between the hard mask material layer 102 and the target layer 100 and reduce the stress generated between the film layers. In this embodiment, the material of the adhesion layer 101 is silicon oxide.

[0110] Subsequently, the hard mask material layer 102 is patterned using the mask sidewalls 150 as a mask to form a hard mask layer. Therefore, even if the mask sidewalls 150 are damaged during the patterning of the target layer 100, the hard mask layer can continue to be used as an etching mask, which is beneficial for improving the process stability of patterning the target layer 100 and correspondingly improving the accuracy of pattern transfer. In addition, the processes of forming the core layer 120, removing the core layer 120 and the filler layer 140, and etching the dummy sidewalls 130 using the mask sidewalls 150 as a mask all include etching processes. The hard mask material layer 102 can also define the etching stop position in these etching processes to avoid etching damage to the film layer below it. In this embodiment, the material of the hard mask material layer 102 is silicon nitride.

[0111] The core layer 120 is used to provide support for forming the sidewall structure layer 200 .

[0112] The core layer 120 will be removed later. Therefore, the core layer 120 is made of a material that is easily removable. The material of the core layer 120 has etching selectivity with the materials of the dummy sidewall spacers 130 and the mask sidewall spacers 150, thereby minimizing damage to other film layers during the core layer 120 removal process and reducing the difficulty of removing the core layer 120. The material of the core layer 120 includes one or more of amorphous silicon, silicon nitride, silicon oxide, and amorphous carbon. In this embodiment, the material of the core layer 120 is amorphous silicon.

[0113] In the sidewall structure layer 200, the dummy sidewall 130 is not used as a mask for the patterned target layer 100. The mask sidewall 150 will be used as a mask later to remove the dummy sidewall 130 located in the cutting area II, which is beneficial to prevent the dummy sidewall 130 from having an adverse effect on the patterned target layer 100, thereby improving the accuracy of the graphic transfer; moreover, after the filling layer 140 and the core layer 120 are subsequently removed, the dummy sidewall 130 is located at the bottom of the mask sidewall 150 and is also used to provide support for the mask sidewall 150.

[0114] In this embodiment, the dummy spacer 130 is made of a material having etching selectivity with the core layer 120, the filling layer 140, and the mask spacer 150. The material of the dummy spacer 130 includes silicon oxide, silicon nitride, silicon oxynitride, silicon, aluminum oxide, titanium nitride, or titanium oxide.

[0115] In this embodiment, the material of the dummy sidewall spacer 130 is silicon oxide.

[0116] In this embodiment, the dummy sidewall spacer 130 is also located at the bottom of the mask sidewall spacer 150 in the target area I. The sidewall structure layer 200 located in the target area I includes the dummy sidewall spacer 130 and the mask sidewall spacer 150 located on the dummy sidewall spacer 130.

[0117] The mask sidewalls 150 are used as a mask for subsequently etching the dummy sidewalls 130 in the cutting area II and patterning the target layer 100. In this embodiment, the mask sidewalls 150 are located only on the target area I. Subsequently, the mask sidewalls 150 can be used as a mask to remove the dummy sidewalls in the cutting area II, and the mask sidewalls 150 can be used as a mask to pattern the target layer 100. Accordingly, this embodiment avoids using a cutting process to remove the dummy sidewalls 130 in the cutting area II.

[0118] The sidewall of the spacer structure layer 200 has a certain inclination. The closer to the bottom of the spacer structure layer 200, the larger the lateral dimension of the spacer structure layer 200, and the greater the deviation between the lateral dimension of the spacer structure layer 200 and the design dimension. The closer to the top of the spacer structure layer 200, the smaller the deviation between the lateral dimension of the spacer structure layer 200 and the design dimension. Therefore, compared with the lateral dimension of the dummy spacer 130, the deviation between the lateral dimension of the mask spacer 150 and the design dimension is smaller, and the graphic accuracy is higher. In the process of patterning the target layer 100 using the mask spacer 150 as a mask, it is beneficial to improve the accuracy of graphic transfer, reduce the deviation between the critical dimension of the target graphic and the design dimension, and correspondingly improve the graphic effect of the patterned target layer 100, thereby improving the graphic accuracy (for example: critical dimension accuracy) and morphology quality of the target graphic, and also beneficial to improve the problem of spacing swing, which is correspondingly beneficial to increasing the process window of subsequent processes, improving the process yield and the performance of the semiconductor structure.

[0119] Therefore, the material of the mask side wall 150 is different from the material of any one of the pseudo side wall 130, the filling layer 140 and the core layer 120, thereby ensuring that the mask side wall 150 has etching selectivity with any one of the pseudo side wall 130, the filling layer 110 and the core layer 120, thereby ensuring that the probability of the subsequent process of removing the filling layer 110 and the core layer 120 causing mis-etching of the mask side wall 150 is low, and ensuring that the mask side wall 150 is used as a mask for etching the pseudo side wall 130 and the patterned target layer 100.

[0120] In this embodiment, the etching selectivity ratio between the dummy spacer 130 and the mask spacer 150 is at least 10:1. The etching selectivity between the mask spacer 150 and the dummy spacer 130 is relatively large, thereby ensuring that the mask spacer 150 can be used as an etching mask for removing the dummy spacer 130 in the cutting area II.

[0121] The material of the mask spacer 150 includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide and titanium. As an example, the material of the mask spacer 150 is silicon nitride.

[0122] The filling layer 140 is used to provide support during the process of forming the mask sidewalls 150. The filling layer 140 will be removed later, so the filling layer 140 is made of a material that is easy to remove. The material of the filling layer 140 includes one or more of amorphous silicon, silicon nitride, silicon oxide and amorphous carbon. In this embodiment, the material of the filling layer 140 is the same as that of the core layer 120. The material of the filling layer 140 is amorphous silicon, which not only helps to avoid the introduction of new types of materials to improve process compatibility and reduce process risks, but also allows the core layer 120 and the filling layer 140 to be removed in the same step later, which helps to simplify the process steps.

[0123] In this embodiment, the semiconductor structure also includes: a sidewall film 125, located between the filling layer 140 and the target layer 100 and connected to the bottom of the dummy sidewall 130; an etching buffer layer 110, located between the core layer 120 and the target layer 100, between the sidewall structure layer 200 and the target layer 100, and between the sidewall film 125 and the target layer 100.

[0124] The spacer film 125 is retained in the semiconductor structure because during the formation of the semiconductor structure, in the step of forming the filling layer 140, the spacer film 125 located on the top surface of the core layer 120 is removed. Therefore, the spacer film 125 located on the target layer 100 is covered by the filling layer 140 and thus retained in the semiconductor structure.

[0125] In this embodiment, the spacer film 125 and the dummy spacer 130 are an integrated structure, and the material of the spacer film 125 is the same as that of the dummy spacer 130 .

[0126] The sidewall film 125 is located on the etching buffer layer 110, so that before the subsequent patterning of the target layer 100, the mask sidewall 150 can be used as a mask to etch the sidewall film 125, the etching buffer layer 110 and the pseudo sidewall 130; after removing the filling layer 140 and the core layer 120, one side of the mask sidewall 150 exposes the sidewall film 120, and the other side exposes the substrate surface. The etching buffer layer 110 is used to reduce the effect of the film height difference on both sides of the mask sidewall 150 on the etching sidewall film 125 and the pseudo sidewall 130, so as to avoid the problem of inconsistent etching depth, thereby preventing the sidewall film 125 and the pseudo sidewall 130 from being etched. The film layer below the layer 110 is damaged, which correspondingly improves the process effect of the subsequent graphic target layer 100. Moreover, the pattern of the mask side wall 150 can be transferred to the pseudo side wall 130, the side wall film 125 and the etching buffer layer 110. When there is a bottom defect at the bottom of the pseudo side wall 130 or the side wall verticality is low, it is beneficial to etch away the bottom defect of the pseudo side wall 130 to prevent the graphic defect of the pseudo side wall 130 from causing adverse effects on the graphic target layer 100, so that the side walls of the etched pseudo side wall 130, the side wall film 125 and the etching buffer layer 110 have higher verticality, thereby improving the accuracy of the graphic transfer.

[0127] In this embodiment, the etching selectivity ratio between the etching buffer layer 110 and the dummy side wall 130 is 1:2 to 2:1, and the etching properties of the etching buffer layer 110 and the dummy side wall 130 are similar, thereby ensuring that the side wall film 125, the dummy side wall 130 and the etching buffer layer 110 can be etched in the same step later using the mask side wall 130 as a mask, which is beneficial to reducing the difficulty of etching the side wall film 125, the dummy side wall 130 and the etching buffer layer 110 using the mask side wall 150 as a mask, and correspondingly improving the verticality of the side wall at the bottom of the dummy side wall 130.

[0128] As an example, the etching selectivity ratio between the etching buffer layer 110 and the dummy sidewall 130 is 1:1.1. In this embodiment, the etching buffer layer 110 is made of a material having etching properties close to those of the dummy sidewall 130, and the material of the etching buffer layer 110 also has etching selectivity with the material of the core layer 120 or the filling layer 140. The material of the etching buffer layer 110 includes silicon oxide, silicon, silicon carbide, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride. Specifically, the material of the etching buffer layer 110 and the dummy sidewall 130 is the same, and the material of the etching buffer layer 110 is silicon oxide.

[0129] In this embodiment, along a direction perpendicular to the substrate surface, the thickness of the spacer film 125 is a reference thickness, and the thickness of the etching buffer layer 110 is 3 to 8 times the reference thickness.

[0130] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0131] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate including a target layer, wherein the substrate includes a target area for forming a target pattern and a cutting area corresponding to a cutting position; forming a discrete core layer on the substrate; forming dummy sidewalls on the sidewalls of the core layer; forming a filling layer on the target layer exposed by the dummy sidewalls and the core layer; Etching a dummy sidewall in the target area to form a trench between the filling layer and the core layer; forming a mask sidewall in the trench, wherein an etching selectivity ratio exists between the dummy sidewall and the mask sidewall; removing the core layer and the filling layer; Using the mask sidewall as a mask, removing the dummy sidewall in the cutting area; The target layer is patterned using the mask sidewall as a mask to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of etching the dummy sidewalls located in the target area includes: forming a protection layer on the core layer and the filling layer to cover the top surface of the dummy sidewalls in the cutting area, wherein the protection layer exposes the dummy sidewalls located in the target area; Using the protective layer as a mask, the dummy sidewalls of the target area are etched; and the protective layer is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the protection layer includes silicon oxide, silicon nitride or titanium nitride.

4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of etching the dummy sidewall spacer located in the target area, the dummy sidewall spacer located in the target area is removed at the entire height or a portion of the height.

5. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the dummy sidewall spacer located in the target area includes one or both of wet etching and dry etching.

6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask sidewall spacer is different from the material of any one of the dummy sidewall spacer, the filling layer and the core layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The etching selectivity ratio between the dummy sidewall spacer and the mask sidewall spacer is at least 10:

1.

8. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the mask sidewall includes: filling the trench with a mask sidewall material, wherein the mask sidewall material also covers the filling layer, the core layer, and the top surface of the dummy sidewall of the cutting area; The mask sidewall material above the top surfaces of the filling layer and the core layer is removed to form the mask sidewall.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process of forming the mask spacer material includes an atomic layer deposition process.

10. The method for forming a semiconductor structure according to claim 8, wherein: An etching process is adopted to remove the mask sidewall material above the top surface of the filling layer and the core layer; the etching process includes a dry etching process.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the core layer and the filling layer includes one or both of dry etching and wet etching.

12. The method for forming a semiconductor structure according to claim 1, wherein: An anisotropic etching process is adopted, with the mask sidewall as a mask, to remove the dummy sidewall located in the cutting area; the anisotropic etching process includes an anisotropic dry etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the dummy sidewall spacer includes: forming a sidewall spacer film that conformally covers the core layer and the target layer, wherein the sidewall spacer film on the sidewall of the core layer serves as the dummy sidewall spacer; The step of forming the filling layer includes: forming a filling material layer covering the spacer film; flattening the filling material layer with the spacer film located on the top surface of the core layer as a stop position; after flattening the filling material layer, removing the filling material layer above the top surface of the core layer to form the filling layer; The step of removing the filling material layer higher than the top surface of the core layer further includes removing the spacer film located on the top surface of the core layer to expose the dummy spacer and the top surface of the core layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the dummy sidewall spacer includes: forming a sidewall spacer film that conformally covers the core layer and the target layer, wherein the sidewall spacer film on the sidewall of the core layer serves as the dummy sidewall spacer; The method for forming a semiconductor structure further includes: after forming the dummy sidewall spacer and before forming the filling layer, removing the sidewall spacer film located on the top surface of the core layer and the target layer.

15. A semiconductor structure, characterized in that include: a substrate comprising a target layer, the substrate comprising a target area for forming a target pattern and a cutting area corresponding to a cutting position; A core layer, separated from the target layer; a sidewall structure layer located on the sidewall of the core layer, the sidewall structure layer comprising a dummy sidewall located in the cutting area and a mask sidewall located in the target area, the mask sidewall being used as a mask for patterning the target layer, and an etching selectivity ratio being established between the dummy sidewall and the mask sidewall; The filling layer is located on the target layer exposed by the core layer and the sidewall structure layer.

16. The semiconductor structure according to claim 15, wherein: The material of the mask sidewall spacer is different from the material of any one of the dummy sidewall spacer, the filling layer and the core layer.

17. The semiconductor structure according to claim 15, wherein: The material of the mask sidewalls includes one or more of silicon nitride, silicon oxide, titanium nitride, titanium oxide and titanium.

18. The semiconductor structure according to claim 15, wherein: The material of the filling layer is the same as that of the core layer.

19. The semiconductor structure according to claim 15, wherein: The dummy sidewall spacer is also located at the bottom of the mask sidewall spacer in the target area. The sidewall structure layer located in the target area includes the dummy sidewall spacer located in the target area and the mask sidewall spacer located on the dummy sidewall spacer.

20. The semiconductor structure according to claim 19, wherein The etching selectivity ratio between the dummy sidewall spacer and the mask sidewall spacer is at least 10:1.

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