Semiconductor structure and method of manufacturing the same

By fabricating fully enclosed gate structures and bit lines on superlattice structures, the problems of high process difficulty and low yield of fully enclosed gate structures have been solved, the process steps have been simplified, the product yield has been improved, and the development of three-dimensional DRAM structures has been facilitated.

CN114121820BActive Publication Date: 2026-07-24CHANGXIN MEMORY TECH INC +1
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2021-11-19
Publication Date
2026-07-24

Smart Images

  • Figure CN114121820B_ABST
    Figure CN114121820B_ABST
Patent Text Reader

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate; forming a laminated structure on the surface of the substrate, wherein the laminated structure comprises first semiconductor material layers and first sacrificial layers which are alternately stacked from bottom to top; patterning and etching the laminated structure to remove part of the first sacrificial layers and form horizontal strip structures; forming a full-surrounding gate structure which covers part of the surface of the horizontal strip structures; and forming bit lines which are formed in the same horizontal plane as the horizontal strip structures, are disconnected from the horizontal strip structures, and are connected to the disconnected parts of the horizontal strip structures. The preparation method of the semiconductor structure removes the first sacrificial layers in the laminated structure after patterning the laminated structure to obtain the horizontal strip structures which are arranged in parallel in suspension; and then the full-surrounding gate structure and the bit lines are prepared on the basis of the horizontal strip structures, so that the process steps are simplified, the process difficulty is reduced under the condition of continuous size miniaturization, and the product yield is improved.
Need to check novelty before this filing date? Find Prior Art