Method of forming dynamic random access memory

Abstract

A method for forming a dynamic random access memory includes: providing a substrate, the substrate having a first surface and a second surface, the substrate including a plurality of active regions separated from each other and parallel to a first direction, and the plurality of active regions arranged along a second direction, each of the active regions including a plurality of channel regions and word line regions between adjacent channel regions; forming a word line gate structure in the word line regions; forming a first isolation trench in the channel regions; forming a regulating structure on an inner wall surface of the first isolation trench, the regulating structure including a first region and a second region on the first region, a thickness of the second region being greater than a thickness of the first region; forming a cover layer to close a top of the first isolation trench, and forming a cavity in the first isolation trench. By reducing the size of the opening of the first isolation trench, the process difficulty of sealing the first isolation trench to form the cavity is effectively reduced. In addition, the difference in sealing time is reduced, the uniformity between the cavities formed is improved, and the performance of the device structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a dynamic random access memory. Background Technology

[0002] With the rapid development of technology, semiconductor memories are widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory, and it is the most commonly used solution for applications that store large amounts of data.

[0003] Typically, dynamic random access memory (DRAM) consists of multiple memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and each memory cell is electrically connected to each other through word lines and bit lines.

[0004] However, existing dynamic random access memory still has many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a dynamic random access memory, which can effectively reduce the difficulty of the process and improve the performance of the device.

[0006] To address the aforementioned problems, the present invention provides a method for forming a dynamic random access memory (DRAM), comprising: providing a substrate having a first surface and a second surface opposite to each other; the substrate including a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions arranged along a second direction, wherein the first direction is different from the second direction; each active region including a plurality of channel regions and word line regions located between adjacent channel regions; the word line regions within adjacent active regions being arranged along the second direction; forming word line gate structures within the word line regions, each word line gate structure being parallel to the second direction and arranged along the first direction, and each word line gate structure penetrating the plurality of active regions; etching a portion of the channel regions from the first surface to the second surface, forming a first isolation trench within the channel regions; forming an adjustment structure on the inner wall surface of the first isolation trench, the adjustment structure including a first region and a second region, wherein the distance from the second region to the first surface is less than the distance from the first region to the first surface, and the thickness of the second region is greater than the thickness of the first region; forming a capping layer to seal the top of the first isolation trench, and forming a cavity within the first isolation trench.

[0007] Optionally, the adjustment structure includes: a protective layer located on the sidewalls of the first region and the second region, and an adjustment layer located on the sidewall of the second region.

[0008] Optionally, the method of forming an adjustment structure on the inner wall surface of the first isolation trench includes: forming a protective layer on the sidewall and bottom surface of the first isolation trench; forming a sacrificial layer in the first isolation trench, the sacrificial layer being located on the protective layer and the top surface of the sacrificial layer being lower than the first surface; after forming the sacrificial layer, forming an adjustment layer on the exposed sidewall of the first isolation trench, the adjustment structure being composed of the protective layer and the adjustment layer; and after forming the adjustment structure, removing the sacrificial layer.

[0009] Optionally, the material of the protective layer includes silicon oxide; the material of the conditioning layer includes silicon oxide.

[0010] Optionally, the material of the sacrificial layer is different from the materials of the protective layer and the conditioning layer; the material of the sacrificial layer includes carbon; the process for removing the sacrificial layer includes an ashing process.

[0011] Optionally, the method of forming a word line grid structure in the word line area includes: forming a word line grid trench in each word line area, the word line grid trench extending from the first surface to the second surface, and the word line grid trench penetrating the active area along the second direction; and forming the word line grid structure in each word line grid trench.

[0012] Optionally, the process of forming the word line grid structure further includes: forming an isolation structure within the word line grid groove.

[0013] Optionally, the method of forming the word line gate structure and the isolation structure in each of the word line gate trenches includes: forming an initial word line gate structure in each of the word line gate trenches; etching a portion of the initial word line gate structure from the first surface to the second surface; forming a plurality of second isolation trenches parallel to the second direction in the substrate; the second isolation trenches penetrating the initial word line gate structure from the first surface to the second surface; and forming the initial word line gate structure into two mutually independent word line gate structures; and forming the isolation structure in the second isolation trenches.

[0014] Optionally, the spacing between the isolation structure and the second surface is less than or equal to the spacing between the word line grid structure and the second surface.

[0015] Optionally, before forming the word line grid trench, the method further includes forming an isolation layer between adjacent active regions.

[0016] Optionally, the method for forming the isolation layer includes: forming an isolation material layer between adjacent active regions and on the first surface; and planarizing the isolation material layer until the first surface is exposed, thereby forming the isolation layer.

[0017] Optionally, after forming the word grid trench and before forming the initial word grid structure, the method further includes: forming a planarization layer at the bottom of the word grid trench; the word grid structure is located on the planarization layer.

[0018] Optionally, the method for forming a flattening layer at the bottom of the character grid groove includes: forming a flattening material layer at the bottom of the character grid groove using a spin coating process, wherein the flattening material layer is a fluid; and curing the flattening material layer to form the flattening layer.

[0019] Optionally, the material of the planarization layer includes an insulating dielectric material; the insulating dielectric material includes silicon oxide or silicon nitride.

[0020] Optionally, after forming a cavity in the first isolation trench, the method further includes: forming a first source / drain doped region in the first surface of each channel region; thinning the substrate from the second surface in the direction of the first surface; and after the thinning process, forming a second source / drain doped region in the second surface of each channel region.

[0021] Optionally, after forming a cavity in the first isolation trench, the method further includes: forming a plurality of capacitor structures on the first surface, each capacitor structure being electrically connected to a first source / drain doped region; and forming a plurality of bit line layers parallel to the first direction on the second surface, each bit line layer being electrically connected to a plurality of second source / drain doped regions in an active region.

[0022] Optionally, after forming a cavity in the first isolation trench, the method further includes: forming a plurality of bit line layers parallel to the first direction on the first surface, each bit line layer being electrically connected to a plurality of first source / drain doped regions in an active region; and forming a plurality of capacitor structures on the second surface, each capacitor structure being electrically connected to a second source / drain doped region.

[0023] Optionally, the depth of the second source / drain doped region is greater than or equal to the spacing between the word line gate structure and the second surface of the substrate.

[0024] Optionally, before forming the plurality of capacitor structures, the method further includes: forming a first conductive plug on each of the first source / drain doped regions, wherein each capacitor structure is electrically connected to one of the first conductive plugs.

[0025] Optionally, before forming the plurality of capacitor structures, the method further includes: forming a first conductive plug on each of the second source / drain doped regions, wherein each capacitor structure is electrically connected to one of the first conductive plugs.

[0026] Optionally, before forming the plurality of bit line layers, the method further includes: forming a plurality of second conductive plugs, wherein the plurality of second conductive plugs electrically connect each bit line layer to a plurality of second source / drain doped regions within a corresponding active region.

[0027] Optionally, before forming the plurality of bit line layers, the method further includes: forming a plurality of second conductive plugs, wherein the plurality of second conductive plugs electrically connect each bit line layer to a plurality of first source / drain doped regions within a corresponding active region.

[0028] Optionally, the word grid structure includes: a word grid dielectric layer located on the sidewalls and bottom surface of the word grid trench, and a word grid layer located on the word grid dielectric layer.

[0029] Optionally, the word line grid layer includes a single-layer structure or a composite structure.

[0030] Optionally, when the word line gate layer is a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.

[0031] Optionally, when the word line gate layer is a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, wherein the first gate layer and the second gate layer are made of different materials.

[0032] Optionally, the material of the first gate layer includes metal or polysilicon; the material of the second gate layer includes polysilicon or metal.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] In the method for forming the technical solution of the present invention, an adjustment structure is formed on the inner wall surface of the first isolation trench. The adjustment structure includes a first region and a second region. The distance from the second region to the first surface is less than the distance from the first region to the first surface, and the thickness of the second region is greater than the thickness of the first region. By reducing the opening size of the first isolation trench, the process difficulty of sealing the first isolation trench to form a cavity is effectively reduced. Furthermore, the variability in sealing time is reduced, improving the uniformity among the formed cavities, thereby enhancing the performance of the device structure.

[0035] Furthermore, after forming the word line gate trench and before forming the initial word line gate structure, the method further includes: forming a planarization layer at the bottom of the word line gate trench; the word line gate structure is located on the planarization layer. By forming a planarization layer at the bottom of the word line gate trench, the controllability of subsequent process steps, as well as the stability and reliability of the final device structure, can be effectively improved. Attached Figure Description

[0036] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a dynamic random access memory.

[0037] Figures 3 to 21 This is a schematic diagram of the structure of each step in a method for forming a dynamic random access memory according to an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, existing dynamic random access memories still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0039] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a dynamic random access memory.

[0040] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 having a first surface 101 and a second surface 102 opposite to each other. The substrate 100 includes a plurality of mutually discrete active regions 113 parallel to a first direction, and the plurality of active regions 113 are arranged along a second direction, the first direction being perpendicular to the second direction. Each active region 113 includes a plurality of word line regions 103 and a plurality of channel regions 104, and the plurality of word line regions 103 and the plurality of channel regions 104 in each active region 113 are spaced apart along the first direction. A word line gate trench (not shown) is formed in each word line region 103, the word line gate trench extending from the first surface 101 to the second surface 102. The second surface 102 extends, and the word line gate trench penetrates the active region along the second direction; an initial word line gate structure (not shown) is formed in each word line gate trench; a portion of the initial word line gate structure is etched from the first surface 101 to the second surface 102, and a plurality of first isolation trenches (not shown) parallel to the second direction are formed in the substrate 100. The first isolation trenches penetrate the initial word line gate structure from the first surface 101 to the second surface 102, and cause the initial word line gate structure to form two mutually independent word line gate structures 105; a first isolation structure 106 is formed in the first isolation trench.

[0041] Please refer to Figure 2A portion of the channel region 103 is etched from the first surface 101 toward the second surface 102 to form a plurality of second isolation trenches (not shown) parallel to the second direction within the substrate 100; a capping layer 107 is formed to seal the top of the second isolation trenches to form a cavity 112; a first source / drain doped region 108 is formed within the first surface 101 of each channel region 103; a plurality of capacitor structures 109 are formed on the first surface 101, each capacitor structure 109 being electrically connected to one of the first source / drain doped regions 108; the substrate 100 is thinned from the second surface 102 toward the first surface 101; a second source / drain doped region 110 is formed within the second surface 102 of each channel region 103; a plurality of bit line layers 111 parallel to the first direction are formed on the second surface 102, each bit line layer 111 being electrically connected to a plurality of the second source / drain doped regions 110 in one of the active regions 113.

[0042] In this embodiment, a cavity 112 is formed by sealing the top of the second isolation trench with a cover layer 107, which provides better isolation. Furthermore, the dielectric constant within the cavity 112 is lower than that of conventional isolation materials. Therefore, forming the cavity 112 effectively reduces the parasitic capacitance formed between adjacent word line gate structures 105.

[0043] Existing technology directly deposits the dielectric material of the capping layer to seal the opening of the second isolation trench. However, the large opening of the second isolation trench increases the difficulty of the sealing process. Furthermore, the varying sealing times for each of the second isolation trenches affect the amount of material entering the trench, thus impacting the uniformity of the formed cavity 112 and consequently affecting the performance of the device structure.

[0044] Based on this, the present invention provides a method for forming a dynamic random access memory (DRAM). By reducing the size of the opening of the first isolation trench, the process difficulty of sealing the first isolation trench to form a cavity is effectively reduced. Furthermore, the variability in sealing time is reduced, improving the uniformity among the formed cavities, thereby enhancing the performance of the device structure.

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figures 3 to 21 This is a schematic diagram of the structure of each step in a method for forming a dynamic random access memory according to an embodiment of the present invention.

[0047] Please refer to Figures 3 to 5 , Figure 4 yes Figure 3 Schematic diagram of the cross section along line AA. Figure 5 yes Figure 3 A schematic cross-sectional view along the BB line shows a substrate 200 having a first surface 201 and a second surface 202. The substrate 200 includes a plurality of mutually discrete active regions 203 parallel to a first direction X, and the plurality of active regions 203 are arranged along a second direction Y. The first direction X is different from the second direction Y. Each active region 203 includes a plurality of channel regions 205 and word line regions 204 located between adjacent channel regions 205. The word line regions 204 in adjacent active regions 203 are arranged along the second direction Y.

[0048] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0049] In this embodiment, the channel region 205 and the word line region 204 are used to form transistor devices in the future.

[0050] Please refer to Figure 6 , Figure 6 and Figure 4 The view directions are consistent, and an isolation layer 206 is formed between adjacent active regions 203.

[0051] In this embodiment, the method for forming the isolation layer 206 includes: forming an initial isolation layer (not shown) between adjacent active regions 203 and on the first surface 201; and planarizing the initial isolation layer until the first surface 201 is exposed, thereby forming the isolation layer 206.

[0052] In this embodiment, the material of the isolation layer 206 is silicon oxide.

[0053] In this embodiment, after forming the isolation layer 206, the method further includes: forming a word line grid structure within the word line region 204, wherein each word line grid structure is parallel to the second direction Y and arranged along the first direction X, and each word line grid structure penetrates through a plurality of the active regions 203. For the specific formation process of the word line grid structure, please refer to [reference needed]. Figures 7 to 10 .

[0054] Please refer to Figure 7 A word line grid groove 207 is formed in each word line area 204. The word line grid groove 207 extends from the first surface 201 to the second surface 202, and the word line grid groove 207 penetrates the active area 203 along the second direction Y.

[0055] In this embodiment, the word line grid groove 207 provides space for the subsequent formation of a word line grid structure within the word line grid groove 207.

[0056] In this embodiment, the method for forming the word line gate trench 207 includes: forming a first patterned layer (not shown) on the first surface 201 of the substrate 200, wherein the first patterned layer exposes the word line region 204; using the first patterned layer as a mask, etching is performed from the first surface 201 toward the second surface 202 to form the word line gate trench 207.

[0057] In this embodiment, the depth of the word line gate trench 207 is less than the depth of the isolation layer 206. In other embodiments, the depth of the word line gate trench may be equal to the depth of the isolation layer.

[0058] In this embodiment, during the formation of the word line gate trench 207, the isolation layer 206 and the word line region 204 need to be etched simultaneously. Because the isolation layer 206 and the word line region 204 are made of different materials, their etching rates differ during the etching process. This can easily lead to unevenness at the bottom of the final word line gate trench 207, which in turn can affect the controllability of subsequent manufacturing processes and the stability and reliability of the final device structure.

[0059] In this embodiment, please continue to refer to Figure 7 A flat layer 208 is formed at the bottom of the character line grid groove 207.

[0060] In this embodiment, the method for forming a planarization layer 208 at the bottom of the word grid groove 207 includes: forming a planar material layer (not shown) at the bottom of the word grid groove 207 using a spin coating process, wherein the planar material layer is a fluid; and curing the planar material layer to form the planarization layer 208.

[0061] In this embodiment, the planarization layer 208 is made of an insulating dielectric material; the insulating dielectric material is silicon oxide. In other embodiments, the insulating dielectric material may also be silicon nitride.

[0062] By forming a flattening layer 208 at the bottom of the word line gate trench 207, the controllability of subsequent manufacturing processes and the stability and reliability of the final device structure can be effectively improved.

[0063] In other embodiments, when the flatness of the bottom of the word line grid trench is high, the flat layer may not need to be formed.

[0064] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 A schematic diagram of the cross-section along the CC line shows that an initial word line grid structure 209 is formed within each of the word line grid grooves 207.

[0065] In this embodiment, the initial word grid structure 209 includes: an initial word grid dielectric layer located on the sidewall and bottom surface of the word grid trench 207, and an initial word grid layer (not shown) located on the initial word grid dielectric layer.

[0066] Please continue to refer to this. Figure 9 In this embodiment, the initial word line gate structure 209 does not completely fill the word line gate trench 107. After forming the initial word line gate structure 209, the method further includes: forming a dielectric layer 210 on the first surface 201 of the substrate 200, the dielectric layer 210 filling the word line gate trench 207, and the dielectric layer 210 exposing the surface of the channel region 205.

[0067] Please refer to Figure 10 , Figure 10 and Figure 9 With the view direction consistent, a portion of the initial word line gate structure 209 is etched from the first surface 201 to the second surface 202, and a plurality of second isolation trenches 211 parallel to the second direction Y are formed in the substrate 200. The second isolation trenches 211 penetrate the initial word line gate structure 209 from the first surface 201 to the second surface 202, and cause the initial word line gate structure 209 to form two mutually independent word line gate structures 212.

[0068] In this embodiment, the word line grid structure 212 is formed by first forming an initial word line grid structure 209, and then dividing the initial word line grid structure 209 into two independent word line grid structures 212 by forming the second isolation trench 211. Since the individual word line grid structure 212 has a small graphic size and the spacing between adjacent word line grid structures 212 is also small, the corresponding exposure process is more difficult. By first forming an initial word line grid structure 209 with a larger graphic size and a larger adjacent spacing, the difficulty of the exposure process can be effectively reduced.

[0069] In this embodiment, the word grid structure 212 includes: a word grid dielectric layer located on the sidewall and bottom surface of the word grid trench 207, and a word grid layer (not shown) located on the word grid dielectric layer.

[0070] In this embodiment, the word line gate layer adopts a composite structure, which includes a first gate layer and a second gate layer (not shown) located on the first gate layer. The first gate layer and the second gate layer are made of different materials.

[0071] In this embodiment, the first gate layer is made of polysilicon, and the second gate layer is made of metal; in other embodiments, the first gate layer may also be made of metal, and the corresponding second gate layer may be made of polysilicon.

[0072] In other embodiments, the word line gate layer may also be a single-layer structure. When the word line gate layer is a single-layer structure, the material of the word line gate layer may be polycrystalline silicon or metal.

[0073] In this embodiment, the word line grid structure 212 is located on the planarization layer 208.

[0074] Please refer to Figure 11 The isolation structure 213 is formed within the second isolation trench 211.

[0075] In this embodiment, the method for forming the isolation structure 213 includes: forming an isolation material layer (not shown) in the second isolation trench 211 and on the first surface 201; and planarizing the isolation material layer until the first surface 201 is exposed to form the isolation structure 213.

[0076] In this embodiment, the isolation structure 213 ensures that the word line gate structure 212 is connected to the channel region 205 on only one side, thereby making the formed transistor a single-channel structure. A single-channel dynamic random access memory is less prone to leakage current problems during operation.

[0077] In this embodiment, the material of the isolation structure 213 is silicon oxide.

[0078] In this embodiment, the distance between the isolation structure 213 and the second surface 202 is smaller than the distance between the word line grid structure 212 and the second surface 202. The isolation structure 213 can completely separate the two word line grid structures 212 within the word line grid groove 207, effectively preventing short circuits between the two word line grid structures 212.

[0079] In other embodiments, the spacing between the isolation structure and the second surface may also be equal to the spacing between the word line grid structure and the second surface.

[0080] Please refer to Figure 12 A portion of the channel region 205 is etched from the first surface 201 toward the second surface 202, forming a first isolation trench 214 within the channel region 205.

[0081] In this embodiment, the method for forming the first isolation trench 214 includes: forming a second patterned layer (not shown) on the first surface 201 of the substrate 200, wherein the second patterned layer exposes a portion of the top surface of the channel region 205; using the second patterned layer as a mask, etching is performed from the first surface 201 to the second surface 202 using an etching process to form the first isolation trench 214.

[0082] In this embodiment, after forming the first isolation trench 214, the method further includes: forming an adjustment structure on the inner wall surface of the first isolation trench 214. The adjustment structure includes a first region and a second region, wherein the distance from the second region to the first surface is less than the distance from the first region to the first surface 201, and the thickness of the second region is greater than the thickness of the first region. For the specific formation process of the adjustment structure, please refer to [reference needed]. Figures 13 to 15 .

[0083] Please refer to Figure 13 A protective layer 215 is formed on the sidewalls and bottom surface of the first isolation trench 214.

[0084] In this embodiment, the protective layer 215 is also formed on the bottom surface of the first isolation trench 214 and on the first surface 201.

[0085] In this embodiment, the protective layer 215 is formed using atomic layer deposition.

[0086] In this embodiment, the protective layer 215 is made of silicon oxide. The protective layer 215 serves two purposes: firstly, it protects the sidewalls of the first isolation trench 214, preventing oxidation of the sidewalls during subsequent heat treatment processes, which would reduce the thickness of the trench; secondly, during subsequent thinning processes from the second surface 202 to the first surface 201, until the protective layer 215 is exposed, it prevents excessive thinning that could expose the resulting cavity.

[0087] Please refer to Figure 14 A sacrificial layer 216 is formed in the first isolation trench 214. The sacrificial layer 216 is located on the protective layer 215, and the top surface of the sacrificial layer 216 is lower than the first surface 201.

[0088] In this embodiment, the method for forming the sacrificial layer 216 includes: forming a sacrificial material layer (not shown) in the first isolation trench 214 and on the first surface 201; planarizing the sacrificial material layer until the surface of the protective layer 215 is exposed to form an initial sacrificial layer (not shown); and performing a back etching process on the initial sacrificial layer to form the sacrificial layer 216.

[0089] In this embodiment, the material of the sacrificial layer 216 is different from the material of the protective layer 215 and the subsequently formed conditioning layer.

[0090] In this embodiment, the sacrificial layer 216 is made of carbon. By choosing carbon as the material for the sacrificial layer 216, it is easier to remove it completely in the future.

[0091] Please refer to Figure 15 After the sacrificial layer 216 is formed, an adjustment layer 217 is formed on the sidewall exposed by the first isolation trench 214, and the adjustment structure is composed of the protective layer 215 and the adjustment layer 217.

[0092] In this embodiment, the method for forming the adjustment layer 217 includes: forming an initial adjustment layer (not shown) on the exposed sidewall of the first isolation trench 214 and the first surface 201; and planarizing the initial adjustment layer and the protective layer 215 until the first surface 201 is exposed, thereby forming the adjustment layer 217.

[0093] In this embodiment, the adjustment structure includes a first region I and a second region II. The distance from the second region II to the first surface 201 is less than the distance from the first region I to the first surface 201, and the thickness of the second region II is greater than the thickness of the first region I.

[0094] It should be noted that the thickness direction is along the first direction X.

[0095] In this embodiment, the adjustment layer 217 is made of silicon oxide.

[0096] Please continue to refer to this. Figure 15 In this embodiment, after forming the adjustment structure, the method further includes removing the sacrificial layer 216.

[0097] In this embodiment, the process of removing the sacrificial layer 216 is an ashing process.

[0098] Please refer to Figure 16 A covering layer 218 is formed to seal the top of the first isolation trench 214, and a cavity 219 is formed inside the first isolation trench 214.

[0099] In this embodiment, an adjustment structure is formed on the inner wall surface of the first isolation trench 214. The adjustment structure includes a first region I and a second region II. The distance from the second region II to the first surface 201 is less than the distance from the first region I to the first surface 201, and the thickness of the second region II is greater than the thickness of the first region I. By reducing the opening size of the first isolation trench 214, the process difficulty of sealing the first isolation trench 214 to form a cavity is effectively reduced. Furthermore, the difference in sealing time is reduced, improving the uniformity among the formed cavities 219, thereby improving the performance of the device structure.

[0100] In this embodiment, the capping layer 218 is formed using a chemical vapor deposition process.

[0101] In this embodiment, the material of the cover layer 218 is silicon oxide.

[0102] Please refer to Figure 17 After forming a cavity 219 in the first isolation trench 214, a first source / drain doped region 220 is formed in the first surface 201 of each channel region 205.

[0103] In this embodiment, the method of forming a first source / drain doped region 220 in the first surface 201 of each channel region 205 includes: using an ion implantation process to implant first ions from the first surface 201 to the second surface 202, thereby forming a first source / drain doped region 220 in the first surface 201 of each channel region 205.

[0104] In this embodiment, the first ion is an N-type ion; in other embodiments, the first ion may also be a P-type ion.

[0105] Please refer to Figure 18 A plurality of capacitor structures 221 are formed on the first surface 201, and each capacitor structure 221 is electrically connected to a first source / drain doped region 220.

[0106] In this embodiment, before forming a plurality of capacitor structures 221, the method further includes: forming a first conductive plug 222 on each of the first source / drain doped regions 220, and each capacitor structure 221 being electrically connected to a first conductive plug 222; in other embodiments, the first conductive plug may not be formed.

[0107] In this embodiment, the capacitor structure 221 includes: an upper electrode layer, a lower electrode layer, and a dielectric layer (not shown) located between the upper electrode layer and the lower electrode layer.

[0108] In other embodiments, a plurality of bit line layers parallel to the first direction may be formed on the first surface, each bit line layer being electrically connected to a plurality of first source / drain doped regions in an active region; before forming the plurality of bit line layers, the method further includes: forming a plurality of second conductive plugs, the plurality of second conductive plugs respectively electrically connecting each bit line layer to a plurality of first source / drain doped regions in a corresponding active region.

[0109] Please refer to Figure 19 The substrate 200 is thinned from the second surface 202 toward the first surface 201.

[0110] The process of thinning the substrate 200 from the second surface 202 toward the first surface 201 includes physical mechanical polishing (PMP), chemical mechanical polishing (CMP), or wet etching. In this embodiment, the process of thinning the substrate 200 from the second surface 202 toward the first surface 201 is CMP.

[0111] The thinning process continues until the surface of the insulating layer 206 is exposed.

[0112] In this embodiment, the depths of the isolation structure and the adjustment structure are equal to the depth of the isolation layer 206. Therefore, after the thinning process, the second side of the substrate 200 still exposes the surfaces of the isolation structure 213 and the adjustment structure.

[0113] In other embodiments, the depth of the isolation structure and the adjustment structure may be less than the depth of the isolation layer, and after the thinning process, the second side of the substrate does not expose the surfaces of the isolation structure and the adjustment structure.

[0114] Please refer to Figure 20 After the thinning process, a second source / drain doped region 223 is formed in the second surface 202 of each channel region 205.

[0115] In this embodiment, the method for forming a second source / drain doped region 223 in the second surface 202 of each channel region 205 includes: using an ion implantation process to implant second ions from the second surface 202 to the first surface 201, thereby forming a second source / drain doped region 223 in the second surface 202 of each channel region 205.

[0116] The second ion has the same electrical type as the first ion.

[0117] In this embodiment, the second ion is an N-type ion; in other embodiments, when the first ion is a P-type ion, the second ion may also be a P-type ion.

[0118] In this embodiment, the depth of the second source / drain doped region 223 is greater than the distance between the word line gate structure 212 and the second surface 202 of the substrate 200; in other embodiments, the depth of the second source / drain doped region 223 may also be equal to the distance between the word line gate structure and the second surface of the substrate.

[0119] From this point on, a number of transistors are formed within the substrate 200.

[0120] Please refer to Figure 21 A plurality of bit line layers 224 parallel to the first direction X are formed on the second surface 202, and each bit line layer 224 is electrically connected to a plurality of second source / drain doped regions 223 in an active region 203.

[0121] In this embodiment, by arranging the capacitor structure 221 and the bit line layer 224 on the first surface 201 and the second surface 202 of the substrate 200 respectively, the space available for the capacitor structure 221 and the bit line layer 224 during arrangement can be increased, thereby effectively reducing the difficulty of circuit wiring and manufacturing processes. It can also effectively reduce the area occupied by a single memory structure, thereby increasing the memory's storage density. Furthermore, the formation of the capacitor structure 221 and the bit line layer 224 can be performed separately on the first surface 201 and the second surface 202 of the substrate 200, which can effectively improve process efficiency.

[0122] Furthermore, from the perspective of exposure process, since the capacitor structure 221 has a hole-like structure and the bit line layer 224 has a line-like structure, the hole-like structure is more difficult to expose, while the line-like structure is relatively easier to expose. Moreover, the exposure requirements are higher when processing from the second surface 202. Therefore, arranging the more difficult-to-expose capacitor structure 221 on the first surface 201 of the substrate 200 and arranging the less difficult-to-expose bit line layer 224 on the second surface 202 of the substrate 200 can effectively reduce the difficulty of the exposure process.

[0123] From the perspective of signal extraction, the upper electrode plate of the capacitor structure 221 and the bit line layer 224 need to be extracted. Since the upper electrode plates of each capacitor structure 221 are interconnected within the same dynamic random access memory (DRAM), forming a large conductive area, the extraction of the capacitor structure 221 is relatively easy. The bit line layer 224 has a smaller linewidth, making its extraction more difficult. Because signal extraction during the formation of the DRAM is performed from the second surface 202 of the substrate 200, arranging the capacitor structure 221 (which has easier lead-in) on the first surface 201 of the substrate 200 and arranging the bit line layer 224 (which has more difficult lead-in) on the second surface 202 of the substrate 200 effectively reduces the process difficulty of signal extraction.

[0124] In this embodiment, a two-dimensional matrix is ​​formed using one capacitor structure 221 and one transistor as a unit. The basic operation mechanism is divided into read and write. During read, the bit line layer 224 is first charged to half of the operating voltage, and then the transistor is turned on, allowing the bit line layer 224 and the capacitor structure 221 to share charge. If the internal stored value is 1, the voltage of the bit line layer 224 is raised to above half of the operating voltage by charge sharing; conversely, if the internal stored value is 0, the voltage of the bit line layer 224 is pulled down to below half of the operating voltage. After obtaining the voltage of the bit line layer 224, it is then amplified to determine whether the internal value is 0 or 1. During write, the transistor is turned on. To write 1, the voltage of the bit line layer 224 is raised to the operating voltage so that the capacitor structure 221 stores the operating voltage; to write 0, the bit line layer 224 is lowered to 0 volts so that the capacitor structure 221 has no charge.

[0125] In this embodiment, before forming the plurality of bit line layers 224, the method further includes forming a plurality of second conductive plugs 225, wherein the plurality of second conductive plugs 225 electrically connect each bit line layer 224 to a plurality of second source / drain doped regions 223 in a corresponding active region 203; in other embodiments, the second conductive plugs may not be formed.

[0126] The bit line layer 224 is made of metal, including tungsten, aluminum, copper, etc. In this embodiment, the bit line layer 224 is made of tungsten.

[0127] In this embodiment, the method for forming the bit line layer 224 includes: forming a bit line material layer (not shown) on the second surface 202; forming a third patterning layer (not shown) on the bit line material layer, wherein the third patterning layer exposes a portion of the bit line material layer; and etching the bit line material layer from the second surface 202 to the first surface 201 using the third patterning layer as a mask to form a plurality of bit line layers 224.

[0128] The process for forming the bit line material layer includes: metal electroplating, selective metal growth, or deposition; the deposition process includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the bit line material layer is formed using atomic layer deposition.

[0129] In other embodiments, a plurality of capacitor structures may be formed on the second surface, each capacitor structure being electrically connected to a second source / drain doped region; before forming the plurality of capacitor structures, the method further includes: forming a first conductive plug on each second source / drain doped region, each capacitor structure being electrically connected to a first conductive plug.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a dynamic random access memory, characterized in that, include: A substrate is provided having a first surface and a second surface opposite to each other. The substrate includes a plurality of mutually discrete active regions parallel to a first direction, and the plurality of active regions are arranged along a second direction, the first direction being different from the second direction. Each active region includes a plurality of channel regions and word line regions located between adjacent channel regions, and the word line regions within adjacent active regions are arranged along the second direction. A word line grid structure is formed within the word line area, each word line grid structure being parallel to the second direction and arranged along the first direction, and each word line grid structure penetrating through a plurality of active areas; The trench area is etched from the first surface in the direction of the second surface to form a first isolation trench in the trench area; An adjustment structure is formed on the inner wall surface of the first isolation trench. The adjustment structure includes a first region and a second region. The distance from the second region to the first surface is less than the distance from the first region to the first surface, and the thickness of the second region is greater than the thickness of the first region. A covering layer is formed to seal the top of the first isolation trench, creating a cavity within the first isolation trench; wherein, The adjustment structure includes: a protective layer located on the sidewalls of the first region and the second region, and an adjustment layer located on the sidewall of the second region; A method for forming an adjustment structure on the inner wall surface of the first isolation trench includes: forming a protective layer on the sidewall and bottom surface of the first isolation trench; forming a sacrificial layer in the first isolation trench, the sacrificial layer being located on the protective layer and the top surface of the sacrificial layer being lower than the first surface; after forming the sacrificial layer, forming an adjustment layer on the exposed sidewall of the first isolation trench, the adjustment structure being composed of the protective layer and the adjustment layer; and after forming the adjustment structure, removing the sacrificial layer.

2. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The protective layer is made of silicon oxide; the conditioning layer is made of silicon oxide.

3. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The material of the sacrificial layer is different from the materials of the protective layer and the conditioning layer; The material of the sacrificial layer includes carbon; the process for removing the sacrificial layer includes an ashing process.

4. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The method of forming a word line grid structure in the word line area includes: forming a word line grid trench in each word line area, the word line grid trench extending from the first surface to the second surface and penetrating the active area along the second direction; and forming the word line grid structure in each word line grid trench.

5. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The process of forming the word line grid structure also includes: forming an isolation structure within the word line grid groove.

6. The method for forming a dynamic random access memory as described in claim 5, characterized in that, The method of forming the word line gate structure and the isolation structure in each of the word line gate trenches includes: forming an initial word line gate structure in each of the word line gate trenches; etching a portion of the initial word line gate structure from the first surface to the second surface; forming a plurality of second isolation trenches parallel to the second direction in the substrate, the second isolation trenches penetrating the initial word line gate structure from the first surface to the second surface; and forming the initial word line gate structure into two mutually independent word line gate structures; and forming the isolation structure in the second isolation trenches.

7. The method for forming a dynamic random access memory as described in claim 6, characterized in that, The distance between the isolation structure and the second surface is less than or equal to the distance between the word line grid structure and the second surface.

8. The method for forming a dynamic random access memory as described in claim 4, characterized in that, Before forming the word line grid trench, the method further includes forming an isolation layer between adjacent active regions.

9. The method for forming a dynamic random access memory as described in claim 8, characterized in that, The method for forming the isolation layer includes: forming an isolation material layer between adjacent active regions and on the first surface; and planarizing the isolation material layer until the first surface is exposed, thereby forming the isolation layer.

10. The method for forming a dynamic random access memory as described in claim 6, characterized in that, After forming the word grid trench and before forming the initial word grid structure, the method further includes: forming a planarization layer at the bottom of the word grid trench; the word grid structure is located on the planarization layer.

11. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The method for forming a flat layer at the bottom of the character grid groove includes: forming a flat material layer at the bottom of the character grid groove using a spin coating process, wherein the flat material layer is a fluid; and curing the flat material layer to form the flat layer.

12. The method for forming a dynamic random access memory as described in claim 10, characterized in that, The material of the planarization layer includes an insulating dielectric material; The insulating dielectric material includes silicon oxide or silicon nitride.

13. The method for forming a dynamic random access memory as described in claim 1, characterized in that, After forming a cavity in the first isolation trench, the method further includes: forming a first source / drain doped region in the first surface of each channel region; thinning the substrate from the second surface in the direction of the first surface; and forming a second source / drain doped region in the second surface of each channel region after the thinning process.

14. The method for forming a dynamic random access memory as described in claim 13, characterized in that, After forming a cavity in the first isolation trench, the method further includes: forming a plurality of capacitor structures on the first surface, each capacitor structure being electrically connected to a first source / drain doped region; and forming a plurality of bit line layers parallel to the first direction on the second surface, each bit line layer being electrically connected to a plurality of second source / drain doped regions in an active region.

15. The method for forming a dynamic random access memory as described in claim 13, characterized in that, After forming a cavity in the first isolation trench, the method further includes: forming a plurality of bit line layers parallel to the first direction on the first surface, each bit line layer being electrically connected to a plurality of first source / drain doped regions in an active region; and forming a plurality of capacitor structures on the second surface, each capacitor structure being electrically connected to a second source / drain doped region.

16. The method for forming a dynamic random access memory as described in claim 13, characterized in that, The depth of the second source / drain doped region is greater than or equal to the spacing between the word line gate structure and the second surface of the substrate.

17. The method for forming a dynamic random access memory as described in claim 14, characterized in that, Before forming the plurality of capacitor structures, the method further includes: forming a first conductive plug on each of the first source / drain doped regions, wherein each capacitor structure is electrically connected to one of the first conductive plugs.

18. The method for forming a dynamic random access memory as described in claim 15, characterized in that, Before forming the plurality of capacitor structures, the method further includes: forming a first conductive plug on each of the second source / drain doped regions, wherein each of the capacitor structures is electrically connected to one of the first conductive plugs.

19. The method for forming a dynamic random access memory as described in claim 14, characterized in that, Before forming the plurality of bit line layers, the method further includes: forming a plurality of second conductive plugs, wherein the plurality of second conductive plugs electrically connect each bit line layer to a plurality of second source / drain doped regions within a corresponding active region.

20. The method for forming a dynamic random access memory as described in claim 15, characterized in that, Before forming the plurality of bit line layers, the method further includes: forming a plurality of second conductive plugs, wherein the plurality of second conductive plugs electrically connect each bit line layer to a plurality of first source / drain doped regions within a corresponding active region.

21. The method for forming a dynamic random access memory as described in claim 1, characterized in that, The word grid structure includes: a word grid dielectric layer located on the sidewalls and bottom surface of the word grid trench, and a word grid layer located on the word grid dielectric layer.

22. The method for forming a dynamic random access memory as described in claim 21, characterized in that, The word line grid layer includes a single-layer structure or a composite structure.

23. The method for forming a dynamic random access memory as described in claim 22, characterized in that, When the word line gate layer is a single-layer structure, the material of the word line gate layer includes: metal or polysilicon.

24. The method for forming a dynamic random access memory as described in claim 23, characterized in that, When the word line gate layer is a composite structure, the word line gate layer includes a first gate layer and a second gate layer located on the first gate layer, and the first gate layer and the second gate layer are made of different materials.

25. The method for forming a dynamic random access memory as described in claim 24, characterized in that, The material of the first gate layer includes metal or polysilicon; the material of the second gate layer includes polysilicon or metal.

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