Semiconductor module

Abstract

A semiconductor module capable of appropriately generalizing components is provided. In the semiconductor module, a semiconductor chip (10) is provided with a drain portion (D) on one of a pair of opposing surfaces and with a source portion (S) and a gate portion (G) on the other surface. A substrate (20) includes three power supply patterns (23) capable of transmitting power supply electric power and at least two signal patterns (22) capable of transmitting control signals. The three power supply patterns (23) and the two signal patterns (22) all extend in parallel with each other along a first direction (X). Of the three power supply patterns (23), two power supply patterns (23) are capable of mounting the semiconductor chip (10) and connecting with the drain portion (D) of the mounted semiconductor chip (10), and the remaining one power supply pattern (23) is capable of connecting with the source portion (S) of the semiconductor chip (10). The two signal patterns (22) are capable of connecting with the gate portion (G) of the semiconductor chip (10).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor module. BACKGROUND

[0002] In the past, as a semiconductor module, a power semiconductor module provided with a substrate and a case in which the substrate is assembled is described in Patent Literature 1. The power semiconductor module constitutes a general case of a substrate capable of assembling both a power module and an intelligent power module, for example, by providing a terminal for connecting with a substrate of an intelligent power module to the case, and realizes generalization of components.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 11-16937 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, the power semiconductor module described in the above Patent Literature 1 controls different for the power module and the intelligent power module, for example, and thus requires use of substrates different in wiring pattern, and in manufacturing the power semiconductor module, a plurality of substrates different in wiring pattern need to be prepared according to a circuit, and manufacturing efficiency can be reduced.

[0008] Therefore, the present application is completed in view of the above circumstances, and an object thereof is to provide a semiconductor module capable of appropriately generalizing components.

[0009] MEANS OF SOLVING THE PROBLEM

[0010] In order to solve the above problem and achieve the object, a semiconductor module according to the present application is characterized by including: a semiconductor chip provided with a drain portion on one surface of a pair of surfaces facing each other and a source portion and a gate portion on the other surface; and a substrate including: a base material; three power supply patterns provided on the base material and capable of transmitting power supply power; and two signal patterns provided on the base material and capable of transmitting a control signal, the substrate being capable of mounting the semiconductor chip, the three power supply patterns and the two signal patterns extending in parallel with each other along a first direction, two of the power supply patterns being capable of mounting the semiconductor chip and connecting with the drain portion of the mounted semiconductor chip, the remaining one of the power supply patterns being capable of connecting with the source portion of the mounted semiconductor chip, and the two signal patterns being capable of connecting with the gate portion of the mounted semiconductor chip.

[0011] In the semiconductor module described above, it is preferable that, of the three power supply patterns, the one power supply pattern connectable with the source portion be disposed between the two power supply patterns capable of mounting the semiconductor chip along a second direction orthogonal to the first direction, that the signal patterns be provided four in number, and that two of the signal patterns be connectable with the gate portion and the remaining two be connectable with the source portion, that the two signal patterns connectable with the gate portion be disposed in pairs across the three power supply patterns along the second direction, and that the two signal patterns connectable with the source portion be disposed in pairs across the three power supply patterns along the second direction, and that the two power supply patterns capable of mounting the semiconductor chip also serve as signal patterns for the drain portion.

[0012] In the semiconductor module described above, it is preferable that the semiconductor module further include an external connection pattern connectable with any of the three power supply patterns and connectable with an external connection object located outside the substrate, and that the external connection pattern extend along a second direction orthogonal to the first direction and be disposed in pairs across at least the three power supply patterns along the first direction.

[0013] In the semiconductor module described above, it is preferable that the semiconductor module further include a base portion on which the substrate is placed, and a housing assembled to the base portion on which the substrate is placed, the housing being configured to include a housing main body, a power supply terminal provided to the housing main body and connectable with the power supply patterns, and a signal terminal provided to the housing main body and connectable with the signal patterns.

[0014] In the semiconductor module described above, it is preferable that, of the three power supply patterns, one be a power supply connection pattern on which the semiconductor chip is mounted and with which the drain portion of the mounted semiconductor chip is connected, another be a power supply connection pattern with which the source portion of the mounted semiconductor chip is connected, and the remaining one be a power supply non-connection pattern with which none of the drain portion, the source portion, and the gate portion of the mounted semiconductor chip is connected, that the signal patterns be provided four in number, one be a signal connection pattern with which the gate portion of the mounted semiconductor chip is connected, another be a signal connection pattern with which the source portion of the mounted semiconductor chip is connected, and the remaining two be signal non-connection patterns with which none of the drain portion, the source portion, and the gate portion of the mounted semiconductor chip is connected, and that the mounted semiconductor chip constitute a unidirectional circuit that turns on or turns off a current flowing in one direction among the power supply patterns.

[0015] In the semiconductor module described above, preferably, of the three power supply patterns, two of the power supply patterns mount the semiconductor chip and are connected to the drain portion of the mounted semiconductor chip, respectively, and the remaining one of the power supply patterns is connected to the source portion of the mounted semiconductor chip, the signal patterns are provided four, two of the signal patterns are connected to the gate portion of any one of the mounted semiconductor chips, and the remaining two of the signal patterns are connected to the source portion of any one of the mounted semiconductor chips, and the mounted semiconductor chips constitute a bidirectional circuit that makes a current flowing bidirectionally in the power supply pattern pass or cut off.

[0016] In the semiconductor module described above, preferably, the semiconductor module further has an external connection pattern that can be connected to any one of the three power supply patterns and can be connected to an external connection object located outside the substrate, the external connection pattern extends along a second direction orthogonal to the first direction and is provided in pairs along the first direction at least through the three power supply patterns, the substrate on which the semiconductor chip is mounted is provided three, is arranged along the second direction, respectively, adjacent substrates are connected to each other via the external connection pattern, in each of the substrates, of the three power supply patterns, two of the power supply patterns mount the semiconductor chip and are connected to the drain portion of the mounted semiconductor chip, respectively, and the remaining one of the power supply patterns is connected to the source portion of the mounted semiconductor chip mounted on one of the power supply patterns, one of the two power supply patterns connected to the drain portion is connected to the source portion of the mounted semiconductor chip mounted on the other of the power supply patterns, the signal patterns are provided four, two of the signal patterns are connected to the gate portion of any one of the mounted semiconductor chips, and the remaining two of the signal patterns are connected to the source portion of any one of the mounted semiconductor chips, and the mounted semiconductor chips constitute an inverter circuit that converts direct current into alternating current.

[0017] Effects of the Invention

[0018] In the semiconductor module described above, of the three power supply patterns, two of the power supply patterns can mount the semiconductor chip and can be connected to the drain portion of the mounted semiconductor chip, and the remaining one of the power supply patterns can be connected to the source portion of the mounted semiconductor chip, so that components (substrates) can be appropriately generalized. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is an exploded perspective view showing an example of the basic structure of the semiconductor module according to the first embodiment.

[0020] Figure 2 is a perspective view showing a structure example of a substrate according to the first embodiment.

[0021] Figure 3 is a perspective view showing a structure example of a housing according to the first embodiment.

[0022] Figure 4 is a plan view showing a structure example (first modification) of a semiconductor module according to the first embodiment.

[0023] Figure 5 is a circuit diagram showing a structure example (first modification) of a semiconductor module according to the first embodiment.

[0024] Figure 6 is a plan view showing a structure example (second modification) of a semiconductor module according to the first embodiment.

[0025] Figure 7 is a circuit diagram showing a structure example (second modification) of a semiconductor module according to the first embodiment.

[0026] Figure 8 is a plan view showing a structure example (third modification) of a semiconductor module according to the first embodiment.

[0027] Figure 9 is a circuit diagram showing a structure example (third modification) of a semiconductor module according to the first embodiment.

[0028] Figure 10 is a plan view showing a structure example of a semiconductor module according to a modification of the first embodiment.

[0029] Figure 11 is a circuit diagram showing a structure example of a semiconductor module according to a modification of the first embodiment.

[0030] Figure 12 is an exploded perspective view showing a basic structure example of a semiconductor module according to the second embodiment.

[0031] Figure 13 is a plan view showing a structure example (first modification) of a semiconductor module according to the second embodiment.

[0032] Figure 14 is a circuit diagram showing a structure example (first modification) of a semiconductor module according to the second embodiment.

[0033] Figure 15 is a plan view showing a structure example (second modification) of a semiconductor module according to the second embodiment.

[0034] Figure 16 is a circuit diagram showing a structural example of a semiconductor module according to the second embodiment (second modification).

[0035] Symbol explanation

[0036] 1, 1A, 1B, 1C, 1D, 1E semiconductor module

[0037] 10, 10A, 10B, 10C, 10D semiconductor chip

[0038] 20 substrate

[0039] 21 base material

[0040] 23 power supply pattern

[0041] 231 first power supply pattern

[0042] 232 second power supply pattern

[0043] 233 third power supply pattern

[0044] 22, 221, 222, 223, 224 signal pattern

[0045] 24, 24A external connection pattern (external connection object)

[0046] 30 base portion

[0047] 40, 40A, 40B housing

[0048] 41 housing main body

[0049] 42 power supply terminal (external connection object)

[0050] 43 signal terminal

[0051] D drain portion

[0052] S source portion

[0053] G gate portion

[0054] P1 unidirectional circuit

[0055] P2 bidirectional circuit

[0056] P3 inverter circuit

[0057] X first direction

[0058] Y second direction DETAILED DESCRIPTION

[0059] Embodiments for carrying out the present application will be explained in detail with reference to the accompanying drawings. The present application is not limited to the contents described in the following embodiments. In addition, among the components described in the following, those which can be easily ascertained by those skilled in the art or substantially identical components are encompassed. Furthermore, the structures described in the following can be appropriately combined. In addition, various omissions, substitutions, or alterations of the structures can be made within a scope that does not depart from the gist of the present application.

[0060] [First Embodiment]

[0061] A semiconductor module 1 according to the embodiments will be explained with reference to the accompanying drawings. First, a basic structure of the semiconductor module 1 will be explained, and then various modifications of the semiconductor module 1 corresponding to the structure of a semiconductor chip 10 will be explained.

[0062] [Basic Structure]

[0063] Figure 1 is an exploded perspective view showing a basic structure example of the semiconductor module 1 according to the first embodiment. Figure 2 is a perspective view showing a structure example of the substrate 20 according to the first embodiment. Figure 3 is a perspective view showing a structure example of the housing 40 according to the first embodiment. In Figures 1 to 3 , a state in which the semiconductor chip 10 is not mounted on the substrate 20 is shown.

[0064] As shown in Figures 1 to 3 , the basic structure of the semiconductor module 1 includes the semiconductor chip 10, the substrate 20, the base portion 30, and the housing 40. Furthermore, the semiconductor module 1 is configured to various semiconductor circuits corresponding to the structure of the semiconductor chip 10 by mounting the semiconductor chip 10 to the basic structure (refer to Figure 4 , etc.).

[0065] Here, in the present embodiment, a direction in which a power pattern 23 and a signal pattern 22 formed on a pattern formation surface M (refer to Figure 2 ) of the substrate 20 are extended is taken as a first direction X, a direction orthogonal to the first direction X on the pattern formation surface M of the substrate 20 is taken as a second direction Y, and a direction orthogonal to the pattern formation surface M of the substrate 20 is taken as a third direction Z. The first direction X, the second direction Y, and the third direction Z are orthogonal to each other.

[0066] The semiconductor chip 10 passes or cuts off electric current. The semiconductor chip 10 is, for example, an N-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), as Figure 2As shown, the semiconductor chip 10 is configured to include a drain portion D, a source portion S, and a gate portion G. The semiconductor chip 10 is provided with the drain portion D on one surface of a pair of surfaces facing each other in the third direction Z, and is provided with the source portion S and the gate portion G on the other surface. The semiconductor chip 10 is mounted to the power pattern 23 in a state where the drain portion D abuts on the power pattern 23.

[0067] The substrate 20 configures a circuit. The substrate 20 is configured to include a base material 21, a signal pattern 22, a power pattern 23, and an external connection pattern 24.

[0068] The base material 21 is capable of mounting the semiconductor chip 10. The base material 21 is formed of an insulating member such as resin, and is configured to be a flat plate and a rectangular shape. The base material 21 is provided with three, each having the same shape. Each base material 21 has a pair of surface portions in the third direction Z, and a pattern formation surface M on which each pattern is formed is provided on one surface portion. Four signal patterns 22, three power patterns 23, and two external connection patterns 24 are formed on the pattern formation surface M. The base material 21 mounts the semiconductor chip 10 on the power pattern 23 formed in the base material 21 according to the semiconductor circuit to be implemented.

[0069] The four signal patterns 22 (221 to 224) are conductive patterns capable of transmitting control signals. The four signal patterns 22 are provided on the base material 21 and are formed in linear shapes. The four signal patterns 22 are formed in straight linear shapes and extend in parallel with each other in the first direction X. The four signal patterns 22 are each formed in the same thickness, that is, formed in the same length in the width in the second direction Y, and are formed thinner than the three power supply patterns 23. The length of each of the four signal patterns 22 (221 to 224) in the first direction X is formed in the same length, and the two signal patterns 221, 222 and the remaining two signal patterns 223, 224 are arranged in pairs with the three power supply patterns 23 interposed therebetween in the second direction Y. In other words, of the four signal patterns 22, the two signal patterns 221, 222 are arranged on one side of the three power supply patterns 23 in the second direction Y, and the remaining two signal patterns 223, 224 are arranged on the other side of the three power supply patterns 23 in the second direction Y. The positions of the respective end portions on one side in the first direction X of the four signal patterns 22 are aligned, and the positions of the respective end portions on the other side in the first direction X are also aligned. Of the four signal patterns 22, the two signal patterns 22 are capable of being connected to the gate portions G of the semiconductor chip 10, and the remaining two signal patterns 22 are capable of being connected to the source portions S of the semiconductor chip 10. Of the four signal patterns 22 (221 to 224), the two signal patterns 222, 223 capable of being connected to the gate portions G are arranged in pairs with the three power supply patterns 23 interposed therebetween in the second direction Y, and the two signal patterns 221, 224 capable of being connected to the source portions S are arranged in pairs with the three power supply patterns 23 interposed therebetween in the second direction Y. Specifically, of the four signal patterns 22 (221 to 224), the two signal patterns 222, 223 on the inner side (the side of the three power supply patterns 23) in the second direction Y are capable of being connected to the gate portions G of the semiconductor chip 10, and the two signal patterns 221, 224 on the outer side (the side opposite to the three power supply patterns 23) are capable of being connected to the source portions S of the semiconductor chip 10.

[0070] The three power supply patterns 23 (231 to 233) are conductive patterns capable of transmitting power supply electric power. The three power supply patterns 23 are provided on the base material 21 and formed in a linear shape. The three power supply patterns 23 are formed in a straight line shape and extend in parallel with each other in the first direction X. Also, the three power supply patterns 23 and the two signal patterns 22 extend in parallel with each other in the first direction X. The three power supply patterns 23 are each formed in the same thickness, that is, formed in the same length in the width of the second direction Y, and formed thicker than the four signal patterns 22. The length of each of the three power supply patterns 23 in the first direction X is formed in the same length, and in this example, formed in the same length as the length of the four signal patterns 22 in the first direction X. The three power supply patterns 23 are arranged in the second direction Y so as to be sandwiched between the two signal patterns 221, 222 and the remaining two signal patterns 223, 224. The positions of the respective end portions on one side in the first direction X of the three power supply patterns 23 are aligned, and the positions of the respective end portions on the other side in the first direction X are also aligned. Also, the positions of the respective end portions on one side in the first direction X of the three power supply patterns 23 are aligned with the positions of the respective end portions on one side in the first direction X of the four signal patterns 22, and the positions of the respective end portions on the other side in the first direction X are also aligned with the positions of the respective end portions on the other side in the first direction X of the four signal patterns 22. The three power supply patterns 23 are sequentially composed of a first power supply pattern 231, a second power supply pattern 232, and a third power supply pattern 233 in the second direction Y. The first and third power supply patterns 231, 233 are power supply connection patterns capable of mounting the semiconductor chip 10 and connecting to the drain portion D of the mounted semiconductor chip 10. The second power supply pattern 232 is a power supply connection pattern capable of connecting to the source portion S of the mounted semiconductor chip 10. Of the three power supply patterns 23, the two first and third power supply patterns 231, 233 capable of mounting the semiconductor chip 10 are arranged on both sides in the second direction Y, and the second power supply pattern 232 capable of connecting to the source portion S of the semiconductor chip 10 is arranged in the center in the second direction Y. In other words, for the three power supply patterns 23 (231 to 233), one second power supply pattern 232 capable of connecting to the source portion S is arranged between the two first and third power supply patterns 231, 233 capable of mounting the semiconductor chip 10 in the second direction Y. The two first and third power supply patterns 231, 233 capable of mounting the semiconductor chip 10 can also be used as signal patterns 22 for the drain portion D.

[0071] The two external connection patterns 24 are conductive patterns capable of transmitting power supply electric power. The two external connection patterns 24 are provided to the substrate 21 and formed in a linear shape. The two external connection patterns 24 are formed in a straight line shape and extend in parallel with each other along the second direction Y. The two external connection patterns 24 are each formed in the same thickness, that is, the width length in the first direction X is formed in the same length, and formed in the same thickness as the three power supply patterns 23 described above. The two external connection patterns 24 are each formed in the same length in the second direction Y, and the two external connection patterns 24 are provided in pairs along the first direction X with the three power supply patterns 23 interposed therebetween. Typically, the two external connection patterns 24 are provided in pairs along the first direction X with the three power supply patterns 23 and the four signal patterns 22 interposed therebetween. In other words, for the two external connection patterns 24 (241, 242), the first external connection pattern 241 is disposed on one side of the three power supply patterns 23 and the four signal patterns 22 in the first direction X, and the second external connection pattern 242 is disposed on the other side of the three power supply patterns 23 and the four signal patterns 22. The positions of the respective end portions on one side in the second direction Y of the two external connection patterns 24 are aligned, and the positions of the respective end portions on the other side in the second direction Y are also aligned. The external connection patterns 24 can be connected to any one of the three power supply patterns 23 and to an external connection object (a power supply terminal 42 described later, another external connection pattern 24) located on the outside of the substrate 20.

[0072] The base portion 30 accommodates the three substrates 20. The base portion 30 is formed of a metal member having thermal conductivity and is configured in a flat plate shape and a rectangular shape. The base portion 30 has thermal conductivity, and thus heat generated by the semiconductor chips 10 mounted on the substrates 20 can be efficiently dissipated. The base portion 30 has a pair of face portions in the third direction Z, and a substrate mounting surface N is provided to the face portion on one side, which accommodates the three substrates 20 and the case 40 (see FIG. 1). Figure 1

[0073] The case 40 is a box that accommodates the substrates 20 on which the semiconductor chips 10 are mounted. The case 40 is configured to include a case main body 41, a power supply terminal 42, a signal terminal 43, and a relay terminal 44.

[0074] The case main body 41 is formed of an insulating member such as resin and has three accommodation portions 411. The three accommodation portions 411 are formed in a rectangular shape in accordance with the outer shape of the substrate 20 and are arranged in line along the second direction Y. The three accommodation portions 411 individually accommodate the substrates 20.

[0075] ​The power terminal 42 is a terminal connected to a power supply system, and is provided to the housing main body 41. The power terminal 42 is configured to include a first terminal 421 and a second terminal 422. One of the first terminal 421 and the second terminal 422 is provided to each of the housing main body 41. The first terminal 421 is provided to one side in the first direction X of one of the housing main body 41. The second terminal 422 is provided to the other side in the first direction X of one of the housing main body 41. The first terminal 421 and the second terminal 422 are provided to each of the three housing main body 41. The first terminal 421 and the second terminal 422 are connectable to the power pattern 23. For example, the first terminal 421 is connected to a positive electrode of a power supply and the power pattern 23, and the second terminal 422 is connected to a load and the power pattern 23.

[0076] The signal terminal 43 is a terminal connected to a control system, and is provided to the housing main body 41. For example, six of the signal terminals 43 are provided to one of the housing main body 41. The six signal terminals 43 (D11, G11, S11, D12, G12, S12) are provided to each of the three housing main body 41. Of the six signal terminals 43, three of the signal terminals 43 (D11, G11, S11) are provided to one side in the second direction Y of one of the housing main body 41, and the remaining three of the signal terminals 43 (D12, G12, S12) are provided to the other side in the second direction Y of one of the housing main body 41. The six signal terminals 43 are connectable to the signal pattern 22.

[0077] The relay terminal 44 is a terminal that connects adjacent substrates 20 to each other. The relay terminal 44 is provided to the housing 40, and is arranged between the adjacent substrates 20 in the second direction Y. For example, the relay terminal 44 is arranged between the external connection pattern 24 of the central substrate 20 and the external connection pattern 24 of the substrate 20 on one side of the central substrate 20 in the second direction Y. Further, the relay terminal 44 is arranged between the external connection pattern 24 of the central substrate 20 and the external connection pattern 24 of the substrate 20 on the other side of the central substrate 20 in the second direction Y. The relay terminal 44 connects the adjacent substrates 20 to each other via the external connection pattern 24. The housing 40 configured as described above is assembled to the base portion 30 on which the substrates 20 are placed. For example, the housing 40 is bonded and fixed to the base portion 30. Also, in the semiconductor module 1, the semiconductor chip 10 and the like on the substrate 20 are resin-sealed in a state in which the substrate 20 on which the semiconductor chip 10 is mounted and the housing 40 are assembled to the base portion 30.

[0078] [First Modification]

[0079] Next, an example in which the semiconductor chip 10 is mounted to the substrate 20 to configure the unidirectional circuit P1 in the basic structure described above will be described.Figure 4 is a plan view showing a structure example (first modification) of the semiconductor module 1 according to the first embodiment. Figure 5 is a circuit diagram showing a structure example (first modification) of the semiconductor module 1 according to the first embodiment. In addition, in the circuit diagram of Figure 5 , a structure example of the semiconductor module 1 shown in Figure 4 is simplified and illustrated.

[0080] Figure 4 The semiconductor module 1 shown in , for example, is provided in a power supply system of a vehicle, and turns on or off a current flowing from a power supply of the vehicle to a load section in one direction (one way). The semiconductor module 1 has the semiconductor chip 10, the substrate 20, the base section 30, and the housing 40. The semiconductor module 1 can be disposed at various positions in the power supply system of the vehicle. For example, in a case where the semiconductor module 1 is disposed between a positive electrode side of a power supply and a load section, the first terminal 421 of the power supply terminal 42 is connected to the positive electrode side of the power supply of the vehicle, and the second terminal 422 of the power supply terminal 42 is connected to the load section. In addition, in a case where the semiconductor module 1 is disposed between a negative electrode side of a power supply and a load section, the first terminal 421 of the power supply terminal 42 is connected to the load section, and the second terminal 422 of the power supply terminal 42 is connected to the negative electrode side of the power supply of the vehicle. In addition, in the semiconductor module 1, the first terminal 421 of the power supply terminal 42 is connected to the first external connection pattern 241 via the wire Wa, and the second terminal 422 of the power supply terminal 42 is connected to the second external connection pattern 242 via the wire Wa. Furthermore, in the semiconductor module 1, the first external connection pattern 241 is connected to the first power supply pattern 231 via the wire Wa, and the second external connection pattern 242 is connected to the second power supply pattern 232 via the wire Wa.

[0081] The semiconductor chip (mounting semiconductor chip) 10 is mounted on the power supply pattern 23, and each semiconductor chip 10 is connected in parallel to the power supply pattern 23. For example, three semiconductor chips 10 are mounted on the first power supply pattern 231, respectively, and the drain section D of each semiconductor chip 10 is directly connected to the first power supply pattern 231, and the source section S of each semiconductor chip 10 is connected to the second power supply pattern 232 via the wire Wa. In other words, among the three power supply patterns 23, one first power supply pattern 231 is a power supply connection pattern on which the semiconductor chip 10 is mounted and to which the drain section D of the mounted semiconductor chip 10 is connected, and the other second power supply pattern 232 is a power supply connection pattern to which the source section S of the semiconductor chip 10 is connected via the wire Wa. Furthermore, the remaining one third power supply pattern 233 is a power supply non-connection pattern which is not connected to the drain section D, the source section S, and the gate section G of the semiconductor chip 10. That is, in the third power supply pattern 233 which is a power supply non-connection pattern, no current flows when power is supplied from the power supply to the load section.

[0082] In addition, the source portion S of each of the three semiconductor chips 10 is connected to the signal pattern 221 for the source via the wire Wb, and the gate portion G of each of the three semiconductor chips 10 is connected to the signal pattern 222 for the gate via the wire Wb. In other words, in the signal patterns 22, one signal pattern 222 is a signal connection pattern connected to the gate portion G of the semiconductor chip 10, and the other signal pattern 221 is a signal connection pattern connected to the source portion S of each of the semiconductor chips 10. Further, the remaining two signal patterns 223, 224 are signal non-connection patterns not connected to the drain portion D, the source portion S, and the gate portion G. Moreover, in the two signal patterns 221, 222 that are signal connection patterns, a control signal flows when each of the semiconductor chips 10 is controlled, and in the two signal patterns 223, 224 that are signal non-connection patterns, a control signal does not flow when each of the semiconductor chips 10 is controlled.

[0083] The signal pattern 221 for the source is connected to the signal terminal S11 (S21, S31) for the source of the case 40 via the wire Wb, and the signal pattern 222 for the gate is connected to the signal terminal G11 (G21, G31) for the gate of the case 40 via the wire Wb. The first power supply pattern 231 is connected to the signal terminal D11 (D21, D31) for the drain of the case 40 via the wire Wb. Each of the signal terminals S11 (S21, S31), D11 (D21, D31), and G11 (G21, G31) of the case 40 is connected to an external control portion (not shown). Each of the semiconductor chips 10 constitutes a unidirectional circuit P1 (see FIG. 2) that is energized or cut off according to a control signal output from the control portion. Figure 5 The signal pattern 221 for the source is connected to the signal terminal S11 (S21, S31) for the source of the case 40 via the wire Wb, and the signal pattern 222 for the gate is connected to the signal terminal G11 (G21, G31) for the gate of the case 40 via the wire Wb. The first power supply pattern 231 is connected to the signal terminal D11 (D21, D31) for the drain of the case 40 via the wire Wb. Each of the signal terminals S11 (S21, S31), D11 (D21, D31), and G11 (G21, G31) of the case 40 is connected to an external control portion (not shown). Each of the semiconductor chips 10 constitutes a unidirectional circuit P1 (see FIG. 2) that is energized or cut off according to a control signal output from the control portion.

[0084] In addition, Figure 4 In the semiconductor module 1 shown, the three substrates 20 on which the semiconductor chips 10 are mounted are housed in the case 40, and three identical unidirectional circuits P1 are constituted. Further, each of the substrates 20 has the same structure, and thus detailed description is omitted for the other substrates 20.

[0085] [Second Modification]

[0086] Next, the semiconductor module 1A related to the second modification will be described. The semiconductor module 1A is different from the semiconductor module 1 related to the first modification in that a bidirectional circuit P2 is constituted. Figure 6 is a plan view showing a structure example (second modification) of the semiconductor module 1A related to the first embodiment. Figure 7is a circuit diagram showing a structure example of the semiconductor module 1A according to the first embodiment (second modification). In addition, in the circuit diagram of Figure 7 , a structure example of the semiconductor module 1A shown in FIG. 10 is simplified and shown. Figure 6

[0087] Figure 6 The semiconductor module 1A shown in FIG. 10 is provided in a power supply system of a vehicle, for example, and turns on or off a current flowing bidirectionally between a power supply of the vehicle and a load section. The semiconductor module 1A includes the semiconductor chips 10A, 10B, the substrate 20, the base section 30, and the housing 40. In the semiconductor module 1A, the first terminal 421 of the power supply terminal 42 is connected to the power supply of the vehicle, and the second terminal 422 of the power supply terminal 42 is connected to the load section. The first terminal 421 of the power supply terminal 42 of the semiconductor module 1A is connected to the first external connection pattern 241 via the wire Wa, and the second terminal 422 of the power supply terminal 42 is connected to the second external connection pattern 242 via the wire Wa. In the semiconductor module 1A, the first external connection pattern 241 is connected to the first power supply pattern 231 via the wire Wa, and the second external connection pattern 242 is connected to the third power supply pattern 233 via the wire Wa.

[0088] The semiconductor chips 10A, 10B, which are mounted with the semiconductor chips, are mounted on the power supply patterns 23 in six, three of which are connected in parallel to the power supply patterns 23, and the remaining three of which are connected in parallel to the other power supply patterns 23. The three semiconductor chips 10A are mounted on the first power supply patterns 231, for example, respectively, and the drain sections D of the respective semiconductor chips 10A are connected directly to the first power supply patterns 231, and the source sections S of the respective semiconductor chips 10A are connected to the second power supply patterns 232 via the wires Wa. In addition, the remaining three semiconductor chips 10B are mounted on the third power supply patterns 233, respectively, and the drain sections D of the respective semiconductor chips 10B are connected directly to the third power supply patterns 233, and the source sections S of the respective semiconductor chips 10B are connected to the second power supply patterns 232 via the wires Wa. In other words, two of the three power supply patterns 23, the first and third power supply patterns 231, 233, are mounted with the semiconductor chips 10A, 10B and connected to the drain sections D of the mounted semiconductor chips 10A, 10B, respectively, and the remaining one, the second power supply pattern 232, is connected to the source sections S of the semiconductor chips 10A, 10B via the wires Wa. Also, the three power supply patterns 23 do not include a power supply non-connection pattern which is not connected to the drain sections D, the source sections S, and the gate sections G of the semiconductor chips 10A, 10B, and all of the power supply patterns 23 are power supply connection patterns which are connected to at least one of the drain sections D, the source sections S, and the gate sections G of the semiconductor chips 10A, 10B.

[0089] ​The respective source portions S of the three semiconductor chips 10A are connected to the signal pattern 221 for the source via the conductive lines Wb, and the respective gate portions G are connected to the signal pattern 222 for the gate via the conductive lines Wb. Further, the respective source portions S of the remaining three semiconductor chips 10B are connected to the signal pattern 224 for the source via the conductive lines Wb, and the respective gate portions G are connected to the signal pattern 223 for the gate via the conductive lines Wb. In other words, of the signal patterns 22, two signal patterns 222, 223 are connected to any one of the gate portions G of the semiconductor chips 10A, 10B, and the remaining two signal patterns 221, 224 are connected to any one of the source portions S of the semiconductor chips 10A, 10B. Also, the four signal patterns 22 do not include a signal non-connection pattern that is not connected to the drain portions D, the source portions S, and the gate portions G, and all of the signal patterns 22 are signal connection patterns that are connected to any one of the drain portions D, the source portions S, and the gate portions G.

[0090] The signal pattern 221 for the source is connected to the signal terminal S11 (S21, S31) for the source of the case 40 via the conductive lines Wb, and the signal pattern 222 for the gate is connected to the signal terminal G11 (G21, G31) for the gate of the case 40 via the conductive lines Wb. Further, the signal pattern 224 for the source is connected to the signal terminal S12 (S22, S32) for the source of the case 40 via the conductive lines Wb, and the signal pattern 223 for the gate is connected to the signal terminal G12 (G22, G32) for the gate of the case 40 via the conductive lines Wb.

[0091] The first power pattern 231 is connected to the signal terminal D11 (D21, D31) for the drain of the case 40 via the conductive lines Wb. Further, the third power pattern 233 is connected to the signal terminal D12 (D22, D32) for the drain of the case 40 via the conductive lines Wb. The respective signal terminals S11, S12 (S21, S22, S31, S32), D11, D12 (D21, D22, D31, D32), G11, G12 (G21, G22, G31, G32) of the case 40 are connected to an external control portion (omitted from the drawing). The respective semiconductor chips 10A, 10B constitute a bidirectional circuit P2 (refer to FIG. 6) that is energized or cut off according to a control signal output from the control portion. Figure 7 For example, the respective semiconductor chips 10A, 10B are energized or cut off according to a voltage (control signal) applied to the gate portions G by the control portion.

[0092] Further, Figure 6In the semiconductor module 1A shown, the three substrates 20 on which the semiconductor chips 10A, 10B are mounted are housed in the case 40, and constitute three identical bidirectional circuits P2. Also, each of the substrates 20 is of the same structure, so detailed description will be omitted for the other substrates 20.

[0093] [Third Modification]

[0094] Next, the semiconductor module 1B related to the third modification will be described. The semiconductor module 1B differs from the semiconductor modules 1, 1A related to the first and second modifications in that it constitutes a 3-phase inverter circuit P3. Figure 8 is a plan view showing a structure example (third modification) of the semiconductor module 1B related to the first embodiment. Figure 9 is a circuit diagram showing a structure example (third modification) of the semiconductor module 1B related to the first embodiment.

[0095] Figure 8 The semiconductor module 1B shown is provided, for example, in a power supply system of a vehicle, and converts direct-current power supplied from a power supply of the vehicle into alternating-current power. The semiconductor module 1B has a plurality of semiconductor chips 10C, 10D, three substrates 20, a base portion 30, and a case 40. In the semiconductor module 1B, the three substrates 20 on which the semiconductor chips 10C, 10D are mounted are arranged along the second direction Y. In the semiconductor module 1B, the first terminal 421 is connected to the positive (+B) of the power supply of the vehicle, the second terminal 422, the third terminal 423, and the fourth terminal 424 are connected to input terminals of a load portion, and the fifth terminal 425 is connected to the ground GND in the power supply terminals 42 of the case 40. In the semiconductor module 1B, the first terminal 421 is connected to the first power supply pattern 231, and the second terminal 422 is connected to the third power supply pattern 233. In the semiconductor module 1B, the first power supply pattern 231 is connected to the second external connection pattern 242, and the second power supply pattern 232 is connected to the first external connection pattern 241. In the semiconductor module 1B, adjacent substrates 20 are connected to each other via the external connection patterns 24. That is, in the semiconductor module 1B, the first external connection pattern 241 is connected to the first external connection pattern 241 of the adjacent substrate 20 via the relay terminal 44, and the second external connection pattern 242 is connected to the second external connection pattern 242 of the adjacent substrate 20 via the relay terminal 44.

[0096] The semiconductor chips 10C, 10D are mounted on the six power supply patterns 23 in the first substrate 20 (the substrate 20 on the side of the second direction Y), three of which are connected in parallel to the power supply patterns 23, and the remaining three are connected in parallel to the other power supply patterns 23. The three semiconductor chips 10C are mounted on the first power supply patterns 231, for example, and the drain portions D of the respective semiconductor chips 10C are connected directly to the first power supply patterns 231, and the source portions S of the respective semiconductor chips 10C are connected to the third power supply patterns 233 via the wires Wa. In addition, the remaining three semiconductor chips 10D are mounted on the third power supply patterns 233, and the drain portions D of the respective semiconductor chips 10D are connected directly to the third power supply patterns 233, and the source portions S of the respective semiconductor chips 10D are connected to the second power supply patterns 232 via the wires Wa. In other words, two of the three power supply patterns 23, the first and third power supply patterns 231, 233, on which the semiconductor chips 10C, 10D are mounted are connected to the drain portions D of the mounted semiconductor chips 10C, 10D, and the remaining one, the second power supply pattern 232, is connected to the source portions S of the semiconductor chips 10D mounted on one of the third power supply patterns 233. Furthermore, one of the two first and third power supply patterns 231, 233, on which the semiconductor chips 10C, 10D are mounted, is connected to the source portions S of the semiconductor chips 10C, 10D mounted on the other of the first and third power supply patterns 231, 233.

[0097] The respective source portions S of the three semiconductor chips 10C are connected to the source signal patterns 221 via the wires Wb, and the respective gate portions G are connected to the gate signal patterns 222 via the wires Wb. In addition, the respective source portions S of the remaining three semiconductor chips 10D are connected to the source signal patterns 224 via the wires Wb, and the respective gate portions G are connected to the gate signal patterns 223 via the wires Wb. In other words, of the signal patterns 22, two of the signal patterns 222, 223 are connected to the gate portions G of the semiconductor chips 10, and the remaining two of the signal patterns 221, 224 are connected to the source portions S of the semiconductor chips 10.

[0098] The source signal patterns 221 are connected to the source signal terminals S11 of the housing 40 via the wires Wb, and the gate signal patterns 222 are connected to the gate signal terminals G11 of the housing 40 via the wires Wb. In addition, the source signal patterns 224 are connected to the source signal terminals S12 of the housing 40 via the wires Wb, and the gate signal patterns 223 are connected to the gate signal terminals G12 of the housing 40 via the wires Wb.

[0099] The first power supply pattern 231 is connected to the signal terminal D11 for the drain of the housing 40 via a wire Wb. In addition, the third power supply pattern 233 is connected to the signal terminal D12 for the drain of the housing 40 via a wire Wb. The signal terminals S11, S12, D11, D12, G11, G12 of the housing 40 are connected to a control unit (not shown) outside.

[0100] The substrate 20 different from the first substrate 20 described above is also configured in the same manner as the substrate 20 described above. That is, in the second substrate 20 (the substrate 20 in the center in the second direction Y), six semiconductor chips 10C, 10D are mounted on the power supply pattern 23, three of which are connected in parallel to the power supply pattern 23, and the remaining three are connected in parallel to the other power supply pattern 23. The connection relationship of the semiconductor chips 10C, 10D is the same as that of the first substrate 20 described above, and thus detailed description is omitted.

[0101] The signal pattern 221 for the source is connected to the signal terminal S21 for the source of the housing 40 via a wire Wb, and the signal pattern 222 for the gate is connected to the signal terminal G21 for the gate of the housing 40 via a wire Wb. In addition, the signal pattern 224 for the source is connected to the signal terminal S22 for the source of the housing 40 via a wire Wb, and the signal pattern 223 for the gate is connected to the signal terminal G22 for the gate of the housing 40 via a wire Wb.

[0102] The first power supply pattern 231 is connected to the signal terminal D21 for the drain of the housing 40 via a wire Wb. In addition, the third power supply pattern 233 is connected to the signal terminal D22 for the drain of the housing 40 via a wire Wb. The signal terminals S21, S22, D21, D22, G21, G22 of the housing 40 are connected to a control unit (not shown) outside.

[0103] The third substrate 20 different from the first and second substrates 20 described above is also configured in the same manner as the first and second substrates 20. That is, in the third substrate 20 (the substrate 20 on the other side in the second direction Y), six semiconductor chips 10C, 10D are mounted on the power supply pattern 23, three of which are connected in parallel to the power supply pattern 23, and the remaining three are connected in parallel to the other power supply pattern 23. The connection relationship of the semiconductor chips 10C, 10D is the same as that of the first substrate 20 described above, and thus detailed description is omitted.

[0104] The signal pattern 221 for the source electrode is connected to the signal terminal S31 for the source electrode of the case 40 via the lead wire Wb, and the signal pattern 222 for the gate electrode is connected to the signal terminal G31 for the gate electrode of the case 40 via the lead wire Wb. In addition, the signal pattern 224 for the source electrode is connected to the signal terminal S32 for the source electrode of the case 40 via the lead wire Wb, and the signal pattern 223 for the gate electrode is connected to the signal terminal G32 for the gate electrode of the case 40 via the lead wire Wb.

[0105] The first power pattern 231 is connected to the signal terminal D31 for the drain electrode of the case 40 via the lead wire Wb. In addition, the third power pattern 233 is connected to the signal terminal D32 for the drain electrode of the case 40 via the lead wire Wb. The signal terminals S31, S32, D31, D32, G31, and G32 of the case 40 are connected to an external control unit (not shown). Each of the semiconductor chips 10C and 10D constitutes an inverter circuit P3 (see FIG. 6) that converts direct-current power into alternating-current power in accordance with a control signal output from the control unit. For example, each of the semiconductor chips 10C and 10D converts direct-current power into alternating-current power in accordance with a voltage (control signal) applied to the gate portion G by the control unit. Figure 9 ). For example, each of the semiconductor chips 10C and 10D converts direct-current power into alternating-current power in accordance with a voltage (control signal) applied to the gate portion G by the control unit.

[0106] As described above, the semiconductor module 1 according to the first embodiment includes the semiconductor chip 10 and the substrate 20. The semiconductor chip 10 has the drain portion D provided on one of the opposing pair of surfaces and has the source portion S and the gate portion G provided on the other surface. The substrate 20 is capable of mounting the semiconductor chip 10 and includes the base material 21, the three power patterns 23 provided on the base material 21 and capable of transmitting power, and the at least two signal patterns 22 provided on the base material 21 and capable of transmitting a control signal. The three power patterns 23 and the two signal patterns 22 extend in parallel with each other along the first direction X. Of the three power patterns 23, two of the power patterns 23 are capable of mounting the semiconductor chip 10 and capable of connecting to the drain portion D of the mounted semiconductor chip 10, and the remaining one of the power patterns 23 is capable of connecting to the source portion S of the semiconductor chip 10. The two signal patterns 22 are capable of connecting to the gate portion G of the semiconductor chip 10.

[0107] According to this structure, the semiconductor module 1 can realize various circuits using the same substrate 20 by changing the combination of the semiconductor chips 10 mounted to the power supply patterns 23. Also, the semiconductor module 1 is configured of three power supply patterns 23, so it can realize various circuits while suppressing an increase in the number of power supply patterns 23 that are not used depending on the type of circuit. That is, the semiconductor module 1 can save waste of power supply patterns 23 while ensuring versatility of the circuit. In addition, in the semiconductor module 1, the three power supply patterns 23 and the two signal patterns 22 extend in parallel with each other along the first direction X, so the connectivity with the semiconductor chips 10 can be improved. As a result, the semiconductor module 1 can appropriately generalize the substrate 20 (component). Also, the semiconductor module 1, when manufacturing the semiconductor module 1, does not need to prepare a plurality of substrates having different wiring patterns depending on the type of circuit to be realized, so it can suppress a decrease in manufacturing efficiency. In addition, the semiconductor module 1, by generalizing the substrate 20, can realize a reduction in design man-hours and a reduction in component management cost. The semiconductor module 1 can generalize the housing 40 by generalizing the substrate 20, so it can set the arrangement of the signal terminals 43 of the housing 40 to the same arrangement. Thus, the semiconductor module 1 can generalize the substrate that controls the control section of the semiconductor module 1 via the signal terminals 43.

[0108] In the above semiconductor module 1, the three power supply patterns 23 are arranged along a second direction Y orthogonal to the first direction X between the two power supply patterns 23 to which the semiconductor chips 10 can be mounted, with one power supply pattern 23 capable of being connected to the source section S. The signal patterns 22 are provided four, two of the signal patterns 22 being capable of being connected to the gate section G, and the remaining two signal patterns 22 being capable of being connected to the source section S. Also, of the four signal patterns 22, the two signal patterns 22 capable of being connected to the gate section G are arranged in pairs along the second direction Y with the three power supply patterns 23 interposed therebetween, and the two signal patterns 22 capable of being connected to the source section S are arranged in pairs along the second direction Y with the three power supply patterns 23 interposed therebetween. The two power supply patterns 23 to which the semiconductor chips 10 can be mounted can also serve as signal patterns for the drain section D.

[0109] According to this structure, the semiconductor module 1 can use the second power supply pattern 232 as a power supply connection pattern for the source of the first and third power supply patterns 231, 233. Furthermore, in the semiconductor module 1, since the second power supply pattern 232 is positioned between the first power supply pattern 231 and the third power supply pattern 233, the first and third power supply patterns 231, 233 can be connected to the second power supply pattern 232 without crossing the power supply patterns 23. Thus, the semiconductor module 1 can relatively shorten the wire Wa connecting the first and third power supply patterns 231, 233 to the second power supply pattern 232. In the semiconductor module 1, since the four signal patterns 22 are arranged outside the three power supply patterns 23, the length of the wire Wb connected to the four signal patterns 22 can be shortened compared to a case where the four signal patterns 22 are arranged inside the three power supply patterns 23. Thus, the semiconductor module 1 can reduce the inductance component of the wire Wb, and can relatively increase the frequency at which the semiconductor chip 10 is driven. In addition, the semiconductor module 1 can suppress short-circuiting of the wire Wb connected to the four signal patterns 22 and the three power supply patterns 23. Furthermore, the semiconductor module 1 can suppress reduction in the wiring space of the wire Wa connected to the three power supply patterns 23 by the wire Wb connected to the four signal patterns 22.

[0110] In the above-described semiconductor module 1, an external connection pattern 24 is further provided, which can be connected to any one of the three power supply patterns 23 and can be connected to an external connection object (a power supply terminal 42, an adjacent external connection pattern 24) positioned outside the substrate 20, the external connection pattern 24 extending along a second direction Y orthogonal to the first direction X and being arranged in pairs along the first direction X with at least three power supply patterns 23 therebetween. According to this structure, the semiconductor module 1 can connect adjacent substrates 20 via the external connection pattern 24, for example, and thus can improve expandability.

[0111] In the above-described semiconductor module 1, a base portion 30 on which the substrate 20 is placed and a housing 40 assembled to the base portion 30 on which the substrate 20 is placed are further provided. The housing 40 is configured to include a housing main body 41, a power supply terminal 42 provided to the housing main body 41 and connectable to the power supply pattern 23, and a signal terminal 43 provided to the housing main body 41 and connectable to the signal pattern 22. According to this structure, the semiconductor module 1 can connect the substrate 20 to a power supply and a load portion via the power supply terminal 42 of the housing 40, and can connect the substrate 20 to a control portion via the signal terminal 43 of the housing 40, and thus can improve connectivity.

[0112] In the semiconductor module 1 described above, of the three power supply patterns 23, one power supply pattern 23 is a power supply connection pattern to which the semiconductor chip 10 is mounted and which is connected to the drain portion D of the mounted semiconductor chip 10, another power supply pattern 23 is a power supply connection pattern which is connected to the source portion S of the semiconductor chip 10, and the remaining one power supply pattern 23 is a power supply non-connection pattern which is not connected to the drain portion D, the source portion S, and the gate portion G. The signal patterns 22 are provided four in number, one signal pattern 22 is a signal connection pattern which is connected to the gate portion G of the semiconductor chip 10, another signal pattern 22 is a signal connection pattern which is connected to the source portion S of the semiconductor chip 10, and the remaining two signal patterns 22 are signal non-connection patterns which are not connected to the drain portion D, the source portion S, and the gate portion G. Further, the semiconductor chip 10 constitutes a unidirectional circuit Pl which makes the current flowing in one direction in the power supply patterns 23 to be on or off. In this way, the semiconductor module 1 can constitute the unidirectional circuit Pl as one of the variations depending on the arrangement of the semiconductor chip 10 mounted on the substrate 20.

[0113] In the semiconductor module IA described above, of the three power supply patterns 23, two power supply patterns 23 are mounted with the semiconductor chip 10 and are connected to the drain portion D of the mounted semiconductor chip 10, respectively, and the remaining one power supply pattern 23 is connected to the source portion S of the semiconductor chip 10. The signal patterns 22 are provided four in number, two signal patterns 22 are connected to the gate portion G of either one of the semiconductor chips 10, and the remaining two signal patterns 22 are connected to the source portion S of either one of the semiconductor chips 10. Further, the semiconductor chip 10 constitutes a bidirectional circuit P2 which makes the current flowing in both directions in the power supply patterns 23 to be on or off. In this way, the semiconductor module IA can constitute the bidirectional circuit P2 as one of the variations depending on the arrangement of the semiconductor chip 10 mounted on the substrate 20.

[0114] In the semiconductor module IB described above, an external connection pattern 24 is further provided, the external connection pattern 24 being connectable with any one of the three power supply patterns 23 and being connectable with an external connection pattern 24 located outside the substrate 20, the external connection pattern 24 extending along a second direction Y orthogonal to the first direction X and being arranged in pairs along the first direction X with at least three power supply patterns 23 interposed therebetween. The substrate 20 on which the semiconductor chip 10 is mounted is provided in three, arranged in line along the second direction Y orthogonal to the first direction X. The adjacent substrates 20 are connected to each other via the external connection pattern 24. In each of the substrates 20, two of the three power supply patterns 23 mount the semiconductor chip 10 and are connected to the drain portion D of the mounted semiconductor chip 10, respectively, and the remaining one power supply pattern 23 is connected to the source portion S of the semiconductor chip 10 mounted on one power supply pattern 23, and one of the two power supply patterns 23 connected to the drain portion D is connected to the source portion S of the semiconductor chip 10 mounted on the other power supply pattern 23. The signal pattern 22 is provided in four, two of the signal patterns 22 being connected to any one gate portion G of the semiconductor chip 10, and the remaining two signal patterns 22 being connected to any one source portion S of the semiconductor chip 10. Further, the semiconductor chip 10 constitutes an inverter circuit P3 that converts direct-current electric power into alternating-current electric power. In this way, the semiconductor module IB can constitute the inverter circuit P3 as one of the variations depending on the arrangement of the semiconductor chip 10 mounted on the substrate 20.

[0115] [Variation of the First Embodiment]

[0116] Next, a variation of the embodiment will be described. In the variation, the same reference numerals are assigned to the same constituent elements as those of the embodiment, and detailed description thereof will be omitted. Figure 10 is a plan view showing a structure example of a semiconductor module 1C related to the variation of the first embodiment. Figure 11 is a circuit diagram showing a structure example of the semiconductor module 1C related to the variation of the first embodiment. The semiconductor module 1C is different from the semiconductor module 1 of the first embodiment in that the external connection pattern 24A is not provided to the substrate 20A but is provided to the case 40A.

[0117] The semiconductor module 1C includes the semiconductor chip 10, the substrate 20A, the base portion 30, and the case 40A.

[0118] The substrate 20A is configured to include the base material 21, the signal pattern 22 (221 to 224), and the power supply pattern 23 (231 to 233), and does not include the external connection pattern 24A.

[0119] The housing 40A is configured to include a housing body 41, power supply terminals 42 (421, 422), signal terminals 43 (D11, S11, G11, D12, S12, G12, etc.), and external connection patterns 24A. Two external connection patterns 24A are provided on the housing body 41 in each substrate 20A and are formed in a linear shape. The two external connection patterns 24A (241A, 242A) are formed in a straight line and extend parallel to each other along the second direction Y. The two external connection patterns 241A and 242A are formed to have the same thickness, that is, their width and length in the first direction X are formed to be the same. The length of each of the two external connection patterns 241A and 242A in the second direction Y is formed to be the same, and they are arranged in pairs along the first direction X, separated by at least three power supply patterns 23 (231 to 233). Typically, two external connection patterns 241A and 242A are arranged in pairs along the first direction X, separated by three power supply patterns 23 (231-233) and four signal patterns 22 (221-224). The ends of the two external connection patterns 241A and 242A on one side of the second direction Y are aligned, and the ends of the two external connection patterns 241A and 242A on the other side of the second direction Y are also aligned. The two external connection patterns 241A and 242A can be connected to any one of the three power supply patterns 23 and can be connected to external connection objects (power supply terminals 42 (421, 422), other external connection patterns 24A) located outside the substrate 20A. Thus, the semiconductor module 1C can also be a structure in which two external connection patterns 241A and 242A are disposed in the housing 40A within each substrate 20A. Furthermore, in Figure 10 as well as Figure 11 The diagram illustrates an example of a semiconductor module 1C constituting the aforementioned unidirectional circuit P1.

[0120] [Second Implementation]

[0121] Next, the semiconductor module 1D according to the second embodiment will be described. Figure 12 This is an exploded perspective view showing a basic structural example of the semiconductor module 1D according to the second embodiment. The semiconductor module 1D differs from the semiconductor module 1 according to the first embodiment in that it has a substrate 20B.

[0122] like Figure 12 As shown, the basic structure of the semiconductor module 1D includes a semiconductor chip 10, a substrate 20B, a base portion 30A, and a housing 40B. Furthermore, by mounting the semiconductor chip 10 relative to this basic structure, the semiconductor module 1D can form various semiconductor circuits corresponding to the structure of the semiconductor chip 10.

[0123] The substrate 20B is composed of a substrate 21, a signal pattern 22 and a power supply pattern 23, but does not include an external connection pattern 24.

[0124] The base portion 30A is used to mount one substrate 20B. The base portion 30A is formed of a metal member having heat conductivity, and is configured in a flat plate shape and a rectangular shape. The base portion 30A has a pair of face portions in the third direction Z, and a substrate mounting surface N is provided on one side face portion, the substrate mounting surface N mounting one substrate 20B and the case 40B.

[0125] The case 40B is a housing that houses the substrate 20B on which the semiconductor chip 10 is mounted. The case 40B is configured to include a case main body 41A, a power terminal 42, and a signal terminal 43, but does not include a relay terminal 44.

[0126] The case main body 41A is formed of an insulating member such as resin, and has one housing portion 411. The one housing portion 411 is formed in a rectangular shape so as to match the outer shape of the substrate 20B.

[0127] The power terminal 42 is provided to the case main body 41A, and is configured to include a first terminal 421 and a second terminal 422. The first terminal 421 is provided on one side in the first direction X in the one housing portion 411. The second terminal 422 is provided on the other side in the first direction X in the one housing portion 411.

[0128] The signal terminal 43 is provided to the case main body 41A, and is configured to include a signal terminal S11, S12 for a source, a signal terminal D11, D12 for a drain, and a signal terminal G11, G12 for a gate. The signal terminal S11 for the source, the signal terminal D11 for the drain, and the signal terminal G11 for the gate are provided on one side in the second direction Y in the one housing portion 411. In addition, the signal terminal S12 for the source, the signal terminal D12 for the drain, and the signal terminal G12 for the gate are provided on the other side in the second direction Y in the one housing portion 411.

[0129] The semiconductor module 1D can simplify the structure compared to the semiconductor module 1 in that the external connection pattern 24 and the relay terminal 44 are not included.

[0130] [First Modification of the Second Embodiment]

[0131] Next, an example in which the semiconductor chip 10 is mounted on the substrate 20B described in the above basic structure and housed in the case 40B to configure one unidirectional circuit P1 will be described. Figure 13 is a plan view showing a configuration example (first modification) of the semiconductor module 1D according to the second embodiment. Figure 14 is a circuit diagram showing the configuration example (first modification) of the semiconductor module 1D according to the second embodiment. In addition, in the circuit diagram of Figure 14 in the circuit diagram, the semiconductor chip 10 is simply illustrated.Figure 13 A structure example of the semiconductor module 1D is shown.

[0132] Figure 13 The semiconductor module 1D shown is provided in a power supply system of a vehicle, for example, and makes a current flowing from a power supply of the vehicle to a load section unidirectional (in one direction) to be on or off. The semiconductor module 1D can be disposed at various sites in the power supply system of the vehicle. The semiconductor module 1D is connected with the positive electrode side of the power supply of the vehicle via the first terminal 421 of the power supply terminal 42 and with the load section via the second terminal 422 of the power supply terminal 42, for example, in a case where it is disposed between the positive electrode side of the power supply and the load section. In addition, the semiconductor module 1D is connected with the load section via the first terminal 421 of the power supply terminal 42 and with the negative electrode side of the power supply of the vehicle via the second terminal 422 of the power supply terminal 42, for example, in a case where it is disposed between the negative electrode side of the power supply and the load section. In addition, the first terminal 421 of the power supply terminal 42 of the semiconductor module 1D is connected with the first power supply pattern 231 via the wire Wa, and the second terminal 422 of the power supply terminal 42 is connected with the second power supply pattern 232 via the wire Wa. In addition, the connection relationship of the three semiconductor chips 10, the signal pattern 22, and the power supply terminal 42 is the same as that of the semiconductor module 1 shown in FIG. 1, and thus the description thereof is omitted. In this way, the semiconductor module 1D can also constitute a unidirectional circuit P1. Figure 4 The connection relationship of the three semiconductor chips 10, the signal pattern 22, and the power supply terminal 42 is the same as that of the semiconductor module 1 shown in FIG. 1, and thus the description thereof is omitted. In this way, the semiconductor module 1D can also constitute a unidirectional circuit P1.

[0133] [Second Modification of Second Embodiment]

[0134] Next, the semiconductor module 1E related to the second modification of the second embodiment is described. The semiconductor module 1E is different from the semiconductor module 1D related to the first modification of the second embodiment in that it constitutes a bidirectional circuit P2. Figure 15 is a plan view showing a structure example (second modification) of the semiconductor module 1E related to the second embodiment. Figure 16 is a circuit diagram showing the structure example (second modification) of the semiconductor module 1E related to the second embodiment. In addition, in the circuit diagram of Figure 16 , the three semiconductor chips 10, the signal pattern 22, and the power supply terminal 42 are shown in a simplified manner. Figure 15 A structure example of the semiconductor module 1E shown is shown.

[0135] Figure 15The illustrated semiconductor module IE is provided, for example, in a power supply system of a vehicle, and makes a current flowing from a power supply of the vehicle to a load section pass or cut off. In the semiconductor module IE, for example, the first terminal 421 of the power supply terminal 42 is connected to the power supply of the vehicle, and the second terminal 422 of the power supply terminal 42 is connected to the load section. Since the semiconductor module IE is a bidirectional circuit, the first terminal 421 of the power supply terminal 42 can also be connected to the load section, and the second terminal 422 of the power supply terminal 42 can be connected to the power supply of the vehicle. In addition, the first terminal 421 of the power supply terminal 42 of the semiconductor module IE is connected to the first power supply pattern 231 via the wire Wa, and the second terminal 422 of the power supply terminal 42 is connected to the third power supply pattern 233 via the wire Wa. In addition, the connection relationship of the six semiconductor chips 10, the signal patterns 22, and the power supply patterns 23 is the same as that of the illustrated semiconductor module IA, and thus the description thereof is omitted. In this way, the semiconductor module IE can also constitute a bidirectional circuit P2. Figure 6 The connection relationship of the six semiconductor chips 10, the signal patterns 22, and the power supply patterns 23 is the same as that of the illustrated semiconductor module IA, and thus the description thereof is omitted. In this way, the semiconductor module IE can also constitute a bidirectional circuit P2.

[0136] In the above description, an example in which two of the three power supply patterns 23 on which the semiconductor chips 10 can be mounted are disposed on both sides along the second direction Y, and one of the power supply patterns 23 which can be connected to the source section S is disposed at the center along the second direction Y is described, but the present application is not limited thereto. For example, two of the three power supply patterns 23 on which the semiconductor chips 10 can be mounted can be disposed on one side along the second direction Y, and one of the power supply patterns 23 which can be connected to the source section S can be disposed on the other side along the second direction Y.

[0137] An example in which four signal patterns 22 are provided is described, but the present application is not limited thereto, and at least two signal patterns 22 can be provided. In the case where the signal patterns 22 are two, each of the signal patterns 22 can be connected to the gate section G.

[0138] An example in which the four signal patterns 22 are disposed in pairs along the second direction Y with the three power supply patterns 23 interposed therebetween is described, but the present application is not limited thereto. For example, the four signal patterns 22 can be disposed between the three power supply patterns 23 along the second direction Y.

[0139] The four signal patterns 22 (221 to 224) are described as being formed in the same length and thickness in the first direction X, but are not limited thereto. For example, the four signal patterns 22 (221 to 224) can be formed in different lengths and thicknesses, respectively.

[0140] The semiconductor chip 10 is described as being an N-channel type MOSFET, but is not limited thereto. For example, the semiconductor chip 10 can be a P-channel type MOSFET.

[0141] The four signal patterns 22 are described as being formed in the same length and thickness in the first direction X, but are not limited thereto. For example, the four signal patterns 22 can be formed in different lengths and thicknesses, respectively.

[0142] The three power supply patterns 23 are described as being formed in the same length and thickness in the first direction X, but are not limited thereto. For example, the three power supply patterns 23 can be formed in different lengths and thicknesses, respectively.

[0143] The four signal patterns 22 are described as being formed in the same length as the three power supply patterns 23, but are not limited thereto. For example, the four signal patterns 22 can be shorter than the three power supply patterns 23 or longer than the three power supply patterns 23.

[0144] The base portion 30 is described as being formed in a flat and rectangular shape, but is not limited thereto. For example, the base portion 30 can be formed to have a fin to improve heat dissipation.

[0145] [Reference Example]

[0146] The three power supply patterns 23 are described as being formed in a straight line shape, but as a reference example, can be formed in an L shape.

Claims

1. A semiconductor module, characterized by, Possessing: a semiconductor chip that provides a drain portion on one of a pair of opposing surfaces and a source portion and a gate portion on the other surface; and a substrate that includes a base material, three power supply patterns provided on the base material and capable of transmitting power supply power, and two signal patterns provided on the base material and capable of transmitting control signals, the substrate being capable of mounting the semiconductor chip, the three power supply patterns and the two signal patterns extending in parallel with each other along a first direction, of the three power supply patterns, two of the power supply patterns being capable of mounting the semiconductor chip and connecting with the drain portion of the mounted semiconductor chip, and the remaining one of the power supply patterns being capable of connecting with the source portion of the mounted semiconductor chip, the two signal patterns being capable of connecting with the gate portion of the mounted semiconductor chip, of the three power supply patterns, the one power supply pattern capable of connecting with the source portion being disposed between the two power supply patterns capable of mounting the semiconductor chip along a second direction orthogonal to the first direction, the signal patterns being provided in four, two of the signal patterns being capable of connecting with the gate portion and the remaining two of the signal patterns being capable of connecting with the source portion, the two signal patterns capable of connecting with the gate portion being disposed in pairs along the second direction across the three power supply patterns, and the two signal patterns capable of connecting with the source portion being disposed in pairs along the second direction across the three power supply patterns, the two power supply patterns capable of mounting the semiconductor chip also being capable of serving as signal patterns for the drain portion.

2. The semiconductor module according to claim 1, further comprising an external connection pattern capable of connecting with any one of the three power supply patterns and capable of connecting with an external connection object located outside the substrate, the external connection pattern extending along a second direction orthogonal to the first direction and being disposed in pairs along the first direction at least across the three power supply patterns.

3. The semiconductor module according to claim 1, further comprising: a base portion that holds the substrate; and a housing that is assembled to the base portion that holds the substrate, the housing being configured to include a housing main body, a power supply terminal provided to the housing main body and capable of connecting with the power supply patterns, and a signal terminal provided to the housing main body and capable of connecting with the signal patterns.

4. The semiconductor module according to claim 2, further comprising: a base portion that holds the substrate; and a housing that is assembled to the base portion that holds the substrate, ​ ​ ​ The housing is configured to include a housing main body, a power terminal provided to the housing main body and connectable with the power pattern, and a signal terminal provided to the housing main body and connectable with the signal pattern.

5. The semiconductor module according to any one of claims 1 to 4, wherein of the three power patterns is a power connection pattern connected to the drain portion of the mounted semiconductor chip, another of the three power patterns is a power connection pattern connected to the source portion of the mounted semiconductor chip, and the remaining one of the three power patterns is a power non-connection pattern not connected to the drain portion, the source portion, and the gate portion of the mounted semiconductor chip, the signal patterns are provided four, one of the signal patterns is a signal connection pattern connected to the gate portion of the mounted semiconductor chip, another of the signal patterns is a signal connection pattern connected to the source portion of the mounted semiconductor chip, and the remaining two of the signal patterns are signal non-connection patterns not connected to the drain portion, the source portion, and the gate portion of the mounted semiconductor chip, the mounted semiconductor chip constitutes a unidirectional circuit that turns on or off a current flowing in one direction in the power pattern.

6. The semiconductor module according to any one of claims 1 to 4, wherein of the three power patterns is a power connection pattern connected to the drain portion of the mounted semiconductor chip, another of the three power patterns is a power connection pattern connected to the source portion of the mounted semiconductor chip, and the remaining one of the three power patterns is a power non-connection pattern not connected to the drain portion, the source portion, and the gate portion of the mounted semiconductor chip, the signal patterns are provided four, one of the signal patterns is a signal connection pattern connected to the gate portion of the mounted semiconductor chip, another of the signal patterns is a signal connection pattern connected to the source portion of the mounted semiconductor chip, and the remaining two of the signal patterns are signal non-connection patterns not connected to the drain portion, the source portion, and the gate portion of the mounted semiconductor chip, the mounted semiconductor chip constitutes a bidirectional circuit that turns on or off a current flowing in both directions in the power pattern.

7. The semiconductor module according to claim 1 or 3, wherein the semiconductor module further has an external connection pattern connectable with any one of the three power patterns and connectable with an external connection object located outside the substrate, the external connection pattern extends along a second direction orthogonal to the first direction and is provided in pairs along the first direction at least through the three power patterns, the substrates on which the semiconductor chips are mounted are provided three, arranged along the second direction, the adjacent substrates are connected to each other via the external connection pattern, In each of the substrates, of the three power supply patterns, two of the power supply patterns mount the semiconductor chips and are connected to the drain portions of the mounted semiconductor chips, respectively, one of the remaining power supply patterns is connected to the source portion of the semiconductor chip mounted on one of the power supply patterns, one of the power supply patterns connected to the drain portions is connected to the source portion of the semiconductor chip mounted on the other of the power supply patterns, The signal patterns are provided four, two of the signal patterns are connected to the gate portions of any of the mounted semiconductor chips, the remaining two of the signal patterns are connected to the source portions of any of the mounted semiconductor chips, The mounted semiconductor chips constitute an inverter circuit that converts direct current into alternating current.

8. The semiconductor module according to claim 2 or 4, wherein The substrates on which the semiconductor chips are mounted are provided three, which are arranged along the second direction, respectively, The adjacent substrates are connected to each other via the external connection pattern, In each of the substrates, of the three power supply patterns, two of the power supply patterns mount the semiconductor chips and are connected to the drain portions of the mounted semiconductor chips, respectively, one of the remaining power supply patterns is connected to the source portion of the semiconductor chip mounted on one of the power supply patterns, one of the power supply patterns connected to the drain portions is connected to the source portion of the semiconductor chip mounted on the other of the power supply patterns, The signal patterns are provided four, two of the signal patterns are connected to the gate portions of any of the mounted semiconductor chips, the remaining two of the signal patterns are connected to the source portions of any of the mounted semiconductor chips, The mounted semiconductor chips constitute an inverter circuit that converts direct current into alternating current.

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