A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a functional layer on one side of a substrate, and a connecting line on the other side of the functional layer away from the substrate. The functional layer can comprise a plurality of functional units, and an isolation structure penetrating through the functional layer in a direction perpendicular to the surface of the substrate. The isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into a plurality of groups. The connecting line is used for electrical connection with the functional units. The isolation structure and the functional layer are formed in different ways and have different extension directions, so that the mechanical strength of the contact position of the isolation structure and the functional layer is poor and is prone to breakage. Therefore, the projection of the isolation structure and the connecting line on the surface of the substrate can be intersected, that is, the connecting line can be arranged directly above the isolation structure and across the isolation structure, so that the mechanical strength of the contact position of the isolation structure and the functional layer is enhanced, and the overall mechanical strength of the semiconductor device is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] The demand for large capacity and ultra-thin chips of existing electronic products is increasingly strong. Therefore, chip manufacturing processes are constantly improving, and the number of chip stacking layers is increasing to meet the requirement of large capacity. Meanwhile, with the increase in the number of stacking layers, the thickness of each layer of chip must be reduced. The thinned chip needs to have sufficient strength to ensure the reliability of chip stacking. However, the current chip has defects in strength. SUMMARY

[0003] To solve the above technical problems, the present application provides a semiconductor device and a manufacturing method thereof to improve the mechanical strength of the semiconductor device.

[0004] The present application provides a semiconductor device, comprising:

[0005] a functional layer on one side of a substrate, and a connection line on the side of the functional layer away from the substrate; the functional layer comprises a plurality of functional units, and an isolation structure penetrating through the functional layer in a direction perpendicular to the surface of the substrate, the isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into multiple groups; the connection line is used for electrical connection with the functional units; the projection of the isolation structure on the surface of the substrate and the projection of the connection line on the surface of the substrate intersect.

[0006] Optionally, the connection line comprises a first part extending in a first direction and a second part extending in a second direction.

[0007] The first direction intersects with the extension direction of the isolation structure in the direction parallel to the surface of the substrate, and the projection of the first part on the surface of the substrate has an overlapping area with the projection of the isolation structure on the surface of the substrate; and / or, the second direction intersects with the extension direction of the isolation structure in the direction parallel to the surface of the substrate, and the projection of the second part on the surface of the substrate has an overlapping area with the projection of the isolation structure on the surface of the substrate.

[0008] Optionally, in the extension direction of the isolation structure in the direction parallel to the surface of the substrate, the connection line is a serpentine trace or a zigzag trace.

[0009] Optionally, the isolation structure and the connection line are both a plurality of structures, and the plurality of isolation structures are arranged in parallel.

[0010] There are at least one overlapping area between the projection of the connection line on the substrate surface and the projection of the isolation structure on the substrate surface; and / or, there are at least one overlapping area between the projection of the connection line on the substrate surface and the projection of the plurality of isolation structures on the substrate surface.

[0011] Optionally, the functional layer includes a first film layer on one side of the substrate.

[0012] Optionally, the functional layer includes a first film layer on one side of the substrate, and a second film layer on the side of the first film layer away from the substrate, and a bonding layer is arranged between the first film layer and the second film layer; the functional unit includes a first unit in the first film layer and a second unit in the second film layer; the isolation structure includes a first structure in the first film layer and a second structure in the second film layer.

[0013] Optionally, the first film layer includes a first stack layer, the first stack layer includes an insulating layer and a gate layer stacked in sequence, the first unit is a storage unit, and the first structure penetrates the first stack layer in a direction perpendicular to the substrate surface; the first units in the same group are stacked in the direction perpendicular to the substrate surface, and the first structure includes a conductor structure extending in the direction perpendicular to the substrate surface and an insulating structure on the sidewall of the conductor structure, the conductor structure is connected with a doped structure in the substrate as a common source.

[0014] Optionally, the material of the connection line is aluminum.

[0015] Embodiments of the present application provide a manufacturing method of a semiconductor device, including:

[0016] forming a functional layer on one side of a substrate; the functional layer includes a plurality of functional units and an isolation structure penetrating the functional layer in a direction perpendicular to the substrate surface, and the isolation structure extends in a direction parallel to the substrate surface to separate the plurality of functional units into a plurality of groups;

[0017] forming a connection line on the side of the functional layer away from the substrate; the connection line is used for electrical connection with the functional unit; the projection of the isolation structure on the substrate surface and the projection of the connection line on the substrate surface intersect.

[0018] Optionally, the forming of the connection line on the side of the functional layer away from the substrate includes:

[0019] forming a conductor layer on the side of the functional layer away from the substrate, and etching the conductor layer to form the connection line;

[0020] Or, a dielectric layer is formed on the side of the functional layer away from the substrate, the dielectric layer is etched to obtain a wiring groove, and a conductor material is formed in the wiring groove, the conductor material serving as the connecting line.

[0021] Optionally, the connecting line includes a first portion extending in a first direction and a second portion extending in a second direction.

[0022] The first direction intersects with the extension direction of the isolation structure on the substrate surface, and the projection of the first portion on the substrate surface has an overlapping area with the projection of the isolation structure on the substrate surface; and / or, the second direction intersects with the extension direction of the isolation structure on the substrate surface, and the projection of the second portion on the substrate surface has an overlapping area with the projection of the isolation structure on the substrate surface.

[0023] Optionally, in the extension direction of the isolation structure on the substrate surface, the connecting line is a meandering trace or a zigzag trace.

[0024] Optionally, the isolation structure and the connecting line are both multiple, and the multiple isolation structures are arranged in parallel.

[0025] There are multiple overlapping areas between the projection of at least one connecting line on the substrate surface and the projection of at least one isolation structure on the substrate surface; and / or, there are overlapping areas between the projection of at least one connecting line on the substrate surface and the projections of multiple isolation structures on the substrate surface.

[0026] Optionally, the functional layer includes a first film layer on the side of the substrate.

[0027] Or, the functional layer includes a first film layer on the side of the substrate, and a second film layer on the side of the first film layer away from the substrate, and a bonding layer is arranged between the first film layer and the second film layer; the functional unit includes a first unit in the first film layer and a second unit in the second film layer; the isolation structure includes a first structure in the first film layer and a second structure in the second film layer; then, the forming of the functional layer on the side of the substrate includes:

[0028] forming a first film layer on the side of the substrate and forming a second film layer on the side of the other substrate;

[0029] bonding the first film layer and the second film layer together through a bonding process;

[0030] thinning the other substrate;

[0031] etching the other substrate to obtain multiple interconnection through holes; the multiple interconnection through holes penetrate to the first unit and / or the second unit.

[0032] filling the plurality of interconnected via holes with a conductor material.

[0033] Optionally, the first film layer comprises a first stack layer, the first stack layer comprises an insulating layer and a gate layer stacked in sequence, the first unit is a memory cell, and the first structure penetrates the first stack layer in a direction perpendicular to the substrate surface; the first units in the same group are stacked in the direction perpendicular to the substrate surface, the first structure comprises a conductor structure extending in the direction perpendicular to the substrate surface and an insulating structure on a sidewall of the conductor structure, and the conductor structure is connected with a doped structure in the substrate as a common source;

[0034] Then, the functional layer formed on one side of the substrate comprises:

[0035] forming an initial stack layer comprising an insulating layer and a sacrificial layer stacked in sequence on one side of the substrate;

[0036] forming a channel hole in the initial stack layer and forming a channel structure in the channel hole;

[0037] etching the initial stack layer to obtain a gate line gap penetrating the stack layer in a direction perpendicular to the substrate surface;

[0038] replacing the sacrificial layer with a gate layer through the gate line gap to obtain a first stack layer comprising a gate layer and an insulating layer;

[0039] forming an insulating structure on a sidewall of the gate line gap and filling a conductor structure in the gate line gap, and the conductor structure and the insulating structure constitute a first structure.

[0040] Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a functional layer on one side of a substrate, and a connection line on a side of the functional layer away from the substrate. The functional layer can comprise a plurality of functional units, and an isolation structure penetrating the functional layer in a direction perpendicular to a surface of the substrate. The isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into a plurality of groups. The connection line is used to electrically connect with the functional units. The isolation structure and the functional layer are formed in different ways and have different extension directions, so that the mechanical strength of the contact position of the isolation structure and the functional layer is poor and is prone to breakage. Therefore, the projection of the isolation structure and the connection line on the substrate surface can be intersected, that is, the connection line can be arranged directly above the isolation structure, and the connection line is arranged across the isolation structure, so as to enhance the mechanical strength of the contact position of the isolation structure and the functional layer, thereby enhancing the overall mechanical strength of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0042] Figure 1 A structural schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0043] Figure 2 A device strength schematic diagram of a current semiconductor device;

[0044] Figure 3 A top view of a current semiconductor device;

[0045] Figure 4 A top view of a semiconductor device provided by the embodiment of the present application;

[0046] Figure 5 A top view of another semiconductor device provided by the embodiment of the present application;

[0047] Figure 6 A structural schematic diagram of another semiconductor device provided by the embodiment of the present application;

[0048] Figure 7 A structural schematic diagram of still another semiconductor device provided by the embodiment of the present application;

[0049] Figure 8 A flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the present application;

[0050] Figures 9-12 A structural schematic diagram of a semiconductor device in a manufacturing process of the embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the above objectives, features and advantages of the present application more apparent and comprehensible, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0052] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0053] As described in the background, the current chip has a defect in strength, and the inventors have found that, in a semiconductor device, an isolation structure for isolating different functional units has a cuboid structure, a large aspect ratio, and various filling materials, which causes the position of the isolation structure to be a weak point in terms of strength, thereby affecting the overall strength of the device.

[0054] To solve the above problems, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes a functional layer on one side of a substrate, and a connection line on the side of the functional layer away from the substrate. The functional layer can include a plurality of functional units, and an isolation structure penetrating the functional layer in a direction perpendicular to the surface of the substrate. The isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into multiple groups. The connection line is used to electrically connect with the functional units. The isolation structure and the functional layer are formed in different ways and have different extension directions, so the mechanical strength of the contact position between the isolation structure and the functional layer is poor and prone to breakage. Therefore, the projection of the isolation structure and the connection line on the surface of the substrate can be intersected, i.e., the connection line can be arranged directly above the isolation structure and across the isolation structure, thereby enhancing the mechanical strength of the contact position between the isolation structure and the functional layer and the overall mechanical strength of the semiconductor device.

[0055] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0056] Reference Figure 1 As shown in the structure schematic diagram of a semiconductor device provided by the embodiments of the present application, the semiconductor device can include a functional layer on one side of a substrate 100, and a connection line 160 on the side of the functional layer 11 away from the substrate 100. For ease of description, the substrate 100 can be taken as a bottom support component, and then the functional layer 11 is located above the substrate 100, and the connection line 160 is located above the functional layer 11. Of course, the aforementioned “above” is defined for representing the positional relationship between the film layers, and in fact, the up-down positional relationship between the film layers is related to the placement mode of the semiconductor device. The substrate 100 can be placed as a bottom support component or as a top component.

[0057] Among them, the semiconductor device can be a wafer, and the number of wafers can be one or multiple. The multiple wafers are stacked in sequence along the direction perpendicular to the surface of the substrate 100 (referred to as longitudinal direction), for example, the semiconductor device includes 2, 4, 8, or 16 wafers stacked in the longitudinal direction. The semiconductor device can also be a die, and the number of dies can be one or multiple. The multiple dies are stacked in the direction perpendicular to the surface of the substrate 100 (longitudinal direction), for example, the semiconductor device includes 2, 4, 8, or 16 dies stacked in the longitudinal direction.

[0058] In the embodiment, the substrate 100 is a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, for example, GaAs, InP or SiC, etc., can also be a laminated structure, for example, Si / SiGe, etc., can also be other epitaxial structures, for example, SGOI (Silicon Germanium On Insulator), etc. Figure 1 As shown, in the embodiment, the substrate 100 is a single crystal silicon substrate, and the device structure supported thereon.

[0059] The functional layer 11 can include a plurality of functional units, which can be storage units or logic computing units. The storage units can be NAND storage units or NOR storage units. The functional units can be stacked in the vertical direction to form a three-dimensional semiconductor device, for example, a 3D NAND memory device or a 3D NOR memory device. Of course, the functional units can also be units with other functions, for example, switching units, etc. The semiconductor device can also be a memory device including a three-dimensional memory device and other electronic elements, which are disposed on the same substrate and can be connected to each other to work cooperatively. For example, the semiconductor device includes a three-dimensional memory device and a memory controller, the number of three-dimensional memory devices can be one or more, and the memory controller is used to control the three-dimensional memory device. In the embodiment, the semiconductor device can be implemented and packaged into different types of electronic devices.

[0060] The functional layer 11 further includes an isolation structure 14 extending through the functional layer 11 in the direction perpendicular to the surface of the substrate 100, and the isolation structure 14 extends in the direction parallel to the surface of the substrate 100 to separate the plurality of functional units into a plurality of groups. For example, the isolation structure 14 separates the functional layer 11 into a plurality of regions, and the functional units are formed in each region. The functional units in the same region form a group, and the isolation structure 14 extends in the vertical direction between adjacent regions.

[0061] Specifically, the isolation structure 14 includes a conductor structure 142 extending in the direction perpendicular to the surface of the substrate 100 and an insulating structure 141 on the sidewall of the conductor structure 142. The insulating structure 141 can electrically isolate the conductor structure 142 and the functional units. The material of the insulating structure 141 can be silicon oxide or an organic material such as silicone rubber or silane, etc. The conductor structure 142 can be tungsten or polysilicon, etc.

[0062] The isolation structure 14 is a cuboid structure, and the depth-width ratio is usually large, and the filling material is also various. The isolation structure 14 and the functional layer 11 are different in direction and extension direction, so the mechanical strength of the contact position of the isolation structure 14 and the functional layer 11 is usually low, and is often a crack concentration point of the device, and the modification is difficult. Referring to Figure 2 The abscissa is strength (Strength) in MPa, and the ordinate is the probability (Probability) of fracture. The curve composed of the round dots represents a device with the isolation structure 14, and the curve composed of the square dots represents a device without the isolation structure 14. As can be seen from the figure, the device with the isolation structure 14 is more prone to fracture. In fact, the fracture position of the device with the isolation structure 14 is often the position of the isolation structure 14.

[0063] On the side of the functional layer 11 away from the substrate 100, a connection line 160 can also be formed. The connection line 160 is used to be electrically connected with the functional unit. The connection line 160 can be connected with the functional unit by using an interlayer interconnection structure (not shown in the figure). The person skilled in the art can freely set the position and shape of the interlayer interconnection structure and the connection line 160 according to the position of the functional unit. A dielectric layer can be arranged between different connection lines 160. The material of the connection line 160 can be aluminum, that is, the connection line 160 can be an aluminum line (AL), or can be other conductor materials. An isolation layer 150 can be arranged between the connection line 160 and the functional layer 11, which is used to electrically isolate the functional layer 11 and the connection line 160. The isolation layer 150 can be one layer, or can be multiple layers, and can include one material or multiple materials.

[0064] At present, the extension direction of the connection line 160 can be parallel to the extension direction of the isolation structure 14 in the direction perpendicular to the surface of the substrate 100, and the projections of the two on the surface of the substrate 100 do not overlap. Referring to Figure 3 Fig. 2 shows a structure schematic diagram of a semiconductor device at present. In the figure, Figure 3 A is a top view of a semiconductor device, Figure 3 B is a sectional view of a semiconductor device, in which the isolation structure 14 (ACS) isolates different functional units, and the connection line 160 (AL) can be arranged above the functional unit, that is, after being projected onto a plane parallel to the substrate 100, the connection line 160 is arranged between two isolation structures 14.

[0065] In the embodiments of the present application, the routing of the connection line 160 can be improved, so that the projection of the isolation structure 14 on the surface of the substrate 100 and the projection of the connection line 160 on the surface of the substrate 100 intersect, that is, the connection line 160 can be arranged directly above the isolation structure 14, and the connection line 160 can bear stress from the surface, thereby enhancing the mechanical strength of the region where the isolation structure 14 is located, and thus enhancing the overall mechanical strength of the semiconductor device. The connection line 160 (AL) can be arranged across the isolation structure 14 (ACS), that is, the connection line 160 can be arranged directly above the isolation structure 14 and on both sides of the isolation structure 14, and in this case, the connection line 160 has a projection on the surface of the substrate 100 on both sides of the isolation structure 14.

[0066] Specifically, the connection line 160 can be a curve or a polyline. When the connection line 160 is a polyline, as shown in FIGS. 1B and 1C, the connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100. Figure 4 Figure 5 As shown in FIGS. 1B and 1C, the semiconductor device provided in the embodiments of the present application can be a top view, and the connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100. As shown in FIG. 1B, the first direction and the second direction can both intersect with the extension direction of the isolation structure 14 on the surface of the substrate 100, and as shown in FIG. 1C, one of the first direction and the second direction can intersect with the extension direction of the isolation structure 14 on the surface of the substrate 100. Figure 4 Figure 5 As shown in FIGS. 1B and 1C, the semiconductor device provided in the embodiments of the present application can be a top view, and the connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100. As shown in FIG. 1B, the first direction and the second direction can both intersect with the extension direction of the isolation structure 14 on the surface of the substrate 100, and as shown in FIG. 1C, one of the first direction and the second direction can intersect with the extension direction of the isolation structure 14 on the surface of the substrate 100.

[0067] In specific implementation, the projection on the surface of the substrate 100 of the part of the first part and the second part that is parallel to the connection line 160 intersects with the projection on the surface of the substrate 100 of the isolation structure 14, or the projection on the surface of the substrate 100 of the part of the first part and the second part that is not parallel to the connection line 160 intersects with the projection on the surface of the substrate 100 of the isolation structure 14.

[0068] For example, when the first direction intersects with the extension direction of the isolation structure 14 on the surface of the substrate 100, the projection on the surface of the substrate 100 of the first part can have an overlapping region with the projection on the surface of the substrate 100 of the isolation structure 14, or when the second direction intersects with the extension direction of the isolation structure 14 on the surface of the substrate 100, the projection on the surface of the substrate 100 of the second part can have an overlapping region with the projection on the surface of the substrate 100 of the isolation structure 14. As shown in FIG. 1B, the projection on the surface of the substrate 100 of the first part and the second part of the connection line 160 can have overlapping regions with the projection on the surface of the substrate 100 of the isolation structure 14. Figure 5 ​​As shown, the first direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, and the first part on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface. The second direction is parallel to the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, and the second part on the substrate 100 surface can be arranged to have no overlapping area with the projection of the isolation structure 14 on the substrate 100 surface.

[0069] For example, the first direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, and the first part on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface. The second direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, and the second part on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface. Figure 4

[0070] The connection line 160 can be a periodic pattern, for example, in the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the connection line 160 is a serpentine or a zigzag, which can have a rounded corner or a right angle. The serpentine with a rounded corner can be a wave-shaped line.

[0071] In the embodiment, the isolation structure 14 and the connection line 160 are both multiple, and the multiple isolation structures 14 are arranged in parallel. The projection of at least one connection line 160 on the substrate 100 surface and the projection of one isolation structure 14 on the substrate 100 surface can have multiple overlapping areas, that is, the connection line 160 is located directly above at least one isolation structure 14 (ACS), and the extending direction is consistent with the extending direction of the isolation structure 14 on the substrate 100 plane in parallel, as shown in Figure 4 Figure 5 and / or, the projection of at least one connection line 160 on the substrate 100 surface and the projection of multiple isolation structures 14 on the substrate 100 surface can have overlapping areas, that is, the connection line 160 can be located directly above multiple isolation structures 14 (ACS), as shown in Figure 4

[0072] In addition, in some embodiments, multiple connection lines 160 (AL) can have overlapping areas with the projection of the same isolation structure 14 (ACS) on the substrate 100 surface, that is, multiple connection lines 160 (AL) can be arranged directly above the same isolation structure 14 (ACS), as shown in Figure 4

[0073] ​​​​It can be understood that the connecting line 160 is used to enhance the mechanical strength of the position where the isolation structure 14 is located, and the greater the number of overlapping areas of the projection of the connecting line 160 and the isolation structure 14 on the surface of the substrate 100, the greater the enhancement effect of the connecting line 160 on the mechanical strength, and at the same time, the more the junction between the isolation structure 14 and the functional layer 11 is covered by the connecting line 160, the stronger the mechanical strength of the position where the isolation structure 14 is located.

[0074] When the semiconductor device includes a single wafer or die, the functional layer 11 includes a first film layer 1101 formed on the substrate 100.

[0075] When the semiconductor device includes a plurality of wafers or dies vertically stacked, the functional layer 11 can include, in addition to the first film layer 1101, a second film layer 1102 located on the side of the first film layer 1101 away from the substrate 100, and a bonding layer 170 can be provided between the first film layer 1101 and the second film layer 1102 to bond and combine the first film layer 1101 and the second film layer 1102, and the bonding layer 170 can be used as a part of the isolation layer 150. Figure 6 The second film layer 1102 can be a film layer in another wafer or die, and another substrate can also be provided on the side of the second film layer 1102 away from the substrate 100, which can be used as a part of the isolation layer 150. At this time, the functional unit includes a first unit in the first film layer 1101 and a second unit in the second film layer 1102, and the isolation structure 14 includes a first structure 1401 in the first film layer 1101 and a second structure 1402 in the second film layer 1102.

[0076] Specifically, in a three-dimensional NAND memory device, the functional unit is a storage unit, and the first film layer 1101 is taken as an example for description, and the bonding layer 170 can be used as a part of the isolation layer 150. Figure 7 The first film layer 1101 can include a first stacked layer, and the first stacked layer can include insulating layers 120 and gate layers 110 alternately stacked, and the first film layer 1101 further includes a channel structure 13 vertically penetrating the stacked layer, and the first unit 12 is a storage unit. The material of the insulating layer 120 is silicon oxide, and the material of the gate layer 110 is tungsten, and a gate dielectric layer 111 can be formed between the gate layer 110 and the insulating layer 120, and the number of layers of the stacked layer determines the number of storage units in the vertical direction, and the more the number of layers, the higher the integration of the device.

[0077] The channel structure 13 is formed in the channel hole, and each film layer in the channel structure 13 is sequentially stacked along the radial direction of the channel hole. In the radial direction of the channel hole, from the edge to the center, the channel structure 13 can sequentially include a storage layer 131, a channel layer 132, and a filling layer 134. The storage layer 131 can include a tunneling layer, a charge trapping layer, and a blocking layer. The material of the tunneling layer can be silicon oxide, the material of the charge trapping layer can be silicon nitride, and the material of the blocking layer can be silicon oxide, thereby forming a silicon oxide-silicon nitride-silicon oxide structure of the storage layer 131. The material of the channel layer 132 can be polysilicon, and the material of the filling layer 134 can be silicon oxide. The material of the filling layer 134 can be adjusted according to actual conditions. The bottom of the channel structure 13 is formed with a selectively epitaxially grown doped structure 133.

[0078] The first structure 1401 extends in the direction parallel to the surface of the substrate 100 to separate a plurality of first units 12 into a plurality of groups. In a three-dimensional NAND memory device, the first units 12 in the same group are stacked in the direction perpendicular to the surface of the substrate 100. The first structure 1401 in the embodiment of the present application includes a conductor structure 142 extending in the direction perpendicular to the surface of the substrate 100 and an insulating structure 141 on the sidewall of the conductor structure 142. In a three-dimensional NAND memory device, the conductor structure 142 can be connected with a doped structure 143 in the substrate 100 as a common source. There can be a plurality of first structures 1401, which can be arranged in parallel to form an array. Therefore, the first structure 1401 can also be referred to as an array common source (ACS) structure.

[0079] The connection line 160 is used to electrically connect with the first unit 12. Specifically, the connection line 160 can include a plurality of connection lines, which are respectively used to electrically connect with the source, the drain, the gate, the substrate, etc. in the first unit 12. For example, the connection line 160 can be electrically connected with the source, the drain, the gate, the substrate, etc. in the first unit 12 by using an interlayer interconnection structure.

[0080] Each first unit 12 can include one gate layer 110 extending laterally, a storage layer 131 extending longitudinally and in contact with the gate layer 110, a channel layer 132 in contact with the storage layer 131, and a doped structure 133 below the channel layer 132 as a source. The drain is led out above the channel layer 132. The longitudinally stacked gate layers 110 belong to different first units 12, and each first unit 12 is connected in series.

[0081] The structure of the second film layer 1102 can be similar to that of the first film layer 1101, or can be other structures.

[0082] That is, when the functional layer 11 includes the first film layer 1101, the connecting line 160 can be arranged on the side of the first structure 1401 in the first film layer 1101 away from the substrate 100, and when the functional layer 11 includes the first film layer 1101 and the second film layer 1102, the connecting line 160 can be arranged above the first structure 1401 in the first film layer 1101 and / or the second structure 1402 in the second film layer 1102, so as to improve the overall strength of the semiconductor device.

[0083] The semiconductor device provided in the embodiments of the present application includes a functional layer on one side of a substrate and a connecting line on the side of the functional layer away from the substrate. The functional layer can include a plurality of functional units and an isolation structure penetrating the functional layer in a direction perpendicular to the surface of the substrate. The isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into a plurality of groups. The connecting line is used to electrically connect the functional units. The isolation structure and the functional layer are formed in different ways and extend in different directions, so the mechanical strength of the contact position of the isolation structure and the functional layer is poor and is prone to breakage. Therefore, the projection of the isolation structure and the connecting line on the surface of the substrate can be arranged to intersect, that is, the connecting line can be arranged directly above the isolation structure and cross the isolation structure, so as to enhance the mechanical strength of the contact position of the isolation structure and the functional layer and the overall mechanical strength of the semiconductor device.

[0084] Based on the semiconductor device provided in the above embodiments, the embodiments of the present application further provide a manufacturing method of a semiconductor device. Referring to Figure 8 FIG. 1 shows a flowchart of a manufacturing method of a semiconductor device provided in the embodiments of the present application. The method can include the following steps.

[0085] In S101, a functional layer 11 is formed on one side of a substrate 100.

[0086] In the embodiments of the present application, the substrate 100 is a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, for example, GaAs, InP or SiC, etc. The semiconductor substrate can also be a laminated structure, for example, Si / SiGe, etc. The semiconductor substrate can also be other epitaxial structures, for example, SGOI (Silicon Germanium On Insulator), etc. Referring to FIG. 1, in the present embodiment, the substrate 100 is a single crystal silicon substrate, used to support the device structure thereon. Figure 1

[0087] ​In the embodiments of the present application, the substrate 100 can be used as a bottom support component for the convenience of description, and the functional layer 11 is located above the substrate 100, and the connection line 160 is located above the functional layer 11. Of course, the "above" is defined for representing the positional relationship between the film layers, and in fact, the up-down positional relationship between the film layers is related to the placement mode of the semiconductor device. The substrate 100 can be placed as a bottom support component or as a top component.

[0088] The functional layer 11 can include a plurality of functional units. The functional unit can be a storage unit, which can be a NAND storage unit or a NOR storage unit. The functional units can be stacked in the longitudinal direction, so that the semiconductor device is a three-dimensional memory device, such as a 3D NAND memory device or a 3D NOR memory device.

[0089] The functional layer 11 further includes an isolation structure 14 extending through the stacked layers in the direction perpendicular to the surface of the substrate 100. The isolation structure 14 extends in the direction parallel to the surface of the substrate 100 to separate the plurality of functional units into a plurality of groups. For example, the functional layer 11 is divided into a plurality of regions by the isolation structure 14, and the functional units are formed in each region. The functional units in the same region form a group, and the longitudinal isolation structure 14 is formed between adjacent regions.

[0090] Specifically, the isolation structure 14 in the embodiments of the present application includes a conductor structure 142 extending in the direction perpendicular to the surface of the substrate 100 and an insulating structure 141 on the sidewall of the conductor structure 142. The insulating structure 141 can electrically isolate the conductor structure 142 and the functional unit. The insulating structure 141 can be made of silicon oxide or an organic material such as silicone rubber or silane. The conductor structure 142 can be made of tungsten or polysilicon.

[0091] Specifically, the functional layer 11 can be formed on one side of the substrate 100. The functional layer 11 is etched to obtain an isolation trench, and the isolation structure 14 is formed in the isolation trench. As shown in FIG. 1B, the isolation layer 150 can be formed on the side of the functional layer 111 away from the substrate 100. Figure 9 Figure 10 As shown in FIG. 1C.

[0092] When the semiconductor device includes a single-layer wafer or a single-layer die, the functional layer 11 includes a first film layer 1101 formed on the substrate 100.

[0093] ​When the semiconductor device includes a plurality of wafers or dies stacked longitudinally, the functional layer 11 can include a plurality of functional layers 11 in the plurality of wafers or dies, that is, the functional layer 11 can include, in addition to the first film layer 1101, a second film layer 1102 on the first film layer 1101, and a bonding layer 170 can be arranged between the first film layer 1101 and the second film layer 1102 to bond and combine the first film layer 1101 and the second film layer 1102. The second film layer 1102 can be a film layer in another wafer or die, and another substrate can also be arranged on the side of the second film layer 1102 away from the substrate 100. At this time, the functional unit includes a first unit 12 in the first film layer 1101 and a second unit in the second film layer 1102, and the isolation structure 14 includes a first structure 1401 in the first film layer 1101 and a second structure 1402 in the second film layer 1102.

[0094] The functional layer 11 is formed on the substrate 100, which can specifically be that the first film layer 1101 is formed on one side of the substrate 100, and the second film layer 1102 is formed on the other side of the substrate 100, the first film layer 1101 can have the first structure 1401, and the second film layer 1102 can have the second structure 1402; the bonding layer 170 is formed on the first film layer 1101, as shown in Figure 11 The first film layer 1101 and the second film layer 1102 are bonded together by the bonding layer 170 between the first film layer 1101 and the second film layer 1102 through a bonding process, as shown in Figure 12 In addition, after bonding the first film layer 1101 and the second film layer 1102, the other substrate can also be thinned, etched, and a plurality of interconnection through holes can be obtained, which penetrate the first unit 12 and / or the second unit; a conductor material is filled in the plurality of interconnection through holes to lead out the first unit 12 and / or the second unit.

[0095] In a three-dimensional NAND device, the functional unit is a storage unit, and the first film layer 1101 is taken as an example for description. The first film layer 1101 can include a first stack layer, and the first stack layer can include alternatingly stacked insulating layers 120 and gate layers 110. The first film layer 1101 further includes a channel structure 13 longitudinally penetrating the stack layer, and the first unit 12 is a storage unit.

[0096] The first film layer 1101 further comprises a first structure 1401 extending through the stack in a longitudinal direction, and the isolation structure 14 extends in a direction parallel to the surface of the substrate 100 to separate a plurality of functional units into a plurality of groups, and in a three-dimensional NAND memory device, the memory cells in the same group are stacked in a direction perpendicular to the surface of the substrate 100. The first structure 1401 in the embodiment of the present application comprises a conductor structure 142 extending in a direction perpendicular to the surface of the substrate 100 and an insulating structure 141 on the sidewall of the conductor structure 142, and in a three-dimensional NAND memory device, the conductor structure 142 can be connected with a doped structure 143 in the substrate 100 as a common source, and the first structure 1401 can be multiple to form an array, and thus the first structure 1401 can also be referred to as an ACS structure.

[0097] Each first unit 12 can comprise a gate layer 110 extending in a lateral direction, a storage layer 131 extending in a longitudinal direction and in contact with the gate layer 110, a channel layer 132 in contact with the storage layer 131, a doped structure 133 below the channel layer 132 as a source, and a drain electrode led above the channel layer 132, and the gate layers 110 stacked in the longitudinal direction belong to different first units 12, and each first unit 12 is connected in series.

[0098] Specifically, in the manufacturing method of the three-dimensional NAND memory device, the first film layer 1101 can be formed in the following manner:

[0099] An initial stack of alternating insulating layers 120 and sacrificial layers is formed on one side of the substrate 100. The number of layers of the initial stack determines the number of memory cells in the vertical direction, and the higher the integration of the device, the more layers. The sacrificial layer is silicon nitride, and the insulating layer 120 is silicon oxide, and the initial stack can be formed by chemical vapor deposition, atomic layer deposition or other suitable deposition methods.

[0100] Then, a channel hole can be etched in the initial stack to expose the substrate 100, and a channel structure can be formed in the channel hole. Each film layer in the channel structure 13 is sequentially stacked along the radial direction of the channel hole, and in the radial direction of the channel hole, the channel structure 13 can comprise, in sequence, a storage layer 131, a channel layer 132 and a filling layer 134, the storage layer can comprise a tunneling layer, a charge trapping layer and a barrier layer, wherein the material of the tunneling layer can be silicon oxide, the material of the charge trapping layer can be silicon nitride, and the material of the barrier layer can be silicon oxide, thereby forming a silicon oxide-silicon nitride-silicon oxide structure of the storage layer 131, the material of the channel layer 132 can be polysilicon, and the material of the filling layer 134 can be silicon oxide, which can be adjusted according to actual conditions.

[0101] Then, the initial stack layer can be etched to form gate line gaps (one of the aforementioned isolation trenches) penetrating the initial stack layer in a direction perpendicular to the surface of the substrate 100, and the etching method can be reactive ion etching (RIE).

[0102] Then, the gate line gaps are used to remove the sacrificial layer in the stack layer, and the gate layer 110 is filled in the hollow area formed by removing the sacrificial layer to replace the sacrificial layer with the gate layer, to obtain a first stack layer including the gate layer and the insulating layer. The material of the gate layer 110 can be tungsten, and a gate dielectric layer 111 can also be formed in the hollow area before filling the gate layer 110.

[0103] Then, an insulating structure 141 is formed on the side wall of the isolation trench, the material of the insulating structure 141 can be silicon oxide, or an organic material such as silicone rubber or silane, etc., a conductor structure 142 is filled in the isolation trench, the conductor structure 142 can be tungsten or polysilicon, etc., the insulating structure 141 can electrically isolate the conductor structure 142 and the functional unit, and the insulating structure 141 and the conductor structure 142 constitute a first structure 1401.

[0104] If the structure of the second film layer 1102 is the same as that of the first film layer 1101, the forming method of the second film layer 1102 can refer to the reference method of the first film layer 1101.

[0105] S102, a connection line 160 is formed on the side of the functional layer 11 away from the substrate 100, which can refer to the structure shown in Figure 1 and Figure 6 .

[0106] The connection line 160 can also be formed on the functional layer 11, and the connection line 160 is used to electrically connect with the functional unit. The connection line 160 can be connected with the functional unit respectively by using an interlayer interconnection structure, and the position and shape of the interlayer interconnection structure and the connection line 160 can be freely set by those skilled in the art according to the position of the functional unit. A dielectric layer can be arranged between different connection lines 160, and the material of the connection line 160 can be aluminum or other conductor materials. An isolation layer 150 can be arranged between the wiring layer and the functional layer 11.

[0107] Based on the structure of Figure 10 , the structure after forming the connection line 160 can refer to the structure shown in Figure 1 . Figure 12 Based on the structure of Figure 6 , the structure after forming the connection line 160 can refer to the structure shown in

[0108] The connection line 160 can be formed on the side of the functional layer 11 away from the substrate 100. Specifically, a dielectric layer can be formed on the side of the functional layer 11 away from the substrate 100, the dielectric layer is etched to form a wiring groove, and the wiring groove is filled with a conductor material as the connection line 160. Alternatively, a conductor layer can be formed on the side of the functional layer 11 away from the substrate 100, and the conductor layer is etched to form the connection line 160.

[0109] In the embodiments of the present application, the trace of the connection line 160 can be improved, so that the projection of the isolation structure 14 on the surface of the substrate 100 and the projection of the connection line 160 on the surface of the substrate 100 intersect, that is, the connection line 160 can be arranged directly above the isolation structure 14. The connection line 160 is usually a metal structure and can withstand stress from the surface, thereby enhancing the mechanical strength of the region where the isolation structure 14 is located and the overall mechanical strength of the semiconductor device.

[0110] Specifically, the connection line 160 can be a curve or a polyline. When the connection line 160 is a polyline, refer to FIG. 2A and FIG. 2B, which are top views of the semiconductor device provided by the embodiments of the present application. The connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100. Figure 4 and Figure 5 Specifically, the connection line 160 can be a curve or a polyline. When the connection line 160 is a polyline, refer to FIG. 2A and FIG. 2B, which are top views of the semiconductor device provided by the embodiments of the present application. The connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100. Figure 4 and Figure 5 Specifically, the connection line 160 can be a curve or a polyline. When the connection line 160 is a polyline, refer to FIG. 2A and FIG. 2B, which are top views of the semiconductor device provided by the embodiments of the present application. The connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100.

[0111] Specifically, the connection line 160 can be a curve or a polyline. When the connection line 160 is a polyline, refer to FIG. 2A and FIG. 2B, which are top views of the semiconductor device provided by the embodiments of the present application. The connection line 160 can include a first part extending in a first direction and a second part extending in a second direction, and at least one of the first part and the second part intersects with the projection of the isolation structure 14 on the surface of the substrate 100.

[0112] For example, when the first direction intersects with the extension direction of the isolation structure 14 on the surface of the substrate 100, the projection of the first part on the surface of the substrate 100 can be arranged to have an overlapping region with the projection of the isolation structure 14 on the surface of the substrate 100. Alternatively, when the second direction intersects with the extension direction of the isolation structure 14 on the surface of the substrate 100, the projection of the second part on the surface of the substrate 100 can be arranged to have an overlapping region with the projection of the isolation structure 14 on the surface of the substrate 100. Figure 5As shown, the first direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the projection of the first portion on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface, and the second direction is parallel to the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the projection of the second portion on the substrate 100 surface can be arranged to have no overlapping area with the projection of the isolation structure 14 on the substrate 100 surface.

[0113] For example, the first direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the projection of the first portion on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface, and the second direction intersects with the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the projection of the second portion on the substrate 100 surface can be arranged to have an overlapping area with the projection of the isolation structure 14 on the substrate 100 surface, as shown in Figure 4

[0114] The connection line 160 can be a periodic pattern, for example, in the extending direction of the isolation structure 14 on the substrate 100 surface in parallel, the connection line 160 is a serpentine trace or a zigzag trace, the serpentine trace can have a rounded corner or a right angle, and the serpentine trace with a rounded corner can be a wave-shaped trace.

[0115] In the embodiments of the present application, the isolation structure 14 and the connection line 160 are both multiple, and the multiple isolation structures 14 are arranged in parallel, so that the projection of at least one connection line 160 on the substrate 100 surface and the projection of one isolation structure 14 on the substrate 100 surface have multiple overlapping areas, that is, the connection line 160 is located directly above at least one isolation structure 14 (ACS), and the extending direction is consistent with the extending direction of the isolation structure 14 on the substrate 100 plane, as shown in Figure 4 Figure 5 and / or, the projection of at least one connection line 160 on the substrate 100 surface has an overlapping area with the projection of multiple isolation structures 14 on the substrate 100 surface, that is, the connection line 160 can be located directly above multiple isolation structures 14 (ACS), as shown in Figure 4 In addition, in some embodiments, multiple connection lines 160 (AL) can have overlapping areas with the projection of the same isolation structure 14 (ACS) on the substrate 100 surface, that is, multiple connection lines 160 (AL) can be arranged directly above the same isolation structure 14 (ACS), as shown in Figure 4

[0116] ​​​It can be understood that the connection line 160 is used to enhance the mechanical strength of the position where the isolation structure 14 is located, and the greater the number of overlapping areas of the projection of the connection line 160 and the isolation structure 14 on the surface of the substrate 100, the greater the enhancement of the mechanical strength by the connection line 160, and at the same time, the more the junction of the isolation structure 14 and the functional layer 11 is covered by the connection line 160, the stronger the mechanical strength of the position where the isolation structure 14 is located.

[0117] In the three-dimensional NAND memory device, the connection line 160 can include a plurality of connection lines for electrically connecting the source, the drain, the gate, the substrate, etc. in the functional unit, respectively, for example, the connection line 160 can be electrically connected to the source, the drain, the gate, the substrate, etc. in the functional unit by using the interlayer interconnection structure, respectively.

[0118] The embodiment of the present application provides a manufacturing method of a semiconductor device, a functional layer is formed on one side of a substrate, a wiring layer is formed on the side of the functional layer away from the substrate, the functional layer can include a plurality of functional units, and an isolation structure penetrating the functional layer in a direction perpendicular to the surface of the substrate, the isolation structure extends in a direction parallel to the surface of the substrate to separate the plurality of functional units into a plurality of groups; the connection line is used to electrically connect the functional unit, the isolation structure and the functional layer are formed in different ways, and the extension directions are different, so that the mechanical strength of the contact position of the isolation structure and the functional layer is poor and is easy to break, and therefore the projection of the isolation structure and the connection line on the surface of the substrate can be intersected, that is, the connection line can be arranged directly above the isolation structure, and the connection line is arranged across the isolation structure, so that the mechanical strength of the contact position of the isolation structure and the functional layer can be enhanced, and the overall mechanical strength of the semiconductor device can be enhanced.

[0119] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the difference from other embodiments.

[0120] The above is only the preferred embodiment of the present application, although the preferred embodiment of the present application is disclosed as above, however, it is not used to limit the present application. Any person skilled in the art, without departing from the scope of the technical scheme of the present application, can make many possible changes and modifications to the technical scheme of the present application by using the disclosed method and technical content, or modify the equivalent embodiment of equivalent change. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical scheme of the present application, still belongs to the protection scope of the technical scheme of the present application.

Claims

1. A semiconductor device, characterized by, The application comprises: a functional layer on one side of a substrate, and a connection line on the side of the functional layer away from the substrate; a plurality of functional units in the functional layer, and an isolation structure penetrating the functional layer in a direction perpendicular to the substrate surface, the isolation structure extending in a direction parallel to the substrate surface to separate the plurality of functional units into groups; the connection line is used to electrically connect with the functional units; the projection of the isolation structure on the substrate surface and the projection of the connection line on the substrate surface intersect; the connection line comprises a first part extending in a first direction and a second part extending in a second direction; the first direction intersects with the extension direction of the isolation structure in a direction parallel to the substrate surface, and the projection of the first part on the substrate surface and the projection of the isolation structure on the substrate surface have an overlapping area; and / or, the second direction intersects with the extension direction of the isolation structure in a direction parallel to the substrate surface, and the projection of the second part on the substrate surface and the projection of the isolation structure on the substrate surface have an overlapping area.

2. The semiconductor device according to claim 1, wherein In the extension direction of the isolation structure in a direction parallel to the substrate surface, the connection line is a meandering line or a zigzag line.

3. The semiconductor device according to any one of claims 1-2, wherein Both the isolation structure and the connection line are a plurality of structures, and the plurality of isolation structures are arranged in parallel; There are at least one overlapping area between the projection of the connection line on the substrate surface and the projection of the isolation structure on the substrate surface; and / or, there are at least one overlapping area between the projection of the connection line on the substrate surface and the projection of the plurality of isolation structures on the substrate surface.

4. The semiconductor device according to any one of Claims 1 to 2, wherein The functional layer comprises a first film layer on the side of the substrate; or, the functional layer comprises a first film layer on the side of the substrate and a second film layer on the side of the first film layer away from the substrate, and a bonding layer is arranged between the first film layer and the second film layer; the functional unit comprises a first unit in the first film layer and a second unit in the second film layer; the isolation structure comprises a first structure in the first film layer and a second structure in the second film layer.

5. The semiconductor device of claim 4, wherein, The first film layer comprises a first stack layer, the first stack layer comprises an insulating layer and a gate layer stacked in sequence, the first unit is a storage unit, and the first structure penetrates the first stack layer in a direction perpendicular to the substrate surface; the first units in the same group are stacked in a direction perpendicular to the substrate surface, the first structure comprises a conductor structure extending in a direction perpendicular to the substrate surface and an insulating structure on the sidewall of the conductor structure, and the conductor structure is connected with a doped structure in the substrate as a common source.

6. The semiconductor device according to any one of Claims 1 to 2, wherein The material of the connection line is aluminum.

7. A method of manufacturing a semiconductor device, characterized by The application comprises: forming a functional layer on one side of a substrate; the functional layer comprises a plurality of functional units, and an isolation structure penetrating the functional layer in a direction perpendicular to the substrate surface, the isolation structure extending in a direction parallel to the substrate surface to separate the plurality of functional units into groups; forming a connection line on the side of the functional layer away from the substrate; The connection line is used for electrical connection with the functional unit; a projection of the isolation structure on the substrate surface and a projection of the connection line on the substrate surface intersect; The connection line comprises a first part extending along a first direction and a second part extending along a second direction; The first direction intersects with an extension direction of the isolation structure on the parallel substrate surface, and a projection of the first part on the substrate surface has an overlapping area with a projection of the isolation structure on the substrate surface; And / or, the second direction intersects with an extension direction of the isolation structure on the parallel substrate surface, and a projection of the second part on the substrate surface has an overlapping area with a projection of the isolation structure on the substrate surface.

8. The method of claim 7, wherein, The connection line formed on the side of the functional layer away from the substrate comprises: forming a conductor layer on the side of the functional layer away from the substrate, and etching the conductor layer to form the connection line; Or, forming a dielectric layer on the side of the functional layer away from the substrate, etching the dielectric layer to obtain a wiring groove, and forming a conductor material in the wiring groove, the conductor material serving as the connection line.

9. The method of claim 7, wherein, In the extension direction of the isolation structure on the parallel substrate surface, the connection line is a zigzag or sawtooth-shaped trace.

10. The method according to any one of claims 7-9, characterized in that, Both the isolation structure and the connection line are multiple, and the multiple isolation structures are arranged in parallel; There are multiple overlapping areas between at least one projection of the connection line on the substrate surface and a projection of the isolation structure on the substrate surface; And / or, there are overlapping areas between at least one projection of the connection line on the substrate surface and multiple projections of the isolation structure on the substrate surface.

11. The method according to any one of claims 7-9, characterized in that, The functional layer comprises a first film layer on the side of the substrate; Or, the functional layer comprises a first film layer on the side of the substrate, and a second film layer on the side of the first film layer away from the substrate, and a bonding layer is arranged between the first film layer and the second film layer; the functional unit comprises a first unit in the first film layer and a second unit in the second film layer; The isolation structure comprises a first structure in the first film layer and a second structure in the second film layer; then, the functional layer formed on the side of the substrate comprises: forming a first film layer on the side of the substrate and a second film layer on the side of the other substrate; bonding the first film layer and the second film layer together through the bonding layer between the first film layer and the second film layer by using a bonding process.

12. The method of claim 11, wherein, The first film layer comprises a first stack layer, the first stack layer comprises an insulating layer and a gate layer stacked in sequence, the first unit is a storage unit, and the first structure penetrates the first stack layer in a direction perpendicular to the substrate surface; the first units in the same group are stacked in the direction perpendicular to the substrate surface, the first structure comprises a conductor structure extending in the direction perpendicular to the substrate surface and an insulating structure on the sidewall of the conductor structure, and the conductor structure is connected with a doped structure in the substrate as a common source; Then, the first film layer formed on the side of the substrate comprises: forming an initial stack layer comprising an insulating layer and a sacrificial layer stacked in sequence on the side of the substrate; forming a channel hole in the initial stack layer and forming a channel structure in the channel hole; etching the initial stack layer to obtain a gate line gap penetrating the initial stack layer along a direction perpendicular to the surface of the substrate; replacing the sacrificial layer with a gate layer through the gate line gap to obtain a first stack layer comprising a gate layer and an insulating layer; forming an insulating structure on the sidewall of the gate line gap and filling a conductor structure in the gate line gap, the conductor structure and the insulating structure constituting a first structure.

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