Semiconductor package

Abstract

A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having a chip pad, and a redistribution wiring layer covering a lower surface of the substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two heights and connected to the chip pad. The first redistribution wiring and the second redistribution wiring are arranged in a redistribution region of the redistribution wiring layer, and a dummy pattern extends in an outer region outside the redistribution region to partially cover a corner of the redistribution wiring layer, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0108511, filed on August 27, 2020 with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a fan-out semiconductor package and a method for manufacturing the same. Background Technology

[0004] A fan-out package with relatively thin thickness may include a bezel, a front redistribution wiring layer disposed on the lower surface of the bezel, and a back redistribution wiring layer disposed on the upper surface of the bezel. However, due to the different coefficients of thermal expansion between the individual components of the package, the relatively fragile corners of the outer region of the package (e.g., corner areas within 2 mm to 3 mm of the corner of the outer region) may curl up when heated, resulting in smile warping. Summary of the Invention

[0005] The example embodiment provides a semiconductor package that can reduce the overall package thickness and prevent warping.

[0006] An example embodiment provides a method for manufacturing a semiconductor package.

[0007] According to an embodiment of the present invention, a semiconductor package includes: a substrate having a cavity extending from an upper surface of the substrate to a lower surface of the substrate; at least one semiconductor chip disposed within the cavity of the substrate and having a plurality of chip pads; and a redistribution wiring layer disposed on the lower surface of the substrate and including a first redistribution wiring and a second redistribution wiring and a plurality of dummy patterns, the first redistribution wiring and the second redistribution wiring being stacked at at least two heights and connected to the plurality of chip pads. The redistribution wiring layer includes four outer surfaces, and the first redistribution wiring and the second redistribution wiring are arranged in a redistribution region of the redistribution wiring layer. The redistribution region is a region of the redistribution wiring layer defined by four lines extending parallel to the four outer surfaces of the redistribution wiring layer to form an outer rectangle of the redistribution region. The plurality of dummy patterns are disposed on an outer region of the redistribution wiring layer outside the redistribution region of the redistribution wiring layer to partially cover a plurality of corners of the redistribution wiring layer, respectively. The outermost boundary of the shape created by the outer rectangle of the redistribution region and the plurality of corners forms a non-rectangular shape.

[0008] According to an embodiment of the present invention, a semiconductor package includes: a redistribution wiring layer including a first redistribution wiring and a second redistribution wiring, and a plurality of extended patterns, wherein the first redistribution wiring and the second redistribution wiring are stacked at at least two heights; at least one semiconductor chip disposed on the redistribution wiring layer and having a plurality of chip pads electrically connected to the first redistribution wiring and the second redistribution wiring; and a molded substrate disposed on an upper surface of the redistribution wiring layer and covering the at least one semiconductor chip. The redistribution wiring layer includes four outer surfaces and the first redistribution wiring and the second redistribution wiring disposed in a redistribution region of the redistribution wiring layer. The redistribution region is a region of the redistribution wiring layer defined by four lines extending parallel to the four outer surfaces of the redistribution wiring layer to form a rectangle of the redistribution region. The plurality of extended patterns are disposed on an outer region of the redistribution wiring layer outside the redistribution region of the redistribution wiring layer to partially cover a plurality of corners of the redistribution wiring layer, respectively.

[0009] According to an embodiment of the present invention, a semiconductor package includes: a substrate having a cavity extending from an upper surface of the substrate to a lower surface of the substrate; at least one semiconductor chip disposed in the cavity of the substrate and having a plurality of chip pads; a redistribution wiring layer disposed on the lower surface of the substrate and including a first redistribution wiring and a second redistribution wiring and a plurality of dummy patterns, the first redistribution wiring and the second redistribution wiring being stacked at at least two heights and connected to the plurality of chip pads; and a plurality of external connection members disposed on an outer surface of the redistribution wiring layer and electrically connected to the first redistribution wiring and the second redistribution wiring. The redistribution wiring layer includes four outer surfaces, and the first redistribution wiring and the second redistribution wiring are arranged in a redistribution region of the redistribution wiring layer. The redistribution region is a region of the redistribution wiring layer defined by four lines extending parallel to the four outer surfaces of the redistribution wiring layer to form a rectangle of the redistribution region. The plurality of dummy patterns are disposed on an outer region of the redistribution wiring layer outside the redistribution region of the redistribution wiring layer to partially cover a plurality of corners of the redistribution wiring layer, respectively. A portion of the plurality of external connecting members is disposed on a first region of the redistribution region, the first region of the redistribution region being between the plurality of dummy patterns and the at least one semiconductor chip.

[0010] According to an example embodiment, a semiconductor package as a fan-out package may include a core substrate disposed in a region outside the semiconductor chip and a lower redistribution wiring layer covering the lower surface of the core substrate. The semiconductor package may include a first dummy pattern extending in a first outer region of the core substrate where no metal wiring has been formed to cover its corners. Furthermore, the semiconductor package may include a second dummy pattern extending in a second outer region of the redistribution wiring layer where no redistribution wiring has been formed to cover its corners.

[0011] Therefore, the first dummy pattern and the second dummy pattern can be disposed in the corners of the peripheral region of the semiconductor package to relatively increase the coefficient of thermal expansion in the corners. Thus, the first dummy pattern and the second dummy pattern can be used as reinforcing patterns to prevent the corners from curling upwards in the high-temperature range. Attached Figure Description

[0012] The exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 30 The examples described herein are non-limiting.

[0013] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment.

[0014] Figure 2 It shows Figure 1 A plan view of a semiconductor package.

[0015] Figure 3 It shows Figure 1 A plan view of a portion of the first wiring layer of the core substrate.

[0016] Figure 4 It shows Figure 3 An enlarged planar view of the first dummy pattern in the diagram.

[0017] Figure 5A It shows Figure 1 A plan view of the first redistribution layer in the redistribution layer. Figure 5B It shows Figure 1 A plan view of a portion of the first redistribution layer in the redistribution layer.

[0018] Figure 6 It shows Figure 5A An enlarged planar view of the third dummy pattern in the diagram.

[0019] Figures 7 to 20 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an example embodiment.

[0020] Figure 21 This is a cross-sectional view of a semiconductor package according to an example embodiment.

[0021] Figure 22 It shows Figure 21 A plan view of a semiconductor package.

[0022] Figure 23 It shows Figure 21 A plan view of a portion of the first redistribution layer in the redistribution layer.

[0023] Figures 24 to 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an example embodiment.

[0024] Figure 29 This is a cross-sectional view of a semiconductor package according to an example embodiment.

[0025] Figure 30 This is a cross-sectional view of a semiconductor package according to an example embodiment. Detailed Implementation

[0026] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0027] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment. Figure 2 It shows Figure 1 A plan view of a semiconductor package. Figure 3 It shows Figure 1 A plan view of a portion of the first wiring layer of the core substrate. Figure 4 It shows Figure 3 An enlarged planar view of the first dummy pattern in the diagram. Figure 5A It shows Figure 1 A plan view of the first redistribution layer in the redistribution layer. Figure 5B It shows Figure 1 A plan view of a portion of the first redistribution layer in the redistribution layer. Figure 6 It shows Figure 5A An enlarged planar view of the third dummy pattern in the diagram. Figure 1 It is along Figure 2 The cross-sectional view taken by line A-A' in the diagram. Figure 3 and Figure 5B It shows Figure 2 A plan view of part "B" in the diagram.

[0028] refer to Figures 1 to 6The semiconductor package 10 may include a core substrate 100 having a cavity 106, at least one semiconductor chip 200 disposed in the cavity 106 of the core substrate 100, and a redistribution wiring layer 300 on the lower surface 104 of the core substrate 100. The semiconductor package 10 may also include a back redistribution wiring layer disposed on the upper surface 102 of the core substrate 100 and external connection members 400 disposed on the outer surface of the redistribution wiring layer 300.

[0029] In an example embodiment, the semiconductor package 10 may include a core substrate 100, which is configured to surround a base substrate of the semiconductor chip 200. The core substrate 100 may include core interconnect wiring 120 disposed in a fan-out region outside the region where the semiconductor chip 200 is disposed. The core interconnect wiring 120 can serve as an electrical connection path for the semiconductor chip 200. Therefore, the semiconductor package 10 can be configured as a fan-out package. In an embodiment, the semiconductor package 10 may be configured as a cell package on which a second package is stacked.

[0030] Semiconductor package 10 may be a system-in-package (SIP). For example, one or more semiconductor chips may be disposed in core substrate 100. Logic chips and / or memory chips, including logic circuitry, may be disposed in cavity 106 of core substrate 100. The logic chip may be a controller that controls the memory chip. The memory chip may include various memory circuits, such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, phase-change random access memory (PRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), etc.

[0031] In an example embodiment, the core substrate 100 may have a first surface (upper surface) 102 and a second surface (lower surface) 104 opposite to each other. The core substrate 100 may have a cavity 106 in its intermediate region. The cavity 106 may extend from the first surface 102 of the core substrate 100 to the second surface 104 of the core substrate 100.

[0032] like Figure 2As shown, the semiconductor package 10 may include a first side surface S1 and a second side surface S2 extending in a second direction (Y direction) and spaced apart from each other in a first direction (X direction) different from the second direction (e.g., perpendicular), and a third side surface S3 and a fourth side surface S4 extending in the first direction and spaced apart from each other in the second direction. When viewed in a plan view, the semiconductor package 10 may have a rectangular shape. The semiconductor package may include four corners C1, C2, C3, and C4, corresponding to the four corners of the core substrate 100. In the following, reference numerals C1, C2, C3, and C4 also indicate the four corners of the core substrate 100. The outer surface of the core substrate 100 and the outer surface of the redistribution wiring layer 300 corresponding to the outer surface of the core substrate 100 may constitute the first to fourth side surfaces S1, S2, S3, and S4 of the semiconductor package 10. The first to fourth side surfaces S1, S2, S3, and S4 of the semiconductor package 10 may correspond to the four outer surfaces of the core substrate 100 and the four outer surfaces of the redistribution wiring layer 300. In the following figures, reference numerals S1, S2, S3 and S4 also indicate the four outer surfaces of the core substrate 100 and the redistribution wiring layer 300, respectively.

[0033] The core substrate 100 may include a border region FR defined by the periphery of the cavity 106 and the four outer surfaces S1, S2, S3, and S4 of the core substrate 100. For example, the border region FR may be the area of ​​the core substrate between the periphery of the cavity 106 and the four outer surfaces S1, S2, S3, and S4 of the core substrate 100. The border region FR may include a first wiring region WR1, a first outer region PR1 outside the first wiring region WR1, and a first inner region IR1 inside the first wiring region WR1.

[0034] In an example embodiment, the core substrate 100 may include a plurality of stacked insulating layers 110 and 112 and core interconnect wiring 120 disposed in the insulating layers. The plurality of core interconnect wiring 120 may be disposed in a fan-out region outside the region where the semiconductor chip (die) 200 is located for electrical connection to the semiconductor chip 200.

[0035] For example, the core substrate 100 may include a first insulating layer 110 and a second insulating layer 112 stacked on the first insulating layer 110. The core connection wiring 120 may include a first metal wiring 122, a first contact 123, a second metal wiring 124, a second contact 125, and a third metal wiring 126. The first metal wiring 122 may be disposed on a second surface 104 of the core substrate 100, corresponding to the lower surface of the first insulating layer 110. In an embodiment, the first metal wiring 122 may be buried in the first insulating layer 110, and at least a portion of the first metal wiring 122 may be exposed from the second surface 104. The third metal wiring 126 may be disposed on a first surface 102 of the core substrate 100, corresponding to the upper surface of the second insulating layer 112. In an embodiment, at least a portion of the third metal wiring 126 may be disposed above the first surface 102 and may be exposed from the first surface 102. The number and arrangement of the insulating layers and core connection wiring are not limited thereto. Ordinal numbers such as "first," "second," and "third" may be used solely as labels to distinguish certain elements, steps, etc., from one another. Terms not used in the specification, such as "first" or "second," may still be referred to as "first" or "second" in the claims. Furthermore, terms mentioned with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0036] In an example embodiment, the core substrate 100 may include at least two stacked wiring layers. The core substrate 100 may include dummy patterns disposed in at least one wiring layer. The dummy patterns may be arranged in a first outer region PR1. When the semiconductor package 10 has first to fourth corners C1, C2, C3, and C4, four first dummy patterns 132 may extend from the four corners 122b-C1, 122b-C2, 122b-C3, and 122b-C4 of the first ground pattern 122b toward the four corners C1, C2, C3, and C4 of the core substrate 100, respectively. The first dummy pattern 132 may be an extension of the first ground pattern 122b toward the four corners C1, C2, C3, and C4 of the core substrate 100, respectively. The various dummy patterns discussed herein may also be referred to as “extension patterns”.

[0037] For example, the core substrate 100 may include first to third wiring layers at three different heights. The first wiring layer of the core connection wiring 120 may include a first metal wiring 122 disposed in a first wiring region WR1 and a first dummy pattern 132 disposed in a first outer region PR1. The second wiring layer of the core connection wiring 120 may include a second metal wiring 124 disposed in the first wiring region WR1 and a second dummy pattern 134 disposed in the first outer region PR1. The third wiring layer of the core connection wiring 120 may include a third metal wiring 126 disposed in the first wiring region WR1. Therefore, dummy patterns may be respectively disposed in the first and second wiring layers of the first to third wiring layers of the core substrate 100. The first dummy pattern 132 may be formed on the same plane (e.g., the first lower insulating layer 310) as the first metal wiring 122. In an embodiment, the first dummy pattern 132 may be formed at the same height as the first metal wiring 122. The second dummy pattern 134 may be formed on the same plane (e.g., the first insulating layer 110) as the second metal wiring 124. In an embodiment, the second dummy pattern 134 may be formed at the same height as the second metal wiring 124.

[0038] like Figure 3 and Figure 4 As shown, the first metallic wiring 122 may include a first signal pattern 122a and a first ground pattern 122b. For simplicity, Figure 3 and Figure 4 A corner adjacent to the first corner C1 of the core substrate 100 is shown and described below. A similar description will apply to other corners adjacent to corners C2, C3, and C4 of the core substrate 100. In an embodiment, the first ground pattern 122b may be electrically grounded, and the first signal pattern 122a may be part of a signal path connected to the semiconductor chip 200. A first dummy pattern 132 corresponding to an extended corner of the first ground pattern 122b may be grounded and suppress corner warping of the core substrate 100. The first metal wiring 122 may also include a first power pattern (not shown). The first ground pattern 122b may include a metal pattern having a plurality of vias 123H. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal column shape.

[0039] The first signal pattern 122a, the first ground pattern 122b, and the first power pattern can be arranged in the first wiring area WRI. The first dummy pattern 132 can be disposed in the first outer area PR1 and can extend from the first corner 122b-C1 of the first ground pattern 122b toward the first corner C1 of the core substrate 100 to cover at least a portion of the core substrate 100 between the first corner C1 of the core substrate 100 and the first corner 122b-C1 of the first ground pattern 122b. In an embodiment, the first dummy pattern 132 can extend along the first extension line E1, wherein the first corner 122b-C1 of the first ground pattern 122b and the first corner 132-C1 of the first dummy pattern 132 are disposed on the first extension line E1. In an embodiment, the first corner C1 of the core substrate 100 can also be disposed on the first extension line E1. The inventive concept is not limited thereto. In an embodiment, the first corner C1 of the core substrate 100 is not located on the first extension line E, and the first extension line E1 intersects one of the outer surfaces S1 and S3 connected to the first corner C1 of the core substrate 100. The first dummy pattern 132 may be integrally formed with the first ground pattern 122b. Therefore, the first dummy pattern 132 may include the same metallic material (e.g., copper (Cu)) as the first ground pattern 122b. The thickness of the first dummy pattern 132 may be the same as the thickness of the first ground pattern 122b. For example, the thickness of the first dummy pattern 132 may have a value of approximately 3 μm to approximately 6 μm. Terms such as “approximately” or “about” can reflect amounts, dimensions, orientations, or layouts that vary only in a small relative manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, a range from “approximately 0.1 to approximately 1” can encompass ranges such as deviations of 0%–5% near 0.1 and 0%–5% near 1, particularly where such deviations maintain the same effect as the listed ranges.

[0040] The first outer region PR1 of the border region FR (i.e., the core substrate 100) may have a first width X1 in the second direction (Y direction) and a second width X2 in the first direction (X direction). The first outer region PR1 may be the area of ​​the border region FR between the outer boundary of the core substrate 100 (i.e., the outer surfaces S1 to S4 of the core substrate 100) and the outer boundary of the first ground pattern 122b (i.e., the outer surfaces 122b-S1, 122b-S2, 122b-S3, and 122b-S4 of the first ground pattern 122b). The first width X1 and the second width X2 may be the same or different from each other. For example, the first width X1 and the second width X2 of the first outer region PR1 may have values ​​from 100 μm to 200 μm. In an embodiment, the first width X1 and the second width X2 of the first outer region PR1 may have the same value of 150 μm.

[0041] The first dummy pattern 132 may include a first portion 132-1 and a second portion 132-2. The first portion 132-1 may be the region defined by the first side surface 132-S1 of the first dummy pattern 132, the third side surface 122b-S3 of the first grounding pattern 122b, and the first extension line E1. The second portion 132-2 may be the region defined by the second side surface 132-S2 of the first dummy pattern 132, the first side surface 122b-S1 of the first grounding pattern 122b, and the first extension line E1. The first portion 132-1 may extend a first length L1 away from the first corner 132-C1 of the first dummy pattern 132 in a first direction (X direction). As the first side surface 132-S1 of the first portion 132-1 extends away from the first corner 132-C1 of the first dummy pattern 132 in the first direction (X direction), the first side surface 132-S1 of the first portion 132-1 moves closer to the third side surface 122b-S3 of the first grounding pattern 122b to meet the third side surface 122b-S3 at the first meeting point MP1. The distance between the first corner 132-C1 of the first dummy pattern 132 and the first meeting point MP1 in the first direction can be a first length L1. The second portion 132-2 can extend away from the first corner 132-C1 of the first dummy pattern 132 in the second direction (Y direction) by a second length L2. As the second side surface 132-S2 of the second portion 132-2 extends away from the first corner 132-C1 of the first dummy pattern 132 in the second direction (Y direction), the second side surface 132-S2 of the second portion 132-2 moves closer to the first side surface 122b-S1 of the first grounding pattern 122b to meet the first side surface 122b-S1 at the second confluence point MP2. The distance between the first corner 132-C1 of the first dummy pattern 132 and the second confluence point MP2 in the second direction can be a second length L2. For example, the first length L1 and the second length L2 can be the same or different from each other. In an embodiment, the first length L1 and the second length L2 can have the same value from about 1.4 mm to about 2.9 mm.

[0042] The width W1 (width in the Y direction) of the first portion gradually increases from the first junction point MP1 toward the first corner 132-C1 of the first dummy pattern 132, and gradually decreases toward the first corner 132-C1 of the first dummy pattern 132 beyond the first corner 122b-C1 of the first grounding pattern 122b. The width W2 (width in the X direction) of the second portion gradually increases from the second junction point MP2 toward the first corner 132-C1 of the first dummy pattern 132, and gradually decreases toward the first corner 132-C1 of the first dummy pattern 132 beyond the first corner 122b-C1 of the first grounding pattern 122b. The widths W1 of the first portion and W2 of the second portion can increase linearly or non-linearly toward the first corner 132-C1 of the first dummy pattern 132.

[0043] The distance in a first direction between the first corner C1 of the core substrate 100 and the first confluence point MP1 where the first side surface 132-S1 of the first dummy pattern 132 and the third side surface 122b-S3 of the first ground pattern 122b intersects with each other can be a first distance M1. The distance in a second direction between the first corner C1 of the core substrate 100 and the second confluence point MP2 where the second side surface 132-S2 of the first dummy pattern 132 and the first side surface 122b-S1 of the first ground pattern 122b intersects with each other can be a second distance M2. The first distance M1 and the second distance M2 can be the same or different from each other. For example, the first distance M1 and the second distance M2 can have values ​​from about 1.5 mm to about 3 mm. In an embodiment, the first distance M1 and the second distance M2 can have the same value of about 2 mm.

[0044] The first dummy pattern 132 may be spaced apart from the outer surface of the core substrate 100. For example, the shortest distance in a first direction between the first dummy pattern 132 (i.e., the first corner 132-C1 of the first dummy pattern 132) and the first side surface S1 of the core substrate 100 may be a first distance D1, and the shortest distance in a second direction between the first dummy pattern 132 (i.e., the first corner 132-C1 of the first dummy pattern 132) and the third side surface S3 of the core substrate 100 may be a second distance D2. The first distance D1 and the second distance D2 may be the same or different from each other. For example, the first distance D1 and the second distance D2 may have values ​​from about 30 μm to about 90 μm. In an embodiment, the first distance D1 and the second distance D2 have the same value of about 75 μm.

[0045] In an embodiment, the second metal wiring 124 may have a configuration similar to that of the first metal wiring 122. The second metal wiring 124 may include a second signal pattern and a second ground pattern. The second metal wiring 124 may also include a second power pattern. The second ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal column shape.

[0046] A second signal pattern, a second ground pattern, and a second power pattern can be arranged in the first wiring area WR1. A second dummy pattern 134, having a similar configuration to the first dummy pattern 132, can correspond to the extended corner of the second ground pattern and can be disposed in the first outer area PR1 to cover at least a portion of the corner adjacent to the first corner C1 of the core substrate 100. Four second dummy patterns 134 can extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the core substrate 100, respectively. The second dummy pattern 134 can be integrally disposed with the second ground pattern. The second dummy pattern 134 can include the same metallic material (e.g., copper (Cu)) as the second ground pattern. The thickness of the second dummy pattern 134 can be the same as the thickness of the second ground pattern.

[0047] The second dummy pattern 134 may have substantially the same or similar dimensions as the first dummy pattern 132. Therefore, a description of the second dummy pattern will be omitted. Terms such as “same,” “equal,” “planar,” or “coplanar” used herein when referring to orientation, layout, position, shape, size, quantity, or other measures do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measures, but are intended to cover substantially the same orientation, layout, position, shape, size, quantity, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates, the term “substantially” may be used herein to emphasize this meaning. For example, entries described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0048] In an exemplary embodiment, the semiconductor chip 200 may be disposed within the cavity 106 of the core substrate 100. The sidewalls of the semiconductor chip 200 may be spaced apart from the inner sidewalls of the cavity 106. Therefore, a gap may be formed between the sidewalls of the semiconductor chip 200 and the inner sidewalls of the cavity 106.

[0049] The semiconductor chip 200 may include a substrate and chip pads 210 on an active surface, the active surface being a first surface of the substrate. In an embodiment, transistors of the semiconductor chip 200 may be formed in a region adjacent to the active surface of the substrate. The semiconductor chip 200 may be arranged such that the first surface on which the chip pads 210 are formed faces downward, and the chip pads 210 may be disposed on a second surface 104 of the core substrate 100. The first surface of the semiconductor chip 200 may be coplanar with the second surface 104 of the core substrate 100. The second surface of the semiconductor chip 200, opposite to the first surface, may be at the same height or at a different height from the first surface 102 of the core substrate 100.

[0050] A molding layer 140 may be disposed on the first surface 102 of the core substrate 100 to cover the semiconductor chip 200. The molding layer 140 may be formed to fill the gap between the sidewall of the semiconductor chip 200 and the inner sidewall of the cavity 106. Therefore, the molding layer 140 may cover the second surface of the semiconductor chip 200, the first surface 102 of the core substrate 100, and the inner sidewall of the cavity 106.

[0051] For example, the molding layer 140 may include insulating materials such as epoxy resin (thermosetting dielectric material), photo-imageable dielectric (PID) material, insulating films such as Ajinomoto polymer film (ABF), etc.

[0052] In an exemplary embodiment, the redistribution layer 300 may be disposed on the second surface 104 of the core substrate 100 and the first surface of the semiconductor chip 200. The redistribution layer 300 may include redistribution wiring 302 electrically connected to the chip pads 210 of the semiconductor chip 200 and the core connection wiring 120 of the core substrate 100. The redistribution wiring 302 may be disposed on the second surface 104 of the core substrate 100 to serve as front-side redistribution wiring. The redistribution layer 300 may be a front-side redistribution layer of a fan-out package.

[0053] The redistribution routing layer 300 may include a redistribution region RR. The redistribution region RR may include a second routing region WR2 and a second outer region PR2 outside the second routing region WR2.

[0054] Specifically, the redistribution wiring layer 300 may include a first redistribution wiring layer disposed on the first lower insulating layer 310, the first redistribution wiring layer having a first redistribution wiring 312 disposed in the second wiring region WR2 and a third dummy pattern 314 disposed in the second outer region PR2.

[0055] A first lower insulating layer 310 may be disposed on a second surface 104 of the core substrate 100 and may have first openings that expose chip pads 210 of the semiconductor chip 200 and first metal wirings 122 of the core connection wiring 120, respectively. A first redistribution wiring 312 may be disposed on the first lower insulating layer 310, and some portions of the first redistribution wiring 312 may contact the chip pads 210 and the first metal wirings 122 through the first openings, respectively. A third dummy pattern 314 may be formed on the same plane (e.g., the first lower insulating layer 310) as the first redistribution wiring 312. It should be understood that when an element is referred to as "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element or "contacting" or "touching" another element, there are no intermediate elements at the contact point.

[0056] The redistribution wiring layer 300 may include a second redistribution wiring layer disposed on the second lower insulating layer 320, the second redistribution wiring layer having a second redistribution wiring 322 disposed in the second wiring region WR2 and a fourth dummy pattern 324 disposed in the second outer region PR2.

[0057] The second lower insulating layer 320 may be disposed on the first lower insulating layer 310 and may have second openings that expose the first redistribution wiring 312. The second redistribution wiring 322 may be disposed on the second lower insulating layer 320, and portions of the second redistribution wiring 322 may contact the first redistribution wiring 312 through the second openings. The fourth dummy pattern 324 may be formed on the same plane (e.g., the second lower insulating layer 320) as the second redistribution wiring 322. In an embodiment, the fourth dummy pattern 324 may be formed at the same height as the second redistribution wiring 322.

[0058] The redistribution wiring layer 300 may include a third redistribution wiring layer disposed on a third lower insulating layer 330, the third redistribution wiring layer having third redistribution wiring 332 disposed in the second wiring region WR2.

[0059] The third lower insulating layer 330 may be disposed on the second lower insulating layer 320, and may have a third opening that exposes the second redistribution wiring 322. The third redistribution wiring 332 may be disposed on the third lower insulating layer 330, and some portions of the third redistribution wiring 332 may contact the second redistribution wiring 322 through the third opening.

[0060] The redistribution layer 300 may include a fourth lower insulating layer 340 disposed on the third lower insulating layer 330 to expose portions of the third redistribution wiring 332. The fourth lower insulating layer 340 may serve as a passivation layer. Bump pads (not shown) may be disposed on the portions of the third redistribution wiring 332 exposed by the fourth lower insulating layer 340 as follows. The exposed portions of the third redistribution wiring 332 may serve as landing pads, i.e., package pads.

[0061] like Figure 5A , Figure 5B and Figure 6 As shown, the first redistribution wiring 312 may include a third signal pattern 312a and a third ground pattern 312b. For simplicity, Figure 5B and Figure 6 The corner adjacent to the first corner C1 of the redistribution wiring layer 300 is shown and described below. A similar description will apply to other corners adjacent to corners C2, C3, and C4 of the redistribution wiring layer 300. In an embodiment, the third ground pattern 312b may be electrically grounded, and the third signal pattern 312a may be part of a signal path connected to the semiconductor chip 200. A third dummy pattern 314 corresponding to an extended corner of the third ground pattern 312b may be grounded and suppress corner warping of the redistribution wiring layer 300. The first redistribution wiring 312 may also include a third power pattern (not shown). The third ground pattern 312b may include a metal pattern having a plurality of vias 313. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal column shape.

[0062] The third signal pattern 312a, the third ground pattern 312b, and the third power pattern can be arranged in the second wiring area WR2. The third dummy pattern 314 can be disposed in the second outer area PR2 and can extend from the first corner 312b-C1 of the third ground pattern 312b toward the first corner C1 of the redistribution wiring layer 300 to cover at least a portion of the redistribution wiring layer 300 between the first corner C1 of the redistribution wiring layer 300 and the first corner 312b-C1 of the third ground pattern 312b. In an embodiment, the third dummy pattern 314 can extend along the second extension line E2, wherein the first corner 312b-C1 of the third ground pattern 312b and the first corner 314-C1 of the third dummy pattern 314 are disposed on the second extension line E2. In an embodiment, the first corner C1 of the redistribution wiring layer 300 can also be disposed on the second extension line E2. The inventive concept is not limited thereto. In this embodiment, the first corner C1 of the redistribution layer 300 is not located on the second extension line E2, and the second extension line E2 intersects one of the outer surfaces S1 and S3 connected to the first corner C1 of the redistribution layer 300. The third dummy pattern 314 can be similarly arranged adjacent to the other corners C2, C3, and C4 of the redistribution layer 300, and for simplicity, the description of the dummy patterns adjacent to the corners C2, C3, and C4 of the redistribution layer 300 can be omitted. The third dummy pattern 314 may include the same metallic material (e.g., copper (Cu)) as the third ground pattern 312b. The thickness of the third dummy pattern 314 may be the same as the thickness of the third ground pattern 312b. For example, the thickness of the third dummy pattern 314 may have a value from approximately 3 μm to approximately 6 μm.

[0063] The second outer region PR2 may have a third width X3 in the second direction (Y direction) and a fourth width X4 in the first direction (X direction). The second outer region PR2 may be the region of the redistribution region RR between the outer boundary of the redistribution wiring layer 300 (i.e., the outer surfaces S1 to S4 of the redistribution wiring layer 300) and the outer boundary of the third ground pattern 312b (i.e., the outer surfaces 312b-S1, 312b-S2, 312b-S3, 312b-S4 of the third ground pattern 312b). The third width X3 and the fourth width X4 may be the same as or different from each other. For example, the third width X3 and the fourth width X4 of the second outer region PR2 may have values ​​from 100 μm to 200 μm. In an embodiment, the third width X3 and the fourth width X4 of the second outer region PR2 have a value of 150 μm.

[0064] The third dummy pattern 314 may include a third portion 314-1 and a fourth portion 314-2. The third portion 314-1 may be the region defined by the first side surface 314-S1 of the third dummy pattern 314, the third side surface 312b-S3 of the third grounding pattern 312b, and the second extension line E2. The fourth portion 314-2 may be the region defined by the second side surface 314-S2 of the third dummy pattern 314, the first side surface 312b-S1 of the third grounding pattern 312b, and the second extension line E2. The third portion 314-1 may extend a third length L3 in the first direction (X direction) away from the first corner 314-C1 of the third dummy pattern 314. As the first side surface 314-S1 of the third part 314-1 extends away from the first corner 314-C1 of the third dummy pattern 314 in the first direction (X direction), the first side surface 314-S1 of the third part 314-1 moves closer to the third side surface 312b-S3 of the third grounding pattern 312b to merge with the third side surface 312b-S3 at the third merging point MP3. The distance between the first corner 314-C1 of the third dummy pattern 314 and the third merging point MP3 in the first direction can be a third length L3. The fourth part 314-2 can extend a fourth length L4 away from the first corner 314-C1 of the third dummy pattern 314 in the second direction (Y direction). As the second side surface 314-S2 of the fourth portion 314-2 extends away from the first corner 314-C1 of the third dummy pattern 314 in the second direction (Y direction), the second side surface 314-S2 of the fourth portion 314-2 moves closer to the first side surface 312b-S1 of the third grounding pattern 312b to merge with the first side surface 312b-S1 at the fourth merging point MP4. The distance in the second direction between the first corner 314-C1 of the third dummy pattern 314 and the fourth merging point MP4 can be a fourth length L4. For example, the third length L3 and the fourth length L4 can be the same or different from each other. In an embodiment, the third length L3 and the fourth length L4 can have the same value from 1.4 mm to 2.9 mm. The width W3 (width in the Y direction) of the third part can gradually increase towards the first corner 314-C1 of the third dummy pattern 314, and can gradually decrease towards the first corner 314-C1 of the third dummy pattern 314 beyond the first corner 312b-C1 of the third grounding pattern 312b. The width W4 (width in the X direction) of the fourth part can gradually increase towards the first corner 314-C1 of the third dummy pattern 314, and can gradually decrease towards the first corner 314-C1 of the third dummy pattern 314 beyond the first corner 312b-C1 of the third grounding pattern 312b.

[0065] The widths W3 of the third part and W4 of the fourth part can increase linearly or non-linearly toward the first corner 314-C1 of the third dummy pattern 314.

[0066] The distance in the first direction between the first corner C1 of the redistribution wiring layer 300 and the third confluence point MP3 where the first side surface 314-S1 of the third dummy pattern 314 and the third side surface 312b-S3 of the third grounding pattern 312b intersects with each other can be a third distance M3. The distance in the second direction between the first corner C1 of the redistribution wiring layer 300 and the fourth confluence point MP4 where the second side surface 314-S2 of the third dummy pattern 314 and the first side surface 312b-S1 of the third grounding pattern 312b intersects with each other can be a fourth distance M4. The third distance M3 and the fourth distance M4 can be the same or different from each other. For example, the third distance M3 and the fourth distance M4 can have values ​​from about 1.5 mm to about 3 mm. In an embodiment, the third distance M3 and the fourth distance M4 have the same value of about 2 mm.

[0067] The third dummy pattern 314 may be spaced apart from the outer surface of the redistribution wiring layer 300. For example, the shortest distance in a first direction between the third dummy pattern 314 (i.e., the corner 314-C1 of the third dummy pattern 314) and the first side surface S1 of the redistribution wiring layer 300 may be a third distance D3, and the shortest distance in a second direction between the third dummy pattern 314 (i.e., the corner 314-C1 of the third dummy pattern 314) and the third side surface S3 of the redistribution wiring layer 300 may be a fourth distance D4. The third distance D3 and the fourth distance D4 may be the same or different from each other. For example, the third distance D3 and the fourth distance D4 may have values ​​from about 30 μm to about 90 μm. In an embodiment, the third distance D3 and the fourth distance D4 have the same value of about 75 μm.

[0068] In an embodiment, the second redistribution wiring 322 may have a configuration similar to that of the first redistribution wiring 312. The second redistribution wiring 322 may include a fourth signal pattern and a fourth ground pattern. The second redistribution wiring 322 may also include a fourth power pattern. The fourth ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0069] A fourth signal pattern, a fourth ground pattern, and a fourth power pattern can be arranged in the second wiring area WR2. A fourth dummy pattern 324, having a similar configuration to the third dummy pattern 314, can correspond to the extended corner of the fourth ground pattern and can be disposed in the second outer area PR2 to cover at least a portion of the corner adjacent to the corner C1 of the redistribution wiring layer 300. Four fourth dummy patterns 324 can extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The fourth dummy pattern 324 can be integrally disposed with the fourth ground pattern. The fourth dummy pattern 324 can include the same metallic material (e.g., copper (Cu)) as the fourth ground pattern. The thickness of the fourth dummy pattern 324 can be the same as the thickness of the fourth ground pattern.

[0070] The fourth dummy pattern 324 may have substantially the same or similar dimensions as the third dummy pattern 314. Therefore, a description of the fourth dummy pattern will be omitted.

[0071] For example, the first to fourth lower insulating layers may include polymer layers, dielectric layers, etc. The first to third redistribution wiring may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

[0072] Therefore, the redistribution wiring layer 300 can be disposed on the second surface 104 of the core substrate 100, and can include redistribution wiring electrically connected to the chip pads 210 and the core connection wiring 120, respectively. The redistribution wiring layer 300 can cover the second surface 104 of the core substrate 100 disposed in a region outside the semiconductor chip 200. Some of the redistribution wirings in the redistribution wiring 302 can electrically connect the chip pads 210 of the semiconductor chip 200 to the core connection wiring 120 of the core substrate 100. It is understood that the number, size, arrangement, etc. of the lower insulating layer of the redistribution wiring are shown by way of example, and therefore are not limited thereto.

[0073] In an exemplary embodiment, a back redistribution wiring layer may be disposed on a first surface 102 of the core substrate 100, and may include back redistribution wiring 352 electrically connected to the core connection wiring 120. The back redistribution wiring 352 may be disposed on the first surface 102 of the core substrate 100 to serve as back redistribution wiring.

[0074] The back redistribution wiring 352 can be disposed on the molding layer 140 and can contact the third metal wiring 126 through the fourth opening. The upper insulating layer 350 can be disposed on the molding layer 140 to expose some portions of the back redistribution wiring 352.

[0075] For example, the upper insulating layer 350 may include insulating materials such as epoxy resin (thermosetting dielectric material), photo-imageable dielectric (PID) material, insulating film such as Ajinomoto polymer film (ABF), etc.

[0076] The third dummy pattern 314 and the fourth dummy pattern 324 can be disposed in the front redistribution wiring layer 300 to be arranged in the second outer region PR2, while the metal pattern such as the dummy pattern is not disposed in the back redistribution wiring layer in the second outer region PR2, and the back redistribution wiring 352 can be disposed in the back redistribution wiring layer to be arranged only in the second wiring region WR2.

[0077] The back redistribution wiring layer having the upper insulating layer 350 may include a material with a relatively high coefficient of thermal expansion, such as ABF, and the core substrate 100 having wiring and the front redistribution wiring layer may include materials with relatively low coefficients of thermal expansion. In an embodiment, the back redistribution wiring layer may have a higher coefficient of thermal expansion than the core substrate 100. Dummy patterns 132 and 134 and 314 and 324 respectively disposed in the wiring layer of the core substrate 100 and the front redistribution wiring layer 300 below the core substrate 100 can structurally reinforce the core substrate 100 and the front redistribution wiring layer 300, which are prone to bending at high temperatures, thereby preventing warping that may be caused by such a difference in the coefficients of thermal expansion between the back redistribution wiring layer and the core substrate 100 or between the back redistribution wiring layer and the front redistribution wiring layer 300.

[0078] In an example embodiment, external connection members 400 may be disposed on package pads (i.e., exposed portions of the third redistribution wiring 332) on the outer surface of the redistribution wiring layer 300. For example, external connection members 400 may include solder balls. The diameter of the solder balls may have a value from 300 μm to 500 μm. For example, semiconductor package 10 may be mounted on a module substrate (not shown) using solder balls to form a memory module.

[0079] As described above, the semiconductor package 10, as a fan-out panel-level package, may include a core substrate 100 disposed in a region outside the semiconductor chip 200 and a lower redistribution wiring layer 300 covering a second surface 104 of the core substrate 100. The semiconductor package 10 may include a first dummy pattern 132 and a second dummy pattern 134, which are disposed in a first outer region PR1 where no metal wiring is formed, and extend toward corners C1, C2, C3, and C4 of the core substrate 100. The first dummy pattern 132 and the second dummy pattern 134 may partially cover the corners of the first outer region PR1 of the core substrate 100 adjacent to corners C1, C2, C3, and C4 of the core substrate 100. The semiconductor package 10 may include a third dummy pattern 314 and a fourth dummy pattern 324, which are disposed in a second outer region PR2 where no redistribution wiring is formed, and extend toward the corners C1, C2, C3, and C4 of the redistribution wiring layer 300. The third dummy pattern 314 and the fourth dummy pattern 324 may partially cover the corners of the second outer region PR2 of the redistribution wiring layer 300 adjacent to the corners C1, C2, C3, and C4 of the redistribution wiring layer 300.

[0080] Dummy patterns 132, 134, 314 and 324 adjacent to corners C1, C2, C3 and C4 in the peripheral region of semiconductor package 10 can be used as reinforcement patterns to compensate for the difference in thermal expansion coefficients between the back redistribution wiring layer and the core substrate 100 or between the back redistribution wiring layer and the redistribution wiring layer 300, thereby preventing the corners of the core substrate 100 or the redistribution wiring layer 300 from curling up in the high temperature range.

[0081] The manufacturing process will be explained below. Figure 1 Methods for semiconductor packaging.

[0082] Figures 7 to 20 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an example embodiment. Figure 7 This is a plan view showing a panel in which multiple core substrates are formed.

[0083] Figure 8 , Figures 10 to 13 and Figures 15 to 20 It is along Figure 7 The cross-sectional view taken by line CC′ in the image. Figure 9 It shows Figure 8 A plan view of a portion of the first wiring layer. Figure 14 It shows Figure 13 A plan view of a portion of the first redistributed wiring layer. Figure 9 and Figure 14 It shows Figure 7 The floor plan of part "D1" in the diagram.

[0084] refer to Figures 7 to 9 First, a panel P in which multiple core substrates 100 are formed can be prepared.

[0085] In an example embodiment, the core substrate 100 can be used as a support frame for electrical connections in a semiconductor package having a fan-out panel-level package configuration. The panel P may include a frame region FR on which the core substrate 100 is formed, and a scribe-through region (i.e., a cut region CR surrounding the frame region FR). As described later, the panel P may be sawn along the cut region CR that divides the frame region FR to form a separate core substrate 100.

[0086] The border region FR (i.e., the core substrate 100) may include a first wiring region WR1, a first outer region PR1 outside the first wiring region WR1, and a first inner region IR1 inside the first wiring region WR1. The first outer region PR1 may have a first width X1 in a second direction (Y direction) and a second width X2 in a first direction (X direction). In an embodiment, the first outer region PR1 may extend along the outer boundary line of the border region FR. The outer boundary line of the border region FR may be the outer boundary line of the first outer region PR1. The first width X1 and the second width X2 may be the same as or different from each other. For example, the first width X1 and the second width X2 of the first outer region PR1 may have values ​​from 100 μm to 200 μm. In an embodiment, the first width X1 and the second width X2 of the first outer region PR1 have the same value of 150 μm.

[0087] The core substrate 100 may have a first surface 102 and a second surface 104 opposite to each other. The core substrate 100 may have a cavity 106 in a central region. As described later, the cavity 106 may have a region for accommodating at least one semiconductor chip.

[0088] The core substrate 100 may include a plurality of stacked insulating layers 110 and 112 and core interconnect wiring 120 disposed in the insulating layers. The core interconnect wiring 120 may extend through the core substrate 100 from a first surface 102 to a second surface 104 to serve as an electrical connection path. For example, the core interconnect wiring 120 may serve as a fan-out region outside the area where a semiconductor chip 200 (i.e., a semiconductor die) is disposed, and may be used for electrical connection between the semiconductor chip 200 mounted in the cavity 106 and another semiconductor device connected to the core substrate 100.

[0089] For example, the core substrate 100 may include a first insulating layer 110 and a second insulating layer 112 stacked on the first insulating layer 110. The core connection wiring 120 may include a first metal wiring 122, a first contact 123, a second metal wiring 124, a second contact 125, and a third metal wiring 126. The first metal wiring 122 may be disposed on a second surface 104 of the core substrate 100, corresponding to the lower surface of the first insulating layer 110. In an embodiment, the first metal wiring 122 may be buried in the first insulating layer 110, and at least a portion of the first metal wiring 122 may be exposed from the second surface 104. The third metal wiring 126 may be disposed on a first surface 102 of the core substrate 100, corresponding to the upper surface of the second insulating layer 112. In an embodiment, the third metal wiring 126 may be disposed above the first surface 102 and may be exposed from the first surface 102. The number and arrangement of the insulating layers and core connection wiring are not limited thereto.

[0090] In an example embodiment, the core substrate 100 may include at least two stacked wiring layers. The core substrate 100 may include dummy patterns disposed in at least one wiring layer.

[0091] like Figure 8 and 9 As shown, the core substrate 100 may include first to third wiring layers at three different heights. The first wiring layer of the core connection wiring 120 may include a first metal wiring 122 disposed in a first wiring region WR1 and a first dummy pattern 132 disposed in a first outer region PR1. The second wiring layer of the core connection wiring 120 may include a second metal wiring 124 disposed in the first wiring region WR1 and a second dummy pattern 134 disposed in the first outer region PR1. The third wiring layer of the core connection wiring 120 may include a third metal wiring 126 disposed in the first wiring region WR1. The first dummy pattern 132 and the second dummy pattern 134 may be formed in the first and second wiring layers of the core substrate 100, respectively. The first dummy pattern 132 may be formed on the same plane (e.g., the first lower insulating layer 310) as the first metal wiring 122. In an embodiment, the first dummy pattern 132 may be formed at the same height as the first metal wiring 122. The second dummy pattern 134 may be formed on the same plane (e.g., the first insulating layer 110) as the second metallic wiring 124. In an embodiment, the second dummy pattern 134 may be formed at the same height as the second metallic wiring 124.

[0092] like Figure 9As shown, the first metal wiring 122 may include a first signal pattern 122a and a first ground pattern 122b. The first metal wiring 122 may also include a first power pattern (not shown). The first ground pattern 122b may include a metal pattern having a plurality of vias 123H. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0093] A first signal pattern 122a, a first ground pattern 122b, and a first power pattern may be arranged in a first wiring area WR1. A first dummy pattern 132 may extend from the outer end portion of the first ground pattern 122b in a first outer area PR1 to cover at least a portion of the core substrate 100 adjacent to a corner C1 of the core substrate 100. Four first dummy patterns 132 may extend to cover at least a portion of the core substrate 100 adjacent to the four corners C1, C2, C3, and C4 of the core substrate 100, respectively. In an embodiment, the first dummy pattern 132 may be arranged together with the first ground pattern 122b such that the first dummy pattern 132 can be grounded. For example, the first dummy pattern 132 is an extension corner of the first ground pattern 122b, extending from the first corner 122b-C1 of the first ground pattern 122b toward the first corner C1 of the core substrate 100. The first dummy pattern 132 may include the same metallic material (e.g., copper (Cu)) as the first ground pattern 122b. The thickness of the first dummy pattern 132 can be the same as the thickness of the first ground pattern 122b. For example, the thickness of the first dummy pattern 132 can have a value from about 3 μm to about 6 μm.

[0094] The first dummy pattern 132 may include a first portion extending from a first corner C1 of the core substrate 100 along a first direction (X direction) and a second portion extending from the first corner C1 of the core substrate 100 along a second direction (Y direction). The first portion may extend a first length L1 away from the first corner C1 of the core substrate 100 in the first direction (X direction), and the second portion may extend a second length L2 away from the first corner C1 of the core substrate 100 in the second direction (Y direction). The first length L1 and the second length L2 may be the same as or different from each other. For example, the first length L1 and the second length L2 may have values ​​from about 1.4 mm to about 2.9 mm.

[0095] The first dummy pattern 132 can extend from the outer surface of the core substrate 100 by a first distance M1 in a first direction (X direction) and a second distance M2 in a second direction (Y direction). The first distance M1 and the second distance M2 can be the same as or different from each other. For example, the first distance M1 and the second distance M2 can have values ​​from 1.5 mm to about 3 mm. In an embodiment, the first distance M1 and the second distance M2 can have the same value of about 2 mm.

[0096] The first dummy pattern 132 may be spaced apart from the outer surface of the core substrate 100 by a first distance D1 in a first direction (X direction) and a second distance D2 in a second direction (Y direction). The first distance D1 and the second distance D2 may be the same as or different from each other. For example, the first distance D1 and the second distance D2 may have values ​​from about 30 μm to about 90 μm. In an embodiment, the first distance D1 and the second distance D2 have the same value of about 75 μm.

[0097] Similarly, the second metal wiring 124 may include a second signal pattern and a second ground pattern. The second metal wiring 124 may also include a second power pattern. The second ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0098] A second signal pattern, a second ground pattern, and a second power pattern may be arranged in the first wiring region WR1. A second dummy pattern 134 may extend from the outer end portion of the second ground pattern in the first outer region PR1 to cover at least a portion of the corner adjacent to corner C1 of the core substrate 100. Four second dummy patterns 134 may extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the core substrate 100, respectively. The second dummy pattern 134 may include the same metallic material as the second ground pattern (e.g., copper (Cu)). The thickness of the second dummy pattern 134 may be the same as the thickness of the second ground pattern. For example, the thickness of the second dummy pattern 134 may have a value from about 3 μm to about 6 μm.

[0099] The second dummy pattern 134 may have substantially the same or similar dimensions as the first dummy pattern 132. Therefore, a description of the second dummy pattern will be omitted.

[0100] refer to Figure 10 and Figure 11 The semiconductor chip 200 can be arranged in the cavity 106 of the core substrate 100, and then a molding layer 140 can be formed on the first surface 102 of the core substrate 100 to cover the semiconductor chip 200.

[0101] like Figure 10 As shown, panel P can be disposed on barrier strip 20. The second surface 104 of core substrate 100 can be adhered to barrier strip 20. For example, approximately 200 to approximately 6,000 dies can be disposed in cavities 106 of panel P. As described later, a dicing process can be performed to saw panel P to complete a fan-out panel-level package. Alternatively, multiple semiconductor chips 200 can be disposed within a single cavity 106.

[0102] The semiconductor chip 200 may include a substrate and chip pads 210 on an active surface, the active surface being a first surface of the substrate. In an embodiment, transistors of the semiconductor chip 200 may be formed in a region adjacent to the active surface of the substrate. The semiconductor chip 200 may be arranged such that the first surface on which the chip pads 210 are formed faces downward. The first surface of the semiconductor chip 200 may be coplanar with the second surface 104 of the core substrate 100.

[0103] The semiconductor chip 200 can be disposed within the cavity 106 of the core substrate 100. The sidewalls of the semiconductor chip 200 can be separated from the inner sidewalls of the cavity 106. Therefore, a gap can be formed between the sidewalls of the semiconductor chip 200 and the inner sidewalls of the cavity 106.

[0104] like Figure 11 As shown, a molding layer 140 can be formed on the first surface 102 of the core substrate 100 to cover the semiconductor chip 200. The molding layer 140 can be formed to fill the gap between the sidewalls of the semiconductor chip 200 and the inner sidewalls of the cavity 106. Therefore, the molding layer 140 can cover the second surface of the semiconductor chip 200 opposite to the first surface, the first surface 102 of the core substrate 100, and the inner sidewalls of the cavity 106.

[0105] For example, the molding layer 140 may include insulating materials such as epoxy resin, photo-imageable dielectric (PID) materials, and insulating films such as Ajinomoto polymer film (ABF).

[0106] refer to Figures 12 to 17 A redistribution wiring layer 300 can be formed on the second surface 104 of the core substrate 100 and the first surface of the semiconductor chip 200. The redistribution wiring layer 300 may include redistribution wiring 302 electrically connected to the chip pads 210 of the semiconductor chip 200 and the core connection wiring 120, respectively. The redistribution wiring layer 300 may be the front redistribution wiring layer of a fan-out package.

[0107] The redistribution routing layer 300 may include a redistribution region RR, which may be divided by a cut region CR. The redistribution region RR may include a second routing region WR2 and a second outer region PR2 outside the second routing region WR2. The second outer region PR2 may have a third width X3 in a second direction (Y direction) and a fourth width X4 in a first direction (X direction). In an embodiment, the second outer region PR2 extends along the outer boundary line of the redistribution region RR. The outer boundary line of the redistribution region RR may be the outer boundary line of the second outer region PR2. The third width X3 and the fourth width X4 may be the same as or different from each other. For example, the third width X3 and the fourth width X4 of the second outer region PR2 may have values ​​from 100 μm to 200 μm. In an embodiment, the third width X3 and the fourth width X4 of the second outer region PR2 have a value of 150 μm.

[0108] like Figure 12 As shown, after removing the blocking strip 20, it can be flipped. Figure 11 In the structure, a first lower insulating layer 310 can be formed on the second surface 104 of the core substrate 100, and then the first lower insulating layer 310 can be patterned to form first openings 311 of the first metal wiring 122 that expose the chip pads 210 of the semiconductor chip 200 and the core connection wiring 120, respectively.

[0109] For example, the first lower insulating layer 310 may include a polymer layer, a dielectric layer, etc. The first lower insulating layer 310 may be formed by vapor deposition, spin coating, etc.

[0110] like Figure 13 and Figure 14 As shown, the first redistribution routing layer may include a first redistribution routing 312 disposed in the second routing region WR2 and a third dummy pattern 314 disposed in the second outer region PR2. The first redistribution routing layer may be formed on the first lower insulating layer 310. The first redistribution routing 312 may contact the chip pad 210 and the first metal wiring 122 through the first opening 311, respectively. The third dummy pattern 314 may be formed on the same plane as the first redistribution routing 312 (e.g., on the first lower insulating layer 310).

[0111] In an example embodiment, the first redistribution wiring 312 may be formed on portions of the first lower insulating layer 310, the chip pad 210, and the first metal wiring 122. The first redistribution wiring 312 can be formed by forming a seed layer on a portion of the first lower insulating layer 310 and in a first opening, patterning the seed layer, and performing an electroplating process. Therefore, at least a portion of the first redistribution wiring 312 can contact the chip pad 210 and the first metal wiring 122 through the first opening. The third dummy pattern 314 can be formed using the same process as the first redistribution wiring 312.

[0112] For example, the first redistribution wiring may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

[0113] like Figure 14 As shown, the first redistribution wiring 312 may include a third signal pattern 312a and a third ground pattern 312b. Additionally, the first redistribution wiring 312 may also include a third power pattern (not shown). The third ground pattern 312b may include a metal pattern having multiple vias 313. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0114] The third signal pattern 312a, the third ground pattern 312b, and the third power pattern can be arranged in the second wiring area WR2. The third dummy pattern 314 can extend from the outer end of the third ground pattern 312b in the second outer area PR2 to cover at least a portion of the corner adjacent to corner C1 of the redistribution wiring layer 300. Four third dummy patterns 314 can extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The third dummy pattern 314 can include the same metallic material (e.g., copper (Cu)) as the third ground pattern 312b. The thickness of the third dummy pattern 314 can be the same as the thickness of the third ground pattern 312b. For example, the thickness of the third dummy pattern 314 can have a value from approximately 3 μm to approximately 6 μm.

[0115] The third dummy pattern 314 may include a third portion extending away from the first corner C1 of the redistribution routing layer 300 in the first direction (X direction) and a fourth portion extending away from the first corner C1 of the redistribution routing layer 300 in the second direction (Y direction). The third portion may extend a third length L3 from the first corner C1 of the redistribution routing layer 300 in the first direction (X direction), and the fourth portion may extend a fourth length L4 from the first corner C1 of the redistribution routing layer 300 in the second direction (Y direction).

[0116] The third dummy pattern 314 can extend from the outer surface of the redistribution wiring layer 300 by a third distance M3 in a first direction (X direction) and a fourth distance M4 in a second direction (Y direction). For example, the third distance M3 and the fourth distance M4 can have values ​​from approximately 1.5 mm to approximately 3 mm. The third distance M3 and the fourth distance M4 can be the same as or different from each other. In an embodiment, the third distance M3 and the fourth distance M4 have values ​​of approximately 2 mm.

[0117] The third dummy pattern 314 may be spaced apart from the outer surface of the redistribution wiring layer 300 by a third distance D3 in a first direction (X direction) and a fourth distance D4 in a second direction (Y direction). For example, the third distance D3 and the fourth distance D4 may have values ​​from approximately 30 μm to approximately 90 μm. The third distance D3 and the fourth distance D4 may be the same as or different from each other. In an embodiment, the third distance D3 and the fourth distance D4 may have values ​​of approximately 75 μm.

[0118] like Figure 15 and Figure 16 As shown, a second lower insulating layer 320 can be formed on the first lower insulating layer 310, and then the second lower insulating layer 320 can be patterned to form second openings 321 that expose the first redistribution wiring 312. A second redistribution wiring layer can then be formed on the second lower insulating layer 320, the second redistribution wiring layer including second redistribution wiring 322 arranged in the second wiring region WR2 and a fourth dummy pattern 324 arranged in the second outer region PR2. The second redistribution wiring 322 can contact the first redistribution wiring 312 through the second openings 321. The fourth dummy pattern 324 can be formed on the same plane as the second redistribution wiring 322.

[0119] The second redistribution wiring 322 may include a fourth signal pattern and a fourth ground pattern. The second redistribution wiring 322 may also include a fourth power pattern. The fourth ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0120] A fourth signal pattern, a fourth ground pattern, and a fourth power pattern may be arranged in the second wiring area WR2. A fourth dummy pattern 324 may extend from the outer end of the fourth ground pattern in the second outer area PR2 to cover at least a portion of the corner adjacent to corner C1 of the redistribution wiring layer 300. Four fourth dummy patterns 324 may extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The fourth dummy pattern 324 may include the same metallic material (e.g., copper (Cu)) as the fourth ground pattern. The thickness of the fourth dummy pattern 324 may be the same as the thickness of the fourth ground pattern.

[0121] The fourth dummy pattern 324 may have substantially the same or similar dimensions as the third dummy pattern 314. Therefore, a description of the fourth dummy pattern will be omitted.

[0122] like Figure 17 As shown, a third lower insulating layer 330 can be formed on the second lower insulating layer 320, and then the third lower insulating layer 330 can be patterned to form third openings that expose the second redistribution wiring 322. A third redistribution wiring layer can then be formed on the third lower insulating layer 330, the third redistribution wiring layer including the third redistribution wiring 332 arranged in the second wiring region WR2. A fourth lower insulating layer 340 can then be formed on the third lower insulating layer 330 to expose portions of the third redistribution wiring 332.

[0123] The fourth lower insulating layer 340 can be used as a passivation layer. Bump pads (not shown) and a bump metal layer (UBM) can be formed on the portion of the third redistribution wiring 332 exposed by the fourth lower insulating layer 340.

[0124] refer to Figure 18 and Figure 19 A back redistribution wiring layer can be formed on the first surface 102 of the core substrate 100. The back redistribution wiring layer includes back redistribution wiring 352 electrically connected to the core connection wiring 120.

[0125] like Figure 18 As shown, it can be flipped Figure 17 The structure in the core substrate 100 can then form a fourth opening 142 in the molding layer 140 on the first surface 102 of the core substrate 100 to expose some portions of the third metal wiring 126.

[0126] like Figure 19 As shown, back-side redistribution wiring 352 can be formed on the molding layer 140 to directly contact the third metal wiring 126. Then, an upper insulating layer 350 can be formed on the molding layer 140 to expose some portions of the back-side redistribution wiring 352.

[0127] For example, the upper insulating layer may include insulating materials such as epoxy resin (thermosetting dielectric material), photo-imageable dielectric (PID) material, insulating films such as Ajinomoto polymer film (ABF), etc.

[0128] The third dummy pattern 314 and the fourth dummy pattern 324 can be formed in the front redistribution wiring layer 300 to be arranged in the second outer region PR2, while the metal pattern, such as the dummy pattern, is not formed in the back redistribution wiring layer in the second outer region PR2, and the back redistribution wiring 352 can be formed in the back redistribution wiring layer to be arranged only in the second wiring region WR2.

[0129] refer to Figure 20 An external connection member 400 can be formed on the outer surface of the redistribution wiring layer 300 to be electrically connected to the redistribution wiring 302.

[0130] For example, solder balls, serving as external connection components, can be disposed on the portion of the third redistribution wiring. In this case, the portion of the third redistribution wiring 332 can be used as landing pads, corresponding to package pads. Therefore, semiconductor manufacturing processes can be performed to form a redistribution wiring layer 300 with fan-out solder ball landing pads.

[0131] Then, a sawing process can be performed on the core substrate 100 to form a separate fan-out panel-level package, which includes the core substrate 100 and a redistribution wiring layer 300 formed on the lower surface of the core substrate 100.

[0132] Figure 21 This is a cross-sectional view of a semiconductor package according to an example embodiment. Figure 22 It shows Figure 21 A plan view of a semiconductor package. Figure 23 It shows Figure 21 A plan view of a portion of the first redistribution layer in the redistribution layer. Figure 21 It is along Figure 22 The cross-sectional view taken from line EE′ in the diagram. Figure 23 It shows Figure 22 A partial plan view of the "F" in the diagram. This semiconductor package can be compared with a reference. Figure 1 The semiconductor packages described are substantially the same or similar, except for the configuration of the molded substrate used in place of the core substrate. Therefore, the same reference numerals will refer to the same or similar elements, and any further repetition of descriptions regarding these elements will be omitted.

[0133] refer to Figures 21 to 23The semiconductor package 11 may include a redistribution wiring layer 300, at least one semiconductor chip 200 disposed on the redistribution wiring layer 300, and a molded substrate 500 covering at least one side surface of the semiconductor chip 200 on the upper surface of the redistribution wiring layer. The semiconductor package 11 may also include an external connection member 400 disposed on the lower surface of the redistribution wiring layer 300.

[0134] In an example embodiment, the semiconductor chip 200 may include a plurality of chip pads 210 on an active surface corresponding to a first surface of the semiconductor chip 200. In this embodiment, transistors of the semiconductor chip 200 may be formed in a region adjacent to the active surface of the substrate. The semiconductor chip 200 may be housed in a molding substrate 500 such that the first surface on which the chip pads 210 are formed faces the redistribution wiring layer 300. The first surface of the semiconductor chip 200 and a second surface opposite to the first surface may be exposed by the molding substrate 500.

[0135] The redistribution wiring layer 300 may be disposed on the lower surface 504 (i.e., the second surface) of the molding substrate 500 and may include redistribution wiring 302 electrically connected to the chip pads 210 of the semiconductor chip 200.

[0136] The redistribution routing layer 300 may include a redistribution region RR. The redistribution region RR may include a third routing region WR3 and a third outer region PR3 outside the third routing region WR3.

[0137] The redistribution wiring layer 300 may include a first redistribution wiring layer disposed on a first lower insulating layer 310. The first redistribution wiring layer has a first redistribution wiring 312 disposed in a third wiring region WR3 and a third dummy pattern 314 disposed in a third outer region PR3. The third dummy pattern 314 may be on the same plane as the first redistribution wiring 312.

[0138] The redistribution wiring layer 300 may include a second redistribution wiring layer disposed on the second lower insulating layer 320. The second redistribution wiring layer has a second redistribution wiring 322 disposed in a third wiring region WR3 and a fourth dummy pattern 324 disposed in a third outer region PR3. The fourth dummy pattern 324 may be on the same plane as the second redistribution wiring 322.

[0139] The redistribution wiring layer 300 may include a third redistribution wiring layer disposed on a third lower insulating layer 330, the third redistribution wiring layer having third redistribution wiring 332 disposed in a third wiring region WR3.

[0140] The redistribution wiring layer 300 may include a fourth lower insulating layer 340 disposed on the third lower insulating layer 330 to expose some portions of the third redistribution wiring 332.

[0141] like Figure 23 As shown, the first redistribution wiring 312 may include a third signal pattern 312a and a third ground pattern 312b. The first redistribution wiring 312 may also include a third power pattern (not shown). The third ground pattern 312b may include a metal pattern having a plurality of vias 313.

[0142] The third signal pattern 312a, the third ground pattern 312b, and the third power pattern can be arranged in the third wiring area WR3. The third dummy pattern 314 can extend from the outer end of the third ground pattern 312b in the third outer area PR3 to cover at least a portion of the corner adjacent to corner C1 of the redistribution wiring layer 300. Four third dummy patterns 314 can extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The third dummy pattern 314 can include the same metallic material (e.g., copper (Cu)) as the third ground pattern 312b. The thickness of the third dummy pattern 314 can be the same as the thickness of the third ground pattern 312b.

[0143] The third outer region PR3 may have a third width X3 in the second direction (Y direction) and a fourth width X4 in the first direction (X direction). The third outer region PR3 may extend along the outer boundary line of the redistribution region RR (i.e., the side surfaces S1 to S4 of the semiconductor package 10). The outer boundary line of the redistribution region RR may be the outer boundary line of the third outer region PR3. The third width X3 and the fourth width X4 may be the same or different from each other. For example, the third width X3 and the fourth width X4 of the third outer region PR3 may have values ​​from 100 μm to 200 μm. In an embodiment, the third width X3 and the fourth width X4 of the third outer region PR3 have the same value of 150 μm.

[0144] The third dummy pattern 314 may include a third portion extending away from the first corner C1 of the redistribution wiring layer 300 in the first direction (X direction) and a fourth portion extending away from the first corner C1 of the redistribution wiring layer 300 in the second direction (Y direction). The third portion may extend a third length L3 away from the first corner C1 of the redistribution wiring layer 300 in the first direction (X direction), and the fourth portion may extend a fourth length L4 away from the first corner C1 of the redistribution wiring layer 300 in the second direction (Y direction). The third length L3 and the fourth length L4 may be the same as or different from each other. For example, the third length L3 and the fourth length L4 may have values ​​from 1.4 mm to 2.9 mm.

[0145] Similarly, the second redistribution wiring 322 may include a fourth signal pattern and a fourth ground pattern. The second redistribution wiring 322 may also include a fourth power pattern. The fourth ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0146] A fourth signal pattern, a fourth ground pattern, and a fourth power pattern may be arranged in the third wiring area WR3. A fourth dummy pattern 324 may extend from the outer end of the fourth ground pattern in the third outer area PR3 to cover at least a portion of the corner adjacent to corner C1 of the redistribution wiring layer 300. Four fourth dummy patterns 324 may extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The fourth dummy pattern 324 may be integrally formed with the fourth ground pattern. The fourth dummy pattern 324 may include the same metallic material as the fourth ground pattern (e.g., copper (Cu)). The thickness of the fourth dummy pattern 324 may be the same as the thickness of the fourth ground pattern.

[0147] The fourth dummy pattern 324 may have substantially the same or similar dimensions as the third dummy pattern 314. Therefore, a description of the fourth dummy pattern will be omitted.

[0148] The manufacturing process will be explained below. Figure 21 Methods for semiconductor packaging.

[0149] Figures 24 to 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an example embodiment. Figure 24 This is a plan view of the wafer substrate. Figure 25 , Figure 26 and Figure 28 It is along Figure 24 The cross-sectional view taken from line GG′ in the diagram. Figure 27 It shows Figure 26 A plan view of a portion of the first redistributed wiring layer. Figure 27 It shows Figure 24 A plan view of part "H" in the diagram.

[0150] refer to Figure 24 and Figure 25 After the semiconductor chip 200 is arranged on the wafer substrate W, a molding substrate 500 can be formed on the wafer substrate W to cover the semiconductor chip 200.

[0151] In an example embodiment, the wafer substrate W may be a base substrate on which a plurality of semiconductor chips 200 are disposed, and a molding substrate 500 is formed to cover the semiconductor chips. The wafer substrate W may have a shape corresponding to a wafer on which semiconductor manufacturing processes are performed. The wafer substrate W may include, for example, a silicon substrate, a glass substrate, or a non-metallic or metallic plate.

[0152] The wafer substrate W may include a redistribution region RR on which a redistribution wiring layer is formed, and a dicing region CR surrounding the redistribution region RR. As described later, the redistribution wiring layer and molding components formed on the wafer substrate W may be sawed along the dicing region CR that divides the redistribution region RR into separate redistribution regions.

[0153] In an example embodiment, the semiconductor chip 200 may include a plurality of chip pads 210 on an active surface, which is a first surface of the semiconductor chip 200. In this embodiment, transistors of the semiconductor chip 200 may be formed in a region adjacent to the active surface of the substrate. The semiconductor chip 200 may be disposed on a wafer substrate W such that a second surface opposite to the first surface on which the chip pads 210 are formed faces the wafer substrate W.

[0154] Although not shown in the figure, the semiconductor chip 200 can be attached to the wafer substrate W via a release layer. The release layer may include a polymer tape used as a temporary adhesive. The release layer may include a material that can lose its adhesiveness by exposure to light or heat.

[0155] In an example embodiment, a molding substrate 500 may be formed on a wafer substrate W to cover the semiconductor chip 200. For example, the molding substrate 500 may include epoxy molding compound (EMC). The molding substrate 500 may be formed by molding processes, screen printing processes, lamination processes, etc. The molding substrate 500 may expose the first surface of the semiconductor chip 200 and cover the side surfaces of the semiconductor chip 200.

[0156] refer to Figure 26 and Figure 27 A redistribution wiring layer 300 can be formed on the molded substrate 500.

[0157] In an example embodiment, a first lower insulating layer 310 may be formed on a molded substrate 500, and the first lower insulating layer 310 may be patterned to have first openings in the chip pads 210 that expose the semiconductor chip 200. The first lower insulating layer 310 may include a polymer layer, a dielectric layer, etc. For example, the first lower insulating layer may include a photosensitive insulating layer such as a photoimageable dielectric (PID). The first lower insulating layer 310 may be formed by a vapor deposition process, a spin coating process, etc.

[0158] Then, a first redistribution wiring layer can be formed on the first lower insulating layer 310. The first redistribution wiring layer includes a first redistribution wiring 312 arranged in the third wiring region WR3 and a third dummy pattern 314 arranged in the third outer region PR3. The first redistribution wiring 312 can contact the chip pads 210 through the first opening. The third dummy pattern 314 can be formed on the same plane as the first redistribution wiring 312 (e.g., the first lower insulating layer 310).

[0159] The first redistribution wiring 312 can be formed on some portions of the first lower insulating layer 310 and the chip pad 210. The first redistribution wiring 312 can be formed by forming a seed layer on a portion of the first lower insulating layer 310 and in a first opening, patterning the seed layer, and performing an electroplating process. Therefore, at least a portion of the first redistribution wiring 312 can contact the chip pad 210 through the first opening. The third dummy pattern 314 can be formed using the same process as the first redistribution wiring 312.

[0160] For example, the first redistribution wiring may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

[0161] Then, a second lower insulating layer 320 with a second opening exposing the first redistribution wiring 312 can be formed on the first lower insulating layer 310, and a second redistribution wiring layer can be formed on the second lower insulating layer 320. The second redistribution wiring layer includes second redistribution wiring 322 arranged in a third wiring region WR3 and a fourth dummy pattern 324 arranged in a third outer region PR3. The fourth dummy pattern 324 can be formed on the same plane (e.g., on the second lower insulating layer 320) as the second redistribution wiring 322. In an embodiment, the fourth dummy pattern 324 can be formed at the same height as the second redistribution wiring 322.

[0162] Then, a third lower insulating layer 330 with a third opening exposing the second redistribution wiring 322 can be formed on the second lower insulating layer 320, and a third redistribution wiring layer can be formed on the third lower insulating layer 330, the third redistribution wiring layer including the third redistribution wiring 332 arranged in the third wiring region WR3.

[0163] Then, a fourth lower insulating layer 340 can be formed on the third lower insulating layer 330 to expose some portions of the third redistribution wiring 332. The fourth lower insulating layer 340 can serve as a passivation layer. Bump pads (not shown) and a bump metal layer (UBM) can be formed on the portions of the third redistribution wiring 332 exposed by the fourth lower insulating layer 340. In this case, the exposed portions of the third redistribution wiring 332 can serve as landing pads, corresponding to package pads.

[0164] like Figure 27 As shown, the first redistribution wiring 312 may include a third signal pattern 312a and a third ground pattern 312b. The first redistribution wiring 312 may also include a third power pattern (not shown). The third ground pattern 312b may include a metal pattern having a plurality of vias 313. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0165] The third signal pattern 312a, the third ground pattern 312b, and the third power pattern can be arranged in the third wiring region WR3. The third dummy pattern 314 can extend from the outer end of the third ground pattern 312b in the third outer region PR3 to cover at least a portion of the corner adjacent to corner C1 of the redistribution wiring layer 300. Four third dummy patterns 314 can extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The third dummy pattern 314 can include the same metallic material (e.g., copper (Cu)) as the third ground pattern 312b. The thickness of the third dummy pattern 314 can be the same as the thickness of the third ground pattern 312b. For example, the thickness of the third dummy pattern 314 can have a value from approximately 3 μm to approximately 6 μm.

[0166] The third dummy pattern 314 may include a third portion extending away from the first corner C1 of the redistribution routing layer 300 in the first direction (X direction) and a fourth portion extending away from the first corner C1 of the redistribution routing layer 300 in the second direction (Y direction). The third portion may extend a third length L3 away from the first corner C1 of the redistribution routing layer 300 in the first direction (X direction), and the fourth portion may extend a fourth length L4 away from the first corner C1 of the redistribution routing layer 300 in the second direction (Y direction). The third length L3 and the fourth length L4 may be the same as or different from each other.

[0167] The third dummy pattern 314 can extend from the outer surface of the redistribution wiring layer 300 by a third distance M3 in a first direction (X direction) and a fourth distance M4 in a second direction (Y direction). The third distance M3 and the fourth distance M4 can be the same as or different from each other. For example, the third distance M3 and the fourth distance M4 can have values ​​from about 1.5 mm to about 3 mm. In an embodiment, the third distance M3 and the fourth distance M4 can have values ​​of about 2 mm.

[0168] Similarly, the second redistribution wiring 322 may include a fourth signal pattern and a fourth ground pattern. The second redistribution wiring 322 may also include a fourth power pattern. The fourth ground pattern may include a metal pattern with multiple vias. For example, the metal pattern may include a metallic material such as copper (Cu). The vias may have a cylindrical or polygonal shape.

[0169] A fourth signal pattern, a fourth ground pattern, and a fourth power pattern may be arranged in the third wiring area WR3. A fourth dummy pattern 324 may extend from the outer end of the fourth ground pattern in the third outer area PR3 to cover at least a portion of the corner adjacent to the first corner C1 of the redistribution wiring layer 300. Four fourth dummy patterns 324 may extend to cover at least a portion of the four corners adjacent to the four corners C1, C2, C3, and C4 of the redistribution wiring layer 300, respectively. The fourth dummy pattern 324 may be integrally formed with the fourth ground pattern. The fourth dummy pattern 324 may include the same metallic material as the fourth ground pattern (e.g., copper (Cu)). The thickness of the fourth dummy pattern 324 may be the same as the thickness of the fourth ground pattern.

[0170] The fourth dummy pattern 324 may have substantially the same or similar dimensions as the third dummy pattern 314. Therefore, a description of the fourth dummy pattern will be omitted.

[0171] refer to Figure 28 External connection members 400 can be formed on the redistribution layer 300 to electrically connect to the redistribution wiring 302. For example, solder balls, serving as external connection members 400, can be disposed on the portion of the third redistribution wiring 332. The portion of the third redistribution wiring 332 can serve as a landing pad, which is a package pad connected to the external connection member 400. The external connection member 400 can be disposed in the region of the redistribution region RR between the dummy patterns 314 and 324 and the semiconductor chip 200 (see reference). Figure 1 When the semiconductor package 10 is viewed in a plan view, a portion of the external connection member 400 may be disposed on the area of ​​the third wiring region WR3 and the semiconductor chip 200.

[0172] Therefore, semiconductor manufacturing processes can be performed on a region of the wafer substrate W that has the same size as each die in the wafer to form a redistribution wiring layer 300 with fan-out solder ball landing pads.

[0173] The redistribution layer 300 and the molding substrate 500 can then be cut to form a separate semiconductor package. The redistribution layer 300 can be separated by a sawing process to complete a fan-out package.

[0174] The molding components can be removed by a sawing process to expose the second surface of the semiconductor chip 200, thereby forming a molding substrate 500. Alternatively, the molding substrate 500 can be formed to cover the side surfaces of the semiconductor chip 200.

[0175] Figure 29 This is a cross-sectional view showing a semiconductor package according to an example embodiment. This semiconductor package can be compared with a reference... Figure 1 The semiconductor packages described are substantially the same or similar, except for the configuration of the additional second package. Therefore, the same reference numerals will refer to the same or similar elements, and any further repetitive descriptions of the aforementioned elements will be omitted.

[0176] refer to Figure 29 The semiconductor package 12 may include a first package and a second package 600 stacked on the first package. The first package may include a core substrate 100, a semiconductor chip 200, a lower redistribution layer 300 (i.e., a front redistribution layer), and an upper redistribution layer (i.e., a back redistribution layer). The first package may be related to a reference... Figure 1 The described unit packages are basically the same or similar.

[0177] In an example embodiment, the second package 600 may be stacked on the first package via conductive connection members 650.

[0178] The second package 600 may include a second package substrate 610, a second semiconductor chip 620 and a third semiconductor chip 630 mounted on the second package substrate 610, and a molding member 642 covering the second semiconductor chip 620 and the third semiconductor chip 630 on the second package substrate 610.

[0179] The second package 600 can be stacked on the first package via a conductive connection member 650. For example, the conductive connection member 650 may include solder balls, conductive bumps, etc. The conductive connection member 650 may be disposed between the back redistribution wiring 352 of the upper redistribution wiring layer (i.e., the back redistribution wiring layer) and the second bonding pad 614 of the second package substrate 610. Therefore, the first package and the second package 600 can be electrically connected to each other via the conductive connection member 650.

[0180] The second semiconductor chip 620 and the third semiconductor chip 630 can be stacked on the second packaging substrate 610 via adhesive members. A bonding wire 640 can electrically connect the chip pads 622 and 632 of the second semiconductor chip 620 and the third semiconductor chip 630 to the first bonding pad 612 of the second packaging substrate 610. The second semiconductor chip 620 and the third semiconductor chip 630 can be electrically connected to the second packaging substrate 610 via the bonding wire 640.

[0181] Although the figure shows a second package 600 including two semiconductor chips mounted in a wire-bonded manner, the number of semiconductor chips in the second package, the mounting method, etc. are not limited thereto.

[0182] Figure 30 This is a cross-sectional view showing a semiconductor package according to an example embodiment. This semiconductor package can be compared with a reference... Figure 21 The semiconductor packages described are substantially the same or similar, except for the configuration of the additional second package. Therefore, the same reference numerals will refer to the same or similar elements, and any further repetitive descriptions of the aforementioned elements will be omitted.

[0183] refer to Figure 30 Semiconductor package 13 may include a first package and a second package 600 stacked on the first package. The first package may include a redistribution layer 300, a semiconductor chip 200 disposed on the redistribution layer 300, and a molded substrate 500 covering at least one side surface of the semiconductor chip 200 on the upper surface of the redistribution layer 300. The first package may be related to a reference... Figure 21 The described unit packages are basically the same or similar.

[0184] In an example embodiment, the conductive connection post 550 may extend through at least a portion of the molded substrate 500 in a region outside the semiconductor chip 200. The conductive connection post 550 may be a molded through-hole (MTV) extending from a first surface 502 of the molded substrate 500 to a second surface 504. Additionally, the first package may also include a back redistribution wiring layer disposed on the first surface 502 of the molded substrate 500 and having back redistribution wiring 560.

[0185] The back redistribution wiring 560 can be disposed on the upper surface of the conductive connection posts 550 exposed from the first surface 502 of the molded substrate 500. The conductive connection posts 550 can be electrically connected to the back redistribution wiring 560.

[0186] The first redistribution wiring 312 of the redistribution wiring layer 300 can be disposed on the lower surface of the conductive connection pillars 550 exposed from the second surface 504 of the molding substrate 500. The conductive connection pillars 550 can be electrically connected to the first redistribution wiring 312.

[0187] The second package 600 can be stacked on the first surface 502 of the molded substrate 500 via conductive connection members 650. For example, the conductive connection members 650 may include solder balls, conductive bumps, etc. The conductive connection members 650 may be arranged between the back redistribution wiring 560 on the conductive connection post 550 and the second bonding pad 614 of the second package substrate 610. Therefore, the first package and the second package 600 can be electrically connected to each other via the conductive connection members 650.

[0188] Semiconductor packages can include semiconductor devices such as logic devices or memory devices. Logic devices can include central processing units (CPUs), main processing units (MPUs), or application processors (APs), as well as volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, and ReRAM devices.

[0189] The foregoing describes exemplary embodiments and should not be construed as limiting them. While some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims.

Claims

1. A semiconductor package, comprising: A substrate having a cavity extending from the upper surface of the substrate to the lower surface of the substrate; At least one semiconductor chip is disposed in the cavity of the substrate and has a plurality of chip pads; as well as A redistribution wiring layer is disposed on the lower surface of the substrate and includes a first redistribution wiring, a second redistribution wiring, and a plurality of dummy patterns. The first redistribution wiring and the second redistribution wiring are stacked at at least two heights and connected to the plurality of chip pads. The redistribution wiring layer includes four outer surfaces. The first redistribution wiring and the second redistribution wiring are arranged in the redistribution area of ​​the redistribution wiring layer. The redistribution region is the area defined by four lines in the redistribution routing layer. These four lines extend parallel to the four outer surfaces of the redistribution routing layer to form the outer rectangle of the redistribution region. The plurality of dummy patterns are disposed on the outer region of the redistribution area of ​​the redistribution wiring layer, respectively, to partially cover multiple corners of the redistribution wiring layer. The outermost boundary of the shape created by the outer rectangle and the plurality of corners of the redistributed region forms a non-rectangular shape.

2. The semiconductor package according to claim 1, in, The plurality of dummy patterns are at the same height as at least one of the first redistribution wiring and the second redistribution wiring.

3. The semiconductor package according to claim 1, in, At least one of the first redistribution wiring and the second redistribution wiring includes a grounding pattern disposed on the redistribution area of ​​the redistribution wiring layer. The grounding pattern has four side surfaces and four extended corners, with the four side surfaces extending parallel to the four outer surfaces of the redistribution wiring layer. Each of the four extending corners of the grounding pattern is connected to two corresponding side surfaces of the four side surfaces of the grounding pattern, and extends from a first corner formed at the intersection of the two corresponding side surfaces of the four side surfaces of the grounding pattern. Each of the four extended corners of the grounding pattern is a corresponding pattern among the plurality of dummy patterns.

4. The semiconductor package according to claim 3, in, The plurality of dummy patterns are integrated with the grounding pattern.

5. The semiconductor package according to claim 3, in, The plurality of dummy patterns include a first dummy pattern to a fourth dummy pattern that are respectively adjacent to the four corners of the redistribution wiring layer. The first dummy pattern includes a first dummy pattern side surface, a second dummy pattern side surface, and a first dummy pattern corner at the intersection of the first dummy pattern side surface and the second dummy pattern side surface. The first dummy pattern includes a first portion defined by a side surface of the first dummy pattern, a first side surface of the grounding pattern, and a first line extending from the first corner of the grounding pattern to the corner of the first dummy pattern. Wherein, the first side surface of the grounding pattern and the side surface of the first dummy pattern intersect each other at a first distance from the corner adjacent to the corner of the redistribution wiring layer of the first dummy pattern in a first direction parallel to the first side surface of the grounding pattern. The first dummy pattern further includes a second portion defined by the side surface of the second dummy pattern, the second side surface of the grounding pattern, and the first line extending from the first corner of the grounding pattern to the corner of the first dummy pattern. Wherein, the second side surface of the grounding pattern and the side surface of the second dummy pattern intersect each other at a second distance from the corner adjacent to the corner of the redistribution wiring layer of the first dummy pattern in a second direction parallel to the second side surface of the grounding pattern.

6. The semiconductor package according to claim 5, in, The first distance has a value ranging from approximately 1.5 mm to approximately 3 mm.

7. The semiconductor package according to claim 5, in, The width of the first portion of the first dummy pattern in the second direction gradually increases from the position where the side surface of the first dummy pattern and the first side surface of the ground pattern intersect each other to the first corner of the ground pattern, and gradually decreases from the first corner of the ground pattern to the corner of the first dummy pattern.

8. The semiconductor package according to claim 1, in, The substrate includes a first metal wiring, a second metal wiring, and a plurality of second dummy patterns. The first metal wiring and the second metal wiring are stacked at at least two heights and connected to the first redistribution wiring. The substrate includes four side surfaces and a first metal wiring and a second metal wiring disposed in the wiring area of ​​the substrate. The wiring area is a region of the substrate defined by four lines, which extend parallel to the four side surfaces of the substrate and are spaced apart from the four side surfaces of the substrate by a predetermined distance. The plurality of second dummy patterns are disposed on the outer region of the substrate outside the wiring area of ​​the substrate, so as to partially cover the plurality of corners of the substrate respectively.

9. The semiconductor package according to claim 8, in, The plurality of second dummy patterns are at the same height as at least one of the first metal wiring and the second metal wiring.

10. The semiconductor package according to claim 8, in, At least one of the first metal wiring and the second metal wiring includes a second ground pattern disposed on the wiring area of ​​the substrate. The second grounding pattern has four side surfaces and four extending corners, the four side surfaces extending parallel to the four side surfaces of the substrate. Each of the four extending corners of the second grounding pattern is connected to two corresponding side surfaces of the four side surfaces of the second grounding pattern, and extends from a first corner formed at the intersection of the two corresponding side surfaces of the four side surfaces of the second grounding pattern toward a corner of the substrate adjacent to the first corner of the second grounding pattern. Each of the four extended corners of the second grounding pattern is a corresponding pattern among the plurality of second dummy patterns.

11. A semiconductor package, comprising: The redistribution routing layer includes a first redistribution routing layer, a second redistribution routing layer, and a plurality of extended patterns, wherein the first redistribution routing layer and the second redistribution routing layer are stacked at at least two heights. At least one semiconductor chip is disposed on the redistribution wiring layer and has a plurality of chip pads electrically connected to the first redistribution wiring and the second redistribution wiring; as well as A molded substrate is disposed on the upper surface of the redistribution wiring layer and covers the at least one semiconductor chip. The redistribution wiring layer includes four outer surfaces. The first redistribution wiring and the second redistribution wiring are arranged in the redistribution area of ​​the redistribution wiring layer. The redistribution region is a region defined by four lines in the redistribution wiring layer. These four lines extend parallel to the four outer surfaces of the redistribution wiring layer to form a rectangle representing the redistribution region. The plurality of extended patterns are disposed on the outer region of the redistribution area of ​​the redistribution wiring layer, so as to partially cover the plurality of corners of the redistribution wiring layer.

12. The semiconductor package according to claim 11, in, At least one of the first redistribution wiring and the second redistribution wiring includes a grounding pattern disposed on the redistribution area of ​​the redistribution wiring layer. The grounding pattern has four side surfaces and four extended corners, with the four side surfaces extending parallel to the four outer surfaces of the redistribution wiring layer. Each of the four extending corners of the grounding pattern is connected to two corresponding side surfaces of the four side surfaces of the grounding pattern, and extends from a first corner formed at the intersection of the two corresponding side surfaces of the four side surfaces of the grounding pattern toward a corner of the redistribution wiring layer adjacent to the first corner of the grounding pattern. Each of the four extended corners of the grounding pattern is a corresponding pattern among the plurality of extended patterns.

13. The semiconductor package according to claim 12, in, The plurality of extended patterns are integrally formed with the grounding pattern.

14. The semiconductor package according to claim 12, in, The plurality of extended patterns include a first extended pattern to a fourth extended pattern, which are respectively adjacent to the four corners of the redistribution wiring layer. The first extended pattern includes a first extended pattern side surface, a second extended pattern side surface, and a first extended pattern corner at the intersection of the first extended pattern side surface and the second extended pattern side surface. The first extended pattern includes a first portion defined by a side surface of the first extended pattern, a first side surface of the grounding pattern, and a first line extending from the first corner of the grounding pattern to the corner of the first extended pattern. Wherein, the first side surface of the grounding pattern and the side surface of the first extended pattern intersect each other at a first distance from the corner adjacent to the corner of the redistribution wiring layer in a first direction parallel to the first side surface of the grounding pattern. The first extended pattern further includes a second portion defined by the side surface of the second extended pattern, the second side surface of the grounding pattern, and the first line extending from the first corner of the grounding pattern to the corner of the first extended pattern. Wherein, the second side surface of the grounding pattern and the side surface of the second extension pattern intersect each other at a second distance from the corner adjacent to the corner of the redistribution wiring layer of the first extension pattern in a second direction parallel to the second side surface of the grounding pattern.

15. The semiconductor package according to claim 14, in, The first distance has a value ranging from approximately 1.5 mm to approximately 3 mm.

16. The semiconductor package according to claim 14, in, The width of the first portion of the first extended pattern in the second direction gradually increases from the position where the side surface of the first extended pattern and the first side surface of the grounding pattern intersect each other to the first corner of the grounding pattern, and gradually decreases from the first corner of the grounding pattern to the corner of the first extended pattern.

17. The semiconductor package according to claim 14, in, The corner of the first extended pattern of the first extended pattern is a certain distance from the corner of the redistributed wiring layer in the first direction, the distance having a value from about 30 μm to about 90 μm.

18. The semiconductor package according to claim 14, in, The outer region of the redistributed wiring layer has a predetermined width in the second direction, the predetermined width having a value between 100 μm and 200 μm.

19. The semiconductor package of claim 11, further comprising: A conductive connection post extends from the upper surface of the molded substrate to the lower surface of the molded substrate, passing through at least a portion of the molded substrate, and is electrically connected to the first redistribution wiring. as well as The second package is stacked on the molded substrate and electrically connected to the conductive connection post.

20. A semiconductor package, comprising: A substrate having a cavity extending from the upper surface of the substrate to the lower surface of the substrate; At least one semiconductor chip is disposed in the cavity of the substrate and has a plurality of chip pads; A redistribution wiring layer is disposed on the lower surface of the substrate and includes a first redistribution wiring and a second redistribution wiring, as well as a plurality of dummy patterns. The first redistribution wiring and the second redistribution wiring are stacked at at least two heights and connected to the plurality of chip pads. as well as Multiple external connection components are disposed on the outer surface of the redistribution wiring layer and electrically connected to the first redistribution wiring and the second redistribution wiring. The redistribution routing layer includes four outer surfaces, and a first redistribution routing and a second redistribution routing arranged in the redistribution area of ​​the redistribution routing layer. The redistribution region is a region defined by four lines in the redistribution routing layer. These four lines extend parallel to the four outer surfaces of the redistribution routing layer to form a rectangle representing the redistribution region. The plurality of dummy patterns are disposed on the outer region of the redistribution area of ​​the redistribution wiring layer, respectively, to partially cover multiple corners of the redistribution wiring layer. A portion of the plurality of external connecting components is disposed on a first region of the redistribution region, the first region of the redistribution region being between the plurality of dummy patterns and the at least one semiconductor chip.

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