Integrated circuit systems including memory arrays and methods for forming them

Abstract

This disclosure relates to an integrated circuit system including a memory array and a method for forming the same. A method for forming a memory array including strings of memory cells includes forming an upper stack directly above a lower stack. The lower stack includes vertically alternating lower first layers and lower second layers. The upper stack includes vertically alternating upper first layers and upper second layers. A lower channel opening extends through the lower first layer and the lower second layer. The lower channel opening has a sacrificial material therein. The upper portion of the lower second layer or the lower portion of the upper second layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper second layer above the lower portion comprises silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5.

Description

Technical Field

[0001] The embodiments disclosed herein relate to an integrated circuit system including a memory array comprising strings of memory cells and a method for forming a memory array comprising strings of memory cells. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines interconnect memory cells along the columns of the array, and access lines interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically defined as memory with a retention time of at least approximately 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] A field-effect transistor (FET) is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures, such as a reversible programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory with numerous applications in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, the use of flash memory in solid-state drives to replace conventional hard disk drives is becoming increasingly common in computers and other devices. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they are standardized, and provides the ability to remotely upgrade said devices to enhance their features.

[0006] NAND can serve as the foundational architecture for integrated flash memory. A NAND cell component includes at least one selection device serially coupled to a series combination of memory cells (often referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement comprising vertically stacked memory cells, each memory cell individually including a reversible programmable vertical transistor. Control or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells, each individually including a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and portions of blocks (e.g., sub-blocks) and memory planes, as shown and described, for example, in U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define the longitudinal profile of individual word lines in the individual word line layers of a vertically stacked memory cell array. Connections to these word lines can occur in so-called “staircase structures” at the ends or edges of the vertically stacked memory cell array. A staircase structure includes individual “stairs” (also called “steps” or “staircase steps”) that define contact areas for individual word lines, with vertically extending conductive vias contacting these contact areas to provide electrical access to the word lines. Summary of the Invention

[0008] In one aspect, this disclosure relates to a method for forming a memory array comprising strings of memory cells, comprising: forming an upper stack directly above a lower stack, the lower stack comprising vertically alternating lower first layers and lower second layers, the upper stack comprising vertically alternating upper first layers and upper second layers, a lower channel opening extending through the lower first layers and the lower second layers, the lower channel opening having a sacrificial material; an upper portion of the lower second layer or a lower portion of the upper second layer comprising nonstoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5, a higher portion of the upper second layer above the lower upper second layer comprising silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5; etching the upper channel opening through the upper first layers and the upper second layers to stop on the upper lower second layer or the lower upper second layer; and after the stop, removing the sacrificial material from the lower channel opening and forming a string of channel material in the upper channel opening and the lower channel opening.

[0009] In another aspect, this disclosure relates to an integrated circuit system comprising a memory array containing strings of memory cells, comprising: an upper stack directly above a lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; an upper portion of the lower insulating layer or a lower portion of the upper insulating layer comprising non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5, and a higher portion of the upper insulating layer above the lower upper insulating layer comprising silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5; and a channel material string of memory cells extending through the upper stack and the lower stack, including through the non-stoichiometric silicon dioxide.

[0010] In another aspect, this disclosure relates to an integrated circuit system comprising a memory array containing strings of memory cells, comprising: laterally spaced memory blocks, each comprising a first vertical stack, the first vertical stack comprising alternating insulating and conductive layers, the memory cell strings comprising strings of channel material extending through the insulating and conductive layers, the conductive layers each comprising horizontally elongated conductive lines; a second vertical stack adjacent to the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising alternating upper first and upper second insulating layers with different compositions relative to each other, the lower portion comprising lower first and lower second insulating layers with different compositions relative to each other; and the upper portion of the lower second insulating layer or the lower portion of the upper second insulating layer comprising nonstoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5, the higher portion of the upper second insulating layer above the lower upper second insulating layer comprising silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5. Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of a portion of the substrate during processing according to an embodiment of the present invention, and is along... Figure 2 Cut off line 1-1 in the middle.

[0012] Figure 2 It is along Figure 1 The diagram shows a cross-sectional view taken from line 2-2 in the figure.

[0013] Figure 3 yes Figure 1 and 2 A magnified view of a portion of it.

[0014] Figures 4 to 7 And 10 to 26 are processes according to some embodiments of the present invention. Figures 1 to 3 The diagrammatic sequence of cross-sectional views, extended views, magnified views and / or partial views of the structure or its parts.

[0015] Figure 8 and 9 Alternative examples of methods and / or structural embodiments of the present invention are shown. Detailed Implementation

[0016] Embodiments of the present invention cover methods for forming memory arrays, such as arrays of NAND or other memory cells that may have at least some peripheral control circuitry systems (e.g., CMOS under the array). Embodiments of the present invention cover so-called "post-gate" or "replacement gate" processes, so-called "gate-before" processes, and other existing or future-developed processes independent of transistor gate formation timing. Embodiments of the present invention also cover memory arrays (e.g., NAND architectures) independent of manufacturing methods. Reference Figures 1 to 26 The first example method embodiment is described, which can be considered as a "post-gate" or "replacement gate" process, and from... Figures 1 to 3 start.

[0017] Figures 1 to 3 A configuration 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells will be formed. Configuration 10 includes a substrate 11 having any one or more of the following: conductive / conductive / transducing, semiconductive / semiconductor / semi-conductive, and insulating / insulator / insulator (i.e., electrical in this context). Various materials have already been vertically formed over the substrate 11. The materials may be... Figures 1 to 3The material depicted may be adjacent to, vertically inside, or vertically outside the substrate. For example, other parts of the integrated circuit system or fully fabricated components may be disposed above, around, or within the substrate 11. Control and / or other peripheral circuitry systems for operating components within an array (e.g., array 12) of vertically extending memory cell strings may also be fabricated and may or may not be fully or partially within the array or subarray. Furthermore, multiple subarrays may be fabricated and operated independently, collaboratively, or otherwise relative to each other. In this document, "subarray" may also be considered as an array.

[0018] Including conductor material 17 (e.g., WSi) x A conductive layer 16 (top conductive doped polysilicon) has been formed above the substrate 11. The conductive layer 16 may include portions of a control circuitry system (e.g., the peripheral circuitry below the array and / or the common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed in the array 12.

[0019] Above conductor layer 16, a lower stack 18L comprising vertically alternating lower insulating layers 20L* and lower conductive layers 22L* has been formed (* is used as a suffix to encompass all such identical components specified by numbers, which may or may not have other suffixes). Examples of the thickness of each of the lower layers 20L* and 22L* are 22 to 60 nanometers. Only a small number of lower layers 20L* and 22L* are shown; more likely, the lower stack 18L comprises tens, hundreds, or more than one hundred lower layers 20L* and 22L*. Other circuitry, which may or may not be part of peripheral and / or control circuitry, may lie between conductor layer 16 and lower stack 18L. For example, multiple vertically alternating conductive and insulating material layers of this circuitry may be below the lowermost lower conductive layer 22L* and / or above the uppermost lower conductive layer 22L*. For example, one or more select gate layers (not shown) or dummy layers (not shown) may be located between conductor layer 16 and the lowermost conductive layer 22L*, and one or more select gate layers (not shown) or dummy layers (not shown) may be located above the uppermost lower conductive layer 22L*. Alternatively or additionally, at least one of the depicted lowermost conductive layers 22L* may be a select gate layer. In any case, the lower conductive layer 22L* (alternately referred to as the lower first layer) may not include conductive material, and the lower insulating layer 20L* (alternately referred to as the lower second layer) may not include insulating material or may be insulating at this point in time in conjunction with the example method embodiments (which are “back gate” or “alternate gate”) initially described herein. The example lower conductive layer 22L* includes a first material 26 (e.g., silicon nitride), which may be wholly or partially sacrificial material. The example insulating layer 20L* includes a second material 24 (e.g., comprising silicon dioxide, as explained further below) having a different composition from the first material 26 and may be wholly or partially a sacrificial material. For the purpose of further discussion, the lower first layer 22L* can be considered to include an upper lower first layer 22LU, which, in one embodiment shown, is the uppermost of the lower first layers 22L*. The lower stack 18L may have an uppermost layer, which is either the lower first layer 22L* or the lower second layer 20L*.

[0020] A lower channel opening 25 has been formed (e.g., by etching) through the lower insulating layer 20L* and the lower conductive layer 22L* to the conductor layer 16. The lower channel opening 25 may taper radially inward (not shown) to extend deeper into the lower stack 18L. In some embodiments, the lower channel opening 25 may extend into the conductor material 17 of the conductor layer 16 as shown, or may stop at the top of the conductor layer 16 (not shown). Alternatively, as an example, the lower channel opening 25 may stop at or within the top of the lowermost lower insulating layer 20L*. The reason for extending the lower channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect on the material within the lower channel opening 25. An etch stop material (not shown) may be within or on top of the conductor material 17 of the conductor layer 16 to facilitate stopping the etching of the lower channel opening 25 relative to the conductor layer 16 when necessary. This etch stop material may be a sacrificial or non-sacrificial material. In any case, the lower channel opening 25 can be considered to have an average longitudinal axis 75 (e.g., average if the axis 75 is not perfectly straight), which in one embodiment is vertical.

[0021] A horizontally elongated lower trench 40L has been formed (e.g., by anisotropic etching) into the lower stack 18L to form laterally spaced memory block regions 58. By way of example and for simplicity, the lower channel openings 25 are shown as groups or columns arranged in staggered rows of four and five lower channel openings 25 per row, and arranged in the laterally spaced memory block regions 58, which will include laterally spaced memory blocks 58 in the finished circuit system construction. In this document, "block" generally includes "sub-block". The lower trench 40L will typically be wider than the lower channel openings 25 (e.g., 10 to 20 times wider, but this greater width is not shown for simplicity). The memory block regions 58 and the resulting memory blocks 58 (not shown) can be considered as longitudinally elongated and (e.g.) oriented along direction 55. Any alternative existing or future-developed arrangements and constructions can be used.

[0022] Sacrificial material 59 has been formed in the lower channel opening 25 in the lower first layer 22L* and the lower second layer 20L*. In one embodiment, and as shown, sacrificial material 59 has been formed in the lower trench 40L. In one embodiment, the sacrificial material 59 in the lower channel opening 25 comprises radially outer silicon dioxide 70, radially inner silicon dioxide 72, and radially spaced alumina 71 therebetween. The lower trench 40L may include corresponding alumina 71 and silicon dioxide 70, 72. Materials 70, 71, and 72 are only present in the lower trench opening 25. Figure 3This is specified so as to make it clear in other figures. In one embodiment, the radially outer silicon dioxide 70 and the radially inner silicon dioxide 72 have different compositions relative to each other, and in one of these embodiments, the different compositions are characterized by the concentration of at least one of boron and phosphorus. By way of specific example only, the radially inner silicon dioxide 72 is BPSG, and the radially outer silicon dioxide 70 is undoped silicon dioxide.

[0023] refer to Figure 4 Above the lower stack 18L, an upper stack 18U has been formed comprising vertically alternating upper insulating layers 20U* (alternately referred to as the upper second layer) and upper conductive layers 22U* (alternately referred to as the upper first layer). The upper insulating layers 20U* and upper conductive layers 22U* may have any of the properties described above with respect to the lower insulating layers 20L* and lower conductive layers 22L*. For example, the upper conductive layer 22U* comprises a first material 26 (e.g., silicon nitride), which may be wholly or partially a sacrificial material. For example, the upper insulating layer 20U* is shown to comprise a second material 24, and the upper conductive layer 22U* is shown to comprise the first material 26, although other compositions may of course be used and need not be identical to those in the lower stack 18L. For the purpose of further discussion, the upper first layer 22U* may be considered to comprise a lower upper first layer 22UL, which in one embodiment is the lowest part of the upper first layer 22U*. The upper stack of 18U can have a top layer, which is either the upper first layer 22U* or the upper second layer 20U*.

[0024] The upper portion of the lower second layer 20L* or the lower portion of the upper second layer 20U* comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen atomic ratio greater than 0.5, and in one embodiment not greater than 1.0. The higher upper second layer 20U* above the lower upper second layer comprises silicon dioxide having a silicon-to-oxygen atomic ratio less than or equal to 0.5. This higher upper second layer 20U* may be stoichiometric (i.e., a silicon-to-oxygen atomic ratio of 0.5) or non-stoichiometric (i.e., a silicon-to-oxygen atomic ratio less than 0.5).

[0025] In one embodiment, the upper portion of the lower second layer 20L* comprises nonstoichiometric silica, and in one of these embodiments, it is the uppermost lower second layer 20LU. This is illustrated in the figures by a light dot in material 24, which comprises nonstoichiometric silica with a silicon-to-oxygen ratio greater than 0.5, compared to material 24 comprising silica with a silicon-to-oxygen ratio less than or equal to 0.5. In any case, in one embodiment, multiple upper lower second layers 20L* comprise nonstoichiometric silica (e.g., one or more layers 20L below the upper lower second layer 20LU [not shown] and which may or may not contain the upper lower second layer 20LU). In one embodiment, the lower portion of the upper second layer 20U* comprises nonstoichiometric silica, and in one of these embodiments, it is the lowermost upper second layer 20UL. In any embodiment, the plurality of lower upper second layers 20U comprise nonstoichiometric silica (e.g., one or more layers 20U* above the lower upper second layer 20UL [not shown] and which may or may not contain the lower upper second layer 20UL). In one embodiment, each of the upper portion of the lower second layer 20LU* and the lower portion of the upper second layer 20U* comprises nonstoichiometric silica (and may contain any of the properties just stated above).

[0026] Etch through the upper first layer 22U* and the upper second layer 20U* to stop on the upper lower second layer or the lower upper second layer, which includes non-stoichiometric silicon dioxide. Figure 5 and 6 The upper channel opening 39 is shown, which has been etched through the upper first layer 22U* and the upper second layer 20U* to stop on the upper lower second layer 20LU (i.e., its top or interior), in this example, the upper lower second layer 20LU comprising non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. In one embodiment, and as shown, etching the upper channel opening 39 to the stop (i.e., using the non-stoichiometric silicon dioxide of layer 20LU as an etch stop to stop the etching) exposes the sacrificial material 59. In one embodiment, and as shown, and referring to Figure 7 It can be best understood that individual upper channel openings 39 are formed with an average longitudinal axis 85, which, at the junction of the upper channel opening 39 and the lower channel opening 25, is in the vertical cross-section (e.g., Figure 6 The average longitudinal axis 85 is laterally offset relative to the lower average longitudinal axis 75 in the cross section. Alternatively, the average longitudinal axis 85 may be at an angle (instead of a flat angle) relative to the average longitudinal axis 75.

[0027] Figure 8 and 9Alternative examples of construction 10a are shown below. Similar designations from the above embodiments may be used as appropriate, with some construction differences indicated by the suffix "a" or by different designations. Figure 8 The upper channel opening 39 is etched through the upper first layer 22U* and the upper second layer 20U* to stop on the lower upper second layer 20UL (i.e., its top or interior), in this example, the lower upper second layer 20UL comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. This ensures that etching the upper channel opening 39 to the stop (i.e., using the non-stoichiometric silicon dioxide of layer 20UL as an etch stop to stop the etching) does not expose the sacrificial material 59. Figure 9 The exhibit is then etched through the lower upper second layer 20UL (and through the upper first layer 22U directly below it) to expose the sacrificial material 59. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0028] refer to Figure 10 and 11 Returning to configuration 10, the sacrificial material 59 (i.e., at least some of it) has been removed from the individual lower channel openings 25 through the upper channel opening 39 (e.g., by etching). For example, in the presence of materials 70, 71, and 72, some of materials 70 and / or 71 may be retained (not shown) to facilitate the formation of transistor material (described below).

[0029] Transistor channel material may be vertically formed in individual channel openings along insulating and conductive layers, thus including individual channel material strings that are directly electrically coupled to conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally interposed between the gate region and the channel material. In one embodiment, the memory is formed to include a charge-blocking region, a storage material (e.g., a charge storage material), and an insulating charge-passing material. The storage material of the individual memory cell (e.g., a floating gate material (e.g., doped or undoped silicon) or a charge-trapping material (e.g., silicon nitride, metal dots, etc.)) is vertically formed along the individual in the charge-blocking region. The insulating charge-passing material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide)) is laterally interposed between the channel material and the storage material.

[0030] Figures 12 to 15This illustration shows an embodiment in which charge blocking material 30, storage material 32, and charge passing material 34 are vertically formed along insulating layer 20* and conductive layer 22* in individual upper channel openings 39 and lower channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed by, for example, depositing their respective thin layers over the upper stack 18U and within the individual channel openings 39 and 25, and then at least planarizing this back to the top surface of the upper stack 18U.

[0031] Channel material 36 has also been vertically formed along the insulating layers 20U* / 20L* and the conductive layers 22U* / 22L* in the channel openings 39 / 25, thus including individual operable channel material strings 53 in the channel openings 39 / 25. In one embodiment, the channel material strings 53 have memory cell materials (e.g., 30, 32, and 34) along them and have a second layer material (e.g., 24) horizontally between adjacent channel material strings 53. Due to proportions, materials 30, 32, 34, and 36 in Figure 11 and 12 The material 37 is shown and indicated only as material 37. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Each of materials 30, 32, 34, and 36 has an example thickness of 25 to 100 angstroms. Punch etching can be performed to remove materials 30, 32, and 34 from the substrate of the lower channel opening 25 (not shown) to expose the conductor layer 16, such that the channel material 36 directly abuts the conductor material 17 of the conductor layer 16. This punch etching can occur individually with respect to each of materials 30, 32, and 34 (as shown), or with respect to only some materials (not shown). Alternatively, and by way of example only, punch etching may not be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 via only individual conductive interconnects (not shown). The channel opening 39 / 25 is shown to include a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 39 / 25 may include (a number of) void spaces (not shown) and / or contain no solid material (not shown).

[0032] refer to Figure 16 and 17 The horizontally elongated upper trench 40U has been formed into the lower trench 40L, and then the sacrificial material 59 (not shown) has been removed from there (e.g., by selective etching).

[0033] refer to Figure 18 and 19The first layer material 26 (not shown) in the first layer 22* has been selectively and isotropically etched through the trench 40U / 40L relative to the second layer material 24 in the second layer 20* (e.g., using liquid or vapor H3PO4 as the primary etchant, wherein material 26 comprises silicon nitride and other exposed materials comprise one or more oxides or polysilicon).

[0034] refer to Figures 20 to 26 Conductive material 48 has been deposited into trenches 40U / 40L to fill the volume in the conductive layer 22* derived from the removed material 26. This has thereafter been removed from trenches 40U / 40L, thereby forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0035] A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to the formation of the conductive material 48. The approximate location of the transistor and / or memory cell 56 is... Figure 24 Parentheses are used to indicate this, and some are in Figures 20 to 23 In Figure 25, the transistor and / or memory cell 56 is indicated by a dashed outline, wherein in the depicted example, the transistor and / or memory cell 56 is substantially annular or ring-shaped. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 39 / 25, such that each channel opening 39 / 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surrounding an individual channel opening in an individual conductive layer, wherein each channel opening in the individual conductive layer may have multiple word lines, and not shown). The conductive material 48 can be considered as having a terminal end 50 corresponding to the control gate region 52 of the individual transistor and / or memory cell 56. Figure 24 In the depicted embodiment, the control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered as a memory structure 65 laterally interposed between the control gate region 52 and the channel material 36. In one embodiment, and as shown with respect to the example of “post-gate” processing, the conductive material 48 of the conductive layer 22U / 22L is formed after the channel openings 39 / 25 and / or trenches 40U / 40L are formed. Alternatively, for example with respect to “pre-gate” processing, the conductive material of the conductive layer may be formed before the channel openings 39 / 25 and / or trenches 40U / 40L (not shown).

[0036] A charge-blocking region (e.g., charge-blocking material 30) is located between the storage material 32 and the individual control gate region 52. The charge block can function in the memory cell as follows: in programming mode, the charge block prevents charge carriers from flowing out of the storage material (e.g., floating gate material, charge-trapping material, etc.) toward the control gate; and in erase mode, the charge block prevents charge carriers from flowing from the control gate into the storage material. Therefore, the charge block can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown in the example, the charge-blocking region includes an insulating material 30. By a further example, the charge-blocking region may include a lateral (e.g., radial) outer portion of the storage material (e.g., material 32), wherein this storage material is insulating (e.g., in the absence of any different compositional material between the insulating storage material 32 and the conductive material 48). However, as an additional example, in the absence of any separate insulating material 30, the interface between the storage material and the conductive material of the control gate may be sufficient to act as a charge-blocking region. Furthermore, the interface between conductive material 48 and material 30 (when present) and insulating material 30 can together serve as a charge blocking region, and alternatively or additionally as a lateral outer region of an insulating storage material (e.g., silicon nitride material 32). Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0037] Intermediate material 57 has been formed in trenches 40U / 40L, thereby laterally between laterally adjacent memory blocks 58 and longitudinally along said memory blocks 58. Intermediate material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This can include one or more of insulating, semiconductive, and conductive materials, and in any case, can facilitate the prevention of shorting between conductive layers 22 in the finished circuit system construction. Examples of insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intermediate material 57 can contain through-array pathways (not shown).

[0038] In some embodiments, configuration 10 may be considered to include a first region (e.g., such as...). Figures 20 to 22 (as shown) and the second zone 70 next to the first zone (e.g., as shown) Figure 26 (As shown). The second region 70 may be laterally contacting the first region (not shown), or may be laterally spaced from the first region (e.g., laterally adjacent to but not in contact with it, or laterally distant from and not in contact with it). The second region 70 may be located within one or more memory blocks (not shown). In some embodiments, configuration 10 may be considered to include a first vertical stack (e.g., Figures 20 to 22 The stack 18* in the middle and the second vertical stack (e.g., stack 18* in the second zone 70), wherein the second stack includes an upper portion 18U and a lower portion 18L.

[0039] Any other attributes or aspects shown and / or described in this document with respect to other embodiments may be used in the illustrated embodiments and with reference to the embodiments described above.

[0040] Alternative embodiments may be constructed from the method embodiments described above or other embodiments. In any case, embodiments of the present invention cover integrated circuit systems including memory arrays independent of manufacturing methods. However, such integrated circuit systems and memory arrays may have any of the properties described herein in the method embodiments. Similarly, the above method embodiments may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0041] In one embodiment, an integrated circuit system (e.g., 10) including a memory array (e.g., 49) containing strings (e.g., 56) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) directly above a lower stack (e.g., 18L). The lower stack includes vertically alternating lower conductive layers (e.g., 22L*) and lower insulating layers (e.g., 20L*). The upper stack includes vertically alternating upper conductive layers (e.g., 22U*) and upper insulating layers (e.g., 20U*). The upper portion of the lower insulating layer or the lower portion of the upper insulating layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper insulating layer above the lower upper insulating layer comprises silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5. Channel material strings (e.g., 53) of the memory cells (e.g., 56) extend through the upper and lower stacks, comprising passing through non-stoichiometric silicon dioxide. Any other properties or aspects shown and / or described in this document with respect to other embodiments may be used.

[0042] In one embodiment, an integrated circuit system (e.g., 10) including a memory array (e.g., 49) comprising strings (e.g., 56) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each memory block individually comprising a first vertical stack (e.g., Figure 22 The first vertical stack includes alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). Strings (e.g., 49) of memory cells (e.g., 56) including strings of channel material (e.g., 53) extend through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines (e.g., 29). The second vertical stack (e.g., 18*) Figure 26The 18* in the first vertical stack is adjacent to the second vertical stack. The second vertical stack includes an upper portion (e.g., 18U) and a lower portion (e.g., 18L). The upper portion includes alternating upper first insulating layers (e.g., 22U*) and upper second insulating layers (e.g., 20U*) with different compositions relative to each other. The lower portion includes lower first insulating layers (e.g., 22L*) and lower second insulating layers (e.g., 20L*) with different compositions relative to each other. The upper portion of the lower second insulating layer or the lower portion of the upper second insulating layer includes non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper second insulating layer above the lower upper second insulating layer includes silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0043] The aforementioned processing or construction can be viewed as relative to an array of components, which is formed as a single stack or single layer of such components above or as part of the underlying substrate, or within the stack or layer (although a single stack / layer may have multiple layers). Controls and / or other peripheral circuitry for operating or accessing such components within the array may also be formed as part of the finished construction at any location, and in some embodiments may be below the array (e.g., below-array CMOS). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, the arrays of components may be the same or different from each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses from each other. Intermediate structures may be disposed vertically adjacent to the stacks / layers (e.g., additional circuitry and / or dielectric layers). Similarly, the different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / layers can be manufactured substantially simultaneously.

[0044] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can contain multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting fixtures, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0045] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” refers to a direction along the general surface of the main substrate (i.e., within 10 degrees) and relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal to horizontal. The reference to “fully horizontal” is along the surface of the main substrate (i.e., not at an angle to it) and relative to the direction in which the substrate is handled during manufacturing. Furthermore, as used herein, “vertical” and “horizontal” are generally perpendicular to each other and independent of the substrate’s orientation in three-dimensional space. Additionally, “vertically extending” and “extending in the vertical direction” refer to a direction deviating at least 45° from the fully horizontal. Furthermore, relative to a field-effect transistor, “extending in the vertical direction,” “vertically extending,” “horizontally extending,” “horizontally extending,” and the like refer to the orientation of the transistor’s channel length, along which current flows between the source / drain regions during operation. For bipolar junction transistors, "extending vertically," "extending vertically," "extending horizontally," and the like are orientations that refer to the length of the substrate along which current flows between the emitter and collector during operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within a vertical 10°.

[0046] Furthermore, "directly above," "directly below," and "directly under" require that the two regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. And, using "directly above" without the preceding "directly" only requires that a portion of the region / material / component above another region / material / component is vertically outside that other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components). Similarly, using "directly below" and "under" without the preceding "directly" only requires that a portion of the region / material / component below / under another region / material / component is vertically inside that other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components).

[0047] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any overlying material. Where one or more example components are provided for any material, the material may include, be substantially composed of, or be composed of such components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or yet-to-be-developed technique, examples of which include atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0048] Furthermore, “thickness” itself (without a directional adjective previously) is defined as the average straight-line distance perpendicular to the nearest surface of adjacent materials or regions of different compositions through a given material or region. Additionally, the various materials or regions described herein may have substantially constant or variable thicknesses. If a variable thickness is present, then the thickness refers to the average thickness, unless otherwise indicated, and the material or region will have a minimum and a maximum thickness due to the variable thickness. As used herein, “different compositions” requires only that the portions of two said materials or regions that can be directly abutted against each other are chemically and / or physically different (e.g., if such materials or regions are not homogeneous). If two said materials or regions are not directly abutted against each other, then “different compositions” requires only that the portions of the two said materials or regions that are closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, a material, region, or structure is “directly abutted” against another when there is at least one physical contact between the materials, regions, or structures. In contrast, the words “above,” “on,” “adjacent to,” “along,” and “against” without the preceding “direct” encompass “direct contact” and constructions in which (some) intermediate materials, (some) areas, or (some) structures cause the materials, areas, or structures to be in contact with each other without physical contact.

[0049] In this paper, a region-material-assembly is considered "electrically coupled" to each other if, during normal operation, current can flow continuously from one region-material-assembly to another, and this flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component can be electrically coupled between and to a region-material-assembly. In contrast, when a region-material-assembly is referred to as "directly electrically coupled," there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between directly electrically coupled region-material-assemblies.

[0050] In this document, the terms "row" and "column" are used for ease of distinguishing one series or orientation of features from another series or orientation of features along which components have been or may be formed. "Row" and "column" are used synonymously with any series of regions, components, and / or features and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel to each other, and columns may be as well. Furthermore, rows and columns may intersect each other at 90° or one or more other angles (i.e., other than straight angles).

[0051] The composition of any of the conductive / conductor / conductive materials described herein may be metallic materials and / or conductive-doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metallic compounds or combinations thereof.

[0052] In this document, any use of "selective" in relation to etching, removal, deposition, and / or forming is an action in which said material is acted relative to another said material at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective forming is the deposition, growth, or formation of a material relative to another said material or several materials at a rate of at least 2:1 by volume for at least the first 75 angstroms.

[0053] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0054] in conclusion

[0055] In some embodiments, a method for forming a memory array comprising strings of memory cells includes forming an upper stack directly above a lower stack. The lower stack includes vertically alternating lower first layers and lower second layers. The upper stack includes vertically alternating upper first layers and upper second layers. A lower channel opening extends through the lower first layers and lower second layers. The lower channel opening contains sacrificial material therein. The upper portion of the lower second layer or the lower portion of the upper second layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper second layer above the lower upper second layer comprises silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5. The upper channel opening is etched through the upper first layers and upper second layers to stop on the upper lower second layer or the lower upper second layer. After stopping, sacrificial material is removed from the lower channel opening, and a string of channel material is formed in the upper channel opening and the lower channel opening.

[0056] In some embodiments, an integrated circuit system including a memory array comprising strings of memory cells includes an upper stack directly above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. The upper portion of the lower insulating layer or the lower portion of the upper insulating layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper insulating layer above the lower upper insulating layer comprises silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5. Strings of channel material for the memory cells extend through the upper and lower stacks, including through the non-stoichiometric silicon dioxide.

[0057] In some embodiments, an integrated circuit system including a memory array comprising strings of memory cells includes laterally spaced memory blocks, each including a first vertical stack comprising alternating insulating and conductive layers. The strings of memory cells include strings of channel material extending through the insulating and conductive layers. The conductive layers individually include horizontally elongated conductive lines. A second vertical stack is placed adjacent to the first vertical stack. The second vertical stack includes an upper and a lower portion. The upper portion includes alternating upper first and upper second insulating layers with different compositions relative to each other. The lower portion includes lower first and lower second insulating layers with different compositions relative to each other. The upper portion of the lower second insulating layer or the lower portion of the upper second insulating layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen ratio greater than 0.5. The higher portion of the upper second insulating layer above the lower upper second insulating layer comprises silicon dioxide with a silicon-to-oxygen ratio less than or equal to 0.5.

[0058] In accordance with regulations, the subject matter disclosed herein has been described in language that is more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given their full scope literally and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming a memory array comprising a string of memory cells, comprising: An upper stack is formed directly above the lower stack, the lower stack comprising vertically alternating lower first layer and lower second layer, the upper stack comprising vertically alternating upper first layer and upper second layer, a lower channel opening extending through the lower first layer and lower second layer, the lower channel opening containing sacrificial material; The upper part of the lower second layer or the lower part of the upper second layer includes non-stoichiometric silicon dioxide with a silicon-to-oxygen atomic ratio greater than 0.5, and the higher part of the upper second layer above the lower upper second layer includes silicon dioxide with a silicon-to-oxygen atomic ratio less than or equal to 0.

5. Etch the upper channel opening through the upper first layer and the upper second layer to stop on the upper lower second layer or the lower upper second layer; and After the stop, the sacrificial material is removed from the lower channel opening, and a channel material string is formed in the upper channel opening and the lower channel opening.

2. The method according to claim 1, wherein the silicon-to-oxygen atomic ratio of the non-stoichiometric silicon dioxide is not greater than 1.

0.

3. The method of claim 1, wherein the upper portion of the lower second layer comprises the non-stoichiometric silicon dioxide.

4. The method of claim 3, wherein the upper part of the lower second layer is the uppermost part of the lower second layer.

5. The method of claim 3, wherein the plurality of the upper lower second layers comprise the non-stoichiometric silicon dioxide.

6. The method of claim 1, wherein the lower portion of the upper second layer comprises the non-stoichiometric silicon dioxide.

7. The method of claim 6, wherein the lower part of the upper second layer is the lowest part of the upper second layer.

8. The method of claim 6, wherein the plurality of the lower upper second layers comprise the non-stoichiometric silicon dioxide.

9. The method of claim 1, wherein each of the upper portion of the lower second layer and the lower portion of the upper second layer comprises the nonstoichiometric silicon dioxide.

10. The method of claim 1, wherein the etching of the upper channel opening to stop the sacrificial material from being exposed on the upper lower second layer or the lower upper second layer.

11. The method of claim 1, wherein etching the upper channel opening to stop the sacrificial material from being exposed on the upper lower second layer or the lower upper second layer, and further comprising subsequently etching through the upper lower second layer or the lower upper second layer to expose the sacrificial material.

12. An integrated circuit system comprising a memory array including strings of memory cells, comprising: An upper stack is located directly above a lower stack, the lower stack comprising vertically alternating lower conductive and lower insulating layers, and the upper stack comprising vertically alternating upper conductive and upper insulating layers. The upper portion of the lower insulating layer or the lower portion of the upper insulating layer comprises non-stoichiometric silicon dioxide with a silicon-to-oxygen atomic ratio greater than 0.5, and the higher portion of the upper insulating layer above the lower upper insulating layer comprises silicon dioxide with a silicon-to-oxygen atomic ratio less than or equal to 0.5; and The channel material string of the memory cell extends through the upper stack and the lower stack, including through the non-stoichiometric silicon dioxide.

13. The integrated circuit system according to claim 12, wherein the silicon-to-oxygen atomic ratio of the non-stoichiometric silicon dioxide is not greater than 1.

0.

14. The integrated circuit system of claim 12, wherein the upper portion of the lower insulating layer comprises the nonstoichiometric silicon dioxide.

15. The integrated circuit system of claim 14, wherein the upper portion of the lower insulating layer is the uppermost portion of the lower insulating layer.

16. The integrated circuit system of claim 14, wherein the plurality of the upper lower insulating layers comprise the non-stoichiometric silicon dioxide.

17. The integrated circuit system of claim 12, wherein the lower portion of the upper insulating layer comprises the nonstoichiometric silicon dioxide.

18. The integrated circuit system of claim 17, wherein the lower portion of the upper insulating layer is the lowest portion of the upper insulating layer.

19. The integrated circuit system of claim 17, wherein the plurality of the lower upper insulating layers comprise the non-stoichiometric silicon dioxide.

20. The integrated circuit system of claim 12, wherein each of the upper portion of the lower insulating layer and the lower portion of the upper insulating layer comprises the nonstoichiometric silicon dioxide.

21. An integrated circuit system comprising a memory array including strings of memory cells, comprising: The memory blocks are horizontally spaced, each comprising a first vertical stack, the first vertical stack comprising alternating insulating and conductive layers, the memory cell string comprising a string of channel material extending through the insulating and conductive layers, the conductive layers each comprising horizontally elongated conductive lines. A second vertical stack, located adjacent to the first vertical stack, comprises an upper portion and a lower portion. The upper portion includes alternating upper first and upper second insulating layers with different compositions relative to each other. The lower portion includes lower first and lower second insulating layers with different compositions relative to each other. The upper part of the lower second insulating layer or the lower part of the upper second insulating layer includes non-stoichiometric silicon dioxide with a silicon-to-oxygen atomic ratio greater than 0.5, and the higher part of the upper second insulating layer above the lower upper second insulating layer includes silicon dioxide with a silicon-to-oxygen atomic ratio less than or equal to 0.

5.

22. The integrated circuit system of claim 21, wherein the silicon-to-oxygen atomic ratio of the non-stoichiometric silicon dioxide is not greater than 1.

0.

23. The integrated circuit system of claim 21, wherein the upper portion of the lower second insulating layer comprises the non-stoichiometric silicon dioxide.

24. The integrated circuit system of claim 23, wherein the upper portion of the lower second insulating layer is the uppermost portion of the lower second insulating layer.

25. The integrated circuit system of claim 23, wherein the plurality of the upper lower second insulating layers comprise the non-stoichiometric silicon dioxide.

26. The integrated circuit system of claim 21, wherein the lower portion of the upper second insulating layer comprises the non-stoichiometric silicon dioxide.

27. The integrated circuit system of claim 26, wherein the lower portion of the upper second insulating layer is the lowermost portion of the upper second insulating layer.

28. The integrated circuit system of claim 26, wherein a plurality of lower upper second insulating conductive layers comprise the non-stoichiometric silicon dioxide.

29. The integrated circuit system of claim 21, wherein each of the upper portion of the lower second insulating layer and the lower portion of the upper second insulating layer comprises the nonstoichiometric silicon dioxide.

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