Three-dimensional memory and method for forming the same

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a method for forming the same. The method for forming the three-dimensional memory comprises the following steps: forming a base, the base comprising a substrate, a stacked structure located on the substrate, and a gate trench penetrating the stacked structure, the stacked structure comprising alternating interlayer insulating layers and conductive layers, the conductive layer also covering the sidewalls and bottom wall of the gate trench; forming a dielectric layer covering the surface of the conductive layer in the gate trench; modifying the dielectric layer so that at least the etching rate at the bottom of the dielectric layer is greater than the etching rate at the top of the dielectric layer; and etching away the modified dielectric layer and at least the conductive layer located on the sidewalls and bottom wall of the gate trench. The present invention reduces or even avoids the residual conductive layer at the bottom of the gate trench, thereby improving the leakage phenomenon between gates.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a method for forming the same. Background Art

[0002] With the development of planar flash memory, semiconductor production processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limitations, the limitations of existing development technology, and the limits of stored electron density. Against this backdrop, to address the difficulties faced by planar flash memory and pursue lower unit cell production costs, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D Not-Or) flash memory and 3D NAND (3D Not-And) flash memory.

[0003] Among them, 3D NAND memory takes its small size and large capacity as its starting point, and uses a highly integrated design concept of stacking storage units in a three-dimensional pattern to produce memory with high storage density per unit area and efficient storage unit performance. It has become the mainstream process for the design and production of emerging memories.

[0004] However, current three-dimensional memories such as 3D NAND have leakage between their gates, which results in degradation of the electrical performance of the three-dimensional memory and, in severe cases, even renders the three-dimensional memory useless.

[0005] Therefore, how to reduce the leakage between gates in a three-dimensional memory, thereby improving the electrical performance of the three-dimensional memory and increasing the yield of the three-dimensional memory, is a technical problem that needs to be solved urgently. Summary of the Invention

[0006] The present invention provides a three-dimensional memory and a method for forming the same, which are used to solve the problem of leakage between gates in existing three-dimensional memories, thereby improving the electrical performance of the three-dimensional memory and increasing the yield of the three-dimensional memory.

[0007] In order to solve the above problems, the present invention provides a method for forming a three-dimensional memory, comprising the following steps:

[0008] forming a base, the base comprising a substrate, a stacked structure located on the substrate, and a gate trench penetrating the stacked structure, the stacked structure comprising alternately stacked interlayer insulating layers and conductive layers, the conductive layer also covering sidewalls and a bottom wall of the gate trench;

[0009] forming a dielectric layer in the gate trench to cover the surface of the conductive layer;

[0010] Performing a modification treatment on the dielectric layer so that at least the etching rate of the bottom of the dielectric layer is greater than the etching rate of the top of the dielectric layer;

[0011] The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away.

[0012] Optionally, the specific steps of forming the substrate include:

[0013] providing a substrate;

[0014] forming a stacked layer on the surface of the substrate, wherein the stacked layer comprises interlayer insulating layers and sacrificial layers stacked alternately;

[0015] forming a gate trench penetrating the stacked layer;

[0016] removing the sacrificial layer along the gate trench to form a gap between two adjacent interlayer insulating layers;

[0017] The conductive layer is formed to fill the gap and at least cover the sidewalls and bottom wall of the gate trench.

[0018] Optionally, the specific step of forming a dielectric layer covering the surface of the conductive layer in the gate trench includes:

[0019] A high dielectric constant material is deposited at least in the gate isolation groove to form a dielectric layer covering at least the surface of the conductive layer.

[0020] Optionally, the specific steps of modifying the dielectric layer include:

[0021] The dielectric layer is subjected to an annealing process.

[0022] Optionally, the specific steps of annealing the dielectric layer include:

[0023] Performing a rapid thermal annealing process on the dielectric layer.

[0024] Optionally, the specific steps of making at least the etching rate of the bottom of the dielectric layer greater than the etching rate of the top of the dielectric layer include:

[0025] A heat source is placed above the gate spacer, so that during annealing, at least the temperature of the bottom of the dielectric layer is lower than the temperature of the top of the dielectric layer.

[0026] Optionally, the specific step of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench includes:

[0027] The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away using a wet etching process.

[0028] Optionally, the specific step of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench includes:

[0029] The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away in the same etching process.

[0030] Optionally, the specific steps of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench in the same etching process include:

[0031] The modified dielectric layer, the conductive layer on the sidewalls and bottom wall of the gate trench, and a portion of the conductive layer between adjacent interlayer insulating layers are etched away in the same etching process, thereby forming openings between adjacent interlayer insulating layers and between the interlayer insulating layer at the bottom of the stacked structure and the substrate.

[0032] Optionally, the width of the opening gradually increases in a direction from the top of the gate spacer to the bottom of the gate spacer.

[0033] In order to solve the above problems, the present invention further provides a three-dimensional memory, comprising:

[0034] substrate;

[0035] A stacked structure, located on the substrate, comprising alternately stacked interlayer insulating layers and gate layers;

[0036] a gate spacer, located on the substrate and penetrating the stacked structure;

[0037] An opening is connected to the gate partition groove, and the opening is located between adjacent interlayer insulating layers and between the interlayer insulating layer at the bottom layer of the stacking structure and the substrate. At least the width of the opening located at the bottom layer of the stacking structure is greater than the width of the opening located at the top layer of the stacking structure.

[0038] Optionally, the gate trench extends into the substrate, and a width of a bottom portion of the gate trench is smaller than a width of a top portion of the gate trench.

[0039] Optionally, the width of the opening gradually increases in a direction from the top of the gate spacer to the bottom of the gate spacer.

[0040] Optionally, a width of the opening between the interlayer insulating layer at the bottom layer of the stacked structure and the substrate is 1 nm to 5 nm.

[0041] Optionally, also include:

[0042] an insulating layer, filling the opening and covering the sidewalls of the gate trench;

[0043] The common source electrode fills the gate trench and covers the surface of the insulating layer.

[0044] The three-dimensional memory and its formation method provided by the present invention form a dielectric layer covering the surface of the conductive layer in the gate trench before etching the conductive layer, and utilize a modification process to make the etching rate of the bottom of the dielectric layer greater than the etching rate of the top of the dielectric layer. Therefore, in the process of etching away part of the conductive layer, the etching amount of the conductive layer at the bottom of the gate trench can be greater than the etching amount of the conductive layer at the top of the gate trench, reducing or even avoiding the residual conductive layer at the bottom of the gate trench, reducing or even avoiding the leakage phenomenon between gates, thereby improving the electrical performance of the three-dimensional memory and improving the yield of the three-dimensional memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Attachment Figure 1 is a flow chart of a method for forming a three-dimensional memory in a specific embodiment of the present invention;

[0046] Attachment Figures 2A-2D 1 is a schematic cross-sectional view of the main processes in forming a three-dimensional memory in a specific embodiment of the present invention;

[0047] Attachment Figure 3 It is a schematic structural diagram of a three-dimensional memory in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0048] The specific embodiments of the three-dimensional memory and the method for forming the same provided by the present invention are described in detail below with reference to the accompanying drawings.

[0049] In the current 3D memory manufacturing process, after metal gates are filled through gate spacers, the ends of the metal gates must be etched through the gate spacers to isolate adjacent metal gates. However, metal residue is prone to forming in the smaller feature-size areas at the bottom of the gate spacers, leading to leakage between the gates and affecting the electrical performance of the 3D memory.

[0050] In order to reduce the leakage between gates in a three-dimensional memory and thus improve the electrical performance of the three-dimensional memory, this embodiment provides a method for forming a three-dimensional memory. Figure 1 1 is a flow chart of a method for forming a three-dimensional memory in a specific embodiment of the present invention, Figures 2A-2D 1 is a schematic cross-sectional view of the main process in forming a three-dimensional memory in a specific embodiment of the present invention. The three-dimensional memory described in this specific embodiment may be, but is not limited to, a 3D NAND memory. Figure 1 、 Figure 2A-2D As shown, the method for forming the three-dimensional memory includes the following steps:

[0051] Step S11, forming a base, the base comprising a substrate 20, a stacked structure 21 located on the substrate 20, and a gate trench 22 penetrating the stacked structure 21, the stacked structure 21 comprising alternately stacked interlayer insulating layers 211 and conductive layers 212, the conductive layers 212 also covering the sidewalls and bottom wall of the gate trench 22, as shown in FIG. Figure 2A shown.

[0052] Optionally, the specific steps of forming the substrate include:

[0053] providing a substrate 20;

[0054] forming a stacked layer on the surface of the substrate 20, wherein the stacked layer includes alternately stacked interlayer insulating layers 211 and sacrificial layers;

[0055] forming a gate trench 22 penetrating the stacked layer;

[0056] The sacrificial layer is removed along the gate trench 22 to form a gap between two adjacent layers of the interlayer insulating layer 211 ;

[0057] The conductive layer 212 is formed to fill the gap and at least cover the sidewalls and bottom wall of the gate trench 22 .

[0058] Specifically, the substrate 20 can be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium On Insulator) substrate, etc. In this specific embodiment, the substrate 20 is preferably a Si substrate, which is used to support the device structure thereon. The stacked layer includes the interlayer insulating layer 211 and the sacrificial layer alternately stacked in a direction perpendicular to the substrate 20. The material of the interlayer insulating layer 211 can be an oxide material (such as silicon dioxide), and the material of the sacrificial layer can be a nitride material (such as silicon nitride). Afterwards, the stacked layer is etched to form the gate partition 22 that passes through the stacked layer in a direction perpendicular to the substrate 20. The sacrificial layer is etched away along the gate partition 22 using a wet etching process to form a gap between two adjacent layers of the interlayer insulating layer 211. Next, a conductive material is deposited along the gate trench 22 to form the conductive layer 212 that fills the gap and continuously covers at least the sidewalls and bottom wall of the gate trench 22. The conductive layer 212 may be made of, but is not limited to, a metal material, such as tungsten.

[0059] Step S12: forming a dielectric layer 23 in the gate trench 22 to cover the surface of the conductive layer 212. Figure 2B shown.

[0060] Optionally, the specific steps of forming the dielectric layer 23 covering the surface of the conductive layer 212 in the gate trench 22 include:

[0061] A high-k dielectric material is deposited at least in the gate trench 22 to form a dielectric layer 23 covering at least the surface of the conductive layer 212 .

[0062] Specifically, a high dielectric constant material can be deposited in the gate trench 22 using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, to form the dielectric layer 23 on the surface of the conductive layer 212 covering the sidewalls and bottom wall of the gate trench 22. The high dielectric constant material can be a metal oxide material, such as aluminum oxide, zirconium dioxide, lanthanum oxide, or hafnium dioxide. A person skilled in the art can select the thickness of the deposited dielectric layer 23 based on actual needs, for example, based on the thickness of the conductive layer 212 that needs to be etched away later. In this specific embodiment, the thickness of the dielectric layer 23 can be 1 nm to 10 nm.

[0063] Step S13, modifying the dielectric layer 23 so that at least the etching rate of the bottom of the dielectric layer 23 is greater than the etching rate of the top of the dielectric layer 23, as shown in FIG. Figure 2C shown.

[0064] Among them, the specific method of modifying the dielectric layer 23 can be selected by those skilled in the art according to actual needs. For example, it can be but not limited to element doping treatment or annealing treatment, as long as the etching rate of at least the bottom of the dielectric layer 23 is greater than the etching rate of the top of the dielectric layer 23 after the modification treatment.

[0065] In order to simplify the steps of modifying the dielectric layer 23 and improve the manufacturing efficiency of the three-dimensional memory, the specific steps of modifying the dielectric layer 23 optionally include:

[0066] The dielectric layer 23 is annealed.

[0067] Optionally, the specific steps of annealing the dielectric layer 23 include:

[0068] The dielectric layer 23 is subjected to a rapid thermal annealing process.

[0069] Optionally, the specific steps of making at least the etching rate of the bottom of the dielectric layer 23 greater than the etching rate of the top of the dielectric layer 23 include:

[0070] The heat source is placed above the gate spacer 22 so that during the annealing process, at least the temperature of the bottom of the dielectric layer 23 is lower than the temperature of the top of the dielectric layer 23 .

[0071] Specifically, a heat source such as a laser source or a halogen lamp can be placed above the gate trench 22, and a laser beam or electron beam can be used to irradiate the dielectric layer 23, thereby performing a rapid thermal annealing process on the dielectric layer 23. Since the heat source is located above the gate trench 22, during the annealing process, at least the temperature at the bottom of the dielectric layer 23 is lower than the temperature at the top of the dielectric layer 23. For example, during the annealing process, the temperature of the dielectric layer 23 in the gate trench 22 gradually decreases in a direction from the top of the gate trench 22 to the bottom of the gate trench 22. This results in the annealing degree at the top of the dielectric layer 23 in the gate trench 22 being greater than the annealing degree at the bottom of the dielectric layer 23. For example, the annealing degree of the dielectric layer 23 in the gate trench 22 gradually decreases in a direction from the top of the gate trench 22 to the bottom of the gate trench 22. The difference in annealing degree will cause the difference in etching rate, that is, the etching rate of at least the bottom of the dielectric layer 23 is greater than the etching rate of the top of the dielectric layer 23. For example, the etching rate of the dielectric layer 23 in the gate trench 22 gradually increases in the direction from the top of the gate trench 22 to the bottom of the gate trench 22.

[0072] Those skilled in the art can adjust the temperature difference between the bottom of the dielectric layer 23 and the top of the dielectric layer 23 by adjusting the annealing conditions (e.g., the temperature of the heat source), thereby adjusting the difference between the annealing degree at the bottom of the dielectric layer 23 and the annealing degree at the top of the dielectric layer 23, and ultimately adjusting the difference between the etching rate at the bottom of the dielectric layer 23 and the etching rate at the top of the dielectric layer 23.

[0073] Step S14, etching away the modified dielectric layer 23 and the conductive layer 212 at least on the sidewalls and bottom wall of the gate trench 22. Figure 2D shown.

[0074] In this specific embodiment, through modification, the etching rate of at least the bottom of the dielectric layer 23 is greater than the etching rate of the top of the dielectric layer 23. Therefore, during the etching of the dielectric layer 23 and the conductive layer 212, the dielectric layer 23 at the bottom of the gate trench 22 is etched faster than the dielectric layer 23 at the top of the gate trench 22. As a result, the conductive layer 212 at the bottom of the gate trench 22 begins to etch earlier than the conductive layer 212 at the top of the gate trench 22. Since the etching rate of the conductive layer 212 is the same at all locations, the etching amount of the conductive layer 212 at least at the bottom of the gate trench 22 can be greater than the etching amount of the conductive layer 212 at the top of the gate trench 22. This reduces or even avoids the residual conductive layer 212 in the region with smaller characteristic dimensions at the bottom of the gate trench 22, thereby reducing the probability of leakage between gates, improving the electrical performance of the three-dimensional memory, and increasing the yield of the three-dimensional memory.

[0075] Optionally, the specific steps of etching away the modified dielectric layer 23 and the conductive layer 212 at least on the sidewalls and bottom wall of the gate trench 22 include:

[0076] The modified dielectric layer 23 and at least the conductive layer 212 located on the sidewalls and bottom wall of the gate trench 22 are etched away using a wet etching process.

[0077] In other specific embodiments, those skilled in the art may also use a dry etching process or other etching processes to etch away the modified dielectric layer 23 and at least the conductive layer 212 located on the sidewalls and bottom wall of the gate trench 22 .

[0078] Optionally, the specific steps of etching away the modified dielectric layer 23 and the conductive layer 212 at least on the sidewalls and bottom wall of the gate trench 22 include:

[0079] The modified dielectric layer 23 and at least the conductive layer 212 located on the sidewalls and bottom wall of the gate trench 22 are etched away in the same etching process.

[0080] Optionally, the specific steps of etching away the modified dielectric layer 23 and the conductive layer 212 at least on the sidewalls and bottom wall of the gate trench 22 in the same etching process include:

[0081] In the same etching process, the modified dielectric layer 23, the conductive layer 212 located on the side walls and bottom walls of the gate trench 22, and a portion of the conductive layer 212 located between adjacent interlayer insulating layers 211 are etched away to form openings 24 between adjacent interlayer insulating layers 211 and between the interlayer insulating layer 211 at the bottom layer of the stacked structure 21 and the substrate 20.

[0082] Optionally, the width W of the opening 24 gradually increases in a direction from the top of the gate partition 22 to the bottom of the gate partition 22 .

[0083] Specifically, by selecting a suitable etchant, the entire modified dielectric layer 23, the conductive layer 212 located on the side walls and bottom walls of the gate partition 22, and a portion of the conductive layer 212 located between adjacent interlayer insulating layers 211 can be removed in the same wet etching process, and an opening 24 is formed between two adjacent interlayer insulating layers 211 and between the interlayer insulating layer 211 at the bottom of the stacked structure 21 and the substrate 20, thereby forming a gate layer 213 located between the two adjacent interlayer insulating layers 211, and the two adjacent gate layers 213 are isolated from each other, and each gate layer 213 has an opening 24 that penetrates the layer, so that the two adjacent gate layers 213 can be fully isolated. Because the etching rate at the bottom of the modified dielectric layer 23 is higher than the etching rate at the top of the dielectric layer 23, the amount of conductive layer 212 etched at the bottom of the gate trench 22 is greater than the amount of conductive layer 212 etched at the top of the gate trench 22. Furthermore, the amount of conductive layer 212 etched gradually increases along the direction from the top of the gate trench 22 to the bottom of the gate trench 22, resulting in a width of at least the opening 24 at the bottom of the stacked structure 21 greater than the width of the opening 24 at the top of the stacked structure 21. In one embodiment, the width of the opening 24 gradually increases along the direction from the top of the gate trench 22 to the bottom of the gate trench 22. In this embodiment, the width W of the opening 24 refers to the distance between the end surface of the gate layer 213 facing the gate trench 22 and the sidewall of the gate trench 22, along a direction parallel to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the stacked structure 21).

[0084] In another embodiment, the gate trench 22 extends into the interior of the substrate 20, that is, the gate trench 22 includes a first portion penetrating the stacked structure 21 in a direction perpendicular to the top surface of the substrate 20, and a second portion extending into the substrate 20 and connected to the first portion. The inner walls of the first portion and the second portion are both covered with the conductive layer 212. In the process of removing part of the conductive layer 212 through a wet etching process, the etching of the conductive layer 212 in the second portion will affect the width of the bottom layer of the opening 24 in the stacked structure 21 (that is, the opening between the bottom layer of the interlayer insulating layer 211 in the stacked structure 21 and the substrate 20), so that the width of the bottom layer of the opening 24 in the stacked structure 21 is less than or equal to the width of the opening 24 in the adjacent upper layer.

[0085] In another embodiment, even if the etching of the conductive layer 212 in the second part affects the width of the opening 24 in the bottom layer of the stacked structure 21 (i.e., the opening between the bottom interlayer insulating layer 211 in the stacked structure 21 and the substrate 20), due to the smaller depth of the second part or the smaller amount of the conductive layer 212 in the second part, the width of the opening 24 in the bottom layer of the stacked structure 21 is greater than the width of the opening 24 in the adjacent upper layer.

[0086] In addition, this embodiment also provides a three-dimensional memory. Figure 3 The three-dimensional memory provided in this embodiment can be configured as follows: Figure 1 、 Figure 2A-2D The three-dimensional memory is formed by the method shown in FIG. Figure 3 As shown, the three-dimensional memory includes:

[0087] substrate 20;

[0088] The stacked structure 21 is located on the substrate 20 and includes interlayer insulating layers 211 and gate layers 213 that are alternately stacked;

[0089] a gate partition 22 , located on the substrate 20 and penetrating the stack structure 21 ;

[0090] The opening 24 is connected to the gate partition 22. The opening 24 is located between adjacent interlayer insulating layers 211, and between the interlayer insulating layer 211 at the bottom layer of the stacking structure 21 and the substrate 20. At least the width of the opening 24 located at the bottom layer of the stacking structure 21 is greater than the width of the opening 24 located at the top layer of the stacking structure 21.

[0091] In this specific embodiment, the opening 24 at the bottom of the stacked structure 21 refers to the opening 24 between the interlayer insulating layer 211 at the bottom of the stacked structure 21 and the substrate 20, that is, the opening 24 on the side of the gate layer 213 at the bottom of the stacked structure 21 facing the gate trench 22. The opening 24 at the top of the stacked structure 21 refers to the opening 24 between the two adjacent interlayer insulating layers 211 at the top of the stacked structure 21, that is, the opening 24 on the side of the gate layer 213 at the top of the stacked structure 21 facing the gate trench 22.

[0092] Optionally, the gate trench 22 extends into the substrate 20 , and the width of the bottom of the gate trench 22 is smaller than the width of the top of the gate trench 22 .

[0093] In this embodiment, the bottom width of the gate trench 22 refers to the width of the bottom of the gate trench 22 in a direction parallel to the top surface of the substrate 20. The top width of the gate trench refers to the width of the top of the gate trench 22 in a direction parallel to the top surface of the substrate 20.

[0094] Optionally, the width of the opening 24 gradually increases in a direction from the top of the gate partition 22 to the bottom of the gate partition 22 .

[0095] Optionally, a width of the opening 24 between the interlayer insulating layer 211 at the bottom of the stacked structure 21 and the substrate 20 is 1 nm to 5 nm.

[0096] Optionally, the three-dimensional memory further includes:

[0097] an insulating layer, filling the opening 24 and covering the sidewalls of the gate trench 22;

[0098] The common source electrode fills the gate trench 22 and covers the surface of the insulating layer.

[0099] The three-dimensional memory and its formation method provided in this specific embodiment form a dielectric layer covering the surface of the conductive layer in the gate trench before etching the conductive layer, and utilize a modification process to make the etching rate at the bottom of the dielectric layer greater than the etching rate at the top of the dielectric layer. As a result, during the process of etching away a portion of the conductive layer, the amount of the conductive layer etched at the bottom of the gate trench can be greater than the amount of the conductive layer etched at the top of the gate trench, reducing or even preventing the residual conductive layer at the bottom of the gate trench and reducing or even preventing leakage between gates, thereby improving the electrical performance of the three-dimensional memory and the yield of the three-dimensional memory.

[0100] The above description is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a three-dimensional memory, characterized in that: The steps include: forming a base, the base comprising a substrate, a stacked structure located on the substrate, and a gate trench penetrating the stacked structure, the stacked structure comprising alternately stacked interlayer insulating layers and conductive layers, the conductive layer also covering sidewalls and a bottom wall of the gate trench; forming a dielectric layer in the gate trench to cover the surface of the conductive layer; Performing a modification treatment on the dielectric layer so that at least the etching rate of the bottom of the dielectric layer is greater than the etching rate of the top of the dielectric layer; The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away.

2. The method for forming a three-dimensional memory according to claim 1, wherein: The specific steps of forming the substrate include: providing a substrate; forming a stacked layer on the surface of the substrate, wherein the stacked layer comprises interlayer insulating layers and sacrificial layers stacked alternately; forming a gate trench penetrating the stacked layer; removing the sacrificial layer along the gate trench to form a gap between two adjacent interlayer insulating layers; The conductive layer is formed to fill the gap and at least cover the sidewalls and bottom wall of the gate trench.

3. The method for forming a three-dimensional memory according to claim 2, wherein: The specific steps of forming a dielectric layer covering the surface of the conductive layer in the gate trench include: A high dielectric constant material is deposited at least in the gate isolation groove to form a dielectric layer covering at least the surface of the conductive layer.

4. The method for forming a three-dimensional memory according to claim 3, wherein: The specific steps of modifying the dielectric layer include: The dielectric layer is subjected to an annealing process.

5. The method for forming a three-dimensional memory according to claim 4, wherein: The specific steps of annealing the dielectric layer include: Performing a rapid thermal annealing process on the dielectric layer.

6. The method for forming a three-dimensional memory according to claim 5, wherein: The specific steps of making at least the etching rate of the bottom of the dielectric layer greater than the etching rate of the top of the dielectric layer include: A heat source is placed above the gate spacer, so that during annealing, at least the temperature of the bottom of the dielectric layer is lower than the temperature of the top of the dielectric layer.

7. The method for forming a three-dimensional memory according to claim 1, wherein: The specific steps of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench include: The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away using a wet etching process.

8. The method for forming a three-dimensional memory according to claim 7, wherein: The specific steps of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench include: The modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench are etched away in the same etching process.

9. The method for forming a three-dimensional memory according to claim 8, wherein: The specific steps of etching away the modified dielectric layer and the conductive layer at least on the sidewalls and bottom wall of the gate trench in the same etching process include: The modified dielectric layer, the conductive layer on the sidewalls and bottom wall of the gate trench, and a portion of the conductive layer between adjacent interlayer insulating layers are etched away in the same etching process, thereby forming openings between adjacent interlayer insulating layers and between the interlayer insulating layer at the bottom of the stacked structure and the substrate.

10. The method for forming a three-dimensional memory according to claim 9, wherein: The width of the opening gradually increases in a direction from the top of the gate spacer to the bottom of the gate spacer.

11. A three-dimensional memory, characterized in that: include: substrate; A stacked structure, located on the substrate, comprising alternately stacked interlayer insulating layers and gate layers; a gate partition groove, located on the substrate and passing through the stack structure, wherein the gate partition groove extends into the substrate; An opening is connected to the gate partition groove, and the opening is located between adjacent interlayer insulating layers, and between the interlayer insulating layer at the bottom layer of the stacking structure and the substrate. At least the width of the opening at the bottom layer of the stacking structure is greater than the width of the opening at the top layer of the stacking structure, and the width of the opening at the bottom layer of the stacking structure is less than or equal to the width of the opening of the upper layer adjacent thereto.

12. The three-dimensional memory according to claim 11, wherein: The width of the bottom of the gate partition groove is smaller than the width of the top of the gate partition groove.

13. The three-dimensional memory according to claim 11, wherein: The width of the opening between the interlayer insulating layer at the bottom of the stacked structure and the substrate is 1 nm to 5 nm.

14. The three-dimensional memory according to claim 11, wherein: Also includes: an insulating layer, filling the opening and covering the sidewalls of the gate trench; The common source electrode fills the gate trench and covers the surface of the insulating layer.

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