Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a method for preparing a semiconductor device, wherein a third sidewall structure is formed on the side of the first sidewall structure of the storage area and on the control gate, and a third sidewall structure is also formed on both sides of the gate structure of the logic area; and then a fourth sidewall structure is formed on both sides of the third sidewall structure of the storage area and on both sides of the third sidewall structure of the logic area. The present invention also provides a semiconductor device. By first forming the third sidewall structure in the storage area and then forming the fourth sidewall structure, the lateral length of the control gate and the floating gate is increased by the lateral length of the third sidewall structure, while the total lateral length of the storage area device can remain unchanged. This allows the present application to increase the length of the control gate and the area of overlap between the control gate and the floating gate without increasing the area of the storage area device, thereby increasing the coupling coefficient from the control gate to the floating gate and improving the control capability of the control gate.

Description

Technical Field

[0001] The present application relates to the technical field of split-gate flash memory devices and CMOS device manufacturing, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Floating-gate (FG) split-gate flash memory devices are widely used in various embedded electronic products such as financial IC cards and automotive electronics due to their high storage integration density. Improving the storage integration density is beneficial to saving chip area and reducing manufacturing costs.

[0003] Further scaling of 2-bit / cell floating-gate split-gate flash memory devices revealed that the coupling coefficient from the control gate (CG) to the FG decreased significantly due to the reduction in the overlap area between the control gate (CG) and the FG. While the overlap area between the select gate (SG) and the FG remained essentially unchanged, the coupling coefficient from the SG to the FG increased rapidly. This rapid increase in the SG-to-FG coupling coefficient deteriorated the device's CG's turn-off capability (CG's control capability), leading to severe leakage current, i.e., deteriorating the current characteristics of the flash cell subdomains. Therefore, increasing the CG coupling coefficient (i.e., increasing the overlap area between the CG and the FG) and reducing the SG coupling coefficient are crucial for further scaling of floating-gate split-gate flash memory. Summary of the Invention

[0004] The present application provides a semiconductor device and a method for manufacturing the same, which can solve the problem of poor turn-off capability (control capability) of a control gate in a floating-gate split-gate flash memory device.

[0005] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, the substrate comprising a storage area and a logic area, and having a stacked gate oxide layer, a floating gate, an ONO dielectric layer, a control gate and a silicon nitride layer formed on the substrate;

[0007] forming a first spacer structure, a second spacer structure, a tunneling oxide layer, a select gate, and a select gate oxide layer in sequence in the storage area, wherein the first spacer structure is located in the silicon nitride layer, the second spacer structure is located in the control gate and the ONO dielectric layer and covers a portion of a side surface of the first spacer structure, and the tunneling oxide layer is located in the floating gate and the gate oxide layer and covers the remaining side surfaces of the second spacer structure and the first spacer structure;

[0008] removing the silicon nitride layer, the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer of the logic area;

[0009] forming a gate structure on a surface of the substrate in the logic region;

[0010] Performing ion implantation on the substrate at both sides of the gate structure of the logic region to form a first LDD region;

[0011] removing the silicon nitride layer on both sides of the first spacer structure of the storage area;

[0012] forming third spacer structures on both sides of the first spacer structure in the storage area and on both sides of the gate structure in the logic area respectively;

[0013] removing the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer on both sides of the third spacer structure of the storage area;

[0014] Performing ion implantation on the substrate at both sides of the third sidewall structure of the storage area to form a second LDD region; and

[0015] Fourth spacer structures are formed on both sides of the third spacer structure in the storage area and on both sides of the third spacer structure in the logic area.

[0016] Optionally, in the method for manufacturing the semiconductor device, after forming the second LDD region in the storage area and before forming the fourth spacer structure in the storage area and the logic area, the method for manufacturing the semiconductor device further includes:

[0017] A rapid thermal annealing process is performed on the memory region and the logic region to simultaneously activate the second LDD region of the memory region and the first LDD region of the logic region.

[0018] Optionally, in the method for preparing the semiconductor device, the third sidewall structure of the storage area and the third sidewall structure of the logic area are both lateral sizes.

[0019] Optionally, in the method for preparing the semiconductor device, after removing the silicon nitride layer, the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer of the logic region, and before forming the gate structure of the logic region, the method for preparing the semiconductor device further includes:

[0020] Ion implantation is performed on the substrate of the logic region to form a well region, and the first LDD region is located on the well region.

[0021] Optionally, in the method for manufacturing the semiconductor device, in the logic region, the conductivity type of the implanted ions in the well region is different from the conductivity type of the implanted ions in the first LDD region.

[0022] Optionally, in the method for manufacturing the semiconductor device, after forming the gate structure of the logic region and before forming the first LDD region of the logic region, the method for manufacturing the semiconductor device further includes:

[0023] A thermal oxidation process is performed on the logic region.

[0024] Optionally, in the method for manufacturing the semiconductor device, the step of forming the first spacer structure, the second spacer structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage area includes:

[0025] Etching the silicon nitride layer of the storage area to form a first trench;

[0026] forming a first spacer structure in the first trench, wherein the first spacer structure covers a sidewall of the first trench;

[0027] Etching the control gate and the ONO dielectric layer at the bottom wall of the first trench to form a second trench;

[0028] forming a second spacer structure in the second trench, wherein the second spacer structure covers a portion of a sidewall of the second trench;

[0029] Etching the floating gate and the gate oxide layer on the bottom wall of the second trench to form a third trench;

[0030] forming a tunneling oxide layer, wherein the tunneling oxide layer covers the bottom wall and sidewalls of the third trench;

[0031] forming a select gate, the select gate filling the third trench; and

[0032] A select gate oxide layer is formed, wherein the select gate oxide layer covers the select gate.

[0033] Optionally, in the method for preparing the semiconductor device, the gate structure of the logic region includes: a stacked gate dielectric layer and a polysilicon gate located on a substrate of the logic region.

[0034] On the other hand, an embodiment of the present application further provides a semiconductor device, including:

[0035] a substrate comprising a storage area and a logic area;

[0036] A stacked gate oxide layer, a floating gate, an ONO dielectric layer, and a control gate, as well as a first spacer structure, a second spacer structure, a tunneling oxide layer, a select gate, and a select gate oxide layer, located on the storage area, wherein the first spacer structure is located on the control gate, the second spacer structure is located in the control gate and the ONO dielectric layer and covers a portion of a side surface of the first spacer structure, and the tunneling oxide layer is located in the floating gate and the gate oxide layer and covers the remaining side surfaces of the second spacer structure and the first spacer structure;

[0037] a gate structure located on the logic region;

[0038] a first LDD region in the substrate located on both sides of the gate structure of the logic region;

[0039] third spacer structures located on both sides of the first spacer structure in the logic area and on both sides of the gate structure in the logic area;

[0040] a second LDD region in the substrate located on both sides of the third sidewall structure of the storage region; and

[0041] Fourth spacer structures are located on both sides of the third spacer structure in the storage area and on both sides of the third spacer structure in the logic area.

[0042] The technical solution of this application has at least the following advantages:

[0043] In the present application, the third sidewall structure is first formed on the control gate in the storage area, and the fourth sidewall structure is then formed on the side of the control gate. As a result, the side of the control gate and the side of the floating gate have only the fourth sidewall structure, so that the lateral length of the control gate and the floating gate can be increased by the lateral length of the third sidewall structure, while the total lateral length of the storage area device can remain unchanged. Therefore, without increasing the lateral length and area of the storage area device, the length of the control gate can be increased, the area of overlap between the control gate and the floating gate can be increased, the coupling coefficient from the control gate to the floating gate can be increased, and the coupling coefficient of the select gate can be reduced, thereby improving the control capability of the control gate, avoiding device leakage, and improving the yield and reliability of the device.

[0044] Furthermore, the present application forms the first LDD region of the logic area before forming the third sidewall structure, so that the storage area and the logic area can share a rapid thermal annealing process to simultaneously activate the second LDD region of the storage area and the first LDD region of the logic area; while in the manufacturing process of traditional semiconductor devices, the activation of the second LDD region of the storage area and the activation of the first LDD region of the logic area are carried out in two steps, so the preparation method of the present application simplifies the process steps of the storage area device (split-gate flash memory device) and the logic area device (CMOS device), making the preparation process simpler, while improving production efficiency and reducing production costs.

[0045] In addition, the gate structure side of the logic area described in the present application has the third sidewall structure and the fourth sidewall structure, which is equivalent to that the total thickness of the sidewall structure on the gate structure side is not thinned, thereby being able to maintain all the performance of the logic area device (CMOS device), thereby improving the control capability of the control gate of the storage area while ensuring the yield of the CMOS device in the logic area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figures 1-8 is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention;

[0048] The description of the accompanying drawings is as follows:

[0049] A-storage area, B-logic area;

[0050] 100 - substrate, 101 - second LDD region, 110 - gate oxide layer, 120 - floating gate, 130 - ONO dielectric layer, 140 - control gate, 150 - silicon nitride layer, 160 - first spacer structure, 170 - second spacer structure, 180 - tunneling oxide layer, 190 - select gate, 300 - select gate oxide layer;

[0051] 200 - gate structure, 201 - first LDD region, 210 - gate dielectric layer, 220 - polysilicon gate;

[0052] 310-third side wall structure, 320-fourth side wall structure. DETAILED DESCRIPTION

[0053] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0054] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0056] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0057] On the one hand, the present invention provides a method for preparing a semiconductor device. Figures 1-8 , Figures 1-8 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a semiconductor device according to an embodiment of the present invention.

[0058] First, if Figure 1 As shown, a substrate 100 is provided. The substrate 100 includes a storage area A and a logic area B. A stacked gate oxide layer 110 , a floating gate 120 , an ONO dielectric layer 130 , a control gate 140 and a silicon nitride layer 150 are formed on the substrate 100 .

[0059] The ONO dielectric layer 130 is a stack of bottom silicon dioxide, silicon nitride, and top silicon dioxide.

[0060] It should be noted that, in this embodiment, if etching is performed only on the storage area A, a photoresist mask layer may be applied to the logic area B as a protective layer to protect the semiconductor structure on the logic area B, thereby preventing the semiconductor structure on the logic area B from being accidentally etched. Similarly, if etching is performed only on the logic area B, a photoresist mask layer may be applied to the storage area A as a protective layer to protect the semiconductor structure on the storage area A, thereby preventing the semiconductor structure on the storage area A from being accidentally etched.

[0061] Then, if Figure 2 As shown, a first spacer structure 160, a second spacer structure 170, a tunneling oxide layer 180, a select gate 190, and a select gate oxide layer 300 are sequentially formed in the storage area A. The steps of forming the first spacer structure 160, the second spacer structure 170, the tunneling oxide layer 180, the select gate 190, and the select gate oxide layer 300 in the storage area A may specifically include:

[0062] Step 1: etching the silicon nitride layer 150 in the storage area A to form a first trench;

[0063] Step 2: forming a first spacer structure 160 in the first trench, wherein the first spacer structure 160 covers the sidewall of the first trench;

[0064] Step three: etching the control gate 140 and the ONO dielectric layer 130 at the bottom wall of the first trench to form a second trench;

[0065] Step 4: forming a second spacer structure 170 in the second trench, wherein the second spacer structure 170 covers a portion of the sidewall of the second trench;

[0066] Step 5: etching the floating gate 120 and the gate oxide layer 110 at the bottom wall of the second trench to form a third trench;

[0067] Step 6: forming a tunneling oxide layer 180, wherein the tunneling oxide layer 180 covers the bottom wall and sidewalls of the third trench;

[0068] Step 7: forming a select gate 190, wherein the select gate 190 fills the third trench;

[0069] Step 8: forming a select gate oxide layer 300 , wherein the select gate oxide layer 300 covers the select gate 190 .

[0070] Next, refer to Figure 3 , the silicon nitride layer 150 , the control gate 140 , the ONO dielectric layer 130 , the floating gate 120 and the gate oxide layer 110 of the logic area B are removed.

[0071] Preferably, after removing the silicon nitride layer 150, the control gate 140, the ONO dielectric layer 130, the floating gate 120 and the gate oxide layer 110 of the logic area B, and before forming the gate structure 200 of the logic area B, the method for preparing the semiconductor device further includes: performing ion implantation on the substrate 100 of the logic area B to form a well region.

[0072] Further, such as Figure 3 As shown, a gate structure 200 is formed on the surface of the substrate 100 in the logic area B. Specifically, the gate structure 200 in the logic area B may include: a stacked gate dielectric layer 210 and a polysilicon gate 220 located on the substrate 100 in the logic area B, wherein the step of forming the gate structure 200 may specifically include: forming the gate dielectric layer 210 on the substrate 100 in the logic area B, then depositing the polysilicon gate 220 on the gate dielectric layer 210, and then etching away the polysilicon gate 220 and the gate dielectric layer 210 on both sides through photolithography and etching processes, and retaining the polysilicon gate 220 and the gate dielectric layer 210 directly above the well region of the logic area B to obtain the gate structure 200.

[0073] Preferably, in this embodiment, after forming the gate structure 200 of the logic region B, the method for preparing the semiconductor device may further include: performing a thermal oxidation process on the logic region B to form a protective film on the surface of the polysilicon gate 220 .

[0074] Then, if Figure 4 As shown, ion implantation is performed on the substrate 100 on both sides of the gate structure 200 of the logic region B to form a first LDD region 201 and a Halo region (ring region) (not shown) located on the side of the first LDD region 201. Specifically, the Halo region and the first LDD region 201 are located on the well region. The conductivity type of the implanted ions in the well region is the same as the conductivity type of the implanted ions in the Halo region, and is different from the conductivity type of the implanted ions in the first LDD region 201. For example, for an NMOS transistor device on the logic region B, the conductivity type of the implanted ions in the well region is P-type (for example, implanted boron ions), the conductivity type of the implanted ions in the first LDD region 201 is N-type (for example, implanted arsenic ions), and the Halo region is P-type (for example, implanted boron ions).

[0075] The full name of the first LDD region 201 is: first lightly doped drain region.

[0076] Further, such as Figure 5As shown, the silicon nitride layer 150 on both sides of the first spacer 160 of the storage area A is etched away to the surface of the control gate 140. Specifically, the silicon nitride layer 150 on both sides of the first spacer 160 of the storage area A can be etched away using a dry etching process or a wet etching process.

[0077] Next, continue to refer to Figure 5 , respectively forming a third spacer structure 310 on both sides of the first spacer structure 160 of the storage area A and on both sides of the gate structure 200 of the logic area B. Specifically, the third spacer structure 310 of the storage area A and the third spacer structure 310 of the logic area A are both lateral sizes of

[0078] Further, such as Figure 6 As shown, the control gate 140, the ONO dielectric layer 130, the floating gate 120, and the gate oxide layer 110 on both sides of the third spacer 310 of the storage area A are etched away. Specifically, in this embodiment, a dry etching process can be used to remove the control gate 140, the ONO dielectric layer 130, the floating gate 120, and the gate oxide layer 110 on both sides of the third spacer 310 of the storage area A. It is worth noting that when removing the control gate 140, the ONO dielectric layer 130, the floating gate 120, and the gate oxide layer 110 on both sides of the third spacer 310 of the storage area A, the logic area B can use a photoresist as a mask layer (protective layer) to prevent the semiconductor structure of the logic area B from being accidentally etched.

[0079] Then, if Figure 7 As shown, ion implantation is performed on the substrate 100 on both sides of the third spacer structure 310 of the storage area A to form a second LDD region 101 .

[0080] The full name of the second LDD region 101 is: second lightly doped drain region.

[0081] Preferably, after forming the second LDD region 101 of the memory area A, the method for fabricating the semiconductor device further comprises: performing a rapid thermal annealing process on the memory area A and the logic area B to simultaneously activate the second LDD region 101 of the memory area A and the first LDD region 201 and the Halo region of the logic area B. In the present application, by forming the first LDD region 201 of the logic area B before forming the third spacer 310, the memory area A and the logic area B can share a single rapid thermal annealing process to simultaneously activate the second LDD region 101 of the memory area A and the first LDD region 201 of the logic area B. In conventional semiconductor device manufacturing processes, activation of the second LDD region of the memory area and activation of the first LDD region of the logic area are performed in two separate steps. Therefore, in comparison, the fabrication method of the present application simplifies the process steps for the memory area device (split-gate flash memory device) and the logic area device (CMOS device), simplifying the fabrication process while improving production efficiency and reducing production costs.

[0082] Finally, if Figure 8 As shown, fourth spacers 320 are formed on both sides of the third spacer 310 in the memory area A and on both sides of the third spacer 310 in the logic area B. In this embodiment, the third spacer 310 and the fourth spacer 320 can be formed by first depositing a corresponding material layer covering the semiconductor structure, and then performing photolithography and etching processes to obtain the structures of the third spacer 310 and the fourth spacer 320 required in actual processing.

[0083] In the present application, the third spacer structure 310 is first formed on the control gate 140 in the storage area A, and then the fourth spacer structure 320 is formed on the side of the control gate 140, so that the side of the control gate 140 and the side of the floating gate 120 only have the fourth spacer structure 320, so that the lateral length of the control gate 140 and the floating gate 120 can be increased by the lateral length of the third spacer structure 310, and the control gate 140 and the floating gate 120 are equivalent to increasing the lateral length of the third spacer structure 310. The lateral length of the storage area device can be increased while the total lateral length of the storage area device can remain unchanged. Thus, the length of the control gate 140 can be increased without increasing the lateral length and area of the storage area device, the area of overlap between the control gate 140 and the floating gate 120 can be increased, the coupling coefficient between the control gate 140 and the floating gate 120 can be increased, and the coupling coefficient of the select gate 190 can be reduced, thereby improving the control capability of the control gate 140, avoiding device leakage, and improving the yield and reliability of the device. Furthermore, the gate structure 200 side of the logic area B has the third spacer structure 310 and the fourth spacer structure 320, which is equivalent to the total thickness of the spacer structure on the gate structure 200 side not being thinned, thereby maintaining all the performance of the logic area B device (CMOS device), thereby improving the control capability of the control gate 140 while ensuring the yield of the CMOS device.

[0084] Furthermore, after the fourth sidewall structure 320 is formed on the storage area A and the logic area B respectively, the method for preparing the semiconductor device also includes: performing source and drain injection on the substrate 100 on both sides of the fourth sidewall structure 320 of the storage area A and the substrate 100 on both sides of the fourth sidewall structure 320 of the logic area B to form respective source and drain regions.

[0085] On the other hand, the present invention also provides a semiconductor device. Figure 8 , the semiconductor device comprises:

[0086] A substrate 100, wherein the substrate 100 includes a storage area A and a logic area B;

[0087] A stacked gate oxide layer 110, a floating gate 120, an ONO dielectric layer 130, and a control gate 140, as well as a first spacer structure 160, a second spacer structure 170, a tunneling oxide layer 180, a select gate 190, and a select gate oxide layer 310 located on the storage area A, wherein the first spacer structure 160 is located on the control gate 140, the second spacer structure 170 is located in the control gate 140 and the ONO dielectric layer 130 and covers a portion of a side surface of the first spacer structure 160, and the tunneling oxide layer 180 is located in the floating gate 120 and the gate oxide layer 110 and covers the remaining side surfaces of the second spacer structure 170 and the first spacer structure 160;

[0088] A gate structure 200 located on the logic region B;

[0089] A Halo region and a first LDD region 201 in the substrate 100 located on both sides of the gate structure 200 in the logic region B;

[0090] a third spacer structure 310 located on both sides of the first spacer structure 160 of the logic region B and on both sides of the gate structure 200 of the logic region B;

[0091] a second LDD region 101 in the substrate 100 located on both sides of the third spacer structure 310 of the storage region A; and

[0092] The fourth spacer structures 320 are located on both sides of the third spacer structure 310 of the memory area A and on both sides of the third spacer structure 310 of the logic area B.

[0093] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a logic area, and having a stacked gate oxide layer, a floating gate, an ONO dielectric layer, a control gate and a silicon nitride layer formed on the substrate; forming a first spacer structure, a second spacer structure, a tunneling oxide layer, a select gate, and a select gate oxide layer in sequence in the storage area, wherein the first spacer structure is located in the silicon nitride layer, the second spacer structure is located in the control gate and the ONO dielectric layer and covers a portion of a side surface of the first spacer structure, and the tunneling oxide layer is located in the floating gate and the gate oxide layer and covers the remaining side surfaces of the second spacer structure and the first spacer structure; removing the silicon nitride layer, the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer of the logic area; forming a gate structure on a surface of the substrate in the logic region; Performing ion implantation on the substrate at both sides of the gate structure of the logic region to form a first LDD region; removing the silicon nitride layer on both sides of the first spacer structure of the storage area; forming third spacer structures on both sides of the first spacer structure in the storage area and on both sides of the gate structure in the logic area respectively; removing the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer on both sides of the third spacer structure of the storage area; Performing ion implantation on the substrate at both sides of the third sidewall structure of the storage area to form a second LDD region; and Fourth spacer structures are formed on both sides of the third spacer structure in the storage area and on both sides of the third spacer structure in the logic area.

2. The method for preparing a semiconductor device according to claim 1, wherein: After forming the second LDD region of the storage area and before forming the fourth spacer structure of the storage area and the logic area, the method for preparing the semiconductor device further includes: A rapid thermal annealing process is performed on the memory region and the logic region to simultaneously activate the second LDD region of the memory region and the first LDD region of the logic region.

3. The method for preparing a semiconductor device according to claim 1, wherein: The third sidewall structure of the storage area and the third sidewall structure of the logic area have a horizontal dimension of 4. The method for preparing a semiconductor device according to claim 1, wherein: After removing the silicon nitride layer, the control gate, the ONO dielectric layer, the floating gate, and the gate oxide layer of the logic region, and before forming the gate structure of the logic region, the method for preparing the semiconductor device further includes: Ion implantation is performed on the substrate of the logic region to form a well region, and the first LDD region is located on the well region.

5. The method for preparing a semiconductor device according to claim 4, wherein: In the logic region, the conductivity type of the implanted ions in the well region is different from the conductivity type of the implanted ions in the first LDD region.

6. The method for preparing a semiconductor device according to claim 1, wherein: After forming the gate structure of the logic region and before forming the first LDD region of the logic region, the method for preparing the semiconductor device further includes: A thermal oxidation process is performed on the logic region.

7. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming the first spacer structure, the second spacer structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage area includes: Etching the silicon nitride layer of the storage area to form a first trench; forming a first spacer structure in the first trench, wherein the first spacer structure covers a sidewall of the first trench; Etching the control gate and the ONO dielectric layer at the bottom wall of the first trench to form a second trench; forming a second spacer structure in the second trench, wherein the second spacer structure covers a portion of a sidewall of the second trench; Etching the floating gate and the gate oxide layer on the bottom wall of the second trench to form a third trench; forming a tunneling oxide layer, wherein the tunneling oxide layer covers the bottom wall and sidewalls of the third trench; forming a select gate, the select gate filling the third trench; and A select gate oxide layer is formed, wherein the select gate oxide layer covers the select gate.

8. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure of the logic region includes: a stacked gate dielectric layer and a polysilicon gate located on a substrate of the logic region.

9. A semiconductor device, characterized in that: include: a substrate comprising a storage area and a logic area; A stacked gate oxide layer, a floating gate, an ONO dielectric layer, and a control gate, as well as a first spacer structure, a second spacer structure, a tunneling oxide layer, a select gate, and a select gate oxide layer, located on the storage area, wherein the first spacer structure is located on the control gate, the second spacer structure is located in the control gate and the ONO dielectric layer and covers a portion of a side surface of the first spacer structure, and the tunneling oxide layer is located in the floating gate and the gate oxide layer and covers the remaining side surfaces of the second spacer structure and the first spacer structure; a gate structure located on the logic region; a first LDD region in the substrate located on both sides of the gate structure of the logic region; a third spacer structure located on both sides of the first spacer structure in the logic area and on both sides of the gate structure in the logic area, wherein in the storage area, the third spacer structure is located on the control gate and covers sides of the first spacer structure; a second LDD region in the substrate located on both sides of the third sidewall structure of the storage region; and a fourth sidewall structure located on both sides of the third sidewall structure in the storage area and on both sides of the third sidewall structure in the logic area, wherein, in the storage area, the fourth sidewall structure is located on the substrate and covers a side surface of the gate oxide layer, a side surface of the floating gate, a side surface of the ONO dielectric layer, a side surface of the control gate, and a partial side surface of the third sidewall structure.

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