Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include a method of forming an integrated assembly. A stack of vertically alternating first levels and second levels is formed over a conductive structure. The first levels include a first material and the second levels include an insulative second material. Channel material openings are formed extending through the stack and through at least some of the strips. Channel material pillars are formed within the channel material openings. Slits are formed extending through the stack and through the sacrificial material. The first sacrificial material is replaced with a first conductive material, and then the second sacrificial material is replaced with a second conductive material. At least some of the first material of the stack is replaced with a third conductive material. Some embodiments include an integrated assembly.

Description

Technical Field

[0001] A method for forming an integrated component (e.g., an integrated memory device). Integrated component. Background Technology

[0002] Memory provides data storage for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0004] Before specifically describing NAND, it may be helpful to describe more generally the relationships within an integrated arrangement of memory arrays. Figure 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transfer information to and from memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in memory cells 1003 are to be accessed. Sensing amplifier circuitry 1015 operates to determine the value of information read from memory cells 1003. I / O circuit 1017 transmits information values ​​between memory array 1002 and input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent the values ​​of information read from or to be written to memory cell 1003. Other devices can communicate with device 1000 via I / O lines 1005, address lines 1009, or control lines 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013, the signals representing values ​​of information to be read from or programmed into memory cell 1003. Column decoder 1008 can selectively activate CSEL1 to CSELn signals based on address signals A0 to AX on address line 1009. Selection circuit 1040 can select signals on first data line 1006 and second data line 1013 to enable communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple charge storage device strings. In a first direction (Z-Z'), each charge storage device string may include, for example, thirty-two charge storage devices stacked one on top of the other, wherein each charge storage device corresponds to, for example, one of thirty-two rows (e.g., row 0 to row 31). The charge storage devices of the corresponding strings may share a common channel region, for example, a common channel region formed in a pillar of a corresponding semiconductor material (e.g., polysilicon), around which the charge storage device strings are formed. In a second direction (X-X'), each of sixteen first groups of multiple strings may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., “global control gate (CG) lines”, also called word lines WL). Each of the access lines may couple to a charge storage device within a row. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same row) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. On a third direction (Y-Y'), each of eight second groups of multiple strings may include sixteen strings coupled by a corresponding one of eight data lines. The size of a memory block may include 1,024 pages and approximately 16 MB (e.g., 16WL × 32 rows × 2 bits = 1,024 pages / block, block size = 1,024 pages × 16KB / page = 16 MB). The number of strings, rows, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in Figure 2.

[0006] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction. The memory block 300 comprises fifteen charge storage device strings from one of sixteen first groups of strings described in Figure 2. The multi-string memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I Puzzle Series j and puzzle series KEach subset (e.g., a tile array) comprises a “partial block” (sub-block) of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to the SGDs of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD drivers 332, 334, 336 via a corresponding one of these sub-SGD drivers, where each sub-SGD line corresponds to a specific subset (e.g., a tile array). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the corresponding partial block (e.g., a tile array) string, independent of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a tile array). Each of the sub-SGS drivers 322, 324, 326 may couple or disconnect the SGS of the string of the corresponding partial block (e.g., a tile array) independently of the SGS of the strings of other partial blocks. A global access line (e.g., a global CG line) 350 may be coupled to a charge storage device corresponding to a corresponding row of each of the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314, 316. Each of the substring drivers can simultaneously couple or disconnect the charge storage device corresponding to the corresponding sub-block and / or row, independently of the charge storage devices of other sub-blocks and / or other rows. The charge storage devices corresponding to the corresponding subset (e.g., a sub-block) and the corresponding row may include charge storage devices of a “sub-row” (e.g., a single “patch”). The string corresponding to the corresponding subset (e.g., a sub-block) may be coupled to a corresponding one of sub-sources 372, 374, and 376 (e.g., “patch source”), wherein each sub-source is coupled to a corresponding power source.

[0007] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG4.

[0008] Memory array 200 includes word lines 2021 to 202 N And bit lines 2281 to 228 M .

[0009] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can store charge using floating gate materials (e.g., polysilicon) or charge trapping materials (e.g., silicon nitride, metal nanodots, etc.).

[0010] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side selected gate SGS) 210 and a drain select device (e.g., drain-side selected gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated by boxes in FIG. 4.

[0011] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0012] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to a word line 202. Columns of the charge storage transistor 208 are those transistors coupled to a given positioning line 228 within a NAND string 206. Rows of the charge storage transistor 208 are those transistors typically coupled to a given word line 202.

[0014] Block erasure of vertically stacked memory cells in a three-dimensional NAND architecture can be performed by generating hole carriers underneath them and then using an electric field to sweep the hole carriers upwards along the memory cells.

[0015] A gate-induced drain leakage (GIDL) can be provided using a transistor's gating structure, which generates holes for block erasure of memory cells. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the memory cell string can be configured as channel material pillars, and regions of these pillars can be gated and coupled to the SGS device. The gated portion of the channel material pillar overlaps with the gate of the SGS device.

[0016] At least some of the gatedly coupled portions of the heavily doped channel material pillars may be required. In some applications, the gatedly coupled portions may include both a heavily doped lower region and a lightly doped upper region; wherein both regions overlap with the gate of the SGS device. Specifically, overlapping with the lightly doped region provides the SGS device with non-drain "OFF" characteristics, and overlapping with the heavily doped region provides the SGS device with drain GIDL characteristics. The terms "heavily doped" and "lightly doped" are used relative to each other rather than relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than the adjacent "lightly doped" region and may or may not include heavy doping in the conventional sense. Similarly, a "lightly doped" region is less doped than the adjacent "heavily doped" region and may or may not include light doping in the conventional sense. In some applications, the term "lightly doped" refers to having a doping density of less than or equal to about 10. 18 atoms / cm 3 Semiconductor materials with doped materials, and the term "heavily doped" refers to materials with a dopant concentration greater than or equal to about 10. 22 atoms / cm 3 Semiconductor materials with dopants.

[0017] The channel material can be initially doped to a light doping level, and then a heavily doped region can be formed by diffusion from the adjacent doped semiconductor material outward.

[0018] The goal is to develop new methods for forming memory devices and to develop new memory devices. Summary of the Invention

[0019] One aspect of this disclosure provides a method of forming an integrated component, the method comprising: forming transversely alternating first and second strips over a conductive structure, the first strips comprising a first sacrificial material and the second strips comprising a second sacrificial material; forming a stack of vertically alternating first and insulating second layers over the strips, the first layer comprising a first material and the insulating second layer comprising an insulating second material; forming an opening extending through the stack and through at least some of the strips; forming a unit material pillar within the opening; forming a slit extending through the stack and through the strips, the strips extending along a first direction and the slit extending along a second direction intersecting the first direction; replacing the first sacrificial material with a first conductive material, and then replacing the second sacrificial material with a second conductive material; and replacing at least some of the first materials of the stack with a third conductive material, thereby forming the stack to include a conductive first layer vertically alternating with the insulating second layer.

[0020] Another aspect of this disclosure provides an integrated component comprising: a conductive wide area; alternating first and second structures above the conductive wide area, the first and second structures extending along a first horizontal direction and alternating with each other along a second horizontal direction, the interface between the first and second structures being a detectable boundary region; a stack above the alternating structures and including a conductive first level alternating with an insulating second level along a vertical direction; a cell material pillar extending through the stack and through the structure into the conductive wide area; and a memory cell along the conductive first level and including a region of the cell material pillar.

[0021] Another aspect of this disclosure provides an integrated component comprising: a memory block region situated between a pair of slats extending along a first horizontal direction; a conductive wide region situated below the slats and directly abutting a lower region of the slats; a laminate situated above the conductive wide region and between the slats, the laminate including a first structure alternating with a second structure along a lateral direction, the first and second structures extending along a second horizontal direction substantially orthogonal to the first horizontal direction, the interface between the first and second structures being a detectable boundary region; a stack situated above the laminate and including a conductive first level alternating with an insulating second level along a vertical direction; a cell material pillar extending through the stack and through the laminate into the conductive wide region; and a memory cell along the conductive first level and including a region of the cell material pillar. Attached Figure Description

[0022] Figure 1 shows a block diagram of a prior art memory device having a memory array with memory cells.

[0023] Figure 2 shows a schematic diagram of the prior art memory device of Figure 1 in the form of a 3D NAND memory device.

[0024] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0025] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0026] Figures 5 to 16 A schematic top view of the instance integration component at the instance sequential processing stage of the instance embodiment method for forming an instance memory device.

[0027] Figures 5A to 16A respectively along Figures 5 to 16 A schematic cross-sectional side view of line AA.

[0028] Figure 5A-1 and 16A-1 They are respectively Figure 5A and 16A A schematic cross-sectional side view of an alternative example embodiment of the example embodiment.

[0029] Figures 5B to 16B respectively along Figures 5 to 16 A schematic cross-sectional side view of line BB.

[0030] Figures 11C to 14C To respectively along Figures 11A to 14A The lines CC and respectively along Figures 11B to 14B A schematic cross-sectional top view of line CC. Detailed Implementation

[0031] Some embodiments include a method of using two different sacrificial materials to support alternating stacks of first and second layers. Channel material pillars are formed to extend through the stack and through the sacrificial materials. Subsequently, the first and second sacrificial materials are sequentially replaced with first and second conductive materials, respectively. The first and second conductive materials may or may not be compositionally identical. The first and second conductive materials are incorporated into the source structure.

[0032] refer to Figures 5 to 16 Describe an example implementation. Figures 5 to 16 The instance sequence steps describe the instance methods, where Figure 16 This shows the instance structure that can be formed by instance methods.

[0033] refer to Figures 5 to 5B The instance integration component 10 includes a layer 12 above a conductive wide area 14, and includes alternating stripes 16 and 18 above the layer 12.

[0034] The conductive wide region 14 may be supported by an underlying semiconductor substrate (not shown). The substrate may include semiconductor material and may include, for example, monocrystalline silicon, be primarily composed of monocrystalline silicon, or be composed of monocrystalline silicon. The substrate may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and semiconductor material layers (alone or in an assembly including other materials). The term "substrate" means any support structure, including but not limited to the semiconductor substrate described above.

[0035] The conductive wide region 14 includes a conductive material 20. The conductive material 20 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 20 may include one or more of metal-containing materials, such as various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.) and / or metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.). In some embodiments, the conductive material 20 may include WSi, be primarily composed of WSi, or be composed of WSi, wherein the chemical formula indicates the basic components rather than a specific stoichiometry. WSi may alternatively be referred to as WSix, where x is a number greater than zero.

[0036] Layer 12 includes material 22. In some embodiments, material 22 may include a conductive doped (e.g., heavily doped) semiconductor material. The semiconductor material may include any suitable composition; and in some embodiments may include one or more of, or consist primarily of, or be composed of: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, material 22 may include doped silicon.

[0037] Layer 12 can be formed to any suitable vertical thickness. For example, in some embodiments, layer 12 can be formed to a thickness in the range of about 10 nanometers (nm) to about 20 nm, or in the range of about 10 nm to about 50 nm, etc. In some embodiments, layer 12 may be omitted.

[0038] Strips 16 and 18 comprise materials 24 and 26, respectively. In some embodiments, strips 16 and 18 may be referred to as first and second strips, respectively, and materials 24 and 26 may be referred to as first and second materials, respectively. Materials 24 and 26 are eventually removed and replaced with other materials, and are therefore referred to as sacrificial materials. In some embodiments, materials 24 and 26 may be referred to as first sacrificial material and second sacrificial material, respectively.

[0039] Materials 24 and 26 may comprise any suitable composition and may be selectively removed relative to each other and relative to the materials of layer 12 and wide area 14. In some embodiments, material 24 may comprise silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide; and material 26 may comprise silicon nitride, be composed primarily of silicon nitride, or be composed of silicon nitride.

[0040] Strips 16 and 18 extend along a first horizontal direction (the illustrated x-axis direction) and alternate with each other along a second horizontal direction (the illustrated y-axis direction). In some embodiments, strips 16 and 18 may be considered to alternate laterally with each other. Although strips 16 and 18 are shown as straight along the x-axis direction, in other embodiments, the strips may be curved, wavy, etc.

[0041] Figure 5A The embodiments shown depict strips 16 and 18 having approximately the same lateral thickness. In other embodiments, strips 16 and 18 may have different lateral thicknesses relative to each other. For example, Figure 5A-1 Showing something similar to Figure 5A This is an example of an example embodiment, but in which strips 16 and 18 have different lateral thicknesses relative to each other.

[0042] The alternating strips 16 and 18 can be formed by any suitable method. For example, in some embodiments, one of the materials 24 and 26 can be formed and patterned as strips spaced apart from each other by gaps (grooves), and then the other of the materials 24 and 26 can be formed within the grooves.

[0043] The planarized surface 25 is formed to extend across materials 24 and 26. The planarized surface can be formed by any suitable treatment including, for example, chemical mechanical polishing (CMP).

[0044] Materials 24 and 26 may have any suitable vertical thickness. In some embodiments, such vertical thickness may be in the range of about 10 nm to about 50 nm, or in the range of about 10 nm to about 100 nm, etc.

[0045] refer to Figures 6 to 6BLayer 28 is formed over alternating strips 16 and 18, and more specifically, on planarized surface 25. Layer 28 includes material 30. Material 30 may be conductive and may include, for example, a conductive doped semiconductor material. In some embodiments, material 30 of layer 28 may be the same as material 22 of layer 12. In other embodiments, material 30 of layer 28 may be compositionally different from material 22 of layer 12. In some embodiments, layer 28 may be insulating (e.g., material 30 may include alumina, hafnium oxide, etc.).

[0046] Layer 28 may be referred to as the second layer to distinguish it from the first layer 12. Layer 28 may be formed to the same vertical thickness as layer 12, or to a different vertical thickness. In some embodiments, layer 28 may be formed to a thickness in the range of about 10 nm to about 20 nm, or in the range of about 10 nm to about 50 nm, etc. In some embodiments, layer 28 may be omitted.

[0047] Alternating stacks 32 of first and second levels (rows) 34 and 36 are formed above layer 28. The stack 32 may include any suitable number of alternating levels 34 and 36. Levels 34 ultimately become conductive levels in the memory arrangement. Any suitable number of levels 34 may exist to form the desired number of conductive levels. In some embodiments, at least 8, 16, 32, 64, etc., levels 34 may exist.

[0048] The first layer 34 includes a first material 38. This first material may include any suitable composition, and in some embodiments may include silicon nitride, consist primarily of silicon nitride, or consist of silicon nitride. Material 38 is subsequently removed and replaced with other materials, and may therefore be referred to as a sacrificial material.

[0049] The second layer 36 includes an insulating second material 40 and may be referred to as the insulating second layer. Material 40 may include any suitable composition. In some embodiments, material 40 may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0050] Layers 34 and 36 may have any suitable thickness; and may have the same thickness as each other, or may have different thicknesses relative to each other. In some embodiments, layers 34 and 36 may have a vertical thickness in the range of about 10 nm to about 400 nm.

[0051] refer to Figures 7 to 7B An opening (first opening, unit material opening) 42 is formed to extend through the stack 32 and through at least some of the strips 16 and 18 to the upper surface of the conductive material 20. The opening 42 may be formed in a hermetically sealed arrangement, such as a hexagonal close-packed (HCP) arrangement. The opening 42 may or may not penetrate into the conductive material 20.

[0052] Opening 42 has sidewall surfaces that extend along materials 38 and 40 of stack 32. In the illustrated embodiment, these sidewall surfaces are substantially vertical, meaning vertical within reasonable tolerances for manufacturing and measurement. In other embodiments, the sidewall surfaces of opening 42 may be tapered.

[0053] refer to Figures 8 to 8B Unit material column 44 is formed in opening 42 ( Figures 7 to 7B Within the column 44, each column contains a semiconductor material (channel material) 46, a dielectric material 48 on one side of the semiconductor material 46, and a region 50 on the opposite side of the semiconductor material 46. The semiconductor material 46 is illustrated with dots to aid the reader in identifying this type of material.

[0054] Semiconductor material 46 may include any suitable composition; and in some embodiments may include one or more of, or consist primarily of, or consist of: silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides (e.g., indium gallium zinc oxide), etc. In some embodiments, semiconductor material 46 may include suitably doped silicon, consist primarily of, or consist of suitably doped silicon. Semiconductor material (channel material) 46 forms channel material pillars 52.

[0055] In the illustrated embodiment, the channel material column 52 is configured as an annular ring (e.g., Figure 8 As shown in the top view, these annular rings surround the insulating material 48. This configuration of the channel material pillars can be considered as corresponding to a "hollow" channel configuration, in which the dielectric material 48 is disposed within the cavities of the channel material pillars. In other embodiments, the channel material may be configured as solid pillars rather than as the hollow pillars illustrated.

[0056] The insulating material 48 may include any suitable composition, and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide.

[0057] Region 50 includes one or more cell materials (memory cell materials), wherein these cell materials are typically formed in the opening 42 before the channel material 46. Figures 7 to 7BWithin region 50, the cell material may include tunneling materials, charge storage materials, and charge blocking materials. The tunneling material (also referred to as the gate dielectric material) may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc. The charge storage material may include any suitable composition; and in some embodiments may include charge trapping materials (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include any suitable composition; and in some embodiments may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc.

[0058] In some embodiments, the channel material 46 may be referred to as the first unit material, and the unit material within the region 50 may be referred to as the additional unit material.

[0059] refer to Figures 9 to 9B The slit (second opening) 54 is formed to pass through the stack 32, through the materials 24 and 26 of strips 16 and 18, and to reach the conductive wide area 14. The slit 54 may or may not penetrate into the material 20 of the conductive wide area 14.

[0060] In some embodiments, the first opening 42 is a cylindrical opening (as shown in the reference). Figure 7 Top view and Figure 9 (As can be understood from the top view) and slit 54 is a groove extending along the illustrated y-axis direction (as shown in the reference). Figure 9 (The top view can be understood).

[0061] In some embodiments, strips 16 and 18 can be considered as being along a first direction (x-axis direction, as referenced). Figure 5 (As can be understood from the top view) extends, and slit 54 can be considered as extending along a second direction (the y-axis direction, as referenced) Figure 9 (As can be understood from the top view). The second direction intersects the first direction and, in the illustrated embodiment, is substantially orthogonal to the first direction (wherein the term "substantially orthogonal" means orthogonal within reasonable tolerances for manufacturing and measurement).

[0062] The slit 54 has a sidewall surface 53 that extends along the materials 38 and 40 of the stack 32. In the illustrated embodiment, the sidewall surface 53 is substantially vertical. In other embodiments, the sidewall surface 53 may be tapered.

[0063] refer to Figures 10 to 10B A protective material 56 is formed along the sidewall surface 53 of the slit 54 to line the upper portion 55 of the slit 54, but exposes the lower portion 57 of the slit. The exposed lower portion 57 extends along the materials 24 and 26 of strips 16 and 18. In the illustrated embodiment, the protective material 56 also extends across the top of the stack 32.

[0064] The protective material 56 may include any suitable composition. In some embodiments, the protective material 56 may include silicon, be primarily composed of silicon, or be composed of silicon; and specifically, may include virtually undoped silicon (e.g., only including intrinsic dopant concentrations, and in some embodiments including less than or equal to about 10). 16 atoms / cm 3 (dopant concentration).

[0065] refer to Figures 11 to 11C selectively removes strip 18 relative to materials 20, 22, 24, 30, and 56. Figure 5 , 5A The sacrificial material 26 of 10A). This forms a first conduit (first void) 58, which is located between the first layer 12 and the second layer 28 and along the strip 16. In the illustrated embodiment, the conduit 58 extends through the cell material along the lower region of the cell material pillar 44 to expose the sidewall surface 59 of the semiconductor material (channel material) 46 of the channel material pillar 52.

[0066] In some embodiments, the sacrificial material 26 may include silicon dioxide and may be removed by wet etching using hydrofluoric acid. In some embodiments, the sacrificial material 26 may include silicon nitride and may be removed by wet etching using phosphoric acid.

[0067] refer to Figures 12 to 12C Replacement material 60 is formed in pipe 58 ( Figures 11 to 11C The replacement material 60 may be a conductive doped semiconductor material, and may include the same semiconductor material as the channel material 46. In some embodiments, the replacement material 60 may include conductive doped silicon, be primarily composed of conductive doped silicon, or be composed of conductive doped silicon. The replacement material 60 may be a conductive material, and in some embodiments may be referred to as a first conductive material formed within the layer 62 of the strip (wherein...). Figure 12A and 12B This level is marked as 62).

[0068] The conductive material 60 can be considered as configured as conductive structures (conductive strips) 64, wherein these conductive structures extend linearly along the x-axis direction. Although the conductive structure 64 is shown as straight along the x-axis direction, in other embodiments, the structure 64 may be curved, wavy, etc.

[0069] In the illustrated embodiment, the replacement material 60 is formed as the sidewall surface 59 of the lower region of the channel material column 52 directly abutting.

[0070] Can Figure 11 and 12 The treatment is considered as replacing sacrificial material 26 with replacement material 60. Figure 10A In some embodiments, it may be possible to Figure 11 and12 The treatment is considered as replacing the first sacrificial material (26) with the first replacement material (60).

[0071] refer to Figures 13 to 13C Strip 16 is selectively removed relative to materials 20, 22, 30, 56, and 60. Figures 5 to 5B The sacrificial material 24 (and 12A to 12C) forms a second conduit (second void) 68, which is located between the first layer 12 and the second layer 28 and along the conductive structure (strip) 64. In the illustrated embodiment, the conduit 68 extends through the unit material along the lower region of the unit material pillar 44 to expose the sidewall surface 59 of the semiconductor material (channel material) 46 of the channel material pillar 52.

[0072] In some embodiments, the sacrificial material 24 may include silicon dioxide and may be removed by wet etching with hydrofluoric acid. In some embodiments, the sacrificial material 24 may include silicon nitride and may be removed by wet etching with phosphoric acid.

[0073] refer to Figures 14 to 14C Replacement material 70 is formed in pipe 68 ( Figures 13 to 13C The replacement material 70 may be a conductive doped semiconductor material, and may include the same semiconductor material as the channel material 46. In some embodiments, the replacement material 70 may include conductive doped silicon, be primarily composed of conductive doped silicon, or be composed of conductive doped silicon. The replacement material 70 may be a conductive material, and in some embodiments may be referred to as a second conductive material formed within layer 62.

[0074] The conductive material 70 can be considered as configured as conductive structures (conductive strips) 74, wherein these conductive structures extend linearly along the x-axis. Although the conductive structure 74 is shown as straight along the x-axis, in other embodiments, the structure 74 may be curved, wavy, etc.

[0075] In the illustrated embodiment, the replacement material 70 is formed to directly abut the sidewall surface 59 of the lower region of the channel material column 52, such as... Figure 14B and 14C As shown in the figure.

[0076] Can Figure 13 and 14 The treatment is considered as replacing sacrificial material 24 with replacement material 70. Figures 12 to 12C In some embodiments, it may be possible to Figure 13 and 14 The treatment is considered as replacing the second sacrificial material (24) with the second replacement material (70).

[0077] Figure 14CConductive structures 64 and 74 are shown extending along the illustrated x-axis direction and alternating with each other along the illustrated y-axis direction. Either the x-axis direction or the y-axis direction may be referred to as the first horizontal direction (or the first lateral direction), and the other may be referred to as the second horizontal direction (or the second lateral direction).

[0078] In some embodiments, slit 54 may be considered to extend along a first horizontal direction, and conductive structures 64 and 74 may be considered to extend along a second horizontal direction that is substantially orthogonal to the first horizontal direction.

[0079] Conductive structures 64 and 74 are along interface 72 (in) Figure 14C (The structures 64 and 74 are joined together.) These interfaces can be detectable boundary regions between structures 64 and 74. In some embodiments, structures 64 and 74 may include compositions that are different from each other (i.e., composition 60 may be different from composition 70). For example, compositions 60 and 70 may include the same semiconductor material but may include different degrees of doping relative to each other. Alternatively, compositions 60 and 70 may include semiconductor materials that are different from each other. In some embodiments, structures 64 and 74 may include the same composition. For example, both compositions 60 and 70 may include heavily doped silicon. Heavily doped silicon may include, for example, one or more n-type dopants (e.g., one or more of phosphorus, arsenic, etc.).

[0080] In embodiments where compositions 60 and 70 are identical, the detectable boundary 72 may correspond to a detectable gap between compositions 60 and 70, which is created by the sequential formation of compositions 60 and 70 relative to each other. The gap may be a region where grain boundaries change in orientation, size, etc.; a region where voids or other minute defects occur, etc. In some embodiments, compositions 60 and 70 may be referred to as first and second conductive materials, respectively, and these first and second conductive materials may have compositions that are substantially identical to each other. The term "substantially identical" means identical within reasonable tolerances of manufacturing and measurement.

[0081] In some embodiments, conductive structures 64 and 74 may be considered as forming a laminate 76 together. Regions 78 of the laminate 76 extend between slits 54.

[0082] In some embodiments, conductive structures 64 and 74 may be incorporated into a conductive electrode structure 80 of the memory device. The conductive electrode structure includes conductive structures 64 and 70, and a conductive wide region 20. Figure 14A and 14BIn the illustrated embodiment, the conductive electrode structure 80 further includes material 22 of layer 12. In other embodiments, layer 12 may be omitted. Additionally, if material 30 of layer 28 is conductive, then the conductive electrode structure 80 may include such material. In other embodiments, layer 28 may be omitted or layer 28 may be insulating.

[0083] In the illustrated embodiment, conductive materials 60 and 70 directly abut the surface 59 of the channel material pillar 52. In some embodiments, conductive materials 60 and 70 may comprise conductive doped semiconductor materials. Dopant may diffuse outward from materials 60 and 70 into the channel material (semiconductor material) 46 to form a heavily doped lower portion of the semiconductor material 46. The upper boundary of the heavily doped lower portion of the semiconductor material 46 may be along one of the layers 38, wherein these upper boundaries are schematically illustrated as... Figure 14A and 14B Position 79 within the cross-sectional view. Outward diffusion from the doped materials 60 and 70 into the semiconductor material 46 can be achieved using any suitable process, including, for example, suitable thermal treatment.

[0084] refer to Figures 15 to 15B Remove protective material 56 ( Figures 14A to 14B Additionally, remove material 38 from the first layer 34. Figure 14A and 14B This preserves the void 82 along the first layer 34. The material 38 can be removed using one or more etchants flowing into the slit 54. For example, in some embodiments, the material 38 may include silicon nitride and can be removed using phosphoric acid flowing into the slit 54.

[0085] refer to Figures 16 to 16B Dielectric insulating material 84 and conductive material 86 are formed in the voids 82 ( Figure 15A and 15B )Inside.

[0086] The dielectric barrier material 84 may include any suitable composition, and in some embodiments may include one or more high-k materials. The term "high-k" means a dielectric constant greater than that of silicon dioxide (i.e., greater than about 3.9). Examples of high-k materials include alumina, hafnium oxide, zirconium oxide, etc.

[0087] The conductive material 86 may include any suitable composition; and in some embodiments may include a tungsten core at least partially surrounded by titanium nitride. The conductive material 86 may be referred to as a third conductive material to be used in conjunction with... Figures 11 to 14 The first conductive material 60 and the second conductive material 70 formed by the process are separated.

[0088] In some embodiments, the conductive material 86 can be considered as at least partially filling the voids 82. Figure 15Aand 15B In some embodiments, the conductive material 86 may be considered as a replacement for the sacrificial material 38. Figure 14A and 14B At least some of them.

[0089] Can Figures 16 to 16B The stack 32 is considered to include a conductive first layer 34, which alternates with an insulating second layer 36 along the vertical direction (the illustrated z-axis direction). In the illustrated embodiment, some regions of the dielectric barrier material 84 can be considered as associated with layer 36, and other regions can be considered as associated with layer 34. Alternatively, although the material 84 itself is not conductive, the entire dielectric barrier material 84 can be considered as associated with the conductive layer 34.

[0090] After materials 84 and 86 are formed within void 82, slit 54 may be filled with one or more materials to form slat 88 within the slit. In the illustrated embodiment, slat 88 includes an insulating material 90. The insulating material 90 may include any suitable composition and in some embodiments may include silicon dioxide, be composed primarily of silicon dioxide, or be composed of silicon dioxide. Although slat 88 is shown as comprising a single homogeneous material, in other embodiments, the slat may comprise a laminate of two or more different materials. For example, slat 88 may include a conductive material (e.g., conductive doped silicon) laterally sandwiched between a pair of insulating materials (e.g., materials comprising silicon dioxide).

[0091] Can Figures 16 to 16B Component 10 is considered as a memory device configured to include memory cell 92 and selection device (e.g., source-side selection device, SGS device) 94. The lowest part of conductive layer 34 is designated 34a, and it diffuses outward through the lower portion of the channel material pillar (see above). Figures 14 to 14B The top 79 of the doped region (described) extends to the conductive layer 34a. The conductive layer 34a includes the SGS device 94. In the illustrated embodiment, the dopant within the channel material 46 extends partially across layer 34a to achieve the desired balance between the non-drain "off" characteristics of the SGS device and the drain GIDL characteristics of the SGS device. Although only one of the conductive layers 34 is shown incorporated into the source-side selection device, in other embodiments, multiple conductive layers may be incorporated into the source-side selection device. The conductive layers may be electrically coupled (joined together) to be incorporated together into a long-channel source-side selection device. If multiple conductive layers are incorporated into the source-side selection device, then outwardly diffused dopant may extend upward across two or more of the conductive layers 34 incorporated into the source-side selection device.

[0092] Memory cells 92 (e.g., NAND memory cells) are stacked vertically together. Memory cells 92 are arranged along a first level (conductive level) 34. Each memory cell includes a region of semiconductor material (channel material) 46 and a region of conductive level 34 (control gate region). Regions of conductive levels not included by memory cells 92 can be considered word line regions (or wiring regions) that couple the control gate region to drive circuitry and / or other suitable circuitry. Memory cells 92 also include cell material (e.g., tunneling material, charge storage material, and charge blocking material) within regions 50.

[0093] In some embodiments, the conductive level 34 associated with memory cell 92 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0094] Conductive materials 20, 60, and 70 together form the source structure 80 of the memory device. These source structures may further include one or both of layers 12 and 28. The source structure may be similar to the source structure 216 described in the "Background Art" section. The source structure is shown as being coupled to control circuitry (e.g., CMOS). The control circuitry may be located in the source structure 80 (e.g., as described above). Figure 5 The described base (associated with) may be below or in any other suitable location.

[0095] In some embodiments, the channel material pillar 52 may be considered as representing a large number of substantially uniform channel material pillars extending across the memory device 10; wherein the term “substantially uniform” means uniform within reasonable tolerances in manufacturing and measurement. Figure 16 The top view shows pillars 56 arranged within a matrix (wherein pillars 56 are hexagonally encapsulated in the illustrated embodiment), and shows slits 54 extending along the outer edge of the matrix of channel material pillars. In some embodiments, slits 54 may define block regions (memory block regions) 96, wherein such block regions are located between slats 88. Thus, memory cells 92 can be considered as being located within block regions 96 defined by slits 54. Block regions 96 may be similar to the blocks (or sub-blocks) described above in the "Background Art" section of this disclosure.

[0096] Figure 16A An embodiment is shown in which conductive structures 64 and 74 have approximately the same lateral width. In other embodiments, structures 64 and 74 may have different lateral widths relative to each other. For example, the references above may be used... Figure 5A-1 The components described are not Figure 5A The components are used to generate structures 64 and 74. Figure 16A-1 Showing something similar to Figure 16A Component 10 of the components, but wherein structures 64 and 74 have different lateral widths relative to each other. This can be utilized through the processing described herein. Figure 5A-1 Component replacement Figure 5A Components to form Figure 16A-1 Components.

[0097] The advantage of the process described herein lies in its ability to effectively support the weight of the stack 32 during the fabrication of the laminate 76 (i.e., the laminate of conductive structures 64 and 74). Specifically, this is achieved by replacing the sacrificial structures 16 and 18 one at a time. Figure 5A To form a laminated structure 76, the stack 32 provides significant support throughout the formation of the laminated structure 76. Conventional processes can form homogeneous materials similar to laminated structures, where such homogeneous materials are formed in a single manufacturing step. A challenge encountered in these conventional processes is that the stack 32 may be supported only by unit material pillars 44 at one or more stages of the process, and this may not be sufficient to prevent buckling, bending, and / or even shrinkage of regions of the stack 32.

[0098] While the embodiments described herein utilize the sequential replacement of two different sacrificial materials (24 and 26) to form a laminated structure 76 having two different conductive structures (64 and 74) arranged in an alternating (repeated) manner, it should be understood that in other embodiments, more than two different sacrificial materials may be sequentially replaced. Laminated structures formed using such other embodiments (similar to structure 76) may include two different conductive structures arranged in an alternating (repeated) manner, or may include more than two different conductive structures arranged (e.g., repeated).

[0099] The components and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0100] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0101] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises in the appended claims, rather than to indicate any significant chemical or electrical differences.

[0102] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some cases and another in others may be to provide linguistic variation within this disclosure to simplify the premises of the appended claims.

[0103] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in the specific orientation of the figures or rotated relative to such orientations.

[0104] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0105] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intermediate structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intermediate structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but instead indicate upright alignment.

[0106] A structure (such as a layer, material, etc.) may be described as “vertically extending” to indicate that the structure typically extends upward from the underlying substrate (such as a base). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0107] Some embodiments include a method of forming an integrated component. Alternating strips of first and second sacrificial materials are formed over a conductive structure. An alternating stack of first and insulating second layers is formed over the alternating strips. The first layer comprises a first material and the second layer comprises an insulating second material. Unit material openings are formed to extend through the stack and through at least some of the strips. Unit material pillars are formed within the unit material openings. Slits are formed to extend through the stack and through the strips. The strips extend along a first direction, and the slits extend along a second direction intersecting the first direction. The first sacrificial material is replaced with a first conductive material, and then the second sacrificial material is replaced with a second conductive material. At least some of the first materials in the stack are replaced with a third conductive material, thereby forming the stack having conductive first layers alternating with the insulating second layer.

[0108] Some embodiments include an integrated component having a conductive wide area and alternating first and second stripes above the conductive wide area. The first and second stripes extend along a first direction. The interface between the first and second stripes is a detectable boundary region. A stack having a conductive first level alternating with an insulating second level is located above the stripes. Cell material pillars extend through the stack and through the strips into the conductive wide area. Memory cells are located along the conductive first level and include the area containing the cell material pillars.

[0109] Some embodiments include an integrated component having a memory block region situated between a pair of slats. The slats extend along a first direction. A conductive wide region is located below the slats and directly abuts the lower region of the slats. A laminate is situated above the conductive wide region and between the slats. The laminate includes alternating first and second structures. The first and second structures extend along a second direction substantially orthogonal to the first direction. The interface between the first and second structures is a detectable boundary region. A stack is situated above the laminate and includes a conductive first layer alternating with an insulating second layer. Cell material pillars extend through the stack and through the laminate into the conductive wide region. Memory cells are situated along the conductive first layer and include regions containing cell material pillars.

[0110] As per the description, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming an integrated component, comprising: A first strip and a second strip are formed transversely alternating above a conductive structure, the first strip comprising a first sacrificial material and the second strip comprising a second sacrificial material; A vertically alternating stack of a first layer and an insulating second layer is formed above the strip, wherein the first layer comprises a first material and the insulating second layer comprises an insulating second material; The opening is formed to extend through the stack and through at least some of the strips; A unit material column is formed within the opening; The slit is formed to extend through the stack and through the strip, the strip extending along a first direction, and the slit extending along a second direction intersecting the first direction; The first sacrificial material is replaced with a first conductive material, and then the second sacrificial material is replaced with a second conductive material; as well as At least some of the first materials in the stack are replaced with a third conductive material, thereby forming the stack to include a conductive first layer that alternates vertically with the insulating second layer.

2. The method of claim 1, wherein one of the first sacrificial material and the second sacrificial material comprises silicon nitride, and the other comprises silicon dioxide.

3. The method of claim 1, wherein the first strip and the second strip have the same lateral thickness.

4. The method of claim 1, wherein the first strip and the second strip have different lateral thicknesses relative to each other.

5. The method of claim 1, further comprising forming an insulating strip within the slit.

6. The method according to claim 1, wherein the first conductive material and the second conductive material comprise conductive doped semiconductor materials.

7. The method according to claim 1, wherein the first conductive material and the second conductive material comprise conductive doped silicon.

8. The method of claim 1, wherein the first conductive material and the second conductive material comprise silicon doped with one or more n-type dopants.

9. The method of claim 1, wherein the first conductive material and the second conductive material have compositions that are different from each other.

10. The method of claim 1, wherein the first conductive material and the second conductive material have substantially the same composition and are joined to each other along the gap.

11. The method of claim 1, further comprising forming a first layer over the conductive structure prior to forming the alternating strips, and forming a second layer over the alternating strips prior to forming the stack.

12. The method of claim 11, wherein at least one of the first layer and the second layer comprises a heavily doped semiconductor material.

13. The method of claim 11, wherein the first layer is conductive and wherein the second layer is electrically insulating.

14. The method of claim 1, wherein the unit material pillar comprises a channel material pillar; wherein the first conductive material and the second conductive material comprise heavily doped semiconductor materials and are formed directly against the channel material pillar; and the method further comprises an outwardly diffused dopant from the heavily doped semiconductor material to the channel material pillar, the outwardly diffused dopant extending upward to at least one of the first layers of the stack.

15. The method of claim 14, further comprising configuring the source selection device to include at least one of the first layers.

16. The method of claim 1, further comprising forming a memory cell along the first conductive layer, wherein the memory cell includes a region of the cell material pillar; wherein the integrated assembly includes a memory device including the memory cell; and wherein the first conductive material and the second conductive material, together with the conductive structure, form at least a portion of the source structure of the memory device.

17. An integrated component comprising: Conductive wide area; Alternating first and second structures are located above the conductive wide area, the first and second structures extend along a first horizontal direction and alternate with each other along a second horizontal direction, and the interface between the first and second structures is a detectable boundary region. A stack, which is above an alternating structure and includes a conductive first layer that alternates with an insulating second layer along the vertical direction; A unit material column extends through the stack and through the structure into the conductive wide region; as well as A memory cell that extends along the first conductive layer and includes a region comprising pillars of the cell material.

18. The integrated component of claim 17, wherein the first structure and the second structure have the same lateral thickness.

19. The integrated component of claim 17, wherein the first structure and the second structure have different lateral thicknesses relative to each other.

20. The integrated component of claim 17, wherein the first structure and the second structure each comprise a first conductive material and a second conductive material; and wherein the first conductive material and the second conductive material have substantially the same composition as each other.

21. The integrated component of claim 20, wherein the detectable boundary region is a gap along the interface between the first conductive material and the second conductive material.

22. The integrated component of claim 17, wherein the first structure and the second structure each comprise a first conductive material and a second conductive material; and wherein the first conductive material and the second conductive material have compositions that are different from each other.

23. The integrated component of claim 17, wherein the first structure and the second structure respectively comprise a first doped semiconductor material and a second doped semiconductor material.

24. The integrated component of claim 23, wherein the first doped semiconductor material and the second doped semiconductor material comprise doped silicon.

25. The integrated component of claim 23, wherein the unit material pillar comprises a channel material pillar and includes a tunneling material, a charge trapping material, and a charge blocking material extending laterally outward from the channel material pillar; and wherein the first doped semiconductor material and the second doped semiconductor material are in direct contact with the channel material pillar.

26. The integrated component of claim 17, comprising: The first layer is located above the conductive wide area and below the structure; as well as The second layer is located above the structure and below the stack.

27. The integrated component of claim 26, wherein the first layer and the second layer have the same composition as each other.

28. The integrated component of claim 26, wherein the first layer and the second layer have compositions that are different from each other.

29. The integrated component of claim 26, wherein both the first layer and the second layer are conductive.

30. The integrated component of claim 26, wherein the first layer is conductive and wherein the second layer is electrically insulating.

31. An integrated component comprising: A memory block region situated between a pair of slats extending along a first horizontal direction; A conductive wide region, which is located below the slat and directly abuts the lower region of the slat; A laminate located above the conductive wide area and between the strips, the laminate comprising a first structure alternating with a second structure along a transverse direction, the first structure and the second structure extending along a second horizontal direction substantially orthogonal to the first horizontal direction, the interface between the first structure and the second structure being a detectable boundary region; A stack, which is located above the laminate and includes a conductive first layer that alternates with an insulating second layer along the vertical direction; A unit material column extends through the stack and through the laminate into the conductive wide region; as well as A memory cell that extends along the first conductive layer and includes a region comprising pillars of the cell material.

32. The integrated assembly of claim 31, wherein the slats comprise an insulating material.

33. The integrated assembly of claim 32, wherein the slats and the second insulating layer comprise the same composition as each other.

34. The integrated component of claim 33, wherein the same composition comprises silicon dioxide.

35. The integrated component of claim 31, wherein the first structure and the second structure each comprise a first conductive material and a second conductive material; and wherein the first conductive material and the second conductive material have substantially the same composition.

36. The integrated component of claim 35, wherein the detectable boundary region is a gap along the interface between the first conductive material and the second conductive material.

37. The integrated component of claim 31, wherein the first structure and the second structure respectively comprise a first conductive material and a second conductive material; and wherein the first conductive material and the second conductive material have compositions that are different from each other.

38. The integrated component of claim 31, wherein the first structure and the second structure respectively comprise a first doped semiconductor material and a second doped semiconductor material.

39. The integrated component of claim 31, comprising a layer between the conductive wide region and the laminate.

40. The integrated component of claim 39, wherein the layer is conductive.

41. The integrated component of claim 31, comprising a layer between the laminate and the stack.

42. The integrated component of claim 41, wherein the layer is conductive.

43. The integrated component of claim 41, wherein the layer is electrically insulating.

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