Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. A semiconductor device includes: a substrate having a cell region and a chip protection region, the chip protection region surrounding the cell region; a first chip protection member extending over the chip protection region in a first direction; a second chip protection member extending over the chip protection region in the first direction, the second chip protection member being spaced apart from the first chip protection member; and a third chip protection member extending over the chip protection region in a second direction intersecting the first direction. The first chip protection member includes a first end portion, the second chip protection member includes a second end portion, and the third chip protection member includes a third end portion disposed between the first end portion and the second end portion.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor device. Background Art

[0002] Semiconductor devices include memory cells capable of storing data. Three-dimensional semiconductor devices include memory cells arranged three-dimensionally, thereby enabling reduction of the area of the substrate occupied by the memory cells.

[0003] To increase the integration degree of three-dimensional semiconductor devices, the number of stacked memory cells can be increased. As the number of stacked memory cells increases, the operational reliability of three-dimensional semiconductor devices may deteriorate. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a semiconductor device including: a substrate having a cell region and a chip protection region, the chip protection region surrounding the cell region; a first chip protection member extending over the chip protection region in a first direction; a second chip protection member extending over the chip protection region in the first direction, the second chip protection member being spaced apart from the first chip protection member; and a third chip protection member extending over the chip protection region in a second direction, the second direction intersecting the first direction, wherein the first chip protection member includes a first end portion, the second chip protection member includes a second end portion, and the third chip protection member includes a third end portion disposed between the first end portion and the second end portion.

[0005] According to another aspect of the present disclosure, there is provided a semiconductor device including: a substrate having a cell region and a chip protection region, the chip protection region surrounding the cell region; a first chip protection member extending over the chip protection region in a first direction; a second chip protection member extending over the chip protection region in the first direction, the second chip protection member being spaced apart from the first chip protection member; and a third chip protection member extending over the chip protection region in a second direction, the second direction intersecting the first direction, wherein the first chip protection member includes a first long sidewall extending in the first direction and a first short sidewall extending in the second direction, the second chip protection member includes a second long sidewall extending in the first direction and a second short sidewall extending in the second direction, and the third chip protection member includes a third long sidewall extending in the second direction and a third short sidewall extending in the first direction, and wherein the first short sidewall faces the third long sidewall, and the third short sidewall faces the second long sidewall.

[0006] According to yet another aspect of the present disclosure, a semiconductor device is provided, the semiconductor device including: a connection structure having a connection conductor and a first protection pattern; a semiconductor structure having a stacked structure, a unit plug penetrating the stacked structure, and a second protection pattern; and a protection pad connecting the first protection pattern and the second protection pattern by being disposed between the first protection pattern and the second protection pattern, wherein the first protection pattern and the second protection pattern extend in a first direction, wherein the respective protection pads are spaced apart from each other in the first direction, and wherein the distance by which the respective protection pads are spaced apart from each other in the first direction is shorter than the length of the first protection pattern in the first direction and the length of the second protection pattern in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0008] In the drawings, the dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always denote the same elements.

[0009] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1B is along Figure 1A a cross-sectional view taken along line A1 - A1' shown.

[0011] Figure 1C is along Figure 1A a cross-sectional view taken along line B - B' shown.

[0012] Figure 1D is Figure 1A an enlarged view of region C shown.

[0013] Figure 2A and Figure 3A are plan views showing Figures 1A to 1D a manufacturing method of the semiconductor device shown.

[0014] Figure 2B is along Figure 2A a cross-sectional view taken along line A2 - A2' shown.

[0015] Figure 3B is alongFigure 3A A cross-sectional view taken along the line A3 - A3' shown.

[0016] Figure 4 It shows Figures 1A to 1D A cross-sectional view of a method for manufacturing a semiconductor device shown.

[0017] Figure 5 It shows Figures 1A to 1D A view of the effects of the semiconductor device shown.

[0018] Figure 6 A block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0019] Figure 7 A block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Detailed implementation

[0020] The specific structural descriptions or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0021] An embodiment provides a semiconductor device including a chip guard region structure having improved environmental reliability.

[0022] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0023] Furthermore, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0024] Figure 1A A plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A A cross-sectional view taken along the line A1 - A1' shown. Figure 1C It is along Figure 1A A cross-sectional view taken along the line B - B' shown. Figure 1D It isFigure 1A An enlarged view of the area C shown.

[0025] Referring Figures 1A to 1C , the semiconductor device may include a first substrate 100. The first substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. In one example, the first direction D1 and the second direction D2 may be orthogonal to each other. The first substrate 100 may be a semiconductor substrate. In one example, the first substrate 100 may be a silicon substrate.

[0026] The first substrate 100 may include a cell region CER and a chip protection region CGR. The cell region CER and the chip protection region CGR may be regions separated from each other in a two-dimensional view. The chip protection region CGR may surround the cell region CER.

[0027] A connection structure CNS may be provided on the first substrate 100. The connection structure CNS may include a first insulating layer 110 and a connection conductor CB. The first insulating layer 110 may cover the first substrate 100. The first insulating layer 110 may include an insulating material. In one example, the first insulating layer 110 may include an oxide or a nitride. The first insulating layer 110 may be a multi-layer having a plurality of insulating layers.

[0028] The connection conductor CB may be provided in the first insulating layer 110. The connection conductor CB may be provided on the cell region CER. The connection conductor CB may include a first contact portion CT1 and a first line ML1. The first contact portion CT1 and the first line ML1 may be connected to each other. The first contact portion CT1 and the first line ML1 may include a conductive material.

[0029] A transistor TR may be provided between the connection structure CNS and the first substrate 100. The transistor TR may be provided on the cell region CER. The transistor TR may be a transistor within the peripheral circuit of the semiconductor device or may be connected to the peripheral circuit of the semiconductor device.

[0030] Each transistor TR may include an impurity region IR, a gate insulating layer GI, and a gate electrode GE. The impurity region IR may be formed by doping impurities into the first substrate 100. The impurity region IR may be connected to the connection conductor CB. The impurity region IR may be connected to the first contact portion CT1. The gate insulating layer GI may include an insulating material. In one example, the gate insulating layer GI may include an oxide. The gate electrode GE may include a conductive material. The gate electrode GE may be connected to the connection conductor CB. The gate electrode GE may be connected to the first contact portion CT1.

[0031] The isolation layer can be disposed in the cell region CER of the first substrate 100. The isolation layer IS can electrically isolate the transistors TR from each other. The isolation layer can include an insulating material. In one example, the isolation layer can include an oxide.

[0032] The first bonding structure BDS1 can be disposed on the connection structure CNS. The first bonding structure BDS1 can include a second insulating layer 120 and a first bonding pad BP1. The second insulating layer 120 can cover the first insulating layer 110. The second insulating layer 120 can include an insulating material. In one example, the second insulating layer 120 can include a nitride or an oxide.

[0033] The first bonding pad BP1 can be connected to the connection conductor CB in the connection structure CNS. The first bonding pad BP1 can be connected to the first contact CT1 in the connection structure CNS. The first bonding pad BP1 can be disposed on the cell region CER. The first bonding pad BP1 can be disposed in the second insulating layer 120. The first bonding pad BP1 can include a conductive material. In one example, the first bonding pad BP1 can include copper.

[0034] The second bonding structure BDS2 can be disposed on the first bonding structure BDS1. The second bonding structure BDS2 can include a third insulating layer 130 and a second bonding pad BP2. The third insulating layer 130 can cover the second insulating layer 120. The third insulating layer 130 can include an insulating material. In one example, the third insulating layer 130 can include a nitride or an oxide.

[0035] The second bonding pad BP2 can be connected to the first bonding pad BP1 in the first bonding structure BDS1. The second bonding pad BP2 can be disposed on the cell region CER. The second bonding pad BP2 can be disposed in the third insulating layer 130. The second bonding pad BP2 can include a conductive material. In one example, the second bonding pad BP2 can include copper.

[0036] The width of the first bonding pad BP1 can become wider as it approaches the second bonding pad BP2. In one example, the width of the first bonding pad BP1 in the first direction D1 can become wider as it approaches the second bonding pad BP2. The width of the second bonding pad BP2 can become wider as it approaches the first bonding pad BP1. In one example, the width of the second bonding pad BP2 in the first direction D1 can become wider as it approaches the first bonding pad BP1.

[0037] The semiconductor structure SEM can be disposed on the second bonding structure BDS2. The semiconductor structure SEM can include a fourth insulating layer 140, a second contact portion CT2, a bit line BL, a bit line contact portion BCT, a cell plug PL, a stacked structure STA, a slit structure SLS, and a source structure SOS. The second contact portion CT2, the bit line BL, the bit line contact portion BCT, the cell plug PL, the stacked structure STA, the slit structure SLS, and the source structure SOS can be disposed in the cell region CER. The second contact portion CT2, the bit line BL, the bit line contact portion BCT, the cell plug PL, the stacked structure STA, the slit structure SLS, and the source structure SOS can be disposed in the fourth insulating layer 140.

[0038] The fourth insulating layer 140 can cover the third insulating layer 130. The fourth insulating layer 140 can include an insulating material. In one example, the fourth insulating layer 140 can include an oxide or a nitride. The fourth insulating layer 140 can be a multi-layer having a plurality of insulating layers.

[0039] The second contact portion CT2 can be connected to the second bonding pad BP2 in the second bonding structure BDS2. The second contact portion CT2 can include a conductive material.

[0040] The bit line BL can be connected to the second contact portion CT2. The bit line BL can extend in the first direction D1. The bit line BL can include a conductive material.

[0041] The bit line contact portion BCT can be connected to the bit line BL. The bit line contact portion BCT can include a conductive material.

[0042] The stacked structure STA can include stacked insulating layers IL and conductive patterns CP alternately stacked in the third direction D3. The conductive pattern CP can be used as a word line or a selection line of the semiconductor device. The conductive pattern CP can include a conductive material. The stacked insulating layer IL can include an insulating material. In one example, the stacked insulating layer IL can include an oxide.

[0043] Each cell plug PL can be respectively connected to each bit line contact portion BCT. The cell plug PL can be electrically connected to the transistor TR through the bit line contact portion BCT, the bit line BL, the second contact portion CT2, the second bonding pad BP2, the first bonding pad BP1, the first contact portion CT1, and the first line ML1.

[0044] The cell plug PL can extend in the third direction D3. The cell plug PL can penetrate the stacked insulating layer IL and the conductive pattern CP of the stacked structure STA in the third direction D3.

[0045] Each unit plug PL may include a channel layer CL, a filling layer FI, a memory layer ML, and a capping pattern CA. The channel layer CL, the filling layer FI, and the memory layer ML may extend in a third direction D3 and may penetrate the stacked insulating layer IL and the conductive pattern CP of the stacked structure STA. The channel layer CL may surround the filling layer FI, and the memory layer ML may surround the channel layer CL.

[0046] The filling layer FI may include an insulating material. In one example, the filling layer FI may include an oxide. The channel layer CL may include a conductive material. In one example, the channel layer CL may include polysilicon.

[0047] The memory layer ML may include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a blocking layer surrounding the data storage layer. The tunnel insulating layer may include a material through which charges can tunnel. In one example, the tunnel insulating layer may include an oxide. In one embodiment, the data storage layer may include a material capable of capturing charges. In one example, the data storage layer may include a nitride. In another embodiment, the data storage layer may include various materials according to the data storage method. In one example, the data storage layer may include silicon, a phase change material, or nanodots. The blocking layer may include a material capable of blocking the movement of charges. In one example, the blocking layer may include an oxide.

[0048] The capping pattern CA may be connected to the bit line contact BCT. The capping pattern CA may be connected to the channel layer CL. The capping pattern CA may be disposed between the filling layer FI and the bit line contact BCT. The capping pattern CA may include a conductive material. The capping pattern CA may include the same material as the channel layer CL. In one example, the capping pattern CA may include polysilicon.

[0049] The slit structure SLS may extend in a second direction D2 and a third direction D3. The slit structure SLS may extend in the third direction D3 and may penetrate the stacked structure STA. The stacked insulating layers IL disposed at the same level may be isolated from each other in a first direction D1 through the slit structure SLS. The conductive patterns CP disposed at the same level may be isolated from each other in the first direction D1 through the slit structure SLS. The slit structure SLS may include an insulating material. In one example, the slit structure SLS may include an oxide.

[0050] The source structure SOS can be disposed on the stacked structure STA. The source structure SOS can have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The source structure SOS can be disposed on the cell region CER. The source structure SOS can be connected to the channel layer CL. The source structure SOS can include a conductive material. In one example, the source structure SOS can include polysilicon.

[0051] The fifth insulating layer 150 can be disposed on the semiconductor structure SEM. The fifth insulating layer 150 can cover the semiconductor structure SEM. The fifth insulating layer 150 can include an insulating material. In one example, the fifth insulating layer 150 can include an oxide or a nitride.

[0052] The source contact SC can be disposed in the fifth insulating layer 150. The source contact SC can be connected to the source structure SOS. The source contact SC can be disposed on the cell region CER. The source contact SC can include a conductive material.

[0053] The second line ML2 can be disposed in the fifth insulating layer 150. The second line ML2 can be connected to the source contact SC. The second line ML2 can be disposed on the cell region CER. The second line ML2 can include a conductive material.

[0054] The first chip guard CG1, the second chip guard CG2, the third chip guard CG3, the fourth chip guard CG4, the fifth chip guard CG5, and the sixth chip guard CG6 can be disposed in the first insulating layer to the fifth insulating layer 110, 120, 130, 140, and 150. The first chip guard to the sixth chip guard CG1, CG2, CG3, CG4, CG5, and CG6 can penetrate the fifth insulating layer 150, the first insulating layer to the fourth insulating layer 110, 120, 130, and 140, and extend downward to the first substrate 100. The first chip guard to the sixth chip guard CG1, CG2, CG3, CG4, CG5, and CG6 can extend in a third direction D3. The first chip guard to the sixth chip guard CG1, CG2, CG3, CG4, CG5, and CG6 can penetrate the fourth insulating layer 140 of the semiconductor structure SEM, the third insulating layer 130 of the second bonding structure BDS2, the second insulating layer 120 of the first bonding structure BDS1, and the first insulating layer 110 of the connection structure CNS. The first chip guard to the sixth chip guard CG1, CG2, CG3, CG4, CG5, and CG6 can be disposed on the chip guard region CGR. The number of chip guards CG1, CG2, CG3, CG4, CG5, and CG6 is not limited to the chip guards shown in the drawings.

[0055] The first to third chip protectors CG1, CG2, and CG3 can extend in the second direction D2. The first to third chip protectors CG1, CG2, and CG3 can be spaced apart from each other in the first direction D1. Two first chip protectors CG1 can be spaced apart from each other in the first direction D1. A cell region CER can be provided between the two first chip protectors CG1. A stacked structure STA and a cell plug PL can be provided between the two first chip protectors CG1. Two second chip protectors CG2 can be spaced apart from each other in the first direction D1. The two first chip protectors CG1 and the cell region CER can be provided between the two second chip protectors CG2. Two third chip protectors CG3 can be spaced apart from each other in the first direction D1. The two first chip protectors CG1, the two second chip protectors CG2, and the cell region CER can be provided between the two third chip protectors CG3. The first to third chip protectors CG1, CG2, and CG3 can be parallel to each other.

[0056] The second chip protector CG2 can be provided to be farther from the cell region CER than the first chip protector CG1. The third chip protector CG3 can be provided to be farther from the cell region CER than the second chip protector CG2. The length of the second chip protector CG2 in the second direction D2 can be longer than the length of the first chip protector CG1 in the second direction D2. The length of the third chip protector CG3 in the second direction D2 can be longer than the length of the second chip protector CG2 in the second direction D2.

[0057] The fourth to sixth chip protectors CG4, CG5, and CG6 can extend in the first direction D1. The fourth to sixth chip protectors CG4, CG5, and CG6 can be spaced apart from each other in the second direction D2. The two first chip protectors CG1 and the cell region CER can be provided between the two fourth chip protectors CG4. The stacked structure STA and the cell plug PL can be provided between the two fourth chip protectors CG4. Two fifth chip protectors CG5 can be spaced apart from each other in the second direction D2. The two fourth chip protectors CG4, the two second chip protectors CG2, the two first chip protectors CG1, and the cell region CER can be provided between the two fifth chip protectors CG5. Two sixth chip protectors CG6 can be spaced apart from each other in the second direction D2. The two fifth chip protectors CG5, the two fourth chip protectors CG4, the two third chip protectors CG3, the two second chip protectors CG2, the two first chip protectors CG1, and the cell region CER can be provided between the two sixth chip protectors CG6. The fourth to sixth chip protectors CG4, CG5, and CG6 can be parallel to each other.

[0058] The fifth chip protection member CG5 can be set to be farther from the unit area CER than the fourth chip protection member CG4. The sixth chip protection member CG6 can be set to be farther from the unit area CER than the fifth chip protection member CG5. The length of the fifth chip protection member CG5 in the first direction D1 can be longer than the length of the fourth chip protection member CG4 in the first direction D1. The length of the sixth chip protection member CG6 in the first direction D1 can be longer than the length of the fifth chip protection member CG5 in the first direction D1.

[0059] The unit area CER can be surrounded by the first chip protection member CG1 and the fourth chip protection member CG4. The unit area CER, the first chip protection member CG1, and the fourth chip protection member CG4 can be surrounded by the second chip protection member CG2 and the fifth chip protection member CG5. The unit area CER, the first chip protection member CG1, the fourth chip protection member CG4, the second chip protection member CG2, and the fifth chip protection member CG5 can be surrounded by the third chip protection member CG3 and the sixth chip protection member CG6.

[0060] Referring to Figure 1D , the first chip protection member CG1 can include a first long side wall LS1 and a first short side wall SS1. The first long side wall LS1 can be a side wall extending in the second direction D2. The first short side wall SS1 can be a side wall connecting the respective first long side walls LS1. The length of the first long side wall LS1 can be longer than the length of the first short side wall SS1. The first chip protection member CG1 can include a first end portion EP1. A portion adjacent to each first short side wall SS1 of the first chip protection member CG1 can be defined as the first end portion EP1. One of the side walls of the first end portion EP1 can be the first short side wall SS1. In one embodiment, the first short side wall SS1 can extend in the first direction D1.

[0061] The second chip protection member CG2 can include a second long side wall LS2 and a second short side wall SS2. The second long side wall LS2 can be a side wall extending in the second direction D2. The second short side wall SS2 can be a side wall connecting the respective second long side walls LS2. The length of the second long side wall LS2 can be longer than the length of the second short side wall SS2. The second chip protection member CG2 can include a second end portion EP2. A portion adjacent to each second short side wall SS2 of the second chip protection member CG2 can be defined as the second end portion EP2. One of the side walls of the second end portion EP2 can be the second short side wall SS2. In one embodiment, the second short side wall SS2 can extend in the first direction D1.

[0062] The third chip protection member CG3 may include a third long side wall LS3 and a third short side wall SS3. The third long side wall LS3 may be a side wall extending in the second direction D2. The third short side wall SS3 may be a side wall connecting the respective third long side walls LS3. The length of the third long side wall LS3 may be longer than the length of the third short side wall SS3. The third chip protection member CG3 may include a third end portion EP3. A portion adjacent to each of the third short side walls SS3 of the third chip protection member CG3 may be defined as the third end portion EP3. One of the side walls of the third end portion EP3 may be the third short side wall SS3. In one embodiment, the third short side wall SS3 may extend in the first direction D1.

[0063] The fourth chip protection member CG4 may include a fourth long side wall LS4 and a fourth short side wall SS4. The fourth long side wall Ls4 may be a side wall extending in the first direction D1. The fourth short side wall SS4 may be a side wall connecting the respective fourth long side walls LS4. The length of the fourth long side wall LS4 may be longer than the length of the fourth short side wall SS4. The fourth chip protection member CG4 may include a fourth end portion EP4. A portion adjacent to each of the fourth short side walls SS4 of the fourth chip protection member CG4 may be defined as the fourth end portion EP4. One of the side walls of the fourth end portion EP4 may be the fourth short side wall SS4. In one embodiment, the fourth short side wall SS4 may extend in the second direction D2.

[0064] The fifth chip protection member CG5 may include a fifth long side wall LS5 and a fifth short side wall SS5. The fifth long side wall LS5 may be a side wall extending in the first direction D1. The fifth short side wall SS5 may be a side wall connecting the respective fifth long side walls LS5. The length of the fifth long side wall LS5 may be longer than the length of the fifth short side wall SS5. The fifth chip protection member CG5 may include a fifth end portion EP5. A portion adjacent to each of the fifth short side walls SS5 of the fifth chip protection member CG5 may be defined as the fifth end portion EP5. One of the side walls of the fifth end portion EP5 may be the fifth short side wall SS5. In one embodiment, the fifth short side wall SS5 may extend in the second direction D2.

[0065] The sixth chip protection member CG6 may include a sixth long side wall LS6 and a sixth short side wall SS6. The sixth long side wall LS6 may be a side wall extending in the first direction D1. The sixth short side wall SS6 may be a side wall connecting the respective sixth long side walls LS6. The length of the sixth long side wall LS6 may be longer than the length of the sixth short side wall SS6. The sixth chip protection member CG6 may include a sixth end portion EP6. A portion adjacent to each of the sixth short side walls SS6 of the sixth chip protection member CG6 may be defined as the sixth end portion EP6. One of the side walls of the sixth end portion EP6 may be the sixth short side wall SS6. In one embodiment, the sixth short side wall SS6 may extend in the second direction D2.

[0066] The fourth short side wall SS4 can be disposed between the first long side wall LS1 and the second long side wall LS2 facing each other. The fourth short side wall SS4 can be disposed to be closer to the second long side wall LS2 than to the first long side wall LS1. The second short side wall SS2 can be disposed between the fourth long side wall LS4 and the fifth long side wall LS5 facing each other. The second short side wall SS2 can be disposed to be closer to the fifth long side wall LS5 than to the fourth long side wall LS4. The fifth short side wall SS5 can be disposed between the second long side wall LS2 and the third long side wall LS3 facing each other. The fifth short side wall SS5 can be disposed to be closer to the third long side wall LS3 than to the second long side wall LS2. The third short side wall SS3 can be disposed between the fifth long side wall LS5 and the sixth long side wall LS6 facing each other. The third short side wall SS3 can be disposed to be closer to the sixth long side wall LS6 than to the fifth long side wall LS5.

[0067] The fourth direction D4 can intersect the first direction D1, the second direction D2, and the third direction D3. In one example, the fourth direction D4 can form a 45-degree angle with respect to the first direction D1, a 45-degree angle with respect to the second direction D2, and can be orthogonal to the third direction D3.

[0068] The fourth end portion EP4 of the fourth chip protection member CG4 can be disposed between the first end portion EP1 of the first chip protection member CG1 and the second end portion EP2 of the second chip protection member CG2. A virtual line along the fourth direction D4 connecting the first end portion EP1 of the first chip protection member CG1 and the second end portion EP2 of the second chip protection member CG2 can overlap with the fourth end portion EP4 of the fourth chip protection member CG4. A virtual line along the fourth direction D4 connecting the first end portion EP1 of the first chip protection member CG1 and the second end portion EP2 of the second chip protection member CG2 can pass through the fourth end portion EP4 of the fourth chip protection member CG4. The second end portion EP2 of the second chip protection member CG2 can be disposed between the fourth end portion EP4 of the fourth chip protection member CG4 and the fifth end portion EP5 of the fifth chip protection member CG5. The fifth end portion EP5 of the fifth chip protection member CG5 can be disposed between the second end portion EP2 of the second chip protection member CG2 and the third end portion EP3 of the third chip protection member CG3. The third end portion EP3 of the third chip protection member CG3 can be disposed between the fifth end portion EP5 of the fifth chip protection member CG5 and the sixth end portion EP6 of the sixth chip protection member CG6.

[0069] The fourth end portion EP4 of the fourth chip protection member CG4 can be set to be farther from the cell region CER than the first end portion EP1 of the first chip protection member CG1. The second end portion EP2 of the second chip protection member CG2 can be set to be farther from the cell region CER than the fourth end portion EP4 of the fourth chip protection member CG4. The fifth end portion EP5 of the fifth chip protection member CG5 can be set to be farther from the cell region CER than the second end portion EP2 of the second chip protection member CG2. The third end portion EP3 of the third chip protection member CG3 can be set to be farther from the cell region CER than the fifth end portion EP5 of the fifth chip protection member CG5. The sixth end portion EP6 of the sixth chip protection member CG6 can be set to be farther from the cell region CER than the third end portion EP3 of the third chip protection member CG3.

[0070] The fourth short side wall SS4 of the fourth chip protection member CG4 can be set to be farther from the cell region CER than the first short side wall SS1 of the first chip protection member CG1. The second short side wall SS2 of the second chip protection member CG2 can be set to be farther from the cell region CER than the fourth short side wall SS4 of the fourth chip protection member CG4. The fifth short side wall SS5 of the fifth chip protection member CG5 can be set to be farther from the cell region CER than the second short side wall SS2 of the second chip protection member CG2. The third short side wall SS3 of the third chip protection member CG3 can be set to be farther from the cell region CER than the fifth short side wall SS5 of the fifth chip protection member CG5. The sixth short side wall SS6 of the sixth chip protection member CG6 can be set to be farther from the cell region CER than the third short side wall SS3 of the third chip protection member CG3.

[0071] The first short side wall SS1 of the first chip protection member CG1 may face the fourth long side wall LS4 of the fourth chip protection member CG4. The first short side wall SS1 of the first chip protection member CG1 may be spaced apart from the fourth long side wall LS4 of the fourth chip protection member CG4 in the second direction D2. The fourth short side wall SS4 of the fourth chip protection member CG4 may face the second long side wall LS2 of the second chip protection member CG2. The fourth short side wall SS4 of the fourth chip protection member CG4 may be spaced apart from the second long side wall LS2 of the second chip protection member CG2 in the first direction D1. The second short side wall SS2 of the second chip protection member CG2 may face the fifth long side wall LS5 of the fifth chip protection member CG5. The second short side wall SS2 of the second chip protection member CG2 may be spaced apart from the fifth long side wall LS5 of the fifth chip protection member CG5 in the second direction D2. The fifth short side wall SS5 of the fifth chip protection member CG5 may face the third long side wall LS3 of the third chip protection member CG3. The fifth short side wall SS5 of the fifth chip protection member CG5 may be spaced apart from the third long side wall LS3 of the third chip protection member CG3 in the first direction D1. The third short side wall SS3 of the third chip protection member CG3 may face the sixth long side wall LS6 of the sixth chip protection member CG6. The third short side wall SS3 of the third chip protection member CG3 may be spaced apart from the sixth long side wall LS6 of the sixth chip protection member CG6 in the second direction D2.

[0072] The first chip protection member CG1 may overlap with the fourth chip protection member CG4, the fifth chip protection member CG5, and the sixth chip protection member CG6 in the second direction D2. The fourth chip protection member CG4 may overlap with the second chip protection member CG2 and the third chip protection member CG3 in the first direction D1. The second chip protection member CG2 may overlap with the fifth chip protection member CG5 and the sixth chip protection member CG6 in the second direction D2. The fifth chip protection member CG5 may overlap with the third chip protection member CG3 in the first direction D1. The third chip protection member CG3 may overlap with the sixth chip protection member CG6 in the second direction D2.

[0073] The fourth chip protection member CG4 may include a fourth overlapping portion OP4 that overlaps with the first chip protection member CG1 in the second direction D2. The fourth overlapping portion OP4 may be connected to a fourth end portion EP4. The second chip protection member CG2 may include a second overlapping portion OP2 that overlaps with the fourth chip protection member CG4 in the first direction D1. The second overlapping portion OP2 may be connected to a second end portion EP2. The fifth chip protection member CG5 may include a fifth overlapping portion OP5 that overlaps with the second chip protection member CG2 in the second direction D2. The fifth overlapping portion OP5 may be connected to a fifth end portion EP5. The third chip protection member CG3 may include a third overlapping portion OP3 that overlaps with the fifth chip protection member CG5 in the first direction D1. The third overlapping portion OP3 may be connected to a third end portion EP3. The sixth chip protection member CG6 may include a sixth overlapping portion OP6 that overlaps with the third chip protection member CG3 in the second direction D2. The sixth overlapping portion OP6 may be connected to a sixth end portion EP6.

[0074] The fourth end portion EP4 of the fourth chip protection member CG4 may be disposed between the fourth overlapping portion OP4 of the fourth chip protection member CG4 and the second overlapping portion OP2 of the second chip protection member CG2. The fourth end portion EP4 of the fourth chip protection member CG4 may be disposed adjacent to the second chip protection member CG2. The second end portion EP2 of the second chip protection member CG2 may be disposed between the second overlapping portion OP2 of the second chip protection member CG2 and the fifth overlapping portion OP5 of the fifth chip protection member CG5. The second end portion EP2 of the second chip protection member CG2 may be disposed adjacent to the fifth chip protection member CG5. The fifth end portion EP5 of the fifth chip protection member CG5 may be disposed between the fifth overlapping portion OP5 of the fifth chip protection member CG5 and the third overlapping portion OP3 of the third chip protection member CG3. The fifth end portion EP5 of the fifth chip protection member CG5 may be disposed adjacent to the third chip protection member CG3. The third end portion EP3 of the third chip protection member CG3 may be disposed between the third overlapping portion OP3 of the third chip protection member CG3 and the sixth overlapping portion OP6 of the sixth chip protection member CG6. The third end portion EP3 of the third chip protection member CG3 may be disposed adjacent to the sixth chip protection member CG6.

[0075] The first short side wall SS1 of the first chip protection member CG1 can overlap with the fourth long side wall LS4 of the fourth chip protection member CG4, the fifth long side wall LS5 of the fifth chip protection member CG5, and the sixth long side wall LS6 of the sixth chip protection member CG6 in the second direction D2. The fourth short side wall SS4 of the fourth chip protection member CG4 can overlap with the second long side wall LS2 of the second chip protection member CG2 and the third long side wall LS3 of the third chip protection member CG3 in the first direction D1. The second short side wall SS2 of the second chip protection member CG2 can overlap with the fifth long side wall LS5 of the fifth chip protection member CG5 and the sixth long side wall LS6 of the sixth chip protection member CG6 in the second direction D2. The fifth short side wall SS5 of the fifth chip protection member CG5 can overlap with the third long side wall LS3 of the third chip protection member CG3 in the first direction D1. The third short side wall SS3 of the third chip protection member CG3 can overlap with the sixth long side wall LS6 of the sixth chip protection member CG6 in the second direction D2.

[0076] Referring again to Figure 1B and Figure 1C , each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6 can include a first protection pattern GP1, a first protection pad PA1, a second protection pad PA2, and a second protection pattern GP2. The first protection pattern GP1, the first protection pad PA1, the second protection pad PA2, and the second protection pattern GP2 of each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6 can be sequentially stacked in the third direction D3 to be connected to each other.

[0077] The first protection pattern GP1 can be disposed in the connection structure CNS. The first protection pattern GP1 can be included in the connection structure CNS. The first protection pattern GP1 can be disposed in the first insulating layer 110. The first protection pattern GP1 of each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6 can be stacked in the third direction D3. The first protection pattern GP1 of the first chip protection member to the third chip protection member CG1, CG2, and CG3 can extend in the second direction D2. The first protection pattern GP1 of the fourth chip protection member to the sixth chip protection member CG4, CG5, and CG6 can extend in the first direction D1. The first protection pattern GP1 can include a conductive material. In one example, the first protection pattern GP1 can include copper, aluminum, or tungsten.

[0078] The second protection pattern GP2 can be disposed in the fourth insulating layer 140 and the fifth insulating layer 150 of the semiconductor structure SEM. Some of the second protection patterns GP2 can be included in the semiconductor structure SEM. The second protection patterns GP2 of each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6 can be stacked in the third direction D3. The second protection patterns GP2 of the first chip protection member to the third chip protection member CG1, CG2, and CG3 can extend in the second direction D2. The second protection patterns GP2 of the fourth chip protection member to the sixth chip protection member CG4, CG5, and CG6 can extend in the first direction D1. The second protection pattern GP2 can include a conductive material. In one example, the second protection pattern GP2 can include copper, aluminum, or tungsten.

[0079] The first protection pad PA1 can be disposed between the first protection pattern GP1 and the second protection pattern GP2. A plurality of first protection pads PA1 can be disposed between the first protection pattern GP1 and the second protection pattern GP2 of each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6. The first protection pad PA1 can be disposed in the second insulating layer 120 of the first bonding structure BDS1. The first protection pads PA1 of each of the first chip protection member to the sixth chip protection member CG1, CG2, CG3, CG4, CG5, and CG6 can be disposed on the first protection pattern GP1.

[0080] The first protection pads PA1 of each of the first chip protection member to the third chip protection member CG1, CG2, and CG3 can be arranged in the second direction D2. The first protection pads PA1 of each of the first chip protection member to the third chip protection member CG1, CG2, and CG3 can be evenly spaced apart from each other in the second direction D2. A portion of the second insulating layer 120 can be disposed between the first protection pads PA1 of each of the first chip protection member to the third chip protection member CG1, CG2, and CG3. The second insulating layer 120 can be filled between the first protection pads PA1 of each of the first chip protection member to the third chip protection member CG1, CG2, and CG3.

[0081] The first protection pad PA1 of each of the fourth to sixth chip protection members CG4, CG5, and CG6 may be arranged in the first direction D1. The first protection pads PA1 of each of the fourth to sixth chip protection members CG4, CG5, and CG6 may be evenly spaced from each other in the first direction D1. A portion of the second insulating layer 120 may be provided between the first protection pads PA1 of each of the fourth to sixth chip protection members CG4, CG5, and CG6. The second insulating layer 120 may be filled between the first protection pads PA1 of each of the fourth to sixth chip protection members CG4, CG5, and CG6.

[0082] The first protection pad PA1 may be provided at the same level as the first bonding pad BP1. The first protection pad PA1 may include a conductive material. In one example, the first protection pad PA1 may include copper.

[0083] The second protection pad PA2 may be provided between the first protection pattern GP1 and the second protection pattern GP2. A plurality of second protection pads PA2 may be provided between the first protection pattern GP1 and the second protection pattern GP2 of each of the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6. The second protection pad PA2 may be provided in the third insulating layer 130 of the second bonding structure BDS2. The second protection pad PA2 of each of the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 may be provided on the first protection pad PA1 of each of the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6.

[0084] The second protection pads PA2 of each of the first to third chip protection members CG1, CG2, and CG3 may be arranged in the second direction D2. The second protection pads PA2 of each of the first to third chip protection members CG1, CG2, and CG3 may be evenly spaced from each other in the second direction D2. A portion of the third insulating layer 130 may be provided between the second protection pads PA2 of each of the first to third chip protection members CG1, CG2, and CG3. The third insulating layer 130 may be filled between the second protection pads PA2 of each of the first to third chip protection members CG1, CG2, and CG3.

[0085] The second protection pad PA2 of each of the fourth to sixth chip protection members CG4, CG5, and CG6 may be arranged in the first direction D1. The second protection pads PA2 of each of the fourth to sixth chip protection members CG4, CG5, and CG6 may be evenly spaced from each other in the first direction D1. A portion of the third insulating layer 130 may be provided between the second protection pads PA2 of each of the fourth to sixth chip protection members CG4, CG5, and CG6. The third insulating layer 130 may be filled between the second protection pads PA2 of each of the fourth to sixth chip protection members CG4, CG5, and CG6.

[0086] The second protection pad PA2 may be provided at the same level as the second bonding pad BP2. The second protection pad PA2 may be provided at a level different from the level of the first protection pad PA1. The second protection pad PA2 may include a conductive material. In one example, the second protection pad PA2 may include copper.

[0087] The width of the first protection pad PA1 may become wider as it approaches the second protection pad PA2. In one example, the width of the first protection pad PA1 in the first direction D1 may become wider as it approaches the second protection pad PA2. The width of the second protection pad PA2 may become wider as it approaches the first protection pad PA1. In one example, the width of the second protection pad PA2 in the first direction D1 may become wider as it approaches the first protection pad PA1.

[0088] In each of the first to third chip protection members CG1, CG2, and CG3, the distance between two adjacent first protection pads PA1 spaced from each other in the second direction D2 and the distance between two adjacent second protection pads PA2 spaced from each other in the second direction D2 may be shorter than the length of the first protection pattern GP1 extending in the first direction D1 and the length of the second protection pattern GP2 extending in the first direction D1.

[0089] In one example, referring to Figure 1C , two adjacent first protection pads PA1 of the first chip protection member CG1 may be spaced from each other in the second direction D2 by a first distance FD, and two adjacent second protection pads PA2 of the first chip protection member CG1 may be spaced from each other in the second direction D2 by a second distance SD. The length of the first protection pattern GP1 of the first chip protection member CG1 in the second direction D2 may be longer than the first distance FD and the second distance SD. The length of the second protection pattern GP2 of the first chip protection member CG1 in the second direction D2 may be longer than the first distance FD and the second distance SD.

[0090] In the semiconductor device, according to this embodiment, since the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 are spaced apart from each other at the corners of the chip protection region CGR, the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 may not be formed in any closed curve shape at the corners of the chip protection region CGR. Therefore, compared with the case where the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 are formed in a closed curve shape, the stress that may occur in the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 at the corners of the chip protection region CGR can be reduced. In other words, cracks due to stress concentration can be prevented.

[0091] In the semiconductor device, according to this embodiment, since the first to sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 intersect and overlap each other along the first direction D1 and the second direction D2, the above components provided on the cell region CER can be effectively protected.

[0092] In the semiconductor device, according to this embodiment, since the first protection pads PA1 are arranged to be spaced apart from each other and the second protection pads PA2 are arranged to be spaced apart from each other, the first protection pads PA1 and the second protection pads PA2 can be smoothly joined by a wafer bonding process.

[0093] Figure 2A and Figure 3A is a plan view showing Figures 1A to 1D the manufacturing method of the semiconductor device shown. Figure 2B is a cross-sectional view taken along Figure 2A the line A2 - A2' shown. Figure 3B is a cross-sectional view taken along Figure 3A the line A3 - A3' shown. Figure 4 is a cross-sectional view showing Figures 1A to 1D the manufacturing method of the semiconductor device shown.

[0094] For ease of description, the overlapping description of the components described with reference to Figures 1A to 1D will be omitted.

[0095] The manufacturing method described below is merely Figures 1A to 1D one embodiment of the manufacturing method of the semiconductor device shown, and Figures 1A to 1D the manufacturing method of the semiconductor device shown may not be limited to the method described below.

[0096] Referring to Figure 2A and Figure 2B, a second substrate 200 can be formed. The second substrate 200 can have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. In one example, the second substrate 200 can be a semiconductor substrate or an insulator substrate.

[0097] A semiconductor structure SEM can be formed on the second substrate 200. The formation of the semiconductor structure SEM can include: forming a source structure SOS on the second substrate 200, forming a stacked structure STA having a sacrificial layer and a stacked insulating layer IL on the source structure SOS, forming a cell plug PL penetrating the stacked structure STA, replacing the sacrificial layer of the stacked structure STA with a conductive pattern CP, forming a slit structure SLS, forming a bit line contact BCT connected to the cell plug PL and a bit line BL, and forming a fourth insulating layer 140. The fourth insulating layer 140 can include a plurality of insulating layers required in the processes of forming the source structure SOS, the stacked structure STA, the cell plug PL, the slit structure SLS, the bit line contact BCT, and the bit line BL.

[0098] A second protection pattern GP2 can be formed in the fourth insulating layer 140. The second protection pattern GP2 of each of the first chip protection member to the sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 can be sequentially formed by using the plurality of insulating layers of the fourth insulating layer 140.

[0099] A second bonding structure BDS2 can be formed on the semiconductor structure SEM. The formation of the second bonding structure BDS2 can include: forming a third insulating layer 130 covering the semiconductor structure SEM, and forming a second bonding pad BP2 and a second protection pad PA2 penetrating the third insulating layer 130.

[0100] Referring to Figure 3A and Figure 3B , a first substrate 100 can be formed.

[0101] Subsequently, a transistor TR and a connection structure CNS can be formed on the first substrate 100. The formation of the transistor TR and the connection structure CNS can include: forming a transistor TR on the first substrate 100, forming a connection conductor CB connected to the transistor TR, and forming a first insulating layer 110. The first insulating layer 110 can include a plurality of insulating layers required in the processes of forming the transistor TR and the connection conductor CB.

[0102] The first protection pattern GP1 of each of the first through sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 may be formed on the substrate 100. The first protection pattern GP1 of each of the first through sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 may be sequentially formed by using a plurality of insulating layers of the first insulating layer 110.

[0103] The first bonding structure BDS1 may be formed on the connection structure CNS. The formation of the first bonding structure BDS1 may include: forming a second insulating layer 120 covering the connection structure CNS, and forming a first bonding pad BP1 and a first protection pad PA1 that penetrate the second insulating layer 120.

[0104] Referring to Figure 4 , after flipping the second substrate 200, the semiconductor structure SEM, and the second bonding structure BDS2, the second bonding structure BDS2 and the first bonding structure BDS1 may be bonded to each other. Accordingly, the second bonding pad BP2 of the second bonding structure BDS2 and the first bonding pad BP1 of the first bonding structure BDS1 may be bonded to each other, the second protection pad PA2 of the second bonding structure BDS2 and the first protection pad PA1 of the first bonding structure BDS1 may be bonded to each other, and the second insulating layer 120 and the third insulating layer 130 may be bonded to each other.

[0105] Subsequently, after removing the second substrate 200, a fifth insulating layer 150, a source contact SC, and a second line ML2 may be formed, and a second protection pattern GP2 (see Figure 1B and Figure 1C ) may be formed in the fifth insulating layer 150.

[0106] Figure 5 is a view showing the effects of the semiconductor device shown in Figures 1A to 1D .

[0107] For ease of description, the overlapping description of the components described with reference to Figures 1A to 1D will be omitted.

[0108] Referring to Figure 5 , since the first through sixth chip protection members CG1, CG2, CG3, CG4, CG5, and CG6 intersect and overlap each other along the first direction D1 and the second direction D2, foreign substances existing outside the semiconductor device are difficult to penetrate into the semiconductor device.

[0109] Specifically, referring to the penetration path PT of the foreign object, the foreign object will have to pass through between the sixth overlapping portion OP6 of the sixth chip protection member CG6 and the third end portion EP3 of the third chip protection member CG3, between the third overlapping portion OP3 of the third chip protection member CG3 and the fifth end portion EP5 of the fifth chip protection member CG5, between the fifth overlapping portion OP5 of the fifth chip protection member CG5 and the second end portion EP2 of the second chip protection member CG2, between the second overlapping portion OP2 of the second chip protection member CG2 and the fourth end portion EP4 of the fourth chip protection member CG4, and between the fourth overlapping portion OP4 of the fourth chip protection member CG4 and the first end portion EP1 of the first chip protection member CG1 in sequence, so as to reach components (such as a stacked structure and a cell plug) in the cell region CER in the semiconductor device from the outside of the semiconductor device.

[0110] Therefore, the penetration path PT of the foreign object becomes longer, and it is difficult for the foreign object existing outside the semiconductor device to penetrate into the semiconductor device.

[0111] Figure 6 It is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0112] Referring to Figure 6 , the memory system 1100 according to this embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110.

[0113] The memory device 1120 may include the semiconductor device described above. The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0114] The memory controller 1110 is configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112. The CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for the host connected to the memory system 1100. The ECC circuit 1114 detects and corrects errors contained in the data read from the memory device 1120, and the memory interface 1115 is interfaced with the memory device 1120. In addition, the memory controller 1110 may further include a ROM or the like for storing code data for interfacing with the host.

[0115] The memory system 1100 can be a solid state drive (SSD) or a memory card in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., host) through one of various interface protocols such as the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA (SATA) protocol, the Parallel ATA (PATA) protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, and the Integrated Drive Electronics (IDE) protocol.

[0116] Figure 7 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0117] Referring to Figure 7 , the computing system 1200 according to this embodiment of the present disclosure may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to the system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing an operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor (CIS), and a mobile D-RAM, etc.

[0118] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211 similar to the memory device and the memory controller described with reference to Figure 6 .

[0119] According to the present disclosure, a semiconductor device includes chip protectors spaced apart from each other at corners of a chip protection region, thereby preventing cracks from occurring at the corners of the chip protection region due to stress concentration.

[0120] Exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above embodiments, and many variations can be made within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0121] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the meanings commonly understood by those of ordinary skill in the art to which this disclosure pertains. Terms with definitions as defined in a dictionary should be understood to have a meaning consistent with the context of the relevant art. Terms should not be understood in an idealized or overly formal manner unless clearly defined otherwise in this application.

[0122] Cross - Reference to Related Applications

[0123] This application claims priority to Korean Patent Application No. 10 - 2020 - 0109657, filed with the Korean Intellectual Property Office on August 28, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprises: a substrate having a cell region and a chip protection region, the chip protection region surrounding the cell region; a plurality of chip protection members on the chip protection region, the plurality of chip protection members extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and the plurality of chip protection members including a first chip protection member and a second chip protection member arranged adjacent to each other in the second direction; and a third chip protection member extending on the chip protection region along the second direction, the second direction intersecting the first direction, wherein the first chip protection member includes a first end, wherein the second chip protection member includes a second end, wherein the third chip protection member includes a third end disposed between the first end and the second end in both the first direction and the second direction.

2. The semiconductor device according to claim 1, the semiconductor device further comprising a fourth chip protection member extending on the chip protection region along the second direction, and the fourth chip protection member being spaced apart from the third chip protection member.

3. The semiconductor device according to claim 2, wherein, the fourth chip protection member includes a fourth end, and wherein the second end is disposed between the third end and the fourth end.

4. The semiconductor device according to claim 1, wherein, the third end is disposed farther from the cell region than the first end, and wherein the second end is disposed farther from the cell region than the third end.

5. The semiconductor device according to claim 1, wherein, the first chip protection member includes a first long sidewall extending in the first direction and a first short sidewall extending from the first long sidewall in the second direction, and wherein the length of the first long sidewall is longer than the length of the first short sidewall.

6. The semiconductor device according to claim 5, wherein, the second chip protection member includes a second long sidewall extending in the first direction and a second short sidewall extending from the second long sidewall in the second direction, wherein the length of the second long sidewall is longer than the length of the second short sidewall, and wherein the second long sidewall is disposed farther from the cell region than the first long sidewall, and wherein the second short sidewall is disposed farther from the cell region than the first short sidewall.

7. The semiconductor device according to claim 5, wherein, the third chip protection member includes a third long sidewall extending in the second direction and a third short sidewall extending from the third long sidewall in the first direction, and wherein the third long sidewall faces the first short sidewall.

8. A semiconductor device, the semiconductor device comprises: a substrate having a cell region and a chip protection region, the chip protection region surrounding the cell region; A plurality of chip protection members, the plurality of chip protection members being on the chip protection region, the plurality of chip protection members extending in a first direction, being spaced apart from each other in a second direction intersecting the first direction, and the plurality of chip protection members including a first chip protection member and a second chip protection member arranged adjacent to each other in the second direction; and A third chip protection member, the third chip protection member extending on the chip protection region in the second direction, the second direction intersecting the first direction, wherein the first chip protection member includes a first long sidewall extending in the first direction and a first short sidewall extending in the second direction, the second chip protection member includes a second long sidewall extending in the first direction and a second short sidewall extending in the second direction, and the third chip protection member includes a third long sidewall extending in the second direction and a third short sidewall extending in the first direction, and wherein the first short sidewall faces the third long sidewall, the third short sidewall faces the second long sidewall, and wherein the third short sidewall is disposed between the first short sidewall and the second short sidewall in the first direction.

9. The semiconductor device according to claim 8, wherein, the first chip protection member overlaps with the third chip protection member in the first direction.

10. The semiconductor device according to claim 9, wherein, the third chip protection member overlaps with the second chip protection member in the second direction.

11. The semiconductor device according to claim 8, wherein, the length of the second chip protection member is longer than the length of the first chip protection member.

12. The semiconductor device according to claim 8, wherein, the first long sidewall faces the second long sidewall, and the third short sidewall is disposed between the first long sidewall and the second long sidewall.

13. The semiconductor device according to claim 12, wherein, the third short sidewall is disposed to be closer to the second long sidewall than to the first long sidewall.

14. A semiconductor device, the semiconductor device comprising: A connection structure having a connection conductor and a first protection pattern; A semiconductor structure having a stacked structure, a unit plug penetrating the stacked structure, and a second protection pattern; A plurality of chip protection members extending in a first direction and spaced apart from each other in a second direction, and the plurality of chip protection members including a first chip protection member and a second chip protection member arranged adjacent to each other in the second direction; and A third chip protection member extending in the second direction, wherein each of the first chip protection member and the second chip protection member includes: the first protection pattern in the connection structure, the second protection pattern in the semiconductor structure, and a plurality of protection pads connecting the first protection pattern and the second protection pattern by being disposed between the first protection pattern and the second protection pattern, Wherein, the first protection pattern and the second protection pattern extend in the first direction. Wherein, the plurality of protection pads are spaced apart from each other in the first direction. Wherein, the distance by which the plurality of protection pads are spaced apart from each other in the first direction is shorter than the length of the first protection pattern in the first direction and the length of the second protection pattern in the first direction, and Wherein, the end portion of the third chip protection member is disposed between the end portions of the first chip protection member and the second chip protection member in both the first direction and the second direction.

15. The semiconductor device according to claim 14, Wherein, The protection pads include a first protection pad connected to the first protection pattern and a second protection pad connected to the second protection pattern.

16. The semiconductor device according to claim 15, Wherein, The first protection pad and the second protection pad are disposed at different levels.

17. The semiconductor device according to claim 14, Wherein, The plurality of protection pads are evenly spaced apart from each other in the first direction.

18. The semiconductor device according to claim 14, the semiconductor device further includes an insulating layer filled between the plurality of protection pads.

19. The semiconductor device according to claim 18, Wherein, The insulating layer is disposed between the connection structure and the semiconductor structure.

20. The semiconductor device according to claim 14, the semiconductor device further includes a bonding pad connecting the unit plug and the connection conductor, Wherein, The bonding pad is disposed at the same level as the protection pad.

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