Semiconductor memory device

Abstract

A semiconductor storage device of an embodiment includes: a laminate in which first layers and second layers are alternately laminated; and plate-shaped portions that penetrate the laminate in a lamination direction of the laminate and extend in a first direction that intersects the lamination direction. The first layers are formed of a first insulating material. The second layers each have an insulating region and a conductive region that is connected to the insulating region in the first direction, the insulating region being formed of a second insulating material and being disposed so as to extend from an end of the laminate toward the first direction in a manner of occupying at least between each end of the plate-shaped portions extending in the first direction and an end of the laminate in the first direction. An interface between the insulating region and the conductive region is located farther from the end of the laminate than each end of the plurality of plate-shaped portions in the first direction.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2020-146303, filed on August 31, 2020, and all contents of that Japanese Patent Application are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] For example, consider a semiconductor memory device with a three-dimensional structure, comprising: a stacked body formed by alternating layers of insulating and conductive layers; memory pillars penetrating the stacked body in the stacking direction; and multiple memory cells formed on the memory pillars. Here, the conductive layers function as word lines for the corresponding memory cells. To connect the conductive layers, which serve as word lines, to control circuitry controlling the memory cells, contacts are provided on each conductive layer. These contacts are connected to the conductive layers, which are stepped surfaces due to the stepped shape at the ends of the stacked body.

[0005] To reduce word line resistance and enable high-speed operation of semiconductor memory devices, the current trend is to incorporate this stepped shape not only at the ends of the stacked layers but also near the center. Given this trend, how to construct the ends of the stacked layers has become a key concern. Summary of the Invention

[0006] One embodiment of the present invention provides a semiconductor memory device that can omit the stepped shape at the end of the stacked body at at least one end of the semiconductor memory device having a three-dimensional structure.

[0007] According to one embodiment of the present invention, a semiconductor memory device is provided. The semiconductor memory device includes: a stacked body formed by alternately stacking a plurality of first layers and a plurality of second layers; and a plurality of plate-like portions extending through the stacked body in a stacking direction and extending in a first direction intersecting the stacking direction. The plurality of first layers are formed of a first insulating material. Each second layer has a first insulating region and a conductive region connected to the first insulating region in the first direction. The first insulating region is formed of a second insulating material and is disposed extending from the first end of the stacked body in the first direction, such that it at least occupies the space between a first end of each of the plurality of plate-like portions extending in the first direction and an end of the stacked body in the first direction. The boundary between the first insulating region and the conductive region is located along the first direction at a position further away from the first end of the stacked body than the first end of each of the plurality of plate-like portions. Attached Figure Description

[0008] Figure 1 This is a top view schematically illustrating an example of a semiconductor memory device according to the first embodiment.

[0009] Figure 2 It is a schematic representation. Figure 1 An enlarged top view of a portion of the stepped area of ​​the memory section of a semiconductor memory device.

[0010] Figure 3 It is along Figure 2 A sectional view along line A1-A1 in the diagram.

[0011] Figure 4 It is along Figure 2 A sectional view along line A2-A2.

[0012] Figure 5A It is an enlarged top view schematically representing the slit termination area.

[0013] Figure 5B It is along Figure 5A A cross-sectional view of line L6-L6.

[0014] Figures 6A to 6E It is along Figure 5A A cross-sectional view of each cut line in the diagram.

[0015] Figures 7A to 7E This is a top view used to illustrate the method of forming the slit termination region.

[0016] Figures 8A to 8C It is a diagram showing a cross-section of the laminated body.

[0017] Figure 9 This is a top view schematically representing a silicon nitride layer in a laminate.

[0018] Figures 10A to 10C This is an explanatory diagram showing the slit termination region of the semiconductor memory device in Comparative Example 1.

[0019] Figure 11 This is a top view showing the conductive layer in the slit termination region of Comparative Example 1.

[0020] Figure 12A and Figure 12B This is a top view schematically illustrating the relationship between the etch length of the silicon nitride layer etched through the slit and the length of the barrier layer within the slit.

[0021] Figures 13A to 13C This is an explanatory diagram illustrating the slit termination region of the semiconductor memory device in Comparative Example 2.

[0022] Figure 14A This is a top view schematically showing the central portion of the semiconductor memory device according to the first embodiment.

[0023] Figure 14B This is a schematic cross-sectional view of the end of the semiconductor memory device of the first embodiment extending along its long side.

[0024] Figure 15A This is a top view schematically illustrating an example of a semiconductor memory device according to the second embodiment.

[0025] Figure 15B This is a partial cross-sectional view schematically showing the end of the semiconductor memory device according to the second embodiment.

[0026] Figure 16 This is a cross-sectional view of the semiconductor memory device of the third embodiment near the end extending in the long side direction, along the short side direction.

[0027] Figure 17 This is a cross-sectional view of the semiconductor memory device of Variation Example 1 of the third embodiment, near the end extending in the long side direction, along the short side direction.

[0028] Figure 18 This is a cross-sectional view of the semiconductor memory device of Variation 2 of the third embodiment, near the end extending in the long side direction, along the short side direction.

[0029] Figure 19 This is a top view showing the stepped region of the semiconductor memory device in the first variation example.

[0030] Figure 20A It is along Figure 19 A sectional view along line A3-A3.

[0031] Figure 20B It is along Figure 19 A sectional view along line A4-A4.

[0032] Figure 21 This is a schematic cross-sectional view showing the slit termination region in the second variation example. Detailed Implementation

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings, which are illustrative and do not limit the invention. In all the accompanying drawings, the same or corresponding reference numerals are used for the same or corresponding parts, and repeated descriptions are omitted. Furthermore, the drawings are not intended to show relative ratios between parts or between layers; therefore, specific thicknesses and dimensions should be determined by those skilled in the art with reference to the following non-limiting embodiments.

[0034] Implementation Method 1

[0035] Figure 1This is a top view schematically illustrating an example of the semiconductor memory device 1 according to the first embodiment. (See attached image.) Figure 1 As shown, the semiconductor memory device 1 has a chip-shaped substrate 10. A peripheral circuit section (described later) is formed on the substrate 10, and a stacked layer section including a stacked layer SK and a stacked layer SKI is formed on the peripheral circuit section. The stacked layer SK has a structure formed by alternating layers of conductive and insulating layers, and the stacked layer SKI has a structure formed by alternating layers of different insulating layers. Figure 1 As shown, the semiconductor memory device 1 has two stacked layers SK arranged along its long side direction (X-axis direction), and a memory portion MEM (also called a memory surface) is formed on each of the two stacked layers SK. Furthermore, the semiconductor memory device 1 has a stacked layer SKI surrounding the two stacked layers SK. That is, the stacked layer SKI surrounds the stacked layers SK and has an end portion E extending in the Y-axis direction and an end portion EF extending in the X-axis direction. In this embodiment, the end portion E of the stacked layer SKI coincides with the end portion 1Y of the semiconductor memory device 1, and the end portion EF coincides with the end portion 1X of the semiconductor memory device 1. Therefore, stacked layers SKI appear on all end faces of the semiconductor memory device 1 in this embodiment.

[0036] In the memory section MEM, a memory array region MA, a stepped region FSA, and another memory array region MA are arranged sequentially along the X-axis. Specifically, the stepped region FSA is located in the center of the memory section MEM, sandwiched between two memory array regions MA. Multiple memory cells are arranged three-dimensionally in the memory array region MA. The stepped region FSA includes contacts electrically connected to the gates of the memory cells, and through contacts electrically connecting the peripheral circuitry of the peripheral circuitry section to the contacts. The peripheral circuitry controls the operation of the memory cells. The peripheral circuitry may include, for example, a line decoder and a sense amplifier circuit. The line decoder identifies the region containing the memory cells to be operated, and the sense amplifier circuit senses the data stored in the memory cells. Furthermore, the stepped region FSA is located on the stacked layer SK, but as described below, it partially includes the stacked layer SKI.

[0037] Furthermore, a slit ST extending in the X-axis direction is provided in the semiconductor memory device 1, dividing the memory section MEM in the Y-axis direction.

[0038] The following is for reference Figure 2 To illustrate the structure of the stepped region FSA. Figure 2 This is an enlarged top view schematically representing a portion of the stepped area FSA. However, Figure 2 The upper-level wiring, etc., are omitted. For example... Figure 2As shown, a set of stepped portions FS and through-connection regions C4A are respectively disposed in each finger-shaped region FG divided by two adjacent slits ST. Both the stepped portions FS and the through-connection regions C4A have an elongated shape in the X-axis direction and are arranged in the X-axis direction. In addition, in the cell array regions MA on both sides of the stepped region FSA, as shown, multiple memory pillars MP are disposed that penetrate the stacked body SK in the stacking direction (Z-axis direction). Multiple memory cells are formed at the positions where the memory pillars MP intersect with the multiple conductive layers (described later) of the stacked body SK extending from the stepped region FSA.

[0039] Figure 3 It is along Figure 2 A sectional view along line A1-A1. However, Figure 3 The peripheral circuitry below the stacked layer SK is omitted. The stepped section FS has a stepped shape such that a group of conductive layers WL and insulating layers OL form a segment with the insulating layer OL as the step surface (step surface), and the width (length in the X-axis direction in the figure) of each segment decreases as it rises. An interlayer insulating film SO is formed above the stepped section FS. On each conductive layer WL, a contact CC is connected, through which the interlayer insulating film SO and the insulating layer OL of each segment pass. Here, the conductive layer WL also extends into the memory array region MA and connects to the memory pillar MP within the memory array region MA. The memory pillar MP passes through the stacked layer SK, which is formed by alternating layers of conductive layers WL and insulating layers OL, and reaches the base layer SB, which functions as the source electrode of each memory cell. The memory pillar MP has a core layer C, a channel layer CH, and a memory film arranged concentrically from the center to the outside. The channel layer CH protrudes further into the base layer SB than the memory film M and is electrically connected to the base layer SB. The topmost and bottommost conductive layers WL among the multiple conductive layers WL connected to the memory cylinder MP function as select gate lines, while the conductive layer WL between the topmost and bottommost layers functions as the gate electrode (i.e. word line) of each memory cell.

[0040] Figure 4 It is along Figure 2A cross-sectional view along line A2-A2 is shown. As shown, a multilayer wiring section ML is formed on substrate 10. A transistor Tr, separated by the component separation section EI, is formed on substrate 10. In the multilayer wiring section ML, specifically, wiring L and via V are provided within the interlayer insulating film SO. The transistor Tr in substrate 10, the wiring L and via V in the multilayer wiring section ML constitute the peripheral circuit section PER. Furthermore, a base layer SB, for example made of silicon, is formed on the multilayer wiring section ML, and a stacked body SK is formed on the base layer SB. The stacked body SK has multiple insulating layers OL and multiple insulating layers WL, which are alternately stacked layer by layer. The insulating layers OL are formed of an insulating material, and in this embodiment, specifically, for example, silicon oxide. In the following description, the insulating layer OL will be referred to as the silicon oxide layer OL. In addition, the conductive layers WL may also be formed of metals such as tungsten or molybdenum.

[0041] The slit ST penetrates the laminate SK and reaches the substrate SB. An insulating material, such as silicon oxide, is embedded inside the slit ST. Alternatively, a conductive material can be embedded inside the slit ST, separated by an insulating material covering the sidewalls of the slit ST. In this case, the conductive material can also be connected to the substrate SB to function as, for example, a source wire contact. Stepped portions FS are provided in the finger regions FG on both sides of the slit ST in the center of the figure. A through-contact region C4A is provided in the finger region FG further outward from the finger region FG with the stepped portions FS. Figure 4 In the diagram, the connection point CC is connected to the fifth step surface counting from the bottom of the step section FS.

[0042] In the through-contact area C4A, there are two short slits OST, an insulating layer area ON located between them, and a through-contact C4 that penetrates the insulating layer area ON and the substrate layer SB. For example... Figure 2 As shown, the shorter slit OST extends along the X-axis in the same direction as slit ST, but is shorter than slit ST. A barrier layer (not shown) is formed on the inner surface of the shorter slit OST, and an insulating material such as silicon oxide is embedded in the inner region of the barrier layer. In the insulating layer region ON, for example, multiple silicon oxide layers and multiple silicon nitride layers are stacked alternately layer by layer. Thus, the insulating layer region ON is insulating as a whole. Therefore, the through contact C4, which penetrates the insulating layer region ON, is insulated from the conductive layer WL in the laminate SK. The through contact C4 is electrically connected to the wiring L of the peripheral circuit section PER at its lower end, and is further electrically connected to the peripheral circuit through the via V, etc. In addition, the through contact C4 is connected to the upper layer wiring UL at its upper end through the plug CCP, and the upper layer wiring UL is electrically connected to the contact CC through the plug CCP. The contact CC is electrically connected to the memory cell through the conductive layer WL, so the peripheral circuit is electrically connected to the memory cell.

[0043] Next, refer to Figures 5A to 6E This will be used to explain the structure of the region between the end E of the stacked body (similar to a stacked body SKI) and the memory array region MA. This region is, for example,... Figure 1 The region denoted as R is referred to below as the slit termination region R for ease of explanation. Figure 5A This is an enlarged top view of the slit termination region R. Figure 5B It is along Figure 5A A cross-sectional view of line L6-L6. Furthermore... Figure 6A It is along Figure 5A A sectional view of line L1-L1 in the middle. Figure 6B It is along Figure 5A A sectional view of line L2-L2 in the middle. Figure 6C It is along Figure 5A A sectional view of line L3-L3 in the middle. Figure 6D It is along Figure 5A A sectional view of line L4-L4 in the middle. Figure 6E It is along Figure 5A A cross-sectional view of line L5-L5 in the diagram.

[0044] like Figure 5A As shown, the slit ST has an end STE at a specific distance from the end E of the laminated body (laminated body SKI) and extends in the X-axis direction. A barrier layer BL is formed on the inner surface of the slit ST, and an insulating layer IL is formed inside the barrier layer BL. That is, the slit ST defines a plate-like portion including the barrier layer BL and the insulating layer IL. In addition, as described above, a conductive material is embedded inside the slit ST. When this conductive material functions as, for example, a source wire contact by connecting it to the substrate layer SB, the conductive material can be embedded inside the barrier layer BL, which serves as an insulating layer. Furthermore, as Figure 5B As shown, in the finger-shaped region FG of the slit termination region R, the laminate SKI and laminate SK are arranged in the X-axis direction and formed on the base layer SB. According to Figure 5A and Figure 5B It can be seen that the end STE of the slit ST is located within the laminate SKI. That is, the region between the end STE and the end E of the slit ST in the X-axis direction is not occupied by the laminate SK, but by the laminate SKI. Furthermore, as... Figure 5B As shown, the silicon oxide layer OL of the stacked SKI is interconnected with the silicon oxide layer OL of the stacked SK to form a monolith. On the other hand, the silicon nitride layer SN of the stacked SKI and the conductive layer WL of the stacked SK are interconnected between the silicon oxide layers OL. Therefore, in the slit termination region R, multiple silicon oxide layers OL can be arranged separately, with the silicon nitride layer SN extending from the end E in the X-axis direction at a specific length between them, and the conductive layer WL extending in a manner connected to the silicon nitride layer SN in the X-axis direction.

[0045] In addition, in this embodiment, such as Figure 5B As shown, the boundary between the silicon nitride layer SN and the conductive layer WL is neatly arranged in the stacking directions of the laminates SKI and SK. Furthermore, the stacking structure of the laminate SKI is the same as that of the insulating layer region ON. Specifically, in the laminate SKI and the insulating layer region ON, the number of silicon oxide layers OL and silicon nitride layers SN, and the thickness of each layer, are approximately the same. Additionally, the number of layers is not limited to the example shown and can be any number.

[0046] Reference Figure 6A A laminated structure SKI is formed on the basal layer SB. The figure is along... Figure 5A A cross-sectional view along line L1-L1, and a YZ cross-sectional view of the region separating the end E of the laminated body (laminated body SKI) and the end STE of the slit ST. On the other hand, Figure 6B and Figure 6C The diagram illustrates the slits ST. The slits ST penetrate the laminate SKI and reach the base layer SB. Furthermore, these slits ST have a barrier layer BL and an insulating layer IL.

[0047] Reference as along Figure 5A Sectional view of L4-L4 Figure 6D The layer formed on the basal layer SB is not a laminated body SKI, but a laminated body SK. Furthermore, multiple slits ST penetrate this laminated body SK. Figure 6B and Figure 6C Similarly, as illustrated, these slits ST each have a barrier layer BL and an insulating layer IL.

[0048] exist Figure 6E In, with Figure 6D Similarly, multiple slits ST penetrate the laminate SK. However, these slits ST do not contain a barrier layer BL, but only an insulating layer IL.

[0049] Next, refer to Figures 7A to 7E This will explain the method for forming the structure of the slit termination region R. Figures 7A to 7E This is a top view illustrating the method of forming the structure of the slit termination region R.

[0050] Furthermore, the general outline of the manufacturing process of the semiconductor memory device 1 before forming the slit termination region R is as follows. First, the peripheral circuit section PER is formed on a semiconductor substrate such as a silicon wafer. Next, a base layer SB is formed on the peripheral circuit section PER, and a stacked structure (same as the stacked body SKI) is formed thereon by alternately stacking multiple silicon oxide layers OL and multiple silicon nitride layers SN. Then, on the upper surface of the stacked structure, a resist mask with an opening is provided at the location where the step section FS should be formed, and a temporary step section is formed, for example, by a process including etching, refinement of the resist mask, and re-etching. In the temporary step section, the silicon oxide layer OL of the stacked structure is disposed on the step surface. Then, a silicon oxide film, for example, is deposited to cover the temporary step section and the stacked structure. Next, the silicon oxide film is planarized to obtain a silicon oxide film SO (as an interlayer insulating film). Figure 5B Next, in the storage array region MA ( Figure 1 Multiple memory pillars (MPs) forming a through-layer structure in ) Figure 3 The memory pillar MP is formed by, for example, a memory aperture that forms a through-layer structure and reaches the substrate layer SB, and a memory film M is sequentially formed on the inner surface of the memory aperture. Figure 3 It is formed by the channel layer CH and the core layer C.

[0051] Then, the structure of the slit termination region R is formed. Specifically, firstly, as follows... Figure 7A As shown, multiple slits ST are formed. Additionally, as... Figure 1 As shown, a slit ST is formed in a manner that traverses the entire memory section MEM in the X-axis direction and penetrates the silicon oxide film SO and the stack SKI to reach the substrate layer SB (see, for example, reference). Figure 4 Furthermore, ideally, the shorter slit OST should be formed simultaneously with the formation of the slit ST. Figure 2 , Figure 4 ).

[0052] Next, as Figure 7B As shown, a barrier layer BL is deposited on the entire inner surface of the slit ST. The barrier layer BL is formed of a material resistant to the etchant used when etching the silicon nitride layer SN (described later). Such a material could be, for example, silicon oxide. Then, as... Figure 7C As shown, a resist mask RM is formed on the upper surface of the silicon oxide film SO. The resist mask RM covers a specific distance from the end E of the stack SKI. Therefore, the silicon oxide film SO, slits ST, etc., are exposed in a range closer to the memory array region MA than this range.

[0053] Additionally, a barrier layer BL is also deposited on the inner surface of the shorter slit OST formed simultaneously with the slit ST. Furthermore, the resist mask RM can cover the two adjacent shorter slit OSTs formed within the finger region FG. Figure 2 , Figure 4 ).

[0054] Next, etching is performed using a resist mask RM, thus achieving the desired effect. Figure 7D As shown, the barrier layer BL deposited within the slit ST is removed. Then, the resist mask RM is removed by methods such as ashing to obtain an image... Figure 7E That way, the slit ST of the barrier layer BL is preserved.

[0055] Next, the silicon nitride layer SN in the stacked SKI is etched using such a slit ST. Specifically, an etchant capable of dissolving silicon nitride is injected into the slit ST. Phosphoric acid (H3PO4) can be used as an example of such an etchant.

[0056] Figures 8A to 8C This is a schematic diagram showing a cross-section of the etched laminate. Figure 8A It is along Figure 7E A cross-sectional view of line U2-U2. Figure 8B It is along Figure 7E A cross-sectional view of line U4-U4. Figure 8C It is along Figure 7E A cross-sectional view of line U5-U5. Additionally, line U2-U2 corresponds to... Figure 5A The L2-L2 line and the U4-U4 line correspond to Figure 5A The L4-L4 line and the U5-U5 line correspond to Figure 5A The L5-L5 line.

[0057] First refer to Figure 8C Multiple silicon oxide layers OL are arranged with spaces SP separated vertically. Space SP is the space created by etching silicon nitride layers SN. That is, before etching, the silicon nitride layers SN are exposed on the inner surface of the slit ST. By injecting etchant into the slit ST, the silicon nitride layers SN are removed from the exposed surface, thus creating the space SP. Furthermore, the silicon oxide layers OL after removing the silicon nitride films SN are supported by memory pillars MP in the memory array region MA, multiple support pillars (not shown), and a barrier layer BL in the slit ST. The support pillars mentioned here are formed in the stepped region FSA, etc., by forming holes through a stacked structure (slab SKI) consisting of alternating layers of silicon oxide layers SN and multiple silicon nitride layers SN, and embedding an insulating material such as silicon oxide into the holes. However, there are also cases where an insulating film is formed on the inner surface of the holes, and a conductive material is embedded inside.

[0058] on the other hand, Figure 8AIn this process, multiple silicon oxide layers (OL) and multiple silicon nitride layers (SN) are alternately deposited between the slits (ST). This is because the barrier layer (BL) on the inner surface of the slits (ST) prevents the silicon nitride layers (SN) from being etched.

[0059] In addition, as mentioned above, such as Figure 2 and Figure 4 As shown, barrier layers BL are also deposited within the two adjacent shorter slits OST within the finger region FG, therefore the silicon nitride layer SN between them is not removed. Consequently, the silicon nitride layer SN is not etched, and the insulating layer region ON is retained.

[0060] Next refer to Figure 8B Despite the presence of a barrier layer BL on the inner surface of the slit ST, the silicon nitride layer SN is still removed, resulting in a space SP. This is because the etching of the silicon nitride layer SN within the slit ST, starting from the portion where the barrier layer BL is absent, extends to that portion. See below for reference. Figure 9 This will explain how the silicon nitride layer SN in this part is etched. Figure 9 This is a schematic representation of a stacked SKI (e.g., see reference). Figure 5B A top view of the silicon nitride layer SN in the structure. After the etchant is injected from the slit ST, it will resemble... Figure 9 The silicon nitride layer SN is etched as shown by arrow A. That is, in the area where the barrier layer BL is absent, the silicon nitride layer SN is etched, and the space SP continuously expands. Since such etching occurs in each slit ST, the spaces SP expanding from each slit ST are connected within the finger region FG.

[0061] On the other hand, the silicon nitride layer SN is also etched in the direction from the end point EP of the barrier layer BL towards the end point STE of the slit ST. Therefore, as Figure 9 As shown, the silicon nitride layer SN is etched into a quarter-circle shape centered on the endpoint EP. Therefore, in Figure 9 The portion shown by line U4-U4, despite having a barrier layer BL that should have prevented etching, still exhibited spatial SP. Thus, we obtain... Figure 8B The cross-sectional structure shown.

[0062] After removing the silicon nitride layer SN as described above, a metal such as tungsten is embedded within the space SP using, for example, atomic layer deposition (ALD), to form a conductive layer WL. As described above, a reference layer can be obtained. Figures 5A to 6E The structure of the slit termination region R is described.

[0063] Comparative Example 1

[0064] Next, the effects of the structure of the slit termination region R will be explained with reference to Comparative Example 1. Figures 10A to 10CThis is an explanatory diagram showing the structure of the slit termination region of the semiconductor memory device in Comparative Example 1. Figures 8A to 8C This represents the cross-section of the silicon nitride layer SN in the stack after it has been etched. Figure 10A This is a top view showing the slit termination region R1 of Comparative Example 1. Figure 10B It is along Figure 10A A sectional view of line E1-E1. Figure 10C It is along Figure 10A The cross-sectional view along line E2-E2 is also a cross-sectional view along line E3-E3. In addition, the slit termination region R1 also has a stacked structure formed by alternating layers of silicon oxide layer OL and silicon nitride layer SN before etching the silicon nitride layer SN.

[0065] like Figure 10A As shown, multiple slits ST1 are also provided in the slit termination region R1 of Comparative Example 1. However, a layer equivalent to the barrier layer BL of the first embodiment is not formed within the slits ST1. Therefore, the silicon nitride layer SN is exposed on the inner surface of the slits ST1, thereby... Figure 10C As shown, the silicon nitride layer SN is removed to create the space SP. Furthermore, the silicon nitride layer SN is also etched from the end STE1 of the slit ST1 towards the end E of the stacked body. Thus, as... Figure 10B As shown, a space SP is also generated in the portion between the end E of the laminated body and the end STE1 of the slit ST1.

[0066] Figure 11 This is a top view schematically showing the conductive layer WL1 of the slit termination region R1 in Comparative Example 1. That is, Figure 11 The diagram illustrates a conductive layer WL1 formed by embedding metals such as tungsten into the space SP. (Example:) Figure 11 As shown, since metal is also embedded in the portion between the end E of the laminated body and the end STE1 of the slit ST1, the conductive layers WL1 within the finger region FG1 are interconnected, as indicated by arrow AA in the figure. In other words, the effect of the slit ST1 in electrically separating the finger region FG1 is weakened.

[0067] In contrast, in the slit termination region R of the semiconductor memory device 1 of this embodiment, such as Figure 9 As shown, although the space SP extends from the end point EP of the barrier layer BL towards the end point STE of the slit ST, it is separated from this end point STE. Therefore, when a conductive layer WL is formed by embedding a metal (e.g., tungsten) into the space SP, the interface between the retained silicon nitride layer SN and the conductive layer WL is separated from the end point STE of the slit ST in the X-axis direction. In other words, the interface between the silicon nitride layer SN and the conductive layer WL is located along the X-axis direction at a position further away from the end point E of the stacked body than the end point STE of the slit ST. Therefore, no... Figure 11The middle arrow AA indicates the circuitous electrical path at the end STE of the slit ST. Therefore, it hinders the conduction of the conductive layer WL between two adjacent finger regions FG, thus preventing electrical separation between the finger regions FG.

[0068] Furthermore, the distance between the junction of the silicon nitride layer SN and the conductive layer WL and the end point STE of the slit ST depends on the length of the barrier layer BL formed on the inner surface of the slit ST in the X-axis direction. The relationship between this distance and the length of the barrier layer BL is explained below. Figure 12A and 12B This is a top view schematically showing the relationship between the etch length of the silicon nitride layer SN etched through the slit ST and the length of the barrier layer BL.

[0069] like Figure 12A As shown, a space SP is formed by removing the silicon nitride layer SN using etchant injected from the slit ST. On the other hand, a portion of the silicon nitride layer SN is retained between the end E of the stacked body and the end STE of the slit ST. Here, if the etching length of the silicon nitride layer SN is set to EL, and the width of the finger region FG is set to FGW, the silicon nitride layer SN within the finger region FG is replaced with a conductive layer WL in the portion sufficiently away from the end STE of the slit ST. Therefore, the relationship 2×EL≧FGW holds. Furthermore, when the length from the end STE of the slit ST to the end point EP of the barrier layer BL on the inner surface of the slit ST is set to BLL, the boundary between the conductive layer WL formed by embedding metal within the space SP and the silicon nitride layer SN needs to be separated from the end STE of the slit ST, requiring BLL>EL. This is based on… Figure 12B It is clear that when the etching length EL is greater than the length BLL of the barrier layer BL, the space SP extends beyond the end STE of the slit ST and connects on both sides of a slit ST. If metal is embedded into the space SP, the adjacent finger region FG will be electrically conductive.

[0070] Based on the above, if the relationship BLL > FGW / 2 holds between the length of the barrier layer BL (starting from the end STE of the slit ST) and the width FGW of the finger region FG, the finger region FG can be electrically separated. Alternatively, a safety factor can be considered. That is, if the safety factor is set to Sf, the relationship BLL > FGW / 2 + Sf can also be used.

[0071] Comparative Example 2

[0072] Next, we will explain the other effects of the structure of the slit termination region R with reference to Comparative Example 2. Figures 13A to 13C This is an explanatory diagram illustrating the structure of the slit termination region R2 of the semiconductor memory device in Comparative Example 2. (See diagram for example.) Figure 13AAs shown, the inner surface of slit ST2 does not have a layer equivalent to the barrier layer BL. Furthermore, in the diagram representing the area along... Figure 13A Sectional view of line L6-L6 Figure 13B The diagram illustrates a stepped conductive layer WL2 and an interlayer insulating film SO2 embedded in the space above the conductive layer WL2. This shape can be formed by alternatingly stacking silicon oxide layer OL2 and silicon nitride layer (not shown) layer by layer, processing the two ends of the stacked structure along the X-axis into a stepped shape, depositing silicon oxide film SO2 on top of it, and then replacing the silicon nitride layer with the conductive layer WL2 through slit ST2.

[0073] Figure 13C It is a schematic representation. Figure 13B The top view of the bottommost conductive layer WL2L is shown. Figure 13C As shown, the slit ST2, which divides the laminated structure, extends beyond the interface between the silicon oxide film SO2 and the conductive layer WL2L, along the X-axis to the region on the substrate layer SB where the laminated structure has been removed. Furthermore, the end STE2 of slit ST2 is located outside the end of the bottommost conductive layer WL2L. Therefore, it does not produce... Figure 11 Arrow AA indicates the circuitous conductive path at the end of slit ST2, STE. Thus, the structure of Comparative Example 2 also avoids conduction between adjacent finger regions FG2. However, when using the stepped shape of Comparative Example 2 to avoid short circuits between adjacent finger regions FG2, the X-axis length of the slit termination region R2 becomes longer. In particular, Figures 13A to 13C The diagram only shows 6 conductive layers WL2, including the conductive layer WL2L. When the number of conductive layers is, for example, 48 or 64, the length of the slit termination region R2 in the X-axis direction will become longer.

[0074] In contrast, the slit termination region R of the semiconductor memory device 1 according to the first embodiment eliminates the stepped shape at both ends of the stacked structure. Therefore, the X-axis length of the slit termination region R can be shortened, thereby enabling miniaturization of the semiconductor memory device 1. Furthermore, although contacts can be connected to the stepped conductive layers WL2 arranged in the slit termination region R2 of Comparative Example 2, in the semiconductor memory device 1, contacts CC are connected to each conductive layer WL in the stepped portion FS. The stepped portion FS is located at the center of the two memory array regions MA; therefore, compared to the case where contacts are provided in the slit termination region R2, the influence of parasitic resistance of each conductive layer WL can be reduced, and the operation of the memory cells can be accelerated.

[0075] Regarding the structure of the central part of semiconductor memory device 1

[0076] Next, refer to Figure 14AThe structure of the central portion of the semiconductor memory device 1 according to the first embodiment will be described. Figure 14A This is a schematic top view showing the central portion of the semiconductor memory device 1. Here, the central portion corresponds to the area between the two memory units MEM of the semiconductor memory device 1. Figure 1 The area RC is shown. Furthermore... Figure 14A The three slits ST on the left side shown are respectively with Figure 5A The three slits ST shown are connected. That is, Figure 5A This represents one end STE of each slit ST. Figure 14A This indicates the other end, STE.

[0077] in addition, Figure 14A The slit ST on the right side of the image is the memory section MEM on the right side of the semiconductor memory device 1 (see reference). Figure 1 The slit ST has an end STE located at a position separated from the end STE of the left slit ST, and extends along the X-axis. The right slit ST has the same structure as the left slit ST; therefore, the left slit ST will be described below.

[0078] like Figure 14A As shown, a barrier layer BL is provided on the inner surface of the slit ST. Specifically, the barrier layer BL covers a specific length along the X-axis, starting from the end STE of the slit ST on the inner surface of the slit ST. Such a barrier layer BL is referenced... Figures 7A-7E The method of explanation is formed. Furthermore, as referenced... Figures 8A-8C and Figure 9 As explained, the barrier layer BL is provided to prevent the silicon nitride layer SN near the end STE from being etched. That is, the space formed by etching the silicon nitride layer SN is separated from the end STE of the slit ST. The conductive layer WL formed by embedding metal into this space, and the boundary BD between it and the silicon nitride layer SN retained near the end STE, are also separated from the end STE of the slit ST. This boundary BD is the boundary between the laminate SK and the laminate SKI. Therefore, in region RC, the laminate SK and the laminate SKI can be aligned in the X-axis direction, and the end STE of the slit ST is located within the laminate SKI. This structure also prevents the formation of… Figure 11 The electrical path, as indicated by arrow AA, meanders at the end STE of slit ST. Therefore, it prevents the conduction of the conductive layer WL between two adjacent finger regions FG, ensuring electrical separation between the finger regions FG. Additionally, the boundary BD between the stacked layers SK and SKI in the central portion of the semiconductor memory device 1 is shown in the image. Figures 7A-7E As explained, it forms, therefore the boundary BD and Figure 5A Similarly, the lamination directions of the SKI and SK laminations are neatly arranged.

[0079] Regarding the structure of the end EF of the laminate SKI

[0080] Next, refer to Figure 14B To illustrate the end EF of the stacked SKI extending in the X-axis direction. Figure 14B It is along Figure 1 A partial cross-sectional view along line C1-C1 is shown. As illustrated, the silicon oxide layer OL and the silicon nitride layer SN are exposed at the end EF of the stacked SKI. The silicon nitride layer SN extends in the Y-axis direction and is connected to the conductive layer WL. The junction of the silicon nitride layer SN and the conductive layer WL is located between the end EF and the slit ST closest to the end EF. As described above, this structure is formed by removing a portion of the silicon nitride layer SN with etchant injected from the slit ST and filling the resulting space with metal. Here, the distance G between the end EF and the slit ST1 closest to the end EF can be greater than the etching length EL. As a result, the space SP created by removing the silicon nitride layer SN does not reach the end EF, allowing the silicon nitride layer SN to remain at the end EF. In other words, it is possible to prevent the end EF (end 1X of the semiconductor memory device 1) of the stacked SKI from exposing the conductive layer WL. Therefore, for example, in subsequent processes such as dicing, it is possible to prevent unexpected electrical short circuits between the upper and lower conductive layers WL.

[0081] Implementation Method 2

[0082] Next, refer to Figure 15A and Figure 15B The semiconductor memory device of the second embodiment will be described below. Figure 15A This is a top view schematically illustrating an example of the semiconductor memory device 100 according to the second embodiment. Figure 15B It is along Figure 15A A partial sectional view of line C2-C2.

[0083] like Figure 15AAs shown, the semiconductor memory device 100 of the second embodiment has a substrate 10. Two peripheral circuit sections PER and a stacked layer section SKY are formed on the substrate 10. Specifically, on the substrate 10, one peripheral circuit section PER, the stacked layer section SKY, and the other peripheral circuit section PER are arranged sequentially along the Y-axis direction. Each peripheral circuit section PER extends from one end 1Y of the semiconductor memory device 100 along the Y-axis direction to the other end 1Y in the X-axis direction. Furthermore, the length (width) of each peripheral circuit section PER in the Y-axis direction can be determined by taking into account, for example, the peripheral circuits and wiring formed by the peripheral circuit section PER. The stacked layer section SKY is sandwiched between the two peripheral circuit sections PER and has two stacked layers SK and a surrounding stacked layer SKI. Similar to the first embodiment, a memory section MEM is formed on the stacked layer SK. In this embodiment, the memory section MEM omits at least a portion of the structure of the peripheral circuit section PER below the stacked layer section SKY, and except for this point, it can have a structure that is substantially the same as the memory section MEM of the semiconductor memory device 1 of the first embodiment. In addition, when determining the Y-axis length of the peripheral circuit section PER, the number of memory cells in the memory array region MA of the memory section MEM can also be considered.

[0084] Furthermore, the two ends E of the stacked body SKY extending along the Y-axis coincide with the end 1Y of the semiconductor memory device 100. Near the end E of the stacked body SKY, a slit termination region R (as described in the first embodiment) is formed. Figure 5A and Figure 5B That is, the junction of the stacked body SKI and the stacked body SK (the junction of the silicon nitride layer SN and the conductive layer WL) extending from the end E of the stacked body SKY is located further away from the end E of the stacked body SKY than the end STE of the slit ST along the X-axis direction. On the other hand, the two ends EF of the stacked body SKY extending along the X-axis direction are separated from the end 1X of the semiconductor memory device 100 by the length of the peripheral circuit part PER in the Y-axis direction.

[0085] Reference Figure 15B The stacked structure SKI has a stepped portion FSY on the end 1X side of the semiconductor memory device 100. This stepped portion FSY uses a silicon nitride layer SN as a step surface and consists of a set of silicon nitride layers SN and a silicon oxide layer OL. The stepped portion FSY can be formed during the formation of the stepped portion FS of the stepped region FSA. Specifically, it can be formed by refining the resist mask used for formation in the Y-axis direction as shown in the figure, while simultaneously etching the stacked structure formed by the silicon nitride layer SN and the silicon oxide layer OL.

[0086] On the other hand, the stacked body SK is formed by replacing a portion of the silicon nitride layer SN of the stacked body SKI with a conductive layer WL through the slit ST before filling the slit ST with insulating material. In this embodiment, when removing the silicon nitride layer SN through the slit ST, a portion of the silicon nitride layer SN is retained to maintain the stacked body SKI. However, the silicon nitride layer SN can be removed and replaced with the conductive layer WL up to the Y-axis end of each segment of the step portion FSY. In other words, a step portion with the conductive layer WL of the stacked body SK as the step surface can also be provided at the end EF of the stacked body portion SKY. Furthermore, in the illustrated example, the step portion FSY has the silicon nitride layer SN as the step surface, but it can also have the silicon oxide layer OL as the step surface.

[0087] Furthermore, from the viewpoint of miniaturizing the semiconductor memory device 100, the step portion FSY formed on the end EF side of the stacked body portion SKY can also be processed into a step shape, for example, having a step shape along the Y-axis direction of the step portion FS of the step region FSA (see reference). Figure 4 The same inclination. In the embodiments described later, the step shape processed on the end EF side of the laminated body is also the same.

[0088] In addition, such as Figure 15B As shown, a peripheral circuit is provided in the peripheral circuit section PER, which includes, for example, a transistor Tr separated by the component separation section EI. In the illustrated example, a gate contact CS1 is connected to the transistor Tr, penetrating the interlayer insulating film SO. The gate contact CS1 is connected to a plug CP of the upper insulating film SOU embedded in the interlayer insulating film SO. The plug CP is connected, for example, to upper layer wiring (not shown).

[0089] Furthermore, the semiconductor memory device 100 of this embodiment may also have the same stepped region FSA as the semiconductor memory device 1 of the first embodiment. Therefore, the gate contact CS1 can be connected to contact CC and through contact C4 via plug CP or upper-layer wiring. Figure 2 , Figure 4 Electrical connections are provided. In the semiconductor memory device 100, the number of through-contacts C4 provided in the step region FSA may be less than the number of through-contacts C4 in the step region FSA of the semiconductor memory device 1 of the first embodiment. This is because the gate contact CS1 has the same function as the through-contact C4. Furthermore, in the semiconductor memory device 100, the step region FSA may not have through-contacts C4.

[0090] In the semiconductor memory device 100 of this embodiment, the junction between the stacked layer SKI and the stacked layer SK (the junction between the silicon nitride layer SN and the conductive layer WL) is located along the X-axis at the end E of the stacked layer SKY (stacked layer SKI) further away than the end STE of the slit ST. Therefore, in the second embodiment, the same effect as described in Comparative Examples 1 and 2 of the first embodiment can be achieved. Furthermore, in the semiconductor memory device 100 of this embodiment, the structure formed by insulating materials such as the substrate 10, interlayer insulating film SO, and insulating film SOU is exposed at the ends 1X and 1Y, but the conductive layer WL is not exposed. Therefore, for example, in subsequent processes such as dicing, it is possible to prevent unexpected electrical short circuits between the upper and lower conductive layers WL.

[0091] Third implementation method

[0092] Next, refer to Figure 16 The semiconductor memory device according to the third embodiment will be described below. The semiconductor memory device of the third embodiment is provided with two stacked body sections, which is different from the first and second embodiments. Figure 16 This is a cross-sectional view along the Y-axis near the end 1X of the semiconductor memory device 101 in this embodiment, for example, corresponding to a view along... Figure 15A Sectional view of line C2-C2 ( Figure 15B ).

[0093] like Figure 16 As shown, similar to the laminate SK, the laminate SK1 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL. The end of the laminate SK1 in the Y-axis direction (corresponding to the end EF in the second embodiment) Figure 15B The stack SK1 terminates at a position spaced apart from the end 1X of the semiconductor memory device 101. The end of the stack SK1 in the Y-axis direction is processed into a stepped portion FSY1, with the conductive layer WL as the stepped surface, and a segment consisting of a set of conductive layers WL and silicon oxide layer OL. However, the silicon oxide layer OL can also be a stepped surface. Furthermore, Figure 16 Although the illustration is omitted, the memory section MEM is formed in the region opposite to the end 1X of the semiconductor memory device 101, relative to the slit ST of the stacked body SK1.

[0094] Furthermore, an insulating film 52 is formed to cover the stepped portion FSY1 and the substrate 10. The insulating film 52 may be formed of an insulating material such as silicon oxide. In the illustrated example, a transistor Tr, as part of a peripheral circuit, is formed near the interface between the substrate 10 and the insulating film 52. A gate contact CS1 and a junction portion BC on the gate contact CS1 are connected to the transistor Tr in a manner that penetrates the insulating film 52. That is, a multilayer SK1 and a peripheral circuit portion PER are arranged side by side in the Y-axis direction on the substrate 10.

[0095] Furthermore, a bonding layer Bi is formed on the stacked body SK1. The bonding layer Bi may be formed of silicon oxide, for example. The upper surface of the bonding layer Bi is substantially the same as the upper surface of the insulating film 52. The bonding portion BC is disposed above the gate contact CS1 and is disposed at substantially the same height as the bonding layer Bi along the Z-axis direction. The bonding portion BC is formed of a conductive material and is connected to the gate contact CS1. Stacked bodies SKI and SK2 are formed on the bonding portion BC, the insulating film 52, and the bonding layer Bi in an arrangement in the Y-axis direction. Stacked body SKI extends from the junction BD of stacked bodies SKI and SK2 in the Y-axis direction and reaches the end 1X of the semiconductor memory device 101. That is, the end EF of stacked body SKI coincides with the end 1X of the semiconductor memory device 101. On the stacked body SKI, silicon oxide layer OL and silicon nitride layer SN are stacked alternately layer by layer, so at the end 1X of the semiconductor memory device 101, the alternately stacked silicon oxide layer OL and silicon nitride layer SN are exposed.

[0096] Similar to the stacked layer SK1, the stacked layer SK2 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL, and is disposed on the stacked layer SK1 via the bonding layer Bi. Although not shown in the figure, the memory section MEM is formed in the region of the stacked layer SK2 opposite to the end 1X of the semiconductor memory device 101 relative to the slit ST shown in the figure. The memory section MEM of the stacked layer SK2 can also be formed to be aligned with the memory section MEM of the stacked layer SK1 below in the Z-axis direction. In this case, Figure 16 Although the illustration is omitted, the memory cylinders MP (e.g., in the memory array region MA of the memory section MEM) are shown. Figure 3 The memory module (MP) can be configured to penetrate both the stacked layers SK1 and SK2. Here, the conductive layer WL of the stacked layer SK2 also functions as a word line. Therefore, the memory column (MP) can have memory cells at both the stacked layers SK1 and SK2. Furthermore, the step portion FS of the step region FSA of the memory unit (MEM) can be continuously provided from the stacked layer SK2 to the stacked layer SK1. Additionally, the number of through-connections C4 provided in the step region FSA can be less than the number of through-connections C4 in the step region FSA of the semiconductor memory device 1 of the first embodiment. Furthermore, in the semiconductor memory device 101, the step region FSA may not have through-connections C4.

[0097] In addition, such as Figure 16As shown, insulating films 53 and 54 are sequentially formed on the stacked layers SKI and SK2 using insulating materials such as silicon oxide. A contact CS2 is formed, which penetrates the insulating film 53 and the stacked layer SKI and connects to the junction BC. Furthermore, a plug CP is formed, penetrating the insulating film 54 and connecting to the contact CS2. The plug CP connects to upper-layer wiring (not shown), which connects to contacts or through-contacts in the stepped region FSA within the memory section MEM. With this configuration, the peripheral circuitry of the transistor Tr is electrically connected to the memory cells in the memory array region MA.

[0098] Furthermore, a slit ST is formed, which penetrates the insulating film 53, the stacked body SK2, the bonding layer Bi, and the stacked body SK1 and reaches the substrate 10. An insulating material, such as silicon oxide, is embedded within the slit ST. As described above, the slit ST can be used to remove the silicon nitride layer SN before the insulating material is embedded. The silicon nitride layer SN is etched in the Y-axis direction using an etchant injected into the slit ST. In this embodiment, the etching does not reach the end EF of the stacked body SKI, thus preserving the stacked body SKI. As a result, the stacked body SKI and the stacked body SK2 are arranged side-by-side in the Y-axis direction. On the other hand, in the stacked body SK1, the etching length exceeds the Y-axis length of the bottommost silicon nitride layer SN before it is replaced by the conductive layer WL, thereby replacing the entire silicon nitride layer SN with the conductive layer WL. Therefore, the stacked body SK1 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL.

[0099] Furthermore, at both ends of the laminate portion including laminate SK1 and laminate SK2 in the X-axis direction (corresponding to end E in the first embodiment and the second embodiment), laminate SKI is formed, and a reference is provided. Figures 5A-5B and Figures 6A-6E The slit termination region R described refers to the point where the junction of laminate SK1 and laminate SKI is located further away from the X-axis end of laminate SKI than the end of slit ST. Similarly, the junction of laminate SK2 and laminate SKI is also located further away from the X-axis end of laminate SKI than the end of slit ST.

[0100] Therefore, the third embodiment can achieve the same effects as those described in Comparative Examples 1 and 2 of the first embodiment. Furthermore, in the semiconductor memory device 101 of this embodiment, the substrate 10, silicon nitride layer SN, insulating film 52 formed of silicon oxide, etc., are exposed at the periphery, but the conductive layer WL is not exposed. Therefore, for example, in subsequent processes such as dicing, unexpected electrical short circuits between the upper and lower conductive layers WL can be prevented. In addition, the semiconductor memory device 101 has two stacked layers SK1 and SK2 in the Z-axis direction, thus increasing the storage capacity.

[0101] Example 1 of the variation of the third embodiment

[0102] Next, refer to Figure 17 The semiconductor memory device 102 of the third embodiment variation 1 will be described below. Figure 17 This is a cross-sectional view along the Y-axis near the end 1X of the semiconductor memory device 102 in Variation 1 of the third embodiment. The semiconductor memory device 102 has a substrate 10, on which a laminate SK10 and an insulating film 521 are formed. The laminate SK10 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL. A step portion FYL is formed at the Y-axis end of the lower layer of the laminate SK10. On the other hand, the upper layer of the laminate SK10 extends in the Y-axis direction and connects to the laminate SKI at the junction BD on the insulating film 521. The laminate SKI has a structure formed by alternating layers of silicon oxide layer OL and silicon nitride layer SN. In this variation, the end EF of the laminate SKI coincides with the end 1X of the semiconductor memory device 102.

[0103] The stacked layer SK10 also extends to a region opposite to the end 1X of the semiconductor memory device 102, relative to the slit ST. A memory section MEM (not shown) is formed in this region. The conductive layer WL of the stacked layer SK10 also functions as the word line of the memory cell within the memory section MEM. On the other hand, in the peripheral circuit section PER, a transistor Tr, as part of the peripheral circuit, is formed at the interface region between the insulating film 521 and the substrate 10. A gate contact CS1 extending through the stacked layer SK10 is connected to the transistor Tr. In the semiconductor memory device 102, the memory section MEM and the peripheral circuit section PER are also arranged side-by-side on the substrate 10 in the Y-axis direction.

[0104] A bonding layer Bi is formed on the laminate SKI and laminate SK10, and an insulating film 522 and laminate SK20 are formed on the bonding layer Bi. Similar to laminate SK10, laminate SK20 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL, and is disposed on laminate SK10 via bonding layer Bi. The Y-axis end of laminate SK20 (corresponding to end EF in the second embodiment) Figure 15B It terminates at a position spaced apart from the end 1X of the semiconductor memory device 102. A stepped portion FSY2 is formed at the Y-axis end of the stacked body SK20. The stepped portion FSY2 has a conductive layer WL as the step surface and a section consisting of a set of conductive layers WL and a silicon oxide layer OL.

[0105] Furthermore, insulating films 53 and 54 are sequentially formed on the stacked body SK20 and the insulating film 522. A slit ST is provided, which penetrates the insulating film 53, the stacked body SK20, the bonding layer Bi, and the stacked body SK10, and reaches the substrate 10. As described above, the slit ST is used to replace the silicon nitride layer SN with the conductive layer WL. In this variation example 1, when the silicon nitride layer SN is etched in the Y-axis direction using the etchant injected into the slit ST, the etching does not reach the end EF of the stacked body SKI, and the stacked body SKI is exposed at the end 1X of the semiconductor memory device 102. On the other hand, the length of this etching exceeds the Y-axis length of the silicon nitride layer SN located at the bottom layer of the stacked body SK20, so the stacked body SK20 has a structure formed by alternating layers of silicon oxide layer OL and conductive layer WL.

[0106] Furthermore, a contact CS2 is formed that penetrates both insulating film 53 and insulating film 522. Contact CS2 is electrically connected to gate contact CS1 via junction BC. Additionally, a plug CP penetrating insulating film 54 is connected to the upper end of contact CS2. Thus, transistor Tr is electrically connected to a contact in, for example, the stepped region FSA (not shown).

[0107] At both ends of the laminate portion including laminate SK10 and laminate SK20 in the X-axis direction (corresponding to end E in the first embodiment and the second embodiment), laminate SKI is formed, and a reference is provided. Figures 5A-5B and Figures 6A-6E The slit termination region R described refers to the portion of the junction between laminate SK10 and laminate SKI located along the X-axis direction further away from the X-axis end of laminate SKI than the end of slit ST. Similarly, the junction between laminate SK20 and laminate SKI is also located along the X-axis direction further away from the X-axis end of laminate SKI than the end of slit ST.

[0108] Therefore, Variation 1 of the third embodiment can achieve the same effects as those described in Comparative Examples 1 and 2 of the first embodiment. Furthermore, the conductive layer WL is not exposed around the semiconductor memory device 102 in this variation. Therefore, unexpected electrical short circuits between the upper and lower conductive layers WL can be prevented, for example, during subsequent processes such as dicing. In addition, the semiconductor memory device 102 has two stacked layers SK10 and SK20 in the Z-axis direction, thus increasing the storage capacity.

[0109] Example 2 of the variation of the third embodiment

[0110] Next, refer to Figure 18 The semiconductor memory device 103 of the variation example 2 of the third embodiment will be described. Figure 18The above diagram schematically shows a cross-sectional view along the Y-axis near the end 1X of the semiconductor memory device 103 in Variation Example 2 of the third embodiment. Figure 18 As shown, the semiconductor memory device 103 has a substrate 10. On the substrate 10, a first segment of the semiconductor memory device 102 of Variation 1 is disposed as a stacked body, and a second segment of the semiconductor memory device 101 of the third embodiment is formed thereon via a bonding layer Bi. In this configuration, at the junction BD, the stacked body SK2 is connected to the second stacked body SKI, and the stacked body SK10 is connected to the first stacked body SKI. The end EF of the stacked body SKI is exposed at the end 1X of the semiconductor memory device 103.

[0111] At both ends of the laminate portion including laminate SK10 and laminate SK2 in the X-axis direction (relative to end E in the first embodiment and the second embodiment), laminate SKI is formed, and a reference is provided. Figures 5A-5B and Figures 6A-6E The slit termination region R described refers to the portion of the junction between stacked layers SK10 and SKI located along the X-axis direction further away from the end of stacked layer SKI in the X-axis direction than the end of slit ST. Similarly, the junction between stacked layers SK2 and SKI is also located along the X-axis direction further away from the end of stacked layer SKI in the X-axis direction than the end of slit ST. Therefore, variation 2 of the third embodiment can achieve the same effects as those described in comparative examples 1 and 2 of the first embodiment. Furthermore, since the conductive layer WL is not exposed around the semiconductor memory device 103, unexpected electrical short circuits between the upper and lower conductive layers WL can be prevented, for example, during subsequent processes such as dicing. Moreover, since the semiconductor memory device 103 has two stacked layers SK10 and SK2 in the Z-axis direction, the storage capacity can be increased.

[0112] Example of the first variation

[0113] Next, a first variation of the semiconductor memory devices 1, 100, 101 (102, 103) of the first, second, and third embodiments will be described. The semiconductor memory device of the first variation has a step region different from the step region FSA, which is different from the semiconductor memory devices of the previous embodiments; the other structures are the same as in the previous embodiments. Hereinafter, the semiconductor memory device of the first variation will be described focusing on aspects that differ from the semiconductor memory device 1 of the first embodiment.

[0114] Figure 19 The top view schematically illustrates the stepped region FSA1 of the semiconductor memory device in the first variation example. This stepped region FSA1 corresponds to... Figure 1The step region FSA is arranged within the memory section MEM shown. Specifically, memory array regions MA are located on both sides of the step region FSA1. Figure 19 As shown, the semiconductor memory device in the first variation is also divided into a stepped region FSA1 and a memory array region MA using two adjacent slits ST. The region divided by the two slits ST is arranged according to... Figure 2 This is referred to as a finger-shaped component area FG. Within a finger-shaped component area FG, there is a stepped portion FS1 extending in the X-axis direction, and a group of through-connectors C4 arranged side-by-side with the stepped surfaces of FS1 in the Y-axis direction. Furthermore, the contacts CC and through-connectors C4 on the group of stepped surfaces arranged in the Y-axis direction are interconnected via upper-layer wiring (not shown).

[0115] Figure 20A Up along Figure 19 A cross-sectional view along line A3-A3. As shown, a stepped portion FS1 is formed using a silicon oxide layer OL and a conductive layer WL, with the conductive layer WL as the step surface. The stepped portion FS1 differs from the stepped portion FS1 of the semiconductor memory device 1 of the embodiment. Figure 3 That is, the stepped portion FS1 has a lowest segment at the center, and the segments become higher as they are further away from the center. More specifically, the stepped portion FS1 has segments with the second, fourth, sixth, and so on conductive layers WL as stepped surfaces in one direction downward along the X-axis from the lowest segment at the center, which has the lowest segment at the center as the stepped surface. Furthermore, in another direction downward along the X-axis from the lowest segment at the center, there are segments with the third, fifth, seventh, and so on conductive layers WL as stepped surfaces. The contact CC penetrates the interlayer insulating film SO and connects to the stepped surfaces of each segment. Alternatively, it can be as follows... Figure 3 and Figure 4 As shown, the silicon oxide layer OL becomes a stepped surface, and the junction CC penetrates the interlayer insulating film SO and the silicon oxide layer OL, which is a stepped surface, and is connected to the conductive layer WL.

[0116] This stepped portion FS1 can be formed using the same method as the stepped portion FS of the semiconductor memory device 1 in the first embodiment. For example, on the semiconductor substrate SB, a multilayer structure is formed by alternately stacking multiple silicon oxide layers OL and multiple silicon nitride layers SN on the same basis as the multilayer structure SKI. Next, a resist mask with an opening is provided at the location where the stepped portion FS1 is to be formed, and a process including etching using the resist mask, refining the resist mask, and re-etching is performed. As a result, a temporary stepped portion with the silicon nitride layer SN as the step surface is formed. Then, the stepped portion FS1 is obtained by replacing the silicon nitride layer SN with a conductive layer WL.

[0117] In addition, Figure 20AIn the diagram, a contact CCD is connected to the uppermost conductive layer WL. The intersection of the uppermost conductive layer WL and the memory pillar MP forms a drain-side select transistor, meaning the uppermost conductive layer WL functions as a drain-side select gate line. Furthermore, a through-contact C4D is provided adjacent to the contact CCD in the X-axis direction. The through-contact C4D penetrates the silicon oxide layer OL and the conductive layer WL to reach the peripheral circuit section PER (not shown). The lower end of the through-contact C4D is electrically connected to the peripheral circuitry of the peripheral circuit section PER, and the upper end is connected to the upper end of the contact CCD via an upper-layer wiring (not shown). Thus, the drain-side select transistor is controlled by the peripheral circuitry via the through-contact C4D and the contact CCD.

[0118] In addition, the through contact C4D has a spacer layer SL made of insulating material on its outer peripheral surface, which insulates the conductive part inside from the conductive layer WL.

[0119] Figure 20B Up along Figure 19 A sectional view along line A4-A4. (Example) Figure 20B As shown, a group of through-contacts C4 are formed, penetrating the silicon oxide layer OL and the conductive layer WL, and reaching the peripheral circuit section PER (not shown). A spacer layer SL is also provided at each through-contact C4, insulating the conductive portion at the center of the through-contact C4 from the conductive layer WL. Furthermore, Figure 20B In this configuration, contact CCD and through contact C4D are also positioned along the X-axis on either side of a group of through contacts C4. The group of contacts CCD and through contacts C4D arranged along the X-axis are electrically connected to each other via upper-layer wiring (not shown).

[0120] Refer again Figure 19A slit SHE is provided approximately at the center of the finger region FG along the Y-axis. Except for the area between the step portion FS1 and a group of through contacts C4, the slit SHE extends along the X-axis into the memory array region MA and the step region FSA1. Unlike the slit ST that penetrates the stacked layer SK, the slit SHE only disconnects the uppermost conductive layer WL (drain-side select gate line). Thus, drain-side select transistors are independently formed on both sides of the slit SHE. On the other hand, the conductive layer WL below the uppermost conductive layer WL is not disconnected by the slit SHE, but extends into a finger region FG and is shared by all memory pillars MP within the same finger region FG. Therefore, the contacts CC connected to the conductive layer WL are also shared by the memory pillars MP within the same finger region FG. That is, memory cells in the same finger region FG that are configured on the same layer share a single contact CC (and thus share a through contact C4 that is electrically connected to it) and operate through the same conductive layer WL (word line). On the other hand, memory cells on both sides of the slit SHE can operate independently by selecting the gate line on each drain side disconnected by the slit SHE.

[0121] As described above, in the semiconductor memory device of the first variation, a step region FSA1 different from that of the semiconductor memory device 1 of the embodiment is provided, and the semiconductor memory device of the first variation can also have the structure of the slit termination region R. That is, in the semiconductor memory device of the first variation, the same effect as that of the slit termination region R described above can also be obtained.

[0122] Alternatively, a stepped region FSA (FSA) can be applied to one of the two memory units MEM provided in the semiconductor memory device 1 of the first embodiment. Figure 2 For another memory section MEM, the step region FSA1 is not applied. Figure 19 Furthermore, step region FSA or step region FSA1 can be applied to both memory units MEM of the semiconductor memory device 1 of the first embodiment. Additionally, in the semiconductor memory devices 100 and 101 (102 and 103) of the second and third embodiments, step region FSA1 of the first variation can be provided instead of step region FSA. In this case, step region FSA1 can be provided on either or both of the two memory units MEM. However, the number of through contacts C4 may be less than the number of through contacts C4 in the semiconductor memory device 1 of the first embodiment.

[0123] (Second variation example)

[0124] Next, a second variation of the semiconductor memory devices 1, 100, 101 (102, 103) of the first, second, and third embodiments will be described. In the second variation of the semiconductor memory device, the conductive layer WL has a pad layer, which is different from the semiconductor memory device 1, but the other structures are the same. Hereinafter, the semiconductor memory device of the second variation will be described focusing on the differences.

[0125] Figure 21 The above schematic cross-sectional view shows the slit termination region of the second variation example, relative to... Figure 5B . Reference Figure 21 The enlarged view shows that the conductive layer WL is formed inside the padding layer ISL. The padding layer ISL can be formed of an insulating material such as alumina (Al2O3). Furthermore, in the illustrated example, the conductive layer WL includes a first conductive portion EC1 inside the padding layer ISL and a second conductive portion EC2 further inside. The first conductive portion EC1 can be formed, for example, of titanium nitride (TiN), and the second conductive portion EC2 can be formed, for example, of tungsten. As described above, it can be achieved by using a slit ST ( Figure 21 (The text is omitted) Etching and removing the silicon nitride layer SN to form a space SP (e.g.) Figure 8C This structure is formed by sequentially depositing a pad layer ISL, a first conductive part EC1, and a second conductive part EC2 on its inner surface. The pad layer ISL and the first conductive part EC1 function as barrier layers.

[0126] (Other variations)

[0127] The semiconductor memory device of the third embodiment (including variations 1 and 2) has two overlapping stacked layers SK1 and SK2, but is not limited thereto. The semiconductor memory device may also have three or more stacked layers. Furthermore, the number of layers in each stacked layer is not limited to the example shown in the figure and can be arbitrarily determined.

[0128] The semiconductor memory device of the first to third embodiments (including variations) has two memory units MEM, but is not limited thereto. The number of memory units MEM can be three or more, and can be arbitrarily determined.

[0129] While several embodiments of the invention have been described, these embodiments are merely illustrative and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope and spirit of the invention, and are encompassed within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: A laminated body, formed by alternating layers of first and second layers; and Multiple plate-shaped portions penetrate the laminate in the lamination direction of the laminate and extend in a first direction intersecting the lamination direction; The plurality of first layers are formed of a first insulating material. The plurality of second layers each have a first insulating region and a conductive region connected to the first insulating region in the first direction. The first insulating region is formed of a second insulating material and is configured to extend from the first end of the laminate in the first direction, such that it at least occupies the space between the first end of each of the plurality of plate-like portions extending in the first direction and the first end of the laminate in the first direction. The junction between the first insulating region and the conductive region is located along the first direction at a position further away from the first end of the laminate than from the first end of each of the plurality of plate-shaped portions. The plurality of plate-like portions each include an insulating barrier layer that extends along the first direction from each first end of the plurality of plate-like portions at a specific length. When the specific length of the barrier layer extending along the first direction is defined as BLL, and the interval between two adjacent plate-like portions among the plurality of plate-like portions is defined as FGW, the relationship BLL > FGW / 2 holds true.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of second layers further comprises a second insulating region formed of the second insulating material, which is connected to the conductive region in the first direction on the side opposite to the first insulating region, sandwiching the conductive region. Each of the plurality of plate-shaped portions has a second end on the opposite side of the first end in the first direction, located further away from the first end of the laminate than the boundary between the conductive region and the second insulating region.

3. The semiconductor memory device according to claim 1, wherein, The junctions of the first insulating regions and the conductive regions of the plurality of second layers are neatly arranged in the stacking direction.

4. The semiconductor memory device according to claim 2, wherein, The junctions of the second insulating regions and the conductive regions of the plurality of second layers are neatly arranged in the stacking direction.

5. The semiconductor memory device according to claim 1, wherein, Each of the plurality of second layers further comprises a third insulating region formed of the second insulating material, the third insulating region being connected to the conductive region in a second direction intersecting the lamination direction and the first direction.

6. The semiconductor memory device according to claim 5, wherein, The third insulating region of each of the plurality of second layers extends in the second direction and is exposed at the second end of the laminate that intersects with the first end.

7. The semiconductor memory device according to claim 5, wherein, The third insulating region of the plurality of second layers is formed in a stepped shape in the descending section of the second direction.

8. The semiconductor memory device according to claim 1, wherein, The laminate is arranged along the first direction, and each of the plurality of second layers has a first region, a second region, and a third region containing the conductive region. Within the second region of the laminate, the conductive regions of the plurality of second layers are formed in a stepped shape. The semiconductor memory device further comprises: a plurality of columnar portions disposed in the first region and the third region of the stacked body, penetrating the stacked body in the stacking direction, and forming a plurality of memory cells at positions where they intersect at least a portion of the conductive regions of the plurality of second layers; and The connecting portion extends in the stacking direction and is respectively connected to the conductive regions of the plurality of second layers formed in the step shape.

9. The semiconductor memory device according to claim 8, wherein, In the second region, each of the plurality of second layers partially includes a fourth insulating region formed by the second insulating material, and the fourth insulating regions of the plurality of second layers are neatly arranged in the stacking direction.

10. The semiconductor memory device according to claim 9, wherein, Between two adjacent plate-shaped portions of the plurality of plate-shaped portions in the second region, the fourth insulating region is arranged side by side in the first direction with the conductive regions of the plurality of second layers that are formed in the step shape.

11. The semiconductor memory device according to claim 9, further comprising a through-connection portion that penetrates the fourth insulating region in the stacking direction.

12. The semiconductor memory device according to claim 8, wherein, The step shape is either rising or falling in the first direction.

13. The semiconductor memory device according to claim 8, wherein, The step shape has a descending section and an ascending section in the first direction.

14. The semiconductor memory device according to claim 8, wherein, A peripheral circuit section, including a control circuit for controlling the plurality of memory cells, is disposed below the stacked body along the stacking direction.

15. A semiconductor memory device comprising: A laminated body, formed by alternating layers of first and second layers; and Multiple plate-shaped portions penetrate the laminate in the lamination direction of the laminate and extend in a first direction intersecting the lamination direction; The plurality of first layers are formed of a first insulating material. The plurality of second layers each have a first insulating region and a conductive region connected to the first insulating region in the first direction. The first insulating region is formed of a second insulating material and is configured to extend from the first end of the laminate in the first direction, such that it at least occupies the space between the first end of each of the plurality of plate-like portions extending in the first direction and the first end of the laminate in the first direction. The junction between the first insulating region and the conductive region is located along the first direction at a position further away from the first end of the laminate than from the first end of each of the plurality of plate-shaped portions. The semiconductor memory device comprises at least two overlapping stacks.

16. The semiconductor memory device according to claim 15, wherein, The plurality of second layers of at least one of the at least two laminates further have a second insulating region formed of the second insulating material, which is connected to the conductive region in a second direction intersecting the lamination direction and the first direction.

17. The semiconductor memory device according to claim 16, wherein, The second insulating regions of each of the plurality of second layers of at least two of the laminates extend in the second direction and are exposed at the second end of the laminate that intersects with the first end.

18. The semiconductor memory device according to claim 17, wherein, The plurality of second layers of at least one of the other at least two of the laminates terminate along the second direction at a position spaced apart from the second end of the laminate that intersects with the first end.

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