Display panel and display device

Abstract

The present application discloses a display panel and a display device, which relate to the field of display technology and can reduce the width of the peripheral area of the display panel, which is beneficial to reducing the border width of the display device. The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a substrate, a voltage signal line and a retaining wall structure. The voltage signal line is arranged on the peripheral area of the substrate, including an extension section extending along the circumference of the display area, and a lead-out section configured to electrically connect the extension section to an external circuit. The retaining wall structure is arranged on the side of the voltage signal line away from the substrate and surrounds the display area. The retaining wall structure includes a first sub-section and a second sub-section, the orthographic projection of the first sub-section on the substrate is located within the range of the orthographic projection of the extension section on the substrate, and the orthographic projection of the second sub-section on the substrate is separated from the vertical projection of the voltage signal line on the substrate. The present application is used to manufacture a display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, display devices such as mobile phones, televisions, and computers are increasingly being used in people's lives. Narrowing the bezel is a key development trend for display devices. Reducing the width of the peripheral area of the display panel and the bezel width of the display device are currently urgent issues that need to be addressed. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display panel and a display device, which can reduce the width of a peripheral area of the display panel, thereby facilitating reduction in the border width of the display device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, an embodiment of the present disclosure provides a display panel. The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a substrate, a voltage signal line, and a retaining wall structure. The voltage signal line is arranged in the peripheral area, including an extension section extending along the circumference of the display area, and a lead section configured to electrically connect the extension section to an external circuit. The retaining wall structure is arranged on a side of the voltage signal line away from the substrate and surrounds the display area. The retaining wall structure includes a first sub-section and a second sub-section, the orthographic projection of the first sub-section on the substrate is located within the range of the orthographic projection of the extension section on the substrate, and the orthographic projection of the second sub-section on the substrate is separated from the vertical projection of the voltage signal line on the substrate.

[0006] In some embodiments, the display panel further includes an encapsulation layer and an auxiliary connection line. The encapsulation layer covers the retaining wall structure, and the portion of the extension section away from the display area extends beyond an edge of the encapsulation layer. The auxiliary connection line is disposed on a side of the encapsulation layer away from the substrate and is electrically connected to the portion of the extension section extending beyond the encapsulation layer.

[0007] In some embodiments, the auxiliary connection line includes a connecting portion and an extending portion. The connecting portion is electrically connected to a portion of the voltage signal line extending out of the packaging layer. The extending portion is connected to the connecting portion and covers at least a portion of an edge region of the packaging layer.

[0008] In some embodiments, the display panel includes alternating straight side edges and curved corners, wherein the width of the peripheral area at the curved corners is smaller than the width of the peripheral area at the straight side edges. The auxiliary connection line includes a first sub-segment located at the curved corner, wherein a portion of the first sub-segment is located in the display area. The portion of the first sub-voltage signal line segment located in the display area has a grid-like structure.

[0009] In some embodiments, the auxiliary connecting line further includes a second sub-line segment located at a side of the straight line, and the second sub-line segment is located in the peripheral area.

[0010] In some embodiments, the display panel further includes a crack prevention barrier. The crack prevention barrier surrounds the display area and is located on a side of the barrier structure away from the display area. The side of the extension away from the display area contacts the crack prevention barrier.

[0011] In some embodiments, the display panel includes a first source-drain conductive layer, a first planar layer, a second source-drain conductive layer, and a second planar layer. The first source-drain conductive layer is disposed on a substrate and includes a first sub-voltage signal line located in a peripheral area. The first planar layer is disposed on a side of the first source-drain conductive layer away from the substrate and includes a first opening. The second source-drain conductive layer is disposed on a side of the first planar layer away from the first source-drain conductive layer and includes a second sub-voltage signal line. The second sub-voltage signal line is electrically connected to the first sub-voltage signal line through the first opening. The second planar layer is disposed on a side of the second source-drain conductive layer away from the second source-drain conductive layer and includes a second opening. The voltage signal line includes a first sub-voltage signal line and a second sub-voltage signal line.

[0012] In some embodiments, an orthographic projection of the first sub-voltage signal line on the substrate overlaps an orthographic projection of the second sub-voltage signal line on the substrate. The orthographic projection of the retaining wall structure on the substrate is within the range of the orthographic projection of the first sub-voltage signal line on the substrate and is also within the range of the orthographic projection of the second sub-voltage signal line on the substrate.

[0013] In some embodiments, the display panel further comprises an anode layer, a pixel defining layer, and a cathode layer. The anode layer is disposed on a side of the second planar layer away from the substrate and includes a connecting line disposed in the peripheral region, the connecting line being electrically connected to the second sub-voltage signal line through a second opening. The pixel defining layer is disposed on a side of the anode layer away from the substrate and includes a third opening. The cathode layer is electrically connected to the connecting line through the second opening.

[0014] In the display panel provided by the embodiments of the present disclosure, the orthographic projection of the first sub-portion of the retaining wall structure on the substrate lies within the orthographic projection of the extension section on the substrate. This means that the first sub-portion and the voltage signal lines are arranged perpendicular to the substrate. Compared to arranging the first sub-portion and the voltage signal lines along the width of the peripheral area, this reduces the width of the peripheral area occupied by the retaining wall structure and the voltage signal lines, thereby reducing the width of the peripheral area.

[0015] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the display panel in any of the above embodiments.

[0016] The display device provided by the embodiment of the present disclosure, since it adopts the display panel of the above embodiment, can reduce the width of the peripheral area of the display panel, reduce the border width of the display device, and improve the screen-to-body ratio of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and are not intended to limit the actual dimensions of the products involved in the embodiments of the present disclosure.

[0018] Figure 1 is a schematic diagram of a display device according to some embodiments of the present disclosure;

[0019] Figure 2 A circuit structure diagram of a display panel according to some embodiments of the present disclosure;

[0020] Figure 3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0021] Figure 4A for Figure 1 A sectional view along section line AA;

[0022] Figure 4B for Figure 1 Another cross-sectional view along section line AA;

[0023] Figure 5A A structural diagram of auxiliary connecting lines in some embodiments of the present disclosure;

[0024] Figure 5B Another structural diagram of auxiliary connecting lines in some embodiments of the present disclosure;

[0025] Figure 6A for Figure 5A A partial enlarged view of position C in the middle;

[0026] Figure 6B for Figure 5A Another partial enlarged view of point C in the middle;

[0027] Figure 7 for Figure 1 A sectional view along section line BB. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0029] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "some embodiments," "exemplarily," or "such as" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0030] In the description of the present disclosure, it should be understood that the terms "up", "down", "vertical", "horizontal", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0031] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this disclosure, unless otherwise specified, "plurality" means two or more.

[0032] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0033] In this article, "same-layer arrangement" refers to a layer structure formed using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching steps, and the specific patterns in the resulting layer structure may be continuous or discontinuous, at different heights or thicknesses.

[0034] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0035] Some embodiments of the present disclosure provide a display device 1000. Figure 1 The display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, or a virtual reality (VR) device.

[0036] The display device 1000 may be a liquid crystal display (LCD), an electroluminescent display, or a photoluminescent display. If the display device is an electroluminescent display, the electroluminescent display may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display, the photoluminescent display may be a quantum dot photoluminescent display.

[0037] The display device 1000 includes a display panel 100 and a glass cover 200. Figure 1 As shown, the display panel 100 has a display area 101 and a peripheral area 102, and the peripheral area 102 is arranged around the display area 101. The glass cover 200 covers and protects the display panel 100.

[0038] It should be understood that, in some other embodiments, the peripheral area 102 may also exist only on one side or multiple sides of the display area 101. The embodiments of the present disclosure are described by taking the peripheral area 102 surrounding the display area 101 as an example.

[0039] like Figure 2 As shown, Figure 2 is a schematic diagram of the circuit structure of the display panel, and Figure 2 The display panel 100 is rectangular as an example. The display area 101 of the display panel 100 includes a plurality of sub-pixels P arranged in an array. For example, the plurality of sub-pixels P are arranged in a plurality of rows and a plurality of columns, and each row of sub-pixels P includes a plurality of sub-pixels P arranged in a first direction X( Figure 2 The plurality of sub-pixels P are arranged in a horizontal direction in the second direction Y ( Figure 2 A plurality of sub-pixels P are arranged in a vertical direction (in a vertical direction). Each sub-pixel P includes a pixel driving circuit 110 and a light-emitting device 120; and the sub-pixel P is configured to display a picture.

[0040] The pixel driving circuit 110 includes multiple TFTs and at least one capacitor Cst. For example, the pixel driving circuit 110 can be a "7T1C" circuit, a "7T2C" circuit, or a "3T1C" circuit. The embodiments of the present disclosure do not specifically limit the structure of the pixel driving circuit 110. "T" refers to a thin film transistor, and the number before "T" refers to the number of thin film transistors; "C" refers to a capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0041] The peripheral area 102 of the display panel 100 includes a plurality of signal lines. Exemplarily, the plurality of signal lines may include a voltage signal line 130, a VDD signal line (not shown in the figure), a scan signal line GL, and a data line DL. The peripheral area 102 also includes a retaining wall structure (not shown in the figure). In addition, the peripheral area 102 may also include, for example, a gate drive circuit 150, a source driver (Source Driver IC), a circuit board (Source PCB), etc., which are not described one by one here. Among them, the voltage signal line 130 is located at the edge of the peripheral area 102 away from the display area 101 (farther away from the display area 101 compared to other signal lines and circuit structures).

[0042] In related art, at least a portion of the retaining wall structure is disposed on the side of the voltage signal lines that is away from the display area. That is, at least a portion of the retaining wall structure's orthographic projection on the plane where the voltage signal lines lie is located on the side of the voltage signal lines that is away from the display area. This results in a larger width of the peripheral area occupied by the retaining wall structure and the voltage signal lines, hindering the reduction of the width of the peripheral area of the display panel.

[0043] In order to solve the above problems, some embodiments of the present disclosure provide a display panel 100. Figure 3 The display panel 100 includes a substrate 10 , a voltage signal line 130 and a barrier structure 140 .

[0044] The voltage signal line 130 is disposed on the substrate 10 and is located in the peripheral area 102. The voltage signal line 130 includes an extension segment 1301 extending along the circumference of the display area 101, and a lead segment 1302 configured to electrically connect the extension segment 1301 to an external circuit. The extension segment 1301 of the voltage signal line 130 can be configured to electrically connect to the pixel driving circuit 110 within the display area 101, and the lead segment 1302 of the voltage signal line 130 can be electrically connected to an external circuit (such as a driver circuit board (Source PCB)).

[0045] Exemplarily, the peripheral region 102 includes a first sub-region 1021, a second sub-region 1022, a third sub-region 1023, and a fourth sub-region 1024. An extension section 1301 of the voltage signal line 130 extends along the second sub-region 1022, the third sub-region 1023, and the fourth sub-region 1024. Both ends of the extension section 1301 are located in the first sub-region 1021, with a gap between the ends of the extension section 1301. An extension section 1302 of the voltage signal line 130 is located within the first sub-region 1021 and extends along the second direction Y. One end of the extension section 1302 is connected to the end of the extension section 1301, and the other end extends away from the display area 101.

[0046] The retaining wall structure 140 is disposed on a side of the voltage signal line 130 away from the substrate 10 (eg Figure 4A ) and surrounds the display area 101. The retaining wall structure 140 includes a first sub-portion 1401 and a second sub-portion 1402. The orthographic projection of the first sub-portion 1401 on the substrate 10 is within the range of the orthographic projection of the extension section 1301 on the substrate 10, and the orthographic projection of the second sub-portion 1402 on the substrate 10 is separated from the orthographic projection of the voltage signal line 130 on the substrate 10.

[0047] The retaining wall structure 140 is disposed around the display area 101 and is an annular structure. The second sub-portion 1402 refers to the portion of the retaining wall structure 140 located between the two ends of the extension section 1301 ; the first sub-portion 1401 refers to the portion of the retaining wall structure 140 excluding the second sub-portion 1402 .

[0048] The display panel provided by the embodiment of the present disclosure is as follows: Figure 3 and Figure 4A As shown, Figure 4A for Figure 1The partial structural diagram of the peripheral region 102 is shown along line AA in FIG. The orthographic projection of the first sub-portion 1401 of the retaining wall structure 140 on the substrate 10 is located within the orthographic projection of the extension section 1301 on the substrate 10. That is, the first sub-portion 1401 and the voltage signal line 130 are arranged along a direction Z perpendicular to the substrate 10. Compared to arranging the first sub-portion 1401 and the voltage signal line 130 along the width of the peripheral region 102, the width of the peripheral region 102 occupied by the retaining wall structure 140 and the voltage signal line 130 can be reduced, thereby reducing the width of the peripheral region 102.

[0049] In some embodiments, see Figure 3 and Figure 4A , along a direction parallel to the substrate 10 and perpendicular to the extending direction of the extension section 1301, the maximum size of the first sub-section 1401 is smaller than the size of the extension section 1301. Figure 4A As shown, the cross section of the first sub-portion 1401 is trapezoidal, and the maximum dimension of the first sub-portion 1401 refers to the dimension of the first sub-portion 1401 on the side close to the voltage signal line 130 .

[0050] The orthographic projection of the first sub-portion 1401 on the extension section 1301 is located in the portion of the extension section 1301 close to the display area 101. In other words, the orthographic projection of the first sub-portion 1401 on the extension section 1301 is located within the extension section 1301 and in the portion of the extension section 1301 close to the display area 101. That is, the first sub-portion 1401 extends out from the side of the extension section 1301 away from the display area 101.

[0051] In this way, the width of the first sub-portion 1401 is smaller than the width of the extension section 1301, and the first sub-portion 1401 is located on the side of the extension section 1301 close to the display area 101, which can reduce the impact of the retaining wall structure 140 on the width of the peripheral area 102 without reducing the width of the voltage signal line 130.

[0052] For example, taking the first sub-portion 1401 and the extension section 1301 in the second sub-region 1022 as an example, along the first direction X, the size of the first sub-portion 1401 is smaller than the size of the extension section 1301. For example, taking the first sub-portion 1401 and the extension section 1301 in the third sub-region 1023 as an example, along the second direction Y, the size of the first sub-portion 1401 is smaller than the size of the extension section 1301.

[0053] In some embodiments, see Figure 4A The display panel 100 further includes an encapsulation layer 30 and an auxiliary connection line 160 .

[0054] The encapsulation layer 30 covers the retaining wall structure 140, and the portion of the extension section 1301 away from the display area 101 extends beyond the edge of the encapsulation layer 30. In other words, the encapsulation layer 30 exposes the portion of the extension section 1301 away from the display area 101. The encapsulation layer 30 is configured to isolate the light-emitting device 120 and the signal line from water and oxygen corrosion. Exemplarily, the encapsulation layer 30 may include a first inorganic layer 31, an organic encapsulation layer 32, and a second inorganic layer 33 stacked in sequence. The first and second inorganic layers 31, 33 are configured to block external water and oxygen, and the organic encapsulation layer 32 is configured to relieve stress and planarize the film layer.

[0055] The auxiliary connection line 160 is electrically connected to the portion of the voltage signal line 130 (the extension section 1301) extending out of the packaging layer 30, and is arranged in parallel with the voltage signal line 130 (eg Figure 5A and Figure 5B In this way, the width of the voltage signal line 130 can be reduced, and the resistance of the voltage signal line 130 can be reduced through the auxiliary connection line 160. Without increasing the resistance of the voltage signal line 130, the width of the voltage signal line 130 is reduced, and the width of the peripheral area 102 is further reduced.

[0056] Exemplarily, the auxiliary connection line 160 covers the portion of the voltage signal line 130 (extension section 1301 ) extending out of the encapsulation layer 30 ; thus, the auxiliary connection line 160 can protect the voltage signal line 130 and reduce the possibility of the voltage signal line 130 being corroded.

[0057] It should be noted that a protective film layer can be provided on the side of the auxiliary connection line 160 away from the substrate 10 to prevent the auxiliary connection line 160 from being directly exposed; alternatively, the display panel 100 further includes a touch structure (not shown in the figure) provided on the side of the encapsulation layer 30 away from the substrate 10, and the touch structure covers and protects the auxiliary connection line 160, thereby preventing the auxiliary connection line 160 from being directly exposed.

[0058] In some embodiments, see Figure 4A The auxiliary connection line 160 includes a connecting portion 161 and an extending portion 162. The connecting portion 161 covers the portion of the voltage signal line 130 extending from the encapsulation layer 30 and is electrically connected to the portion of the voltage signal line 130 extending from the encapsulation layer 30. The extending portion 162 covers at least a portion of the edge region of the encapsulation layer 30, that is, the extending portion 162 covers a portion of the encapsulation layer 30 near the edge of the display panel 100.

[0059] The extension portion 162 is used to increase the width of the auxiliary connection line 160, thereby reducing the resistance of the auxiliary connection line 160 and the resistance of the voltage signal line 130. This is conducive to further reducing the width of the voltage signal line 130, thereby reducing the width of the peripheral area of the display panel 100 and reducing the border width of the display device 1000.

[0060] In some embodiments, as Figure 1 and Figure 3 As shown, the display panel 100 includes alternating straight side edges 103 and curved corners 104, and the width D2 of the peripheral area 102 at the curved corners 104 is smaller than the width D1 of the peripheral area 102 at the straight side edges 103. This helps to bend the display panel 100 to form a curved surface.

[0061] For example, when the display panel 100 is a flexible display panel with curved surfaces on all sides, the curved corners 104 can reduce the difficulty of bending the display panel 100 .

[0062] Based on the above design, the width of the voltage signal line 130 at the curved corner 104 of the display panel 100 may be set to be narrower than that of the voltage signal line 130 at the straight side 103 of the display panel 100 .

[0063] In some embodiments, as Figure 5A As shown, the auxiliary connection line 160 may only include a first sub-segment 1601 located at the arc-shaped corner 104. Part of the first sub-segment 1601 (part of the extension 162) covers a portion of the encapsulation layer 30 located in the display area 101, and the portion of the display area 101 covered by the first sub-segment 1601 is in a grid shape.

[0064] The width of the voltage signal line 130 at the straight side 103 is relatively wide, so the auxiliary connection line 160 does not need to be set at the straight side 103. Since the width of the peripheral area 102 at the curved corner 104 is relatively small, the first sub-segment 1601 covers part of the display area 101, which can increase the width of the first sub-segment 1601 at the curved corner 104, thereby reducing the resistance of the voltage signal line 130 at the curved corner 104. This is beneficial to reducing the width of the peripheral area 102 at the curved corner 104. The portion of the extension 162 covering the display area 101 is in a grid shape, or the portion of the extension 162 covering the encapsulation layer 30 is in a grid shape. In this way, the influence of the extension 162 on the light extraction efficiency of the display area 101 can be reduced.

[0065] For example, see Figure 6A The first sub-segment 1601 includes a plurality of conductive lines that cross each other, and the plurality of conductive lines are interwoven to form a grid structure, thereby reducing the area where the first sub-segment 1601 blocks the light-emitting device 120 and reducing the impact of the first sub-segment 1601 on the light extraction efficiency of the display panel 100.

[0066] Alternatively, see Figure 6BThe first sub-line segment 1601 may include multiple avoidance openings 1603, each avoidance opening 1603 is opposite to the light-emitting device 120 of a sub-pixel P, that is, the orthographic projection of the avoidance opening 1603 on the substrate 100 covers the orthographic projection of the light-emitting device 120 opposite to it on the substrate 100; so that the light emitted by the light-emitting device 120 can pass through the avoidance opening 1603 and be emitted.

[0067] In some embodiments, as Figure 5B As shown, the auxiliary connecting line 160 may include a first sub-segment 1601 located at the arc corner 104 and a second sub-segment 1602 located at the straight side 103 .

[0068] like Figure 5B As shown, the extension portion 162 of the second sub-segment 1602 covers at least a portion of the encapsulation layer 30 located in the peripheral region 102. This can reduce the resistance of the voltage signal line 130 at the straight side 103 and reduce the width of the peripheral region 102 at the straight side 103.

[0069] In the related art, in order to ensure low resistance of the voltage signal line 130 , the width of the voltage signal line is usually between 200 μm and 400 μm.

[0070] In the embodiments of the present disclosure, by providing auxiliary connection lines 160, the width of the voltage signal line 130 can be designed to be 100 μm to 200 μm. This reduces the width of the voltage signal line 130 while ensuring low resistance of the voltage signal line 130, thereby reducing the width of the border area 102 of the display panel 100. For example, the width of the voltage signal line 130 can be 100 μm, 150 μm, 185 μm, or 200 μm, etc., which are not further described here.

[0071] It should be understood that the widths of the voltage signal line 130 at different locations may be equal or unequal. For example, the width of the voltage signal line 130 at the straight side 103 is equal at all locations and is greater than the width of the voltage signal line 130 at the curved corner 104. The widths of the voltage signal line 130 at the curved corner 104 may be equal or unequal.

[0072] In the embodiments of the present disclosure, see Figure 7 , Figure 7 for Figure 1 In the middle display area 101, a cross-sectional view along the section line BB is shown. Figure 7 Only a thin film transistor (TFT) and a light emitting device 120 are shown as examples.

[0073] like Figure 7As shown, the display panel 100 includes a substrate 10, which can be a flexible substrate or a rigid substrate. For example, if the substrate 10 is a flexible substrate, the substrate 10 material can be a high-temperature resistant resin (polyimide). The underside of the substrate 10 can be a process-bearing glass substrate, which can be non-destructively separated from the process-bearing glass substrate using the Laser Lift-Off (LLO) process.

[0074] The display panel 100 further includes a barrier layer 11 disposed on the substrate 10. The barrier layer 11 may be composed of multiple layers of inorganic materials. Figure 7 In the direction from bottom to top in the figure, the display panel 100 further includes an active layer 12, a first gate dielectric layer 13, a first gate layer 14, a second gate dielectric layer 15, a second gate layer 16, an interlayer dielectric layer 17, a first source-drain conductive layer 18, a first planarizing layer 19, a second source-drain conductive layer 20, and a second planarizing layer 21, which are sequentially arranged on the side of the blocking layer 11 away from the substrate 10.

[0075] The TFT includes a semiconductor pattern 121 located in the active layer 12, a gate electrode 141 located in the first gate layer 14, and a source electrode 181 and a drain electrode 182 located in the first source-drain conductive layer 18. The capacitor Cst may include a first electrode plate 142 located in the first gate layer 14 and a second electrode plate 16' located in the second gate layer 16. The pixel driving circuit 110 may also include signal lines (such as a VDD signal line and a data line) located in the first source-drain conductive layer 18 and the second source-drain conductive layer 20.

[0076] See Figure 4A In the peripheral region 102, the first source-drain conductive layer 18 includes a first sub-voltage signal line 131 located in the peripheral region 102. The first planar layer 19 includes a first opening 191, which exposes at least a portion of the first sub-voltage signal line 131. The second source-drain conductive layer 20 includes a second sub-voltage signal line 132, which is electrically connected to the first sub-voltage signal line 131 through the first opening 191. The second planar layer 21 includes a second opening (not shown), which exposes at least a portion of the second sub-voltage signal line 132.

[0077] In an embodiment of the present disclosure, the voltage signal line 130 includes a first sub-voltage signal line 131 and a second sub-voltage signal line 132, which can increase the thickness of the voltage signal line 130 (the dimension along the direction Z perpendicular to the substrate 10), which is beneficial to reducing the resistance of the voltage signal line 130.

[0078] In some embodiments, referring to 4A, the orthographic projection of the first sub-voltage signal line 131 on the substrate 10 overlaps (partially overlaps or completely overlaps) with the orthographic projection of the second sub-voltage signal line 132 on the substrate 10, which can reduce the width of the voltage signal line 130 and is beneficial to reducing the width of the peripheral area 102.

[0079] For example, see Figure 4A The orthographic projection of the first sub-voltage signal line 131 on the substrate 10 completely overlaps (or substantially overlaps) the orthographic projection of the second sub-voltage signal line 132 on the substrate 10, thereby minimizing the width of the voltage signal line 130. The second sub-voltage signal line 132 refers to the portion of the second source / drain conductive layer 20 located within the first opening 191.

[0080] The orthographic projection of the retaining wall structure 140 on the substrate 10 is located within the orthographic projection range of the first sub-voltage signal line 131 on the substrate 10 and is located within the orthographic projection range of the second sub-voltage signal line 132 on the substrate 10 , which is beneficial to reducing the width of the peripheral area 102 .

[0081] See Figure 7 The display panel 10 further includes an anode layer 22, a pixel defining layer 23, a light emitting layer 24, a spacer layer 25 and a cathode layer 26, which are sequentially arranged on the side of the second planar layer 21 away from the substrate 10 in a direction perpendicular to the substrate 10 and away from the substrate 10.

[0082] The anode layer 22 includes a plurality of mutually separated anodes 221 ( Figure 7 Only one anode 221 is exemplarily shown in the figure. The pixel defining layer 23 has a plurality of fourth openings, each of which exposes at least a portion of an anode 221.

[0083] The light-emitting layer 24 includes a plurality of light-emitting functional patterns 241, each of which is at least partially located within a fourth opening. The light-emitting layer 24 may include one or more layers of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0084] The cathode layer 26 may be a whole layer structure and may be made of a transparent conductive material, such as indium tin oxide (ITO).

[0085] The spacer layer 25 includes a plurality of spacers 251 , and the spacers 251 are used to support the mask in the evaporation process.

[0086] A light emitting device 120 includes an anode 221 , a light emitting functional pattern 241 located on the anode 221 , and a portion of the cathode layer 26 contacting the light emitting functional pattern 241 .

[0087] In the surrounding area 102, see Figure 4A and Figure 7 The anode layer 22 includes a connecting line 222 , and the connecting line 222 is electrically connected to the second sub-voltage signal line 132 through a second opening (not shown in the figure).

[0088] The pixel defining layer 23 includes a third opening (not shown) that exposes at least a portion of the connecting line 222. The cathode layer 26 is electrically connected to the connecting line 222 through the third opening. Specifically, the voltage signal line 130 is electrically connected to the cathode layer 26 and is configured to transmit a voltage signal to the cathode layer 26.

[0089] The encapsulation layer 30 is disposed on a side of the cathode layer 26 away from the substrate 10 .

[0090] The retaining wall structure 140 may include at least one of a first spacer 211 disposed on the same layer and made of the same material as the second planar layer 21 , a second spacer 231 disposed on the same layer and made of the same material as the pixel defining layer 23 , and a third spacer 262 disposed on the same layer and made of the same material as the spacer layer 25 .

[0091] The number of the retaining wall structure 140 may be one or more, which is not specifically limited in the embodiments of the present disclosure.

[0092] For example, see Figure 4A The number of the retaining wall structure 140 can be one. The retaining wall structure 140 includes a first spacer 211, a second spacer 231 and a third spacer 252 that are stacked.

[0093] For example, see Figure 4B The number of retaining wall structures 140 can be two, and the two retaining wall structures 140 are respectively a first retaining wall structure 140A and a second retaining wall structure 140B. The second retaining wall structure 140B is arranged on the side of the first retaining wall structure 140A close to the display area 101. The first retaining wall structure 140A may include a first pad 211, a second pad 231, and a third pad 252 arranged in a stacked manner. The second retaining wall structure 140B may include a fourth pad 232 and a fifth pad 253 arranged in a stacked manner. The fourth pad 232 is arranged in the same layer as the pixel defining layer 23 and is made of the same material, and the fifth pad 253 is arranged in the same layer as the spacer layer 25 and is made of the same material.

[0094] In some embodiments, see Figure 4A The display panel 100 further includes a crack prevention barrier 170, which surrounds the display area 101 and is located on the side of the barrier structure 140 away from the display area 101. The crack prevention barrier 170 is located on the side of the voltage signal line 130 away from the display area 101 and is in direct contact with the voltage signal line 130. Specifically, the side of the extended section 1301 of the voltage signal line 130 away from the display area 101 contacts the crack prevention barrier 170. This further reduces the width of the peripheral area 102.

[0095] The anti-crack retaining wall 170 can protect the voltage signal line 130 from the side of the display area 101 , thereby reducing the risk of water and oxygen corrosion on the voltage signal line 130 .

[0096] The crack prevention barrier 170 is at least partially embedded in a portion of the inorganic material layers (barrier layer 11, first gate dielectric layer 13, second gate dielectric layer 15, and interlayer dielectric layer 17) in the peripheral region 102. The crack prevention barrier 170 is made of an organic material. The crack prevention barrier 170 can also reduce stress generated in the bent edge region of the flexible display panel 100, preventing breakage of signal lines in the edge region and improving the display panel's product yield.

[0097] For example, the crack prevention barrier 170 can be provided in the same layer as the first planar layer 19 and made of the same material, so that the manufacturing process of the display panel 100 can be simplified.

[0098] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0099] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: The display panel has a display area and a peripheral area surrounding the display area; the display panel includes: substrate; a voltage signal line, disposed in the peripheral area, comprising an extension segment extending along the circumference of the display area, and a lead segment configured to electrically connect the extension segment to an external circuit; a retaining wall structure, disposed on a side of the voltage signal line away from the substrate and surrounding the display area; the retaining wall structure comprising a first sub-portion and a second sub-portion, wherein the orthographic projection of the first sub-portion on the substrate is within the range of the orthographic projection of the extension section on the substrate, and the orthographic projection of the second sub-portion on the substrate is separated from the perpendicular projection of the voltage signal line on the substrate; an encapsulation layer covering the retaining wall structure; a portion of the extension section away from the display area extends out of an edge of the encapsulation layer; The auxiliary connection line is arranged on a side of the packaging layer away from the substrate and is electrically connected to a portion of the extension section extending out of the packaging layer.

2. The display panel according to claim 1, wherein: The auxiliary connecting line includes: a connecting portion electrically connected to a portion of the voltage signal line extending out of the packaging layer; The extension portion is connected to the connection portion and covers at least a portion of an edge region of the encapsulation layer.

3. The display panel according to claim 1, wherein: The display panel includes alternately connected straight side edges and arc-shaped corners, wherein the width of the peripheral area at the arc-shaped corner is smaller than the width of the peripheral area at the straight side edges; The auxiliary connection line includes a first sub-segment located at the arc corner, a portion of the first sub-segment is located in the display area, and a portion of the first sub-segment located in the display area is a grid structure.

4. The display panel according to claim 3, wherein: The auxiliary connection line further includes a second sub-line segment located at a side of the straight line, and the second sub-line segment is located in the peripheral area.

5. The display panel according to claim 1, wherein: The display panel further includes: an anti-crack retaining wall, surrounding the display area and located on a side of the retaining wall structure away from the display area; A side of the extension section away from the display area contacts the crack prevention retaining wall.

6. The display panel according to any one of claims 1 to 5, wherein: The display panel includes: A first source-drain conductive layer is provided on the substrate and includes a first sub-voltage signal line located in the peripheral area; a first planarization layer, disposed on a side of the first source / drain conductive layer away from the substrate, and comprising a first opening; a second source-drain conductive layer, disposed on a side of the first planar layer away from the first source-drain conductive layer, comprising a second sub-voltage signal line, the second sub-voltage signal line being electrically connected to the first sub-voltage signal line through the first opening; a second planarization layer, disposed on a side of the second source / drain conductive layer away from the first planarization layer, and comprising a second opening; The voltage signal line includes the first sub-voltage signal line and the second sub-voltage signal line.

7. The display panel according to claim 6, wherein: The orthographic projection of the first sub-voltage signal line on the substrate overlaps with the orthographic projection of the second sub-voltage signal line on the substrate; The orthographic projection of the retaining wall structure on the substrate is located within the range of the orthographic projection of the first sub-voltage signal line on the substrate, and is also located within the range of the orthographic projection of the second sub-voltage signal line on the substrate.

8. The display panel according to claim 6, wherein: The display panel further includes: an anode layer, disposed on a side of the second planar layer away from the substrate, comprising a connecting line disposed in the peripheral region, the connecting line being electrically connected to the second sub-voltage signal line through the second opening; a pixel defining layer, disposed on a side of the anode layer away from the substrate, and comprising a third opening; The cathode layer is electrically connected to the connecting line through the third opening.

9. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 8.

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